From patchwork Wed Apr 26 10:32:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kumar, Udit" X-Patchwork-Id: 87799 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp145166vqo; Wed, 26 Apr 2023 03:43:57 -0700 (PDT) X-Google-Smtp-Source: AKy350bEnegRnpIE1AmmMYwgCpGb1TPYZkRAZvHHaXdpQp5DZAVA80OplsmnLUSpmJqIS3PleMiP X-Received: by 2002:a17:90a:1f46:b0:24b:3123:8dd8 with SMTP id y6-20020a17090a1f4600b0024b31238dd8mr20708757pjy.27.1682505836873; Wed, 26 Apr 2023 03:43:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682505836; cv=none; d=google.com; s=arc-20160816; b=Z6WgLvHnfZ7tcZusZa9bPydZVDO/B6EEcq0+8PB02eTjbpiBCBVuUJjVwjyQUgPW1R M4zDVNijo4DVmHBaMHEWjCEY/0qVk+2OAoVCgLkEEiahvhokLy1PIFKr5vIHip5GJn4D xhmJTSIiKdiSKUKo7ZYIaFFIg6qd/lP5QEE7+btjWKYtfKXb3g6pcDpjFZsT71FlqoSO nffgDQP5gcvhWwQAqLx4JjU0ZgMwtUzUR7CfrHjYGXVlYsDIG95VIMLd90VkrZ96gMuf O6FK5Sbu4q30/vtBWh0chxDfHWZTiZEc2kzTbZ1fA23iQ2OrWYCzY+3Sx3/D1BxJdr7x AhiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tiSYdIUuh63p4V7PBX949y1a5Hkhd1GxXUX/p/+tcaE=; b=1IcM8zvRzs/SpZ+8slEf8g/ZbYAs+TKHQgSAy9BPO79MFNmuBzlFPRF+ezVzSGjkSw Gx+u/XULY0qOBsBF0/suRBXjf3N5qqajy0pMqPb+vYc5y8IMK7xC1T/0kiWdg7mzaeqB NfqfwVGRR22pyLy58OF8B4SUEIO4AWoo6b/oxDrLnf14CbRtdEaswiXpZ8d8lTidFXEy APPx/4mxhd4+9aRx8HzTdSzbZh5bcKjyC57QELZSoQTQt54kpakAHDSvyiZWnPe5J9/2 4KlBJs/YzwNNrO4DLX6devtoqZxdVdYM0ebx2yOo/Fc4MQqD5JsRuZwuytXurDAHXKtK 7+/Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=rkB+5xtv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id o18-20020a17090aeb9200b002474701edc0si15918550pjy.188.2023.04.26.03.43.44; Wed, 26 Apr 2023 03:43:56 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=rkB+5xtv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240476AbjDZKdT (ORCPT + 99 others); Wed, 26 Apr 2023 06:33:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33652 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240436AbjDZKdJ (ORCPT ); Wed, 26 Apr 2023 06:33:09 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0179D5242; Wed, 26 Apr 2023 03:32:45 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 33QAWUqw009823; Wed, 26 Apr 2023 05:32:30 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1682505150; bh=tiSYdIUuh63p4V7PBX949y1a5Hkhd1GxXUX/p/+tcaE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=rkB+5xtvLfrLwPcEym7tvff1QbdnCrbKMWr+amFbAKvceZNTSWfuZEJXozcerthOg yWiuR/BXjrZIC5fAlG6i/mm4ZhmG8KsvMSrtCuRflrOvPkF5crdBZvlCNzEOmfykmH 5idU3AHzwjGuEZLml+GnN6TRTkseib5girT8P2m4= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 33QAWUmH017241 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 26 Apr 2023 05:32:30 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 26 Apr 2023 05:32:29 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 26 Apr 2023 05:32:29 -0500 Received: from udit-HP-Z2-Tower-G9-Workstation-Desktop-PC.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 33QAWLRT036567; Wed, 26 Apr 2023 05:32:26 -0500 From: Udit Kumar To: , , , , , , , , , CC: Udit Kumar Subject: [PATCH 1/5] arm64: dts: ti: k3-j7200: Add general purpose timers Date: Wed, 26 Apr 2023 16:02:15 +0530 Message-ID: <20230426103219.1565266-2-u-kumar1@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230426103219.1565266-1-u-kumar1@ti.com> References: <20230426103219.1565266-1-u-kumar1@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764235240182950835?= X-GMAIL-MSGID: =?utf-8?q?1764235240182950835?= There are 20 general purpose timers on j7200 that can be used for things like PWM using pwm-omap-dmtimer driver. There are also additional ten timers in the MCU domain. Signed-off-by: Udit Kumar --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 240 ++++++++++++++++++ .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 120 +++++++++ 2 files changed, 360 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index ef352e32f19d..555bde0e7fda 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -971,6 +971,246 @@ watchdog1: watchdog@2210000 { assigned-clock-parents = <&k3_clks 253 5>; }; + main_timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 49 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 49 1>; + assigned-clock-parents = <&k3_clks 49 2>; + power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 50 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 50 1>; + assigned-clock-parents = <&k3_clks 50 2>; + power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 51 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 51 1>; + assigned-clock-parents = <&k3_clks 51 2>; + power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 52 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 52 1>; + assigned-clock-parents = <&k3_clks 52 2>; + power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer4: timer@2440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 53 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 53 1>; + assigned-clock-parents = <&k3_clks 53 2>; + power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer5: timer@2450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 54 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 54 1>; + assigned-clock-parents = <&k3_clks 54 2>; + power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer6: timer@2460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 55 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 55 1>; + assigned-clock-parents = <&k3_clks 55 2>; + power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer7: timer@2470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 57 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 57 1>; + assigned-clock-parents = <&k3_clks 57 2>; + power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer8: timer@2480000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2480000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 58 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 58 1>; + assigned-clock-parents = <&k3_clks 58 2>; + power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer9: timer@2490000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2490000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 59 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 59 1>; + assigned-clock-parents = <&k3_clks 59 2>; + power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer10: timer@24a0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24a0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 60 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 60 1>; + assigned-clock-parents = <&k3_clks 60 2>; + power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer11: timer@24b0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24b0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 62 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 62 1>; + assigned-clock-parents = <&k3_clks 62 2>; + power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer12: timer@24c0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24c0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 63 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 63 1>; + assigned-clock-parents = <&k3_clks 63 2>; + power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer13: timer@24d0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24d0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 63 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 63 1>; + assigned-clock-parents = <&k3_clks 63 2>; + power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer14: timer@24e0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24e0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 65 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 65 1>; + assigned-clock-parents = <&k3_clks 65 2>; + power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer15: timer@24f0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24f0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 66 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 66 1>; + assigned-clock-parents = <&k3_clks 66 2>; + power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer16: timer@2500000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2500000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 67 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 67 1>; + assigned-clock-parents = <&k3_clks 67 2>; + power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer17: timer@2510000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2510000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 68 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 68 1>; + assigned-clock-parents = <&k3_clks 68 2>; + power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer18: timer@2520000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2520000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 69 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 69 1>; + assigned-clock-parents = <&k3_clks 69 2>; + power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer19: timer@2530000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2530000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 70 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 70 1>; + assigned-clock-parents = <&k3_clks 70 2>; + power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + main_r5fss0: r5fss@5c00000 { compatible = "ti,j7200-r5fss"; ti,cluster-mode = <1>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 331b4e482e41..1c09e442b379 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -34,6 +34,126 @@ k3_reset: reset-controller { }; }; + mcu_timer0: timer@40400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 35 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 35 1>; + assigned-clock-parents = <&k3_clks 35 2>; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer1: timer@40410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 71 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 71 1>; + assigned-clock-parents = <&k3_clks 71 2>; + power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer2: timer@40420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 72 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 72 1>; + assigned-clock-parents = <&k3_clks 72 2>; + power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer3: timer@40430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 73 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 73 1>; + assigned-clock-parents = <&k3_clks 73 2>; + power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer4: timer@40440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 74 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 74 1>; + assigned-clock-parents = <&k3_clks 74 2>; + power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer5: timer@40450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 75 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 75 1>; + assigned-clock-parents = <&k3_clks 75 2>; + power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer6: timer@40460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 76 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 76 1>; + assigned-clock-parents = <&k3_clks 76 2>; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer7: timer@40470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 77 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 77 1>; + assigned-clock-parents = <&k3_clks 77 2>; + power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer8: timer@40480000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40480000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 78 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 78 1>; + assigned-clock-parents = <&k3_clks 78 2>; + power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer9: timer@40490000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40490000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 79 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 79 1>; + assigned-clock-parents = <&k3_clks 79 2>; + power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + mcu_conf: syscon@40f00000 { compatible = "syscon", "simple-mfd"; reg = <0x00 0x40f00000 0x00 0x20000>; From patchwork Wed Apr 26 10:32:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kumar, Udit" X-Patchwork-Id: 87802 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp145887vqo; Wed, 26 Apr 2023 03:45:36 -0700 (PDT) X-Google-Smtp-Source: AKy350bVQmjTCkyoIgy2xCR2BeGlDLJYKGor8i5HNBjtNRG881xcNh4duzgDzpOaQXQLAGGzBYvf X-Received: by 2002:a17:903:1cf:b0:19f:a694:6d3c with SMTP id e15-20020a17090301cf00b0019fa6946d3cmr24297738plh.55.1682505936010; Wed, 26 Apr 2023 03:45:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682505935; cv=none; d=google.com; s=arc-20160816; b=nKCF5USgkIknl/biKJmPMe2HDN1g6UlRvxnv5miNOQLlexrYPOB8J23n6BixuZNheZ FM/DqcjQS8UkivjkT3nt4kyKE+mSpmoMqTYVTP1X7yff/tKdKghyEX+qxnRGur0HZlVU rZJr4wz7GtZLupXzqjQI+U7egAaCqxwnA5zKtbMsVmL4qmzBoOReuO6up0fWrb+++3Eg 8u6I1XDxjpnPjjTzF6uuhlO1cgDZ4r+efO/+ZpfW9lS1ekLDBlcLuQFRuCizL/KPNCPe DsEkTj6FtbFyDjqGjJpw6e/xt14aCKQPTq7XFYn4zntmRmlUxICwVKAk5r6/qUJen3D9 3grA== ARC-Message-Signature: i=1; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id lc7-20020a170902fa8700b001a9813e7039si5366272plb.174.2023.04.26.03.45.23; Wed, 26 Apr 2023 03:45:35 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Tu5DWMEL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240518AbjDZKda (ORCPT + 99 others); Wed, 26 Apr 2023 06:33:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33542 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240181AbjDZKdK (ORCPT ); Wed, 26 Apr 2023 06:33:10 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F140525A; Wed, 26 Apr 2023 03:32:49 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 33QAWY9B059994; Wed, 26 Apr 2023 05:32:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1682505154; bh=waGw9Blth8eqen3IxADKOrXO/8la1G/GfpzU9XVAG54=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Tu5DWMELx0PV0C1pUK/+GIA/Z8WNUp7fHapE2wyK574wYdYpcSg4ylwBESOcF/Ui3 Qv1t6I49EXdgKx0GJQJiVhlMDGCrGxCUza+fRwwQ4uw0pti5jO8V8axyYE08b0mi1D K4bYpL4iGlEsH8h60G2yctKUWta65fWbJuFjZ5qs= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 33QAWYm8112864 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 26 Apr 2023 05:32:34 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 26 Apr 2023 05:32:33 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 26 Apr 2023 05:32:33 -0500 Received: from udit-HP-Z2-Tower-G9-Workstation-Desktop-PC.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 33QAWLRU036567; Wed, 26 Apr 2023 05:32:30 -0500 From: Udit Kumar To: , , , , , , , , , CC: Udit Kumar , Tony Lindgren Subject: [PATCH 2/5] arm64: dts: ti: k3-j7200: Configure pinctrl for timer IO Date: Wed, 26 Apr 2023 16:02:16 +0530 Message-ID: <20230426103219.1565266-3-u-kumar1@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230426103219.1565266-1-u-kumar1@ti.com> References: <20230426103219.1565266-1-u-kumar1@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764235344364902591?= X-GMAIL-MSGID: =?utf-8?q?1764235344364902591?= There are timer IO pads in the MCU domain, and in the MAIN domain. These pads can be muxed for the related timers. There are timer IO control registers for input and output. The registers for CTRLMMR_TIMER*_CTRL and CTRLMMR_MCU_TIMER*_CTRL are used to control the input. The registers for CTCTRLMMR_TIMERIO*_CTRL and CTRLMMR_MCU_TIMERIO*_CTRL the output. The multiplexing is documented in TRM "5.1.2.3.1.4 Timer IO Muxing Control Registers" and "5.1.3.3.1.5 Timer IO Muxing Control Registers", and the CASCADE_EN bit is documented in TRM "12.6.3.1 Timers Overview". For chaining timers, the timer IO control registers also have a CASCADE_EN input bit in the CTRLMMR_TIMER*_CTRL in the registers. The CASCADE_EN bit muxes the previous timer output, or possibly and external TIMER_IO pad source, to the input clock of the selected timer instance for odd numered timers. For the even numbered timers, the CASCADE_EN bit does not do anything. The timer cascade input routing options are shown in TRM "Figure 12-3224. Timers Overview". For handling beyond multiplexing, the driver support for timer cascading should be likely be handled via the clock framework. Cc: Nishanth Menon Cc: Vignesh Raghavendra Cc: Tony Lindgren Signed-off-by: Udit Kumar --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 18 ++++++++++++++++++ .../arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 18 ++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 555bde0e7fda..56a793d50a1d 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -392,6 +392,24 @@ cpts@3d000 { }; }; + /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ + main_timerio_input: pinctrl@104200 { + compatible = "pinctrl-single"; + reg = <0x0 0x104200 0x0 0x50>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x000001ff>; + }; + + /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ + main_timerio_output: pinctrl@104280 { + compatible = "pinctrl-single"; + reg = <0x0 0x104280 0x0 0x20>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000001f>; + }; + main_pmx0: pinctrl@11c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 1c09e442b379..abf88238f019 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -173,6 +173,24 @@ chipid@43000014 { reg = <0x00 0x43000014 0x00 0x4>; }; + /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ + mcu_timerio_input: pinctrl@40f04200 { + compatible = "pinctrl-single"; + reg = <0x0 0x40f04200 0x0 0x28>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000F>; + }; + + /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ + mcu_timerio_output: pinctrl@40f04280 { + compatible = "pinctrl-single"; + reg = <0x0 0x40f04280 0x0 0x28>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000F>; + }; + wkup_pmx0: pinctrl@4301c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ From patchwork Wed Apr 26 10:32:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kumar, Udit" X-Patchwork-Id: 87800 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp145442vqo; Wed, 26 Apr 2023 03:44:38 -0700 (PDT) X-Google-Smtp-Source: AKy350YmkiYS+lQzICgL8fsw4/aXz7Kmih0xXLCk86RJeSNDvesdtm3dFeommfQVMwTBU1DqSjBp X-Received: by 2002:a05:6a00:190f:b0:63f:1eb3:824b with SMTP id y15-20020a056a00190f00b0063f1eb3824bmr22686508pfi.17.1682505878297; Wed, 26 Apr 2023 03:44:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682505878; cv=none; d=google.com; s=arc-20160816; b=EKZ5d4WzCCG3kXjV1th/5PSrPL3wFuaJ5DvRKb4I9930ady1FTHIrFq0nPTCetK40f I0Pw2RVadm1llHlIpO1hoos0Gzf7whAHN9lf6Q8Q0xk11UbQXpz/rex8tgLJN/sK6Ktv Gj3dxoffj5u4SZU54NKSlnSm6ssahO3BSupkoZlRb++5p8bBWmAA39ocPJxKfl2vrhju c/M89V6rOJC9hWLOMkow3mKHRqZ3caliPhsQtBjSiWiPthmj1FAdi0m4AC8q69XpHy40 Tcb54NpszB3bYInasa762kL1ggv35sVMeO3TbtsYRLrnfQiASP7UCn6q70unk2pJrsuA ajyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=8eLpTtHETVJBRANnjz+W5hBx7WGRc172Y90EHGq9aTk=; b=BG2GPM7lkwDO4rfs42cIrdA5dS+2k/oo98FyNPKHsO8CxBd1ztWM/Sz4pmY+3b4/8A mS78R2y55+G9pDea4uKEF/AFCx3pPDvC32jDF2V62smiuPoQthNUm8JtgS7gSmk+kcvf xCnKaKOfsyE06FxeGc8Q208I2NBtUUVY6G1JGpFRYzfG8wQ4VffiRk0hidyzKlCvZo9D 0K9th4hETXcjFqQLvfNApR55R1KI2CRDw3om+bH2dQDoJ4MV8UUcMF/B9R+PtXrgmbhp 4Y20sV6UcRDukuu7onYT8tW1WHQjR5IhOw+UN/Y1oFuO6SRJucjdYjVPZQlaotLkn34T kVoQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=CaUQQ4s4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Udit Kumar --- arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 63633e4f6c59..37eb24d69924 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -107,10 +107,12 @@ J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ }; &main_pmx0 { - main_i2c0_pins_default: main-i2c0-pins-default { + main_uart0_pins_default: main_uart0_pins_default { pinctrl-single,pins = < - J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ - J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ + J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */ + J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */ + J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */ + J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */ >; }; @@ -163,6 +165,8 @@ &main_uart0 { status = "okay"; /* Shared with ATF on this platform */ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; }; &main_uart1 { From patchwork Wed Apr 26 10:32:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kumar, Udit" X-Patchwork-Id: 87801 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp145443vqo; Wed, 26 Apr 2023 03:44:38 -0700 (PDT) X-Google-Smtp-Source: AKy350b6S600Y4aoT/5ghp94ca4XR8ukYRNLwCUvKZDxTdA4m5xOXHrHXHNxOCH4YLU++JQUnZs3 X-Received: by 2002:a17:90a:3b0c:b0:247:4c28:311f with SMTP id d12-20020a17090a3b0c00b002474c28311fmr20571448pjc.34.1682505878356; Wed, 26 Apr 2023 03:44:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682505878; cv=none; d=google.com; s=arc-20160816; b=w18zdB3rPLujVk7vjd5TztzMBCcvvQ5dpkD3iZHyavpORRENDHD4XN7GgB6aNBvyxI oEVfuQh3WkCzuBW1rtM9IxVJHxsnIDlE3hw01GtasKWucl9YeVTSfEoaPeOanx+1jXBe WWyZnWO17daJHT/73aYgXPfG+o8nAZCVzw1Y6vSfnjPvq5voZRg1M6br6KKyoxA/a37A wYcqT9c3qW3QILKkOcWjf0aEpHM0oEr/HqWRKAnGwZBeCH5gI5eAvnA95aG8MO+iTl7x swAqnpLOBa1YHHMj4bsjAs2g8GypA/jLYUURT/g9TfCkSHZpOA3ZeUeXCqFzBypIlGiM Nm7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=YLbJp+mrPrbOBSNwMQ/GRPYyLQR+PpHvyhHbKNPpPRk=; b=O2RPyxL6Npi6THLx+k1JY87cHG9q1dWk9omLDjqMFM+2NdPtyyxAyb3kXwoj3wtMSl PYslcaqjotfkcD09sVSckGnqaVgYQUVQOaeiR/UcTzLwQ/XbvJYFTyuk90r0zJEYi0Yn SvMm6SFmNcu0kjC9zsPQnxf8IL8I6+T87l3obg7MA83VF33/cpw+qQPxqsYuJzKGFuFJ udJjXoGn8dzbXMxSIar67daIFF4SRecMq+yH+OTSOgO3iV82WqsOtGGX62diaqn0rM7j 11Xu2xJE3c2o7p4ne9WWGRAA8zwh6jcIzD++t092+EIWuKcysnfr5AejEHjzBpYtNKUl PNZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=RVL4cpmw; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Udit Kumar --- .../dts/ti/k3-j7200-common-proc-board.dts | 22 ++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 37eb24d69924..2cdfd957dd12 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -80,6 +80,24 @@ vdd_sd_dv: gpio-regulator-TLV71033 { }; }; +&wkup_pmx0 { + mcu_uart0_pins_default: mcu_uart0_pins_default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */ + J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */ + J721E_WKUP_IOPAD(0xf8, PIN_INPUT, 0) /* (E20) MCU_UART0_CTSn */ + J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */ + >; + }; + + wkup_uart0_pins_default: wkup_uart0_pins_default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */ + J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ + >; + }; +}; + &wkup_pmx2 { mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < @@ -158,7 +176,9 @@ &wkup_uart0 { &mcu_uart0 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; + clock-frequency = <96000000>; }; &main_uart0 { From patchwork Wed Apr 26 10:32:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kumar, Udit" X-Patchwork-Id: 87803 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp146134vqo; Wed, 26 Apr 2023 03:46:08 -0700 (PDT) X-Google-Smtp-Source: AKy350abBP86cqY9/qdlhWL/sscDqs/N8P1xI+1MnmQe9EsolJBF667ZOT+DI24hitmklyShd0lk X-Received: by 2002:a05:6a21:788d:b0:dc:4369:16a4 with SMTP id bf13-20020a056a21788d00b000dc436916a4mr26560635pzc.19.1682505968152; Wed, 26 Apr 2023 03:46:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682505968; cv=none; d=google.com; s=arc-20160816; b=MygJ/Npcm0HAVIDFj3zSDs6urNNZhPxMaKGNLpPGgOYHz1m57YJR2GR5vm8JN+n2zo S86s0hJh8RvGd6tUanGPI/8Wb+Kiiveta9RYyYUPHSr6czokQvkPUpUeyphu8dNb948D HEVu9lK5+XeHa2NQG3AwfzrCSoUjifEkzNokEhg2ARU/kK4LvGfRb9/BsK0BkVsIwoPb U5KlrsZJjhB+AURJ5kd1RC3VjR9qQu2cob3DqhwVZanVvwNrXn55JCr2iZgRd19s9piD 00smkG2xxbAt3fF7iaW4DvXpXnME4q1Oxa3NNN22dS+DkyTlul3Bf3GYRbbkphQhTFMj YMsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=/fjVMPFor0N4zh6uT/1TO+jeMgeiyy8KcT62Sb/bxyo=; b=QC2/PVcayR1FNNe6V+ZaADuTqrLHo6p5e5qy0czJsNIVlkjIDZb174jc5GEcDuzf9q +CvSGIQOlhmBoc10a7yN7t1Zx3bXMJuRA0l4WWR1pMZCoC54ZIHSZcEKMHMbuLHi8YBr AuH6mflVr8laVdsmJcTKHZs6Ek+Q26od9Ez3gF9IpEBbfId7TE4EFWY3DNZGFv5jysva RrB3CkJkvqV84eP/83ZWkwuJtiphg9cc46JY9bQaRlxx705CvVM8ufGarw0787V/h5Yw HDMAL/iPGPB4X2uGO5RibGy5T2/BlS/yGBEqTEbqxi7Y7UGJ5ZU/EagWFQJzV51LGJC5 irJw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="JC7/vZBs"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Udit Kumar --- arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 5 +++++ arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 3 +++ 2 files changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 2cdfd957dd12..1bcb94aec588 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -81,7 +81,9 @@ vdd_sd_dv: gpio-regulator-TLV71033 { }; &wkup_pmx0 { + bootph-pre-ram; mcu_uart0_pins_default: mcu_uart0_pins_default { + bootph-pre-ram; pinctrl-single,pins = < J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */ J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */ @@ -91,6 +93,7 @@ J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */ }; wkup_uart0_pins_default: wkup_uart0_pins_default { + bootph-pre-ram; pinctrl-single,pins = < J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */ J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ @@ -125,7 +128,9 @@ J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ }; &main_pmx0 { + bootph-pre-ram; main_uart0_pins_default: main_uart0_pins_default { + bootph-pre-ram; pinctrl-single,pins = < J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */ J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */ diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi index 269424154771..d2500837a0e8 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -119,7 +119,9 @@ J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ }; &wkup_pmx2 { + bootph-pre-ram; wkup_i2c0_pins_default: wkup-i2c0-pins-default { + bootph-pre-ram; pinctrl-single,pins = < J721E_WKUP_IOPAD(0x98, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */ J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */ @@ -129,6 +131,7 @@ J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */ &main_pmx0 { main_i2c0_pins_default: main-i2c0-pins-default { + bootph-pre-ram; pinctrl-single,pins = < J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */