From patchwork Sun Apr 23 14:10:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86725 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2216758vqo; Sun, 23 Apr 2023 07:13:13 -0700 (PDT) X-Google-Smtp-Source: AKy350Y9O1IfqylJoJvuzjpxvCqUQO36dQ3y69tfuZqygQXLUcNqoHqxn47w5sWmSuAoGc/nXPsj X-Received: by 2002:a05:6a20:734e:b0:d9:adc3:6a71 with SMTP id v14-20020a056a20734e00b000d9adc36a71mr14166170pzc.1.1682259193010; Sun, 23 Apr 2023 07:13:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682259192; cv=none; d=google.com; s=arc-20160816; b=bnofFFX00JmqsWjTpRhxALK8osZlXsfjzKF1SbXlJw8djMyBO8xegVdmvWBE/YBJ1J Q6MTsamhg0x8GY7O4p9lVSrEcVYXYLM6aLTCDtE73ydOr9oahG+0bcfUVsttjlLGTJ7n qc6pz8+Nc6nDLSSx3IdCO0dr7EwP/wBCxWTpDf8WkXnqsmR6aCxTvUM81bM90cJADeFE aC16+nb8RzRWfW81nNcZ850wA9muv3nrXyIO7lLwVGNPDb47r3GwDnqmUAGeNcmWdT9s /9kvpC4Zjvxow6sWgAhjHge8ze9qJX5kmszSoL29bnW9XwVLcu+1ml+1GnwI1yw1Yo8M phUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=V1oDkmbueRnnz+rHHKvWOOs8MJ4RbGDKdmsY3zOpu8c=; b=RVxgcwCk/FgLaMXy0g+Pci85XkZXlxIIws4BU1+DzTPh0QSy3kimKifRRTnkDiIXLd PdaQMFE17UhOOhiGdSfsNTy1R5F9Q5Q+MdwB5GcJh0REAVX6cBxVNNmNd3UaRvGMGqeC MafpGC6yzEO88hwh70WFphYIl2m29xPvyu0knnU1tr8hV77mXyDIDqZHzbj7mAQLs5hL hsk1ALdcBCLVJReCXIbd4G0CBDnbvL/O9QOu9csJ+6/tp8GjmU/Bt4pUahdiHrRVrX0u eSuaZlTlz+dO0nIxKiTg6UabtitGHwzQOlJmDJcU0AQE1AF8br5Z+DefBqPhh9kSna3W 2uYA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=C8X0Jytt; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id f13-20020a63dc4d000000b0051b1966e6b6si9140871pgj.521.2023.04.23.07.12.56; Sun, 23 Apr 2023 07:13:12 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=C8X0Jytt; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230001AbjDWOMG (ORCPT + 99 others); Sun, 23 Apr 2023 10:12:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59016 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229458AbjDWOME (ORCPT ); Sun, 23 Apr 2023 10:12:04 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B053B9 for ; Sun, 23 Apr 2023 07:12:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=V1oDkmbueRnnz+rHHKvWOOs8MJ4RbGDKdmsY3zOpu8c=; b=C8X0JyttvzfIZRkmdMIeTVc7jr uWzk7FyLU4tVJF6tWDU9ilaTYNyLbwiDmBI9EeXPAmdEV8uAFJVK7/F9zWtAh0UnRw5JRv1xbTYox qgbnp4/71R6hU95uy41F/0g+RaSktaXSjA1a8d9ns7pdr3WHgfypygBfP1cAsJAqIo93Ef/OxE2HE hcXZBOFO4sz7WlbRfmOM/+zeMAZ0dqs/TlNt5y7jhxvWOqDtYp0G8UZfjXtwg2wZZuZnp7SHqVHVy zITmGbRUxLyu9jhIv7+Eqmer4N2pJCz0GYbtQ+gVp3RIF/KiTw+kOwYrUh1XmLpo9aQgUwRZMSRI+ 58vqZ59A==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaRX-00ANVs-0Y; Sun, 23 Apr 2023 16:11:55 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , linux-kernel@vger.kernel.org Subject: [RFC PATCH 01/40] drm/amd/display: fix segment distribution for linear LUTs Date: Sun, 23 Apr 2023 13:10:13 -0100 Message-Id: <20230423141051.702990-2-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763976615595317282?= X-GMAIL-MSGID: =?utf-8?q?1763976615595317282?= From: Harry Wentland The region and segment calculation was incapable of dealing with regions of more than 16 segments. We first fix this. Now that we can support regions up to 256 elements we can define a better segment distribution for near-linear LUTs for our maximum of 256 HW-supported points. With these changes an "identity" LUT looks visually indistinguishable from bypass and allows us to use our 3DLUT. Signed-off-by: Harry Wentland --- .../amd/display/dc/dcn10/dcn10_cm_common.c | 95 +++++++++++++++---- 1 file changed, 76 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c index 7a00fe525dfb..f27413e94280 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c @@ -346,20 +346,37 @@ bool cm_helper_translate_curve_to_hw_format( * segment is from 2^-10 to 2^1 * There are less than 256 points, for optimization */ - seg_distr[0] = 3; - seg_distr[1] = 4; - seg_distr[2] = 4; - seg_distr[3] = 4; - seg_distr[4] = 4; - seg_distr[5] = 4; - seg_distr[6] = 4; - seg_distr[7] = 4; - seg_distr[8] = 4; - seg_distr[9] = 4; - seg_distr[10] = 1; - - region_start = -10; - region_end = 1; + if (output_tf->tf == TRANSFER_FUNCTION_LINEAR) { + seg_distr[0] = 0; /* 2 */ + seg_distr[1] = 1; /* 4 */ + seg_distr[2] = 2; /* 4 */ + seg_distr[3] = 3; /* 8 */ + seg_distr[4] = 4; /* 16 */ + seg_distr[5] = 5; /* 32 */ + seg_distr[6] = 6; /* 64 */ + seg_distr[7] = 7; /* 128 */ + + region_start = -8; + region_end = 1; + } else { + seg_distr[0] = 3; /* 8 */ + seg_distr[1] = 4; /* 16 */ + seg_distr[2] = 4; + seg_distr[3] = 4; + seg_distr[4] = 4; + seg_distr[5] = 4; + seg_distr[6] = 4; + seg_distr[7] = 4; + seg_distr[8] = 4; + seg_distr[9] = 4; + seg_distr[10] = 1; /* 2 */ + /* total = 8*16 + 8 + 64 + 2 = */ + + region_start = -10; + region_end = 1; + } + + } for (i = region_end - region_start; i < MAX_REGIONS_NUMBER ; i++) @@ -372,16 +389,56 @@ bool cm_helper_translate_curve_to_hw_format( j = 0; for (k = 0; k < (region_end - region_start); k++) { - increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]); + /* + * We're using an ugly-ish hack here. Our HW allows for + * 256 segments per region but SW_SEGMENTS is 16. + * SW_SEGMENTS has some undocumented relationship to + * the number of points in the tf_pts struct, which + * is 512, unlike what's suggested TRANSFER_FUNC_POINTS. + * + * In order to work past this dilemma we'll scale our + * increment by (1 << 4) and then do the inverse (1 >> 4) + * when accessing the elements in tf_pts. + * + * TODO: find a better way using SW_SEGMENTS and + * TRANSFER_FUNC_POINTS definitions + */ + increment = (NUMBER_SW_SEGMENTS << 4) / (1 << seg_distr[k]); start_index = (region_start + k + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS; - for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS; + for (i = (start_index << 4); i < (start_index << 4) + (NUMBER_SW_SEGMENTS << 4); i += increment) { + struct fixed31_32 in_plus_one, in; + struct fixed31_32 value, red_value, green_value, blue_value; + uint32_t t = i & 0xf; + if (j == hw_points - 1) break; - rgb_resulted[j].red = output_tf->tf_pts.red[i]; - rgb_resulted[j].green = output_tf->tf_pts.green[i]; - rgb_resulted[j].blue = output_tf->tf_pts.blue[i]; + + in_plus_one = output_tf->tf_pts.red[(i >> 4) + 1]; + in = output_tf->tf_pts.red[i >> 4]; + value = dc_fixpt_sub(in_plus_one, in); + value = dc_fixpt_shr(dc_fixpt_mul_int(value, t), 4); + value = dc_fixpt_add(in, value); + red_value = value; + + in_plus_one = output_tf->tf_pts.green[(i >> 4) + 1]; + in = output_tf->tf_pts.green[i >> 4]; + value = dc_fixpt_sub(in_plus_one, in); + value = dc_fixpt_shr(dc_fixpt_mul_int(value, t), 4); + value = dc_fixpt_add(in, value); + green_value = value; + + in_plus_one = output_tf->tf_pts.blue[(i >> 4) + 1]; + in = output_tf->tf_pts.blue[i >> 4]; + value = dc_fixpt_sub(in_plus_one, in); + value = dc_fixpt_shr(dc_fixpt_mul_int(value, t), 4); + value = dc_fixpt_add(in, value); + blue_value = value; + + rgb_resulted[j].red = red_value; + rgb_resulted[j].green = green_value; + rgb_resulted[j].blue = blue_value; j++; } } From patchwork Sun Apr 23 14:10:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86727 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2219092vqo; Sun, 23 Apr 2023 07:18:16 -0700 (PDT) X-Google-Smtp-Source: AKy350YYYAjeu84giEFsH+3eCgyy+lY0cdihjLk7yennZXZ9Lbgs6cljpuP/NceO++b4yx8gz4KZ X-Received: by 2002:a05:6a20:3953:b0:f2:4c39:8028 with SMTP id r19-20020a056a20395300b000f24c398028mr10595757pzg.21.1682259496192; Sun, 23 Apr 2023 07:18:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682259496; cv=none; d=google.com; s=arc-20160816; b=kzNkrOkxvfDZMUQdR3UTAXxFf7st8dRITMwnx22CFlNl118yVbO51vWA/K5X7FaDi7 2phUIXCrLD7GNfJsTjidxksQF15AOhutl2GvqBwuyb8D7KzVjHf/yCQfKTGEdmg43DV9 vrvQUAXm/t4VuoZMBPEA0LqbxBe/l+9kpnd7ndwvmJUyuJCTrY4r+W63Mf57aETLJw/G eSXVvfANaYnzg4ihkJOR7EzJ8xpoPHGgCO5TLfTjxDlMkE+OU8amJTm0BAwNGg2Khf0w 1cLgLZO4QPIWvbrP2L+12MUxLF3vfVitiKj4fI90d1nL2gOVUNUPXcgJhKUGuY2mJGjF fFNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=VoRYWGMN5c9KG4TgMo/sMnf0C+k2cdqhrvLiKjpRO7A=; b=VCNF1cP1moyTwSKGmhIBXUmqQFFOX2XvaQFtRMs0s+WiNAngTobqOeXq7HCfNXkcar mt2ant58eR9AVcDNHMoutw5i6vRuJhhxztdwj/GFf6DXgOCRC9b/zZj4CwlCPw3aP9Ce 4dO21GE9seKK8vLKarkqfErwzP/6Tctl0tcKhRMQf1p38uG/Bp4KOmWljbpLyIwX/iqk +fXN3sa/K1Ha5zli0iWWtwHDvW2q3aLrFOQJyWP2u03OBecbI9zd1QArgkGwH+YZo3J7 HqZ1H6dwHwbPFqwt1yn9Teh1utOm1H56QFFBeyu6Xe8BZkneOUkp5rf71Bl2H+S/igAu yt6Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=rpOzJFYo; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id z25-20020aa79599000000b006389d389c01si8961876pfj.78.2023.04.23.07.18.02; Sun, 23 Apr 2023 07:18:16 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=rpOzJFYo; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230149AbjDWOMI (ORCPT + 99 others); Sun, 23 Apr 2023 10:12:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59022 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229649AbjDWOMF (ORCPT ); Sun, 23 Apr 2023 10:12:05 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 89BCD10CC for ; Sun, 23 Apr 2023 07:12:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=VoRYWGMN5c9KG4TgMo/sMnf0C+k2cdqhrvLiKjpRO7A=; b=rpOzJFYoeReUqyZCbjrl9+lW6p znpkLJeZlULUEL9KwSv12WzUX8EKLpikCNGiQSyd7zQsBPbdNJVkusoz4CXXLRJzfmsMEsFx1Srr1 tXR9tru/pIjpEr2T/w3wSabpSyrIeJO3xTP+sM3eXr6oq0Ea2VK2yuWDnwfA3JJZ8maDBgLd/MrAO bhkSx05XBtQX1aXmE+4EIFftUvJarzG6BLSDlzUpTjFRZyZMLI6OEhOqMnyLA/UYBWoaptBByRz4V vDOCChvXQz9YXTMxC8YQt8OBEWL7CJXbnegEcmI1NlYJZY5m4Va8RKF2kjpNAa9gtQXNugQDsj88G 4j8B6Amg==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaRa-00ANVs-Ps; Sun, 23 Apr 2023 16:11:58 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , linux-kernel@vger.kernel.org Subject: [RFC PATCH 02/40] drm/amd/display: fix the delta clamping for shaper LUT Date: Sun, 23 Apr 2023 13:10:14 -0100 Message-Id: <20230423141051.702990-3-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763976933391555359?= X-GMAIL-MSGID: =?utf-8?q?1763976933391555359?= From: Harry Wentland The shaper LUT requires a 10-bit value of the delta between segments. We were using dc_fixpt_clamp_u0d10() to do that but it doesn't do what we want it to do. It will preserve 10-bit precision after the decimal point, but that's not quite what we want. We want 14-bit precision and discard the 4 most-significant bytes. To do that we'll do dc_fixpt_clamp_u0d14() & 0x3ff instead. Signed-off-by: Harry Wentland --- .../gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c index f27413e94280..efa6cee649d0 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c @@ -539,10 +539,18 @@ bool cm_helper_translate_curve_to_hw_format( rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green); rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue); + if (fixpoint == true) { - rgb->delta_red_reg = dc_fixpt_clamp_u0d10(rgb->delta_red); - rgb->delta_green_reg = dc_fixpt_clamp_u0d10(rgb->delta_green); - rgb->delta_blue_reg = dc_fixpt_clamp_u0d10(rgb->delta_blue); + uint32_t red_clamp = dc_fixpt_clamp_u0d14(rgb->delta_red); + uint32_t green_clamp = dc_fixpt_clamp_u0d14(rgb->delta_green); + uint32_t blue_clamp = dc_fixpt_clamp_u0d14(rgb->delta_blue); + + if (red_clamp >> 10 || green_clamp >> 10 || blue_clamp >> 10) + DC_LOG_WARNING("Losing delta precision while programming shaper LUT."); + + rgb->delta_red_reg = red_clamp & 0x3ff; + rgb->delta_green_reg = green_clamp & 0x3ff; + rgb->delta_blue_reg = blue_clamp & 0x3ff; rgb->red_reg = dc_fixpt_clamp_u0d14(rgb->red); rgb->green_reg = dc_fixpt_clamp_u0d14(rgb->green); rgb->blue_reg = dc_fixpt_clamp_u0d14(rgb->blue); From patchwork Sun Apr 23 14:10:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86736 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2222123vqo; Sun, 23 Apr 2023 07:26:00 -0700 (PDT) X-Google-Smtp-Source: AKy350ZETOjyE8h6NsFLQYtyHwVVn2X/JGGA0kqS1k1GbjCkVCWNfMJwWBDRjy16arHPIcfRMDpS X-Received: by 2002:a05:6a00:23c4:b0:626:29ed:941f with SMTP id g4-20020a056a0023c400b0062629ed941fmr15710520pfc.5.1682259960388; Sun, 23 Apr 2023 07:26:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682259960; cv=none; d=google.com; s=arc-20160816; b=pQz7Z9iEkT6tGDeca02md5GrLZafD9VT5GV48jBNcy6xBtfoGZ2Xw9mC3wl0lfZ0Mi 04GRwL6hbMa4PgxpYMOIT3PoTypp+Yl9VlXaWIJ21zWXlrAv32NpHl5xKuFmdGtf2GZ9 aSIEOErN+AhtoB6U0K8qCU54woU2a9HHfGQbqN3qVVRLZGcg1FcECoAMn/B0prdL8tC9 1nIW5b7v7VB7KSKfFIGSAwgI2DTHYla7yC0c+2sRejnw3f3886IiOi84h1qVJdjjYgPh A1nz3Xd9h2tTNhT3gS6a4yTB0XZyfztIyhjj48bSUWrvsnDCnRtvptTjdWGc6DV5twoQ 1nuA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=t2oXYPnyQYeafj80rDPPBk4DJ8Bih7Zw8inrjzwVK2k=; b=l6WvUwUGjf733jWV8O09wuKqGrOyMwO83ZDAgiN9FTMmb+lcCKNfGnzu98hwBBpo8w SuoI9XHBJ7SAXKw5vDv1lbB6zbGdaEbR8D3qRhpvDQbMdPoSiB5n3WRvvZc0jL4xOg3H ZOvaRB5GXklzI96qzNk8i87+g/PxQxm+xizO17nk+u/nZhzo6RAr+KuDZf26hSpd9/R6 aDplztwe8hs/1NYp1OMyZ6kg5J1/cO3VksOuIW+cY3RigfmoIj/z/yyiLIgfhre0mF1c IE2W4+Zt9ukJCe6fkDvy+FXmlnhaE8RaSLEY1yocda5fmpAERKN7MWdWEhC/Pf03BS+m 9Okw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=aP6aQ5wQ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id w8-20020a63f508000000b0050be58cbaf7si9512790pgh.733.2023.04.23.07.25.46; Sun, 23 Apr 2023 07:26:00 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=aP6aQ5wQ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230185AbjDWOMR (ORCPT + 99 others); Sun, 23 Apr 2023 10:12:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59128 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230173AbjDWOMM (ORCPT ); Sun, 23 Apr 2023 10:12:12 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F0FE127 for ; Sun, 23 Apr 2023 07:12:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=t2oXYPnyQYeafj80rDPPBk4DJ8Bih7Zw8inrjzwVK2k=; b=aP6aQ5wQasUVq+wLWIjGodQt00 LxejcRVm0NGApRky08NWdEeUpFtwqFGXZfG1nFO+TauDItvUKPJRf4yCfAHbqZI8qYIEhweQNuAZs e2PLcbfp7TVVKU3ZcyHGOl72JvMeTc5Qm5FPNTzGdGWbDtWZ8XSr2FqwIykOJrbQz2CaR9WsQma54 5DUODHpMMNwr+CNxJPFDVcIAq0sWsEWcq2cASJvjU51Dt697lL0odeA0v97oRsyGj3YvynKp/EeG8 3CGyaECE2hrwsRGd1wZtCOcoA67uI+hnGrVSX2jH5VuebhzdRABy7cjpsiXFDDSU//wlF63/I3guE WxIN7RFQ==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaRe-00ANVs-Kv; Sun, 23 Apr 2023 16:12:02 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 03/40] drm/amd/display: introduce Steam Deck color features to AMD display driver Date: Sun, 23 Apr 2023 13:10:15 -0100 Message-Id: <20230423141051.702990-4-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763977420482728633?= X-GMAIL-MSGID: =?utf-8?q?1763977420482728633?= We are enabling a large set of color calibration features to enhance KMS color mgmt but these properties are specific of AMD display HW, and cannot be provided by other vendors. Therefore, set a config option to enable AMD driver-private properties used on Steam Deck color mgmt pipeline. Co-developed-by: Joshua Ashton Signed-off-by: Joshua Ashton Signed-off-by: Melissa Wen --- drivers/gpu/drm/amd/display/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig index 06b438217c61..c45a8deb1098 100644 --- a/drivers/gpu/drm/amd/display/Kconfig +++ b/drivers/gpu/drm/amd/display/Kconfig @@ -53,5 +53,11 @@ config DRM_AMD_SECURE_DISPLAY of crc of specific region via debugfs. Cooperate with specific DMCU FW. +config STEAM_DECK + bool "Enable color calibration features for Steam Deck" + depends on DRM_AMD_DC + help + Choose this option if you want to use AMDGPU features for broader + color management support on Steam Deck. endmenu From patchwork Sun Apr 23 14:10:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86752 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2231371vqo; Sun, 23 Apr 2023 07:48:48 -0700 (PDT) X-Google-Smtp-Source: AKy350Y07AgCHZs61tnTkf26S5k33Hg38jiWSO6rwm9svSaBKB6iebZNlVwSY9MkKhC71wFEr0LB X-Received: by 2002:a05:6a20:ab98:b0:f0:ac6b:379f with SMTP id da24-20020a056a20ab9800b000f0ac6b379fmr11476283pzb.15.1682261327746; Sun, 23 Apr 2023 07:48:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682261327; cv=none; d=google.com; s=arc-20160816; b=QAfCgEZp605yuByn/8PXP5LDciXampB4V88uSFjg4iNH4c5wKTkI0pECNm6kBqOja9 vvAkC1PJuTkBbkfU6+6+rQXV0AzdcCya9b/vv3+uMXbJcyNsDLlosSFarC4fFSBnhEIK rJUm6eFeNgWKqNKxINB30YbgLqDlf9WPgP+YOFat7hExqIVyOyBRtBE+pdSa0DOMTOg4 5sXsoV5DZdUQPnDxrOYNuEuyB+1jtVv4riDQWqJIRmopPskoSdhgbyEO5hqMKLpF1iMB ybKdv9Pv/fJyYOO94KPs7K/AStfnw/RpN9m1u7r/EEbU6HoQJQgRX+hOGclLen6l84Hd SGrw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=61KSS5+ykrC2EpBhN11Qk1hbuXSnyOrLMv+gxM8XJiM=; b=n7LkHcyxE3M4+CctstdnuWlZqJdTnqtpLe577VTlCnHJQry5KBvsfZHfpFHa4jX2Ty q/GPPv1ZWsx26OazPoblrxorq5WipqE2A2Zl+/LrzAUjOOaCJe7cgUN6lRlgxUXmQV4a tMCZuC0MzW5S3kT3NjpJc10tdtdSNhBvBhvx8mt+3+Enc0LJvuJLLKq05PcsV04tBngJ qf6GWRZz+mFP7FaZK+RjL/eTD0yBGsZy25cbALzGYOLkhIrvLqOUgI+A2hsQ+99dbYoW jOo6lTvfSgp8owtiMtm1MsfAdOjk2yIW/PdG7eUvPS7qkXZZoZCt5yYhifA5vj4W7lqd 5ejg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=EBlbem39; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Melissa Wen --- include/drm/drm_mode_object.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/drm/drm_mode_object.h b/include/drm/drm_mode_object.h index 912f1e415685..7e4fb7536c6a 100644 --- a/include/drm/drm_mode_object.h +++ b/include/drm/drm_mode_object.h @@ -60,7 +60,7 @@ struct drm_mode_object { void (*free_cb)(struct kref *kref); }; -#define DRM_OBJECT_MAX_PROPERTY 24 +#define DRM_OBJECT_MAX_PROPERTY 47 /** * struct drm_object_properties - property tracking for &drm_mode_object */ From patchwork Sun Apr 23 14:10:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86750 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2231154vqo; Sun, 23 Apr 2023 07:48:09 -0700 (PDT) X-Google-Smtp-Source: AKy350baUHybexAe6hxIbGbft5t0wgbdFaCiEmAEj3Hn2WSpn9NHSP4ipFQwMPLVd9ZxhYFGDZ0V X-Received: by 2002:a17:90b:3785:b0:247:63c0:705b with SMTP id mz5-20020a17090b378500b0024763c0705bmr11196047pjb.15.1682261289532; Sun, 23 Apr 2023 07:48:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682261289; cv=none; d=google.com; s=arc-20160816; b=PZEtljwo6HRVEHFOqRLmqdgXje6oCXVjsgSAmjpheKybjtYuThyX94qKZT38FkNwOC pJpQWI4HE6b03h4NIoyfmAv/tDlAb7A0Opo/HUg4wnugNZJZo0lsnVv3Xd5v4x5DRvNp +DBVbZFYokin3rbIGWESBFSm+vg6jq9JPGNrsT9y2Su6YkEuC1wGi91+X3hqOEuHhvyT +hCsKg4aIUVGrEQMbRBQQJveQnYI6x1sqE2trgGpcokExDlHC3vKNK+NVQW0xyAywZef NU2DyjNIYU4vSAwFnDuTpqIr/QRuuFjCcEZqrbzKrM2MSy/melnfJDefvJ5rMg+qjDDN n6cg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=MWZg+O3y0ybUoSZE+Ev3495R/hqyYOtAGPPhQThmk+k=; b=rw5TrgiKkXPPtbyRd4wA8J3UuXU9X8JjhYHL6JTWjP9osvaNLUpTuPUu3vxx3hlS8S h6F4i54bIPt0wFz30CBL0IlatuCG5tom1ZwHKRDriQHhp4EQxOGtVzQBEB/gA0WY/Alt Y7jYXq97cZVduHH0tfWSjGfGw3GR7Vvwx5zS9hBg5Q2pXM2BpGyy2cyEy6ES3NFL93I3 l8l4d2O3fxBxOsqp+hpa/+1pd+xNly8t9aSLzjuQBEU6dgQDZJUTa8jGkXUnlw5+0fQx gHoxrIDQnbils1z/O6RvX8t5ESWvjSRMjJ5fIW54a2th1lc9puiTNSTkk4OofwBC3E71 MLgw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=eKogjPhF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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In the next patch, we add CRTC 3D LUT property to DRM color management after this shaper LUT and before the current CRTC gamma LUT. Signed-off-by: Melissa Wen --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 28 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 14 ++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 17 +++ .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 122 +++++++++++++++++- 4 files changed, 179 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 8632ab695a6c..44c22cb87dde 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1247,6 +1247,30 @@ amdgpu_display_user_framebuffer_create(struct drm_device *dev, return &amdgpu_fb->base; } +#ifdef CONFIG_STEAM_DECK +static int +amdgpu_display_create_color_properties(struct amdgpu_device *adev) +{ + struct drm_property *prop; + + prop = drm_property_create(adev_to_drm(adev), + DRM_MODE_PROP_BLOB, + "AMD_SHAPER_LUT", 0); + if (!prop) + return -ENOMEM; + adev->mode_info.shaper_lut_property = prop; + + prop = drm_property_create_range(adev_to_drm(adev), + DRM_MODE_PROP_IMMUTABLE, + "AMD_SHAPER_LUT_SIZE", 0, UINT_MAX); + if (!prop) + return -ENOMEM; + adev->mode_info.shaper_lut_size_property = prop; + + return 0; +} +#endif + const struct drm_mode_config_funcs amdgpu_mode_funcs = { .fb_create = amdgpu_display_user_framebuffer_create, }; @@ -1323,6 +1347,10 @@ int amdgpu_display_modeset_create_props(struct amdgpu_device *adev) return -ENOMEM; } +#ifdef CONFIG_STEAM_DECK + if (amdgpu_display_create_color_properties(adev)) + return -ENOMEM; +#endif return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index b8633df418d4..1fd3497af3b5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -344,6 +344,20 @@ struct amdgpu_mode_info { int disp_priority; const struct amdgpu_display_funcs *funcs; const enum drm_plane_type *plane_type; + + /* Driver-private color mgmt props */ +#ifdef CONFIG_STEAM_DECK + /** + * @shaper_lut_property: CRTC property to set post-blending shaper LUT + * that converts content before 3D LUT gamma correction. + */ + struct drm_property *shaper_lut_property; + /** + * @shaper_lut_size_property: CRTC property for the size of + * post-blending shaper LUT as supported by the driver (read-only). + */ + struct drm_property *shaper_lut_size_property; +#endif }; #define AMDGPU_MAX_BL_LEVEL 0xFF diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 2e2413fd73a4..de63455896cc 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -726,6 +726,23 @@ struct dm_crtc_state { struct dc_info_packet vrr_infopacket; int abm_level; + +#ifdef CONFIG_STEAM_DECK + /* AMD driver-private color mgmt pipeline + * + * DRM provides CRTC degamma/ctm/gamma color mgmt features, but AMD HW + * has a larger set of post-blending color calibration features, as + * below: + */ + /** + * @shaper_lut: + * + * Lookup table used to de-linearize pixel data for gamma correction. + * See drm_crtc_enable_color_mgmt(). The blob (if not NULL) is an array + * of &struct drm_color_lut. + */ + struct drm_property_blob *shaper_lut; +#endif }; #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index e3762e806617..503433e5cb38 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -229,7 +229,9 @@ static void dm_crtc_destroy_state(struct drm_crtc *crtc, if (cur->stream) dc_stream_release(cur->stream); - +#ifdef CONFIG_STEAM_DECK + drm_property_blob_put(cur->shaper_lut); +#endif __drm_atomic_helper_crtc_destroy_state(state); @@ -266,7 +268,12 @@ static struct drm_crtc_state *dm_crtc_duplicate_state(struct drm_crtc *crtc) state->crc_skip_count = cur->crc_skip_count; state->mpo_requested = cur->mpo_requested; /* TODO Duplicate dc_stream after objects are stream object is flattened */ +#ifdef CONFIG_STEAM_DECK + state->shaper_lut = cur->shaper_lut; + if (state->shaper_lut) + drm_property_blob_get(state->shaper_lut); +#endif return &state->base; } @@ -299,6 +306,111 @@ static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc) } #endif +#ifdef CONFIG_STEAM_DECK +/** + * drm_crtc_additional_color_mgmt - enable additional color properties + * @crtc: DRM CRTC + * + * This function lets the driver enable the 3D LUT color correction property + * on a CRTC. This includes shaper LUT, 3D LUT and regamma TF. The shaper + * LUT and 3D LUT property is only attached if its size is not 0. + */ +static void +dm_crtc_additional_color_mgmt(struct drm_crtc *crtc) +{ + struct amdgpu_device *adev = drm_to_adev(crtc->dev); + + if (adev->dm.dc->caps.color.mpc.num_3dluts) { + drm_object_attach_property(&crtc->base, + adev->mode_info.shaper_lut_property, 0); + drm_object_attach_property(&crtc->base, + adev->mode_info.shaper_lut_size_property, + MAX_COLOR_LUT_ENTRIES); + } +} + +static int +atomic_replace_property_blob_from_id(struct drm_device *dev, + struct drm_property_blob **blob, + uint64_t blob_id, + ssize_t expected_size, + ssize_t expected_elem_size, + bool *replaced) +{ + struct drm_property_blob *new_blob = NULL; + + if (blob_id != 0) { + new_blob = drm_property_lookup_blob(dev, blob_id); + if (new_blob == NULL) + return -EINVAL; + + if (expected_size > 0 && + new_blob->length != expected_size) { + drm_property_blob_put(new_blob); + return -EINVAL; + } + if (expected_elem_size > 0 && + new_blob->length % expected_elem_size != 0) { + drm_property_blob_put(new_blob); + return -EINVAL; + } + } + + *replaced |= drm_property_replace_blob(blob, new_blob); + drm_property_blob_put(new_blob); + + return 0; +} + +static int +amdgpu_dm_atomic_crtc_set_property(struct drm_crtc *crtc, + struct drm_crtc_state *state, + struct drm_property *property, + uint64_t val) +{ + struct amdgpu_device *adev = drm_to_adev(crtc->dev); + struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state); + bool replaced = false; + int ret; + + if (property == adev->mode_info.shaper_lut_property) { + ret = atomic_replace_property_blob_from_id(crtc->dev, + &acrtc_state->shaper_lut, + val, + -1, sizeof(struct drm_color_lut), + &replaced); + acrtc_state->base.color_mgmt_changed |= replaced; + return ret; + } else { + drm_dbg_atomic(crtc->dev, + "[CRTC:%d:%s] unknown property [PROP:%d:%s]]\n", + crtc->base.id, crtc->name, + property->base.id, property->name); + return -EINVAL; + } + + return 0; +} + +static int +amdgpu_dm_atomic_crtc_get_property(struct drm_crtc *crtc, + const struct drm_crtc_state *state, + struct drm_property *property, + uint64_t *val) +{ + struct amdgpu_device *adev = drm_to_adev(crtc->dev); + struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state); + + if (property == adev->mode_info.shaper_lut_property) + *val = (acrtc_state->shaper_lut) ? + acrtc_state->shaper_lut->base.id : 0; + else + return -EINVAL; + + return 0; +} +#endif + /* Implemented only the options currently available for the driver */ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { .reset = dm_crtc_reset_state, @@ -317,6 +429,10 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { #if defined(CONFIG_DEBUG_FS) .late_register = amdgpu_dm_crtc_late_register, #endif +#ifdef CONFIG_STEAM_DECK + .atomic_set_property = amdgpu_dm_atomic_crtc_set_property, + .atomic_get_property = amdgpu_dm_atomic_crtc_get_property, +#endif }; static void dm_crtc_helper_disable(struct drm_crtc *crtc) @@ -477,9 +593,11 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, is_dcn = dm->adev->dm.dc->caps.color.dpp.dcn_arch; drm_crtc_enable_color_mgmt(&acrtc->base, is_dcn ? MAX_COLOR_LUT_ENTRIES : 0, true, MAX_COLOR_LUT_ENTRIES); - drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES); +#ifdef CONFIG_STEAM_DECK + dm_crtc_additional_color_mgmt(&acrtc->base); +#endif return 0; fail: From patchwork Sun Apr 23 14:10:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86735 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2222011vqo; Sun, 23 Apr 2023 07:25:41 -0700 (PDT) X-Google-Smtp-Source: AKy350ZrclErT+DhyjNVDsowmjnE08YoTauyZ6jx55vm5InlDIc7e8LOK8RWyfgiN1AXf+WRaJ+B X-Received: by 2002:a05:6a20:c705:b0:f0:9cbd:78ca with SMTP id hi5-20020a056a20c70500b000f09cbd78camr11722741pzb.11.1682259941393; Sun, 23 Apr 2023 07:25:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682259941; cv=none; d=google.com; s=arc-20160816; b=isGMXyp9y3bTazUbAI8jNQETkWTeVEhPyzXGwjMurKIQmPTE81vpSif5ER9RNSfeUj lWD0aU422LmRP6u0UjDrzJpjo4MjwXci7972XhzhlrD3nNqTJ9IYLLjnw4MFEIOyUObC hpHgj3xLfuw23Nzwr+WawEwjYBJBdCqKn1uZ+1HhH7eTgvE/Vpkbqhnk3JwTrbRze84V 6MPyMYDneID6kBq8JaA8ZyiK4lcGO3DqTIZ+uS/ndiZ5l2+fVcFm9VSzUWuKn/wPwzXO uAG1V8cPi7o2b4SFLIUOSEzH1llA3QzvJ7Ods9hj/YX7zQjBmRLhXQOzptSKX+U4xQPp 5F2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Bm3Geo0t068sVPmTEYcYCE9oJGTq0xUkld/+z+807H0=; b=o8ZwoI+vqBYUH43PkQaZB/NBwqzfRuNoBTj2lj4R7sI1QlCy9KM8AIGRT0rqDrTdJy nOFGXh9Q+jRaoV3uE7O3fXudj9vV3CPq4F7I1pWovqsAWJt+fsGMpjNJHaoyNNaC0+lI oO9Kq0erH4cfahr777hBDPhw74QNNb9k5IyO0PH7lkn73jNf39tgQcZ/N8nNDloxTaum LLEAtKGX/34hVh8irPiZ920sCuVsjLKYCtlVNoz3B9IIgbQBuFieyF1zJJRkaDQobJWa Et4Z8k/EI8LjFaEXtGdcZ70rNRA5RfURmpgu3Mwey1A8Gg6eSxtssRvoV4c7YTKU6R7E wrfg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b="B1NZFih/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id z22-20020aa79f96000000b0063b506e148asi6588380pfr.90.2023.04.23.07.25.27; Sun, 23 Apr 2023 07:25:41 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b="B1NZFih/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229476AbjDWOMg (ORCPT + 99 others); Sun, 23 Apr 2023 10:12:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59478 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230246AbjDWOM2 (ORCPT ); Sun, 23 Apr 2023 10:12:28 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DFF4430F4 for ; Sun, 23 Apr 2023 07:12:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=Bm3Geo0t068sVPmTEYcYCE9oJGTq0xUkld/+z+807H0=; b=B1NZFih/nsbd8wN6emS12XMH6n cwfjEmV3Y44Dz3/Jj7ajJQ/7sbm69ggsPB1k5wAAeN0ByvwkioyXOW6e+ROOXLqvS5Fspi704K85n z+HQDTm53njLaBKNoTVb/TByZQ5C8JeVPvNR1IMFkNNu1QCT8vxEMWEi27nofoUNZZqYP48++6puT PyoEa9gUMyzc6wPhuEj6wxGZDC0ffLsJ8oUwacWdtHxZifgKqubO+L94NfMh7hBY1xND4hh6w2lmA acVUfeUsfjyMas0hFFMbpfHUpU5ImuCoznCUlPt/Gam7swjP8337OZHbrF989Pxb1NEMNx3yivn9r Xz+mnWFQ==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaRn-00ANVs-ED; Sun, 23 Apr 2023 16:12:11 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 06/40] drm/amd/display: add 3D LUT driver-private props Date: Sun, 23 Apr 2023 13:10:18 -0100 Message-Id: <20230423141051.702990-7-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763977399875853844?= X-GMAIL-MSGID: =?utf-8?q?1763977399875853844?= Add CRTC 3D LUT for gamma correction using a 3D lookup table. A shaper lut must be set to shape the content for a non-linear space. That details should be handled by the driver according to HW color capabilities. Signed-off-by: Melissa Wen --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 14 +++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 11 ++++++++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 13 ++++++++++++ .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 20 +++++++++++++++++++ 4 files changed, 58 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 44c22cb87dde..2abe5fe87c10 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1267,6 +1267,20 @@ amdgpu_display_create_color_properties(struct amdgpu_device *adev) return -ENOMEM; adev->mode_info.shaper_lut_size_property = prop; + prop = drm_property_create(adev_to_drm(adev), + DRM_MODE_PROP_BLOB, + "AMD_LUT3D", 0); + if (!prop) + return -ENOMEM; + adev->mode_info.lut3d_property = prop; + + prop = drm_property_create_range(adev_to_drm(adev), + DRM_MODE_PROP_IMMUTABLE, + "AMD_LUT3D_SIZE", 0, UINT_MAX); + if (!prop) + return -ENOMEM; + adev->mode_info.lut3d_size_property = prop; + return 0; } #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 1fd3497af3b5..205fa4f5bea7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -357,6 +357,17 @@ struct amdgpu_mode_info { * post-blending shaper LUT as supported by the driver (read-only). */ struct drm_property *shaper_lut_size_property; + /** + * lut3d_property: CRTC property to set post-blending 3D LUT gamma + * correction; a shaper LUT can be used before applying 3D LUT to + * delinearize content. + */ + struct drm_property *lut3d_property; + /** + * @lut3d_size_property: CRTC property for the size of post-blending 3D + * LUT as supported by the driver (read-only). + */ + struct drm_property *lut3d_size_property; #endif }; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index de63455896cc..09c3e1858b56 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -742,6 +742,15 @@ struct dm_crtc_state { * of &struct drm_color_lut. */ struct drm_property_blob *shaper_lut; + /** + * @lut3d: + * + * 3D Lookup table for converting pixel data. Position where it takes + * place depends on hw design, after @ctm or @gamma_lut. See + * drm_crtc_enable_color_mgmt(). The blob (if not NULL) is an array of + * &struct drm_color_lut. + */ + struct drm_property_blob *lut3d; #endif }; @@ -804,6 +813,10 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); +/* 3D LUT max size is 17x17x17 */ +#define MAX_COLOR_3DLUT_ENTRIES 4913 +#define MAX_COLOR_3DLUT_BITDEPTH 12 +/* 1D LUT degamma, regamma and shaper*/ #define MAX_COLOR_LUT_ENTRIES 4096 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 503433e5cb38..0e1280228e6e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -231,6 +231,7 @@ static void dm_crtc_destroy_state(struct drm_crtc *crtc, #ifdef CONFIG_STEAM_DECK drm_property_blob_put(cur->shaper_lut); + drm_property_blob_put(cur->lut3d); #endif __drm_atomic_helper_crtc_destroy_state(state); @@ -270,9 +271,12 @@ static struct drm_crtc_state *dm_crtc_duplicate_state(struct drm_crtc *crtc) /* TODO Duplicate dc_stream after objects are stream object is flattened */ #ifdef CONFIG_STEAM_DECK state->shaper_lut = cur->shaper_lut; + state->lut3d = cur->lut3d; if (state->shaper_lut) drm_property_blob_get(state->shaper_lut); + if (state->lut3d) + drm_property_blob_get(state->lut3d); #endif return &state->base; } @@ -326,6 +330,11 @@ dm_crtc_additional_color_mgmt(struct drm_crtc *crtc) drm_object_attach_property(&crtc->base, adev->mode_info.shaper_lut_size_property, MAX_COLOR_LUT_ENTRIES); + drm_object_attach_property(&crtc->base, + adev->mode_info.lut3d_property, 0); + drm_object_attach_property(&crtc->base, + adev->mode_info.lut3d_size_property, + MAX_COLOR_3DLUT_ENTRIES); } } @@ -381,6 +390,14 @@ amdgpu_dm_atomic_crtc_set_property(struct drm_crtc *crtc, &replaced); acrtc_state->base.color_mgmt_changed |= replaced; return ret; + } else if (property == adev->mode_info.lut3d_property) { + ret = atomic_replace_property_blob_from_id(crtc->dev, + &acrtc_state->lut3d, + val, + -1, sizeof(struct drm_color_lut), + &replaced); + acrtc_state->base.color_mgmt_changed |= replaced; + return ret; } else { drm_dbg_atomic(crtc->dev, "[CRTC:%d:%s] unknown property [PROP:%d:%s]]\n", @@ -404,6 +421,9 @@ amdgpu_dm_atomic_crtc_get_property(struct drm_crtc *crtc, if (property == adev->mode_info.shaper_lut_property) *val = (acrtc_state->shaper_lut) ? acrtc_state->shaper_lut->base.id : 0; + else if (property == adev->mode_info.lut3d_property) + *val = (acrtc_state->lut3d) ? + acrtc_state->lut3d->base.id : 0; else return -EINVAL; From patchwork Sun Apr 23 14:10:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86742 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2224312vqo; Sun, 23 Apr 2023 07:31:13 -0700 (PDT) X-Google-Smtp-Source: AKy350b82iXi+kf5mt9RObGmmcX6G7sOpgcY/XYxzQ1HWnqLKP8L2LpVojEF8j0B16OXD9R6Ex5P X-Received: by 2002:a05:6a20:a10b:b0:f2:eb8b:77a3 with SMTP id q11-20020a056a20a10b00b000f2eb8b77a3mr6979728pzk.35.1682260273658; Sun, 23 Apr 2023 07:31:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682260273; cv=none; d=google.com; s=arc-20160816; b=vFICLIuXXm/rfFK9Ce+XGyUv+5QJ/N6+DLqqVetkfTa25UWzlC/X4H2F3GQGjadnFl LszmAa4chG9DWLfhbROc87r2GSRvu7eA3Y4xau5TSVzZFsgzZ9CFH8/w1LpMl/XC25o5 VJLzyGD5WGjUzsHMrOHB6TobDHJJQWx02UyajcEzZoRhRj3ibRtQjn7V23e1hRi0fiO8 qOD5dOi5WVF+MwjNL1q3oVS47qngqM6vXtaVv54l04a7oyTmd0a02lXYwYp/yb89/gex AMZMV3xbfIlwrd4MYQJ/riDek66dp3lgxZv11K3EaJ3T4r4wC0v1dl4EYEi+WplXqCv7 i9gw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=wQhPhw7uUonhHv6/pWaJwwFqQGY16VHjVM8DO5hkoxs=; b=d5BbC2XLy3Kx3Yf5qv9gl+AQbvOEGtHjuQ8uDsXFZvN8w+G9mgPV123cDwgzONMH/g Hz1PfsdDEm9Te8yTbUJFVGQGxLq5glkCWiBAAn+hDp3ktEDb+bsQbRyQDKB7RoOLA9mw EP82VNld5gPDyjl9VruzXHJsWjQ5EAGHNtseXtTr7zWXrw3IuEGz6Oo+oTsTWIxZp2Tz VZctdpct114LIeqGEx956pMvf+t4kflk86o/LXPN3KubL8vVGp2kTFa/eZcKuN9ZOcrc HRSC1qSPqp71aT660PguQO+skwV9ESxCk2fbsAaToWxWGy7oi4C2ZAExDKEoYsIFIdfx CVwg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=qDuXtaWP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id j3-20020a654283000000b00502e4278d61si8561705pgp.648.2023.04.23.07.30.59; Sun, 23 Apr 2023 07:31:13 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=qDuXtaWP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230270AbjDWOMt (ORCPT + 99 others); Sun, 23 Apr 2023 10:12:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59970 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229659AbjDWOMh (ORCPT ); Sun, 23 Apr 2023 10:12:37 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9A2D510F0 for ; Sun, 23 Apr 2023 07:12:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=wQhPhw7uUonhHv6/pWaJwwFqQGY16VHjVM8DO5hkoxs=; b=qDuXtaWPVP/TKMVjyGy+mjnaLX LxYOPVWECl+YkJA4RcDIRr3nMqDwH2ZnP6/zouD+0EZfJ+tODlPAf6VUkVFj/wj0JO9Cwsg+A0TDk ChIum3eAfJKKKfE0+RWL41Wz7gIy0BPJH8sAatZzDeU20+2Agf6Z4PNBMNTEhg7H3itGe8e2D/gVF tjLHQ8IPFDgQW4rgXvK+AcW167XXtY+Qcfdn03BoHDtUGEQEDRZGxroN6D1TCkRV0vAGZPTsRJO8f P/8X0eEh7eH+PRsl//4vMrDl47QYkSDX8QDDsr3KBcf/J0GZRWnK+Q1/lzQ7yYHwkRt8wIL83Rd87 PWJjHKSQ==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaRq-00ANVs-Bb; Sun, 23 Apr 2023 16:12:14 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 07/40] drm/amd/display: add CRTC gamma TF to driver-private props Date: Sun, 23 Apr 2023 13:10:19 -0100 Message-Id: <20230423141051.702990-8-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763977748288177273?= X-GMAIL-MSGID: =?utf-8?q?1763977748288177273?= From: Joshua Ashton Add predefined transfer function property to DRM CRTC gamma to convert to wire encoding with or without gamma LUT. Co-developed-by: Melissa Wen Signed-off-by: Melissa Wen Signed-off-by: Joshua Ashton --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 22 ++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 4 ++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 23 +++++++++++++++++++ .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 13 +++++++++++ 4 files changed, 62 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 2abe5fe87c10..1913903cab88 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1248,6 +1248,19 @@ amdgpu_display_user_framebuffer_create(struct drm_device *dev, } #ifdef CONFIG_STEAM_DECK +static const struct drm_prop_enum_list drm_transfer_function_enum_list[] = { + { DRM_TRANSFER_FUNCTION_DEFAULT, "Default" }, + { DRM_TRANSFER_FUNCTION_SRGB, "sRGB" }, + { DRM_TRANSFER_FUNCTION_BT709, "BT.709" }, + { DRM_TRANSFER_FUNCTION_PQ, "PQ (Perceptual Quantizer)" }, + { DRM_TRANSFER_FUNCTION_LINEAR, "Linear" }, + { DRM_TRANSFER_FUNCTION_UNITY, "Unity" }, + { DRM_TRANSFER_FUNCTION_HLG, "HLG (Hybrid Log Gamma)" }, + { DRM_TRANSFER_FUNCTION_GAMMA22, "Gamma 2.2" }, + { DRM_TRANSFER_FUNCTION_GAMMA24, "Gamma 2.4" }, + { DRM_TRANSFER_FUNCTION_GAMMA26, "Gamma 2.6" }, +}; + static int amdgpu_display_create_color_properties(struct amdgpu_device *adev) { @@ -1281,6 +1294,15 @@ amdgpu_display_create_color_properties(struct amdgpu_device *adev) return -ENOMEM; adev->mode_info.lut3d_size_property = prop; + prop = drm_property_create_enum(adev_to_drm(adev), + DRM_MODE_PROP_ENUM, + "GAMMA_TF", + drm_transfer_function_enum_list, + ARRAY_SIZE(drm_transfer_function_enum_list)); + if (!prop) + return -ENOMEM; + adev->mode_info.gamma_tf_property = prop; + return 0; } #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 205fa4f5bea7..76337e18c728 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -368,6 +368,10 @@ struct amdgpu_mode_info { * LUT as supported by the driver (read-only). */ struct drm_property *lut3d_size_property; + /** + * @gamma_tf_property: Transfer function for CRTC regamma. + */ + struct drm_property *gamma_tf_property; #endif }; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 09c3e1858b56..1e90a2dd445e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -699,6 +699,23 @@ static inline void amdgpu_dm_set_mst_status(uint8_t *status, extern const struct amdgpu_ip_block_version dm_ip_block; +#ifdef CONFIG_STEAM_DECK +enum drm_transfer_function { + DRM_TRANSFER_FUNCTION_DEFAULT, + + DRM_TRANSFER_FUNCTION_SRGB, + DRM_TRANSFER_FUNCTION_BT709, + DRM_TRANSFER_FUNCTION_PQ, + DRM_TRANSFER_FUNCTION_LINEAR, + DRM_TRANSFER_FUNCTION_UNITY, + DRM_TRANSFER_FUNCTION_HLG, + DRM_TRANSFER_FUNCTION_GAMMA22, + DRM_TRANSFER_FUNCTION_GAMMA24, + DRM_TRANSFER_FUNCTION_GAMMA26, + DRM_TRANSFER_FUNCTION_MAX, +}; +#endif + struct dm_plane_state { struct drm_plane_state base; struct dc_plane_state *dc_state; @@ -751,6 +768,12 @@ struct dm_crtc_state { * &struct drm_color_lut. */ struct drm_property_blob *lut3d; + /** + * @gamma_tf: + * + * Pre-defined transfer function for converting internal FB -> wire encoding. + */ + enum drm_transfer_function gamma_tf; #endif }; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 0e1280228e6e..79324fbab1f1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -272,6 +272,7 @@ static struct drm_crtc_state *dm_crtc_duplicate_state(struct drm_crtc *crtc) #ifdef CONFIG_STEAM_DECK state->shaper_lut = cur->shaper_lut; state->lut3d = cur->lut3d; + state->gamma_tf = cur->gamma_tf; if (state->shaper_lut) drm_property_blob_get(state->shaper_lut); @@ -336,6 +337,11 @@ dm_crtc_additional_color_mgmt(struct drm_crtc *crtc) adev->mode_info.lut3d_size_property, MAX_COLOR_3DLUT_ENTRIES); } + + if(adev->dm.dc->caps.color.mpc.ogam_ram) + drm_object_attach_property(&crtc->base, + adev->mode_info.gamma_tf_property, + DRM_TRANSFER_FUNCTION_DEFAULT); } static int @@ -398,6 +404,11 @@ amdgpu_dm_atomic_crtc_set_property(struct drm_crtc *crtc, &replaced); acrtc_state->base.color_mgmt_changed |= replaced; return ret; + } else if (property == adev->mode_info.gamma_tf_property) { + if (acrtc_state->gamma_tf != val) { + acrtc_state->gamma_tf = val; + acrtc_state->base.color_mgmt_changed |= 1; + } } else { drm_dbg_atomic(crtc->dev, "[CRTC:%d:%s] unknown property [PROP:%d:%s]]\n", @@ -424,6 +435,8 @@ amdgpu_dm_atomic_crtc_get_property(struct drm_crtc *crtc, else if (property == adev->mode_info.lut3d_property) *val = (acrtc_state->lut3d) ? acrtc_state->lut3d->base.id : 0; + else if (property == adev->mode_info.gamma_tf_property) + *val = acrtc_state->gamma_tf; else return -EINVAL; From patchwork Sun Apr 23 14:10:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86730 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2221019vqo; Sun, 23 Apr 2023 07:23:07 -0700 (PDT) X-Google-Smtp-Source: AKy350YnaKOnw35cQBj1I0jJhYuduuxMKcTSOBpzN8rjFYB9QloEnv+M9IPIt1ws5QpzV+IsU+iM X-Received: by 2002:a05:6a20:a120:b0:ef:b596:2fb6 with SMTP id q32-20020a056a20a12000b000efb5962fb6mr15478941pzk.36.1682259786762; Sun, 23 Apr 2023 07:23:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682259786; cv=none; d=google.com; s=arc-20160816; b=UnWs6TNsuRkMj65CDJHCVjDvaJWOXUAY/jPymTknlip46W26eyKaMqSy3Qu0ouV8HE h56QAZIL3HOeZytI+KWuQ6csFHhlWqh2uHPkOHNq37k/l4EM4ijNOq/6/a3xgOgnyBKx IxlMj8YdYQJkukpHiRW4WQ6SlMwxTWGSGILJaBG3J4ZjsDfSgaEx7oLMWFo3gmwBSj69 8w/lWxQQR08rbgARcaLembrDGndqlQmKds+bHedSEm0TzXzUCaF5qlBlnSQfUdMuFR0Q ZMrCfjn8Z/2WNjubKyn7fLh72WzvzCEnlzZOjvPda1tBmrxqYY3R9ByOO1GsLxQAkxt6 JJxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ZF72DZB7Rgk8EtXWwwujfnKdljuruiYf02uBPV9pt/Q=; b=CPfgvs3xPDFctXdAZaOJpZ8wwBDN1QfROsMeC6pSqIu9agw3SiygWElJaMOJHU8ICk 6r4pdBI7dA5nuan3xlyZWVDjO+xGyBRfjW1ih14iD/RjE/WkHVv+b1IOs1sSHF01A6gR HD8mKtdqE382Wil3tY4Oonye54dcmJf8R9o38OT6fh4ckx2RTc9Rs8M/LLAA4+TTgecf YCdF9/1ToVYeOgp592OPV5C2C/t4cclu7fbo4EIZY5iWlipy4A088jNwfc4t4qBYlW4m CAjOr4DCJ1suKqyIyS0tbsJdOmvW5lf/NyC48qhtQ82bBnmsH8AyBp9hrmCBso67zsb+ N8Kw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=NE7h2Ttl; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id f16-20020a63f110000000b00524ba819b3csi8663867pgi.443.2023.04.23.07.22.51; Sun, 23 Apr 2023 07:23:06 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=NE7h2Ttl; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229604AbjDWONX (ORCPT + 99 others); Sun, 23 Apr 2023 10:13:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60812 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230235AbjDWONQ (ORCPT ); Sun, 23 Apr 2023 10:13:16 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BC4593596 for ; Sun, 23 Apr 2023 07:12:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=ZF72DZB7Rgk8EtXWwwujfnKdljuruiYf02uBPV9pt/Q=; b=NE7h2Ttlh5qeOufFgjOAuj/G/N Mp6FYLx78siblzVP66SdNvhoMEkWQ379KPdDVm0g22cVo3yC2oVgwcWaAOKs0kES8gdUaEdDAQkgg V6yplEEC6zaGkUnK/2AgU29axB7rlQcYjd01O06TNsIV4vq4TZT47+NuBevfCZJol5rhmHj1TWXDW GHguQtOBF2nekb6b5BIEwirgX4fRh0Zb32PiIy9cfpdenPEwYT+PTtOdHUgWzGk09qAv2wlaCq2Qh pokXGbQZnEL1lyjypEfC/ZJ/W283j3F7NOzsO/t32qIyViHQKcHjeTF1QBiZTCW/8LHsR+3Q1Vr3p sMXro7iA==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaRv-00ANVs-Ak; Sun, 23 Apr 2023 16:12:19 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 08/40] drm/drm_plane: track color mgmt changes per plane Date: Sun, 23 Apr 2023 13:10:20 -0100 Message-Id: <20230423141051.702990-9-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763977237993226404?= X-GMAIL-MSGID: =?utf-8?q?1763977237993226404?= We will add color mgmt properties to DRM planes in the text patches and we want to track when one of this properties change to define atomic commit behaviors. Using a similar approach from CRTC color props, we set a color_mgmt_changed boolean whenever a plane color prop changes. Signed-off-by: Melissa Wen --- drivers/gpu/drm/drm_atomic.c | 1 + drivers/gpu/drm/drm_atomic_state_helper.c | 1 + include/drm/drm_plane.h | 7 +++++++ 3 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index c0dc5858a723..da2429470c4f 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -724,6 +724,7 @@ static void drm_atomic_plane_print_state(struct drm_printer *p, drm_get_color_encoding_name(state->color_encoding)); drm_printf(p, "\tcolor-range=%s\n", drm_get_color_range_name(state->color_range)); + drm_printf(p, "\tcolor_mgmt_changed=%d\n", state->color_mgmt_changed); if (plane->funcs->atomic_print_state) plane->funcs->atomic_print_state(p, state); diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c index dfb57217253b..3df4c96a902e 100644 --- a/drivers/gpu/drm/drm_atomic_state_helper.c +++ b/drivers/gpu/drm/drm_atomic_state_helper.c @@ -338,6 +338,7 @@ void __drm_atomic_helper_plane_duplicate_state(struct drm_plane *plane, state->fence = NULL; state->commit = NULL; state->fb_damage_clips = NULL; + state->color_mgmt_changed = false; } EXPORT_SYMBOL(__drm_atomic_helper_plane_duplicate_state); diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index 447e664e49d5..6c97380b8c76 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -237,6 +237,13 @@ struct drm_plane_state { /** @state: backpointer to global drm_atomic_state */ struct drm_atomic_state *state; + + /** + * @color_mgmt_changed: Color management properties have changed. Used + * by the atomic helpers and drivers to steer the atomic commit control + * flow. + */ + bool color_mgmt_changed : 1; }; static inline struct drm_rect From patchwork Sun Apr 23 14:10:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86751 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2231338vqo; Sun, 23 Apr 2023 07:48:42 -0700 (PDT) X-Google-Smtp-Source: AKy350bdiz203vcJH55EieKM62QzxD4yGXzgWaCgAPITY//PwS8KsssgvS4/sw608rB2hEAJxxER X-Received: by 2002:a05:6a20:c1a7:b0:f0:929c:e8c5 with SMTP id bg39-20020a056a20c1a700b000f0929ce8c5mr12967643pzb.35.1682261321988; Sun, 23 Apr 2023 07:48:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682261321; cv=none; d=google.com; s=arc-20160816; b=BPNISWxHY6QbDoTRxEFITPC/75ucaIZSeax2ntHke0JHVHbKWQMCo+Q2EJ09WQP3BQ Ivr3nVNqzO4rxe+ykYFGwyIORrTryLWMmvlx90Ki921KVq4jfegv4lGj+mU/x8GAkn6M L6qIk5sO2CKzstydTo7hkqnRddaC8h+nuoZ63UEGoj5h9BmOyjFdCbjACv9zYqa/G006 LSGiCB2ojXCN7pK0tvaXsTxlBUGz0LjzJ+0I0pclD0vHVTVy1b+KOZP47esYrtjvg8zp rX3TQIyVk9SgSE9+dfBe2H64PQ6T3229CXasqzzmg8G/vpRxyvhjHB66ZPcX+pwHptLH drdg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=bS6ARIRzUtaQuNYcssnwhazUAE6VKWzVlbrPhB85lac=; b=ySkzTAHgAStEHCbRgveUyyth5MZcMTcLYD98OOoEIWPKX33ozyKvNFnyvIwnfNX3Ow wpN9V7BdCywHO3Wylrc0G2nbsUkFs1+fJIK+yHhpa7TKOeaZs86BcrDl8T/B8vE9p5UU PJyrfC6ez/t/sznLyXdpZb4BCv2zuZXiFo9T0SNCT0J7BXk+2GPxh2m041FCGYKnk+Eq z4KAmea7IY6OVL2J3bPiEAB0+O5QqEVQ4xlcf9s3oYs1yYp/7VCVf+73DGnDy/W7SWSn CvNBkI0TPRn7c13yJWFyAHashZrd98tUHhTOdTHNUt3E24AP3xZNV5WBSxdB3h/QEL8U yImQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=LvGgwT2a; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id f10-20020a63de0a000000b0051b4a11e026si7391596pgg.625.2023.04.23.07.48.27; Sun, 23 Apr 2023 07:48:41 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=LvGgwT2a; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230240AbjDWONV (ORCPT + 99 others); Sun, 23 Apr 2023 10:13:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60738 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230231AbjDWONP (ORCPT ); Sun, 23 Apr 2023 10:13:15 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 01FAA2D77 for ; Sun, 23 Apr 2023 07:12:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=bS6ARIRzUtaQuNYcssnwhazUAE6VKWzVlbrPhB85lac=; b=LvGgwT2aOKaiVCropiT6vlCv5G t6mr873f067uJixAtakqOAr0rinkoh4+slU7QUIS4RwxRmgC5QgXf5xUOPza0V78koaCEyGleHuH1 j8D6vxWXxhZhAVCiMX51iACPk6n2eTWw6ANiZvbi1DDueil+9x/z/Goh7xnEwcRI7KtyyU5JAl3I1 5gz6BGH8GY/9Ug2PK0EVINTW2oB6emz+Nm5M4Mkw2RGwja6gG6BYryutmeZ3UdVCLLznAYxclZ1Ql CzY26Gi6ulrom1gDv1BwTeBWhRjqNZkTCd7hkRrFlPmey/Fkf/7p52nRfMNSFSvqA9NQEi8lX8m9W +5OwixHA==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaS0-00ANVs-Mu; Sun, 23 Apr 2023 16:12:24 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 09/40] drm/amd/display: move replace blob func to dm plane Date: Sun, 23 Apr 2023 13:10:21 -0100 Message-Id: <20230423141051.702990-10-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763978847968388165?= X-GMAIL-MSGID: =?utf-8?q?1763978847968388165?= From amdgpu_dm_plane we can get it for both CRTC and plane color properties. We are adding new plane properties for AMD driver-private color mgmt. Signed-off-by: Melissa Wen --- .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 37 +------------------ .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 35 ++++++++++++++++++ .../amd/display/amdgpu_dm/amdgpu_dm_plane.h | 7 ++++ 3 files changed, 44 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 79324fbab1f1..27d7a8b18013 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -344,39 +344,6 @@ dm_crtc_additional_color_mgmt(struct drm_crtc *crtc) DRM_TRANSFER_FUNCTION_DEFAULT); } -static int -atomic_replace_property_blob_from_id(struct drm_device *dev, - struct drm_property_blob **blob, - uint64_t blob_id, - ssize_t expected_size, - ssize_t expected_elem_size, - bool *replaced) -{ - struct drm_property_blob *new_blob = NULL; - - if (blob_id != 0) { - new_blob = drm_property_lookup_blob(dev, blob_id); - if (new_blob == NULL) - return -EINVAL; - - if (expected_size > 0 && - new_blob->length != expected_size) { - drm_property_blob_put(new_blob); - return -EINVAL; - } - if (expected_elem_size > 0 && - new_blob->length % expected_elem_size != 0) { - drm_property_blob_put(new_blob); - return -EINVAL; - } - } - - *replaced |= drm_property_replace_blob(blob, new_blob); - drm_property_blob_put(new_blob); - - return 0; -} - static int amdgpu_dm_atomic_crtc_set_property(struct drm_crtc *crtc, struct drm_crtc_state *state, @@ -389,7 +356,7 @@ amdgpu_dm_atomic_crtc_set_property(struct drm_crtc *crtc, int ret; if (property == adev->mode_info.shaper_lut_property) { - ret = atomic_replace_property_blob_from_id(crtc->dev, + ret = amdgpu_dm_replace_property_blob_from_id(crtc->dev, &acrtc_state->shaper_lut, val, -1, sizeof(struct drm_color_lut), @@ -397,7 +364,7 @@ amdgpu_dm_atomic_crtc_set_property(struct drm_crtc *crtc, acrtc_state->base.color_mgmt_changed |= replaced; return ret; } else if (property == adev->mode_info.lut3d_property) { - ret = atomic_replace_property_blob_from_id(crtc->dev, + ret = amdgpu_dm_replace_property_blob_from_id(crtc->dev, &acrtc_state->lut3d, val, -1, sizeof(struct drm_color_lut), diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 322668973747..4e5498153be2 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1411,6 +1411,41 @@ static void dm_drm_plane_destroy_state(struct drm_plane *plane, drm_atomic_helper_plane_destroy_state(plane, state); } +#ifdef CONFIG_STEAM_DECK +int +amdgpu_dm_replace_property_blob_from_id(struct drm_device *dev, + struct drm_property_blob **blob, + uint64_t blob_id, + ssize_t expected_size, + ssize_t expected_elem_size, + bool *replaced) +{ + struct drm_property_blob *new_blob = NULL; + + if (blob_id != 0) { + new_blob = drm_property_lookup_blob(dev, blob_id); + if (new_blob == NULL) + return -EINVAL; + + if (expected_size > 0 && + new_blob->length != expected_size) { + drm_property_blob_put(new_blob); + return -EINVAL; + } + if (expected_elem_size > 0 && + new_blob->length % expected_elem_size != 0) { + drm_property_blob_put(new_blob); + return -EINVAL; + } + } + + *replaced |= drm_property_replace_blob(blob, new_blob); + drm_property_blob_put(new_blob); + + return 0; +} +#endif + static const struct drm_plane_funcs dm_plane_funcs = { .update_plane = drm_atomic_helper_update_plane, .disable_plane = drm_atomic_helper_disable_plane, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h index 930f1572f898..1b05ac4c15f6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h @@ -51,6 +51,13 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, bool tmz_surface, bool force_disable_dcc); +int amdgpu_dm_replace_property_blob_from_id(struct drm_device *dev, + struct drm_property_blob **blob, + uint64_t blob_id, + ssize_t expected_size, + ssize_t expected_elem_size, + bool *replaced); + int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, struct drm_plane *plane, unsigned long possible_crtcs, From patchwork Sun Apr 23 14:10:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86740 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2223025vqo; Sun, 23 Apr 2023 07:28:32 -0700 (PDT) X-Google-Smtp-Source: AKy350Z1utXIZwQHlCmjnFnK5CV3IzRqL5fkmwjJ+4GVlQ4QptFkJF8xAg8g01iZdVy7rj0/2CxR X-Received: by 2002:a17:902:d591:b0:1a6:b2e3:5dc4 with SMTP id k17-20020a170902d59100b001a6b2e35dc4mr10288436plh.14.1682260112486; Sun, 23 Apr 2023 07:28:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682260112; cv=none; d=google.com; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id e5-20020a17090301c500b0019c354055d0si9572096plh.304.2023.04.23.07.28.17; Sun, 23 Apr 2023 07:28:32 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b="gZIKjW/5"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230009AbjDWONb (ORCPT + 99 others); Sun, 23 Apr 2023 10:13:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229749AbjDWONX (ORCPT ); Sun, 23 Apr 2023 10:13:23 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C90B91FDF for ; Sun, 23 Apr 2023 07:12:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=AAZ5sTWcL6d1F4he+h8JfjtWQIRJ5weYPHqgnNEExCI=; b=gZIKjW/5GVEjC1IrACr56Fi8tZ ACTVa/+kOaJqEB5Jev/ClLObH/ZmOOTJ6QtyJAaeDWG/A9uc1EI80NLMoTgC53sorKOtT7uBDGvAd zixe1i8FPGQ5J8WZVUoRescfFFZm6H12wRhwtqOme9GAvUw6Cp2Yn6hbfAKqOXedP2yC6b+P39IVx kjb2ljiKk+Lx6F1FY0dCIp1A8wbcX1dfj7YM5+6/KGbmfRGUoKZd7eLxyL396LN637nE5sOKvsbJn yQMvdGKIA+hUOCpzX7H9aB4rQ2r4XsaU+91m3a65dQLWM3mpLeuiQu2esYmvI4R8JhsIQW4J1LCXT CdWOkNGA==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaS3-00ANVs-Ka; Sun, 23 Apr 2023 16:12:27 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 10/40] drm/amd/display: add plane degamma LUT driver-private props Date: Sun, 23 Apr 2023 13:10:22 -0100 Message-Id: <20230423141051.702990-11-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763977579823801569?= X-GMAIL-MSGID: =?utf-8?q?1763977579823801569?= From: Joshua Ashton Create driver-private properties (not DRM KMS generic) for plane degamma LUT (user-blob and its size). Co-developed-by: Melissa Wen Signed-off-by: Melissa Wen Signed-off-by: Joshua Ashton --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 14 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 10 +++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 11 +++ .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 78 ++++++++++++++++++- 4 files changed, 111 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 1913903cab88..996c9c3fd471 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1303,6 +1303,20 @@ amdgpu_display_create_color_properties(struct amdgpu_device *adev) return -ENOMEM; adev->mode_info.gamma_tf_property = prop; + prop = drm_property_create(adev_to_drm(adev), + DRM_MODE_PROP_BLOB, + "AMD_PLANE_DEGAMMA_LUT", 0); + if (!prop) + return -ENOMEM; + adev->mode_info.plane_degamma_lut_property = prop; + + prop = drm_property_create_range(adev_to_drm(adev), + DRM_MODE_PROP_IMMUTABLE, + "AMD_PLANE_DEGAMMA_LUT_SIZE", 0, UINT_MAX); + if (!prop) + return -ENOMEM; + adev->mode_info.plane_degamma_lut_size_property = prop; + return 0; } #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 76337e18c728..d4e609a8b67e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -372,6 +372,16 @@ struct amdgpu_mode_info { * @gamma_tf_property: Transfer function for CRTC regamma. */ struct drm_property *gamma_tf_property; + /** + * @plane_degamma_lut_property: Plane property to set a degamma LUT to + * convert color space before blending. + */ + struct drm_property *plane_degamma_lut_property; + /** + * @plane_degamma_lut_size_property: Plane property to define the max + * size of degamma LUT as supported by the driver (read-only). + */ + struct drm_property *plane_degamma_lut_size_property; #endif }; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 1e90a2dd445e..b1d0c65d821d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -719,6 +719,17 @@ enum drm_transfer_function { struct dm_plane_state { struct drm_plane_state base; struct dc_plane_state *dc_state; + +#ifdef CONFIG_STEAM_DECK + /* Plane color mgmt */ + /** + * @degamma_lut: + * + * LUT for converting plane pixel data before going into plane merger. + * The blob (if not NULL) is an array of &struct drm_color_lut. + */ + struct drm_property_blob *degamma_lut; +#endif }; struct dm_crtc_state { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 4e5498153be2..7b9d62c70b30 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1337,7 +1337,10 @@ dm_drm_plane_duplicate_state(struct drm_plane *plane) dm_plane_state->dc_state = old_dm_plane_state->dc_state; dc_plane_state_retain(dm_plane_state->dc_state); } - +#ifdef CONFIG_STEAM_DECK + if (dm_plane_state->degamma_lut) + drm_property_blob_get(dm_plane_state->degamma_lut); +#endif return &dm_plane_state->base; } @@ -1404,7 +1407,9 @@ static void dm_drm_plane_destroy_state(struct drm_plane *plane, struct drm_plane_state *state) { struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); - +#ifdef CONFIG_STEAM_DECK + drm_property_blob_put(dm_plane_state->degamma_lut); +#endif if (dm_plane_state->dc_state) dc_plane_state_release(dm_plane_state->dc_state); @@ -1444,6 +1449,68 @@ amdgpu_dm_replace_property_blob_from_id(struct drm_device *dev, return 0; } + +static void +dm_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm, + struct drm_plane *plane) +{ + if (dm->dc->caps.color.dpp.dgam_ram || dm->dc->caps.color.dpp.gamma_corr ) { + drm_object_attach_property(&plane->base, + dm->adev->mode_info.plane_degamma_lut_property, 0); + drm_object_attach_property(&plane->base, + dm->adev->mode_info.plane_degamma_lut_size_property, + MAX_COLOR_LUT_ENTRIES); + } +} + +static int +dm_atomic_plane_set_property(struct drm_plane *plane, + struct drm_plane_state *state, + struct drm_property *property, uint64_t val) +{ + struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); + struct amdgpu_device *adev = drm_to_adev(plane->dev); + bool replaced = false; + int ret; + + if (property == adev->mode_info.plane_degamma_lut_property) { + ret = amdgpu_dm_replace_property_blob_from_id(plane->dev, + &dm_plane_state->degamma_lut, + val, + -1, sizeof(struct drm_color_lut), + &replaced); + dm_plane_state->base.color_mgmt_changed |= replaced; + return ret; + } else { + drm_dbg_atomic(plane->dev, + "[PLANE:%d:%s] unknown property [PROP:%d:%s]]\n", + plane->base.id, plane->name, + property->base.id, property->name); + return -EINVAL; + } + + return 0; +} + +static int +dm_atomic_plane_get_property(struct drm_plane *plane, + const struct drm_plane_state *state, + struct drm_property *property, + uint64_t *val) + +{ + struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); + struct amdgpu_device *adev = drm_to_adev(plane->dev); + + if (property == adev->mode_info.plane_degamma_lut_property) { + *val = (dm_plane_state->degamma_lut) ? + dm_plane_state->degamma_lut->base.id : 0; + } else { + return -EINVAL; + } + + return 0; +} #endif static const struct drm_plane_funcs dm_plane_funcs = { @@ -1454,6 +1521,10 @@ static const struct drm_plane_funcs dm_plane_funcs = { .atomic_duplicate_state = dm_drm_plane_duplicate_state, .atomic_destroy_state = dm_drm_plane_destroy_state, .format_mod_supported = dm_plane_format_mod_supported, +#ifdef CONFIG_STEAM_DECK + .atomic_set_property = dm_atomic_plane_set_property, + .atomic_get_property = dm_atomic_plane_get_property, +#endif }; int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, @@ -1524,6 +1595,9 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, drm_plane_helper_add(plane, &dm_plane_helper_funcs); +#ifdef CONFIG_STEAM_DECK + dm_plane_attach_color_mgmt_properties(dm, plane); +#endif /* Create (reset) the plane state */ if (plane->funcs->reset) plane->funcs->reset(plane); From patchwork Sun Apr 23 14:10:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86726 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2218708vqo; Sun, 23 Apr 2023 07:17:14 -0700 (PDT) X-Google-Smtp-Source: AKy350YydSlmg6CabZafT0Wcnon7p7TwvVknyiC4tNEaWP6RRXqrb9tWM3w2B84Gq/ViffGuGZDy X-Received: by 2002:a17:90a:4902:b0:240:883:8ff8 with SMTP id c2-20020a17090a490200b0024008838ff8mr11431857pjh.3.1682259434634; Sun, 23 Apr 2023 07:17:14 -0700 (PDT) ARC-Seal: i=1; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id b7-20020a656687000000b005211941267asi2418319pgw.153.2023.04.23.07.16.58; Sun, 23 Apr 2023 07:17:14 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=GIDKrGFW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229749AbjDWONc (ORCPT + 99 others); Sun, 23 Apr 2023 10:13:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32856 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230244AbjDWON3 (ORCPT ); Sun, 23 Apr 2023 10:13:29 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 255E43590 for ; Sun, 23 Apr 2023 07:12:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=iBiuc4P8VmKXEvqKrXrkHjYNh/Y8fk7rr++PQPaLmzc=; b=GIDKrGFWjV2LVJfKwgRPiiS6x3 gbHBG2Bm7wGkCLVsMtXx6H7ibDyL641Bk1ZcsxALGNewCyVQaxRZ6hQNqL0Gh8YXD+H/WFlwJB90M XRD2Urv0bhq6OoijHYQ+OsuOl3++mf9n6tFkjJY2anUTL7BzKWdz5jS+Zj1sQwV4UhJZJxvuRtnOF Hy56sb0sKVy1yyELsMyxudELZXIXDYYTEuBXTTeqfFNTuc4kUYZ7ElYd95Mst5lNJoUDgjIxCP2Ay kQkpat7fm7VidyfjwWBLCyLCvNz7qtfLD89aiI7C6BN7wUbaPq5ZGe8npr6QwPWyk1DORMdX5ZFqG 6BY6dGCQ==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaS7-00ANVs-22; Sun, 23 Apr 2023 16:12:31 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , linux-kernel@vger.kernel.org Subject: [RFC PATCH 11/40] drm/amd/display: add plane degamma TF driver-private property Date: Sun, 23 Apr 2023 13:10:23 -0100 Message-Id: <20230423141051.702990-12-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763976868995112407?= X-GMAIL-MSGID: =?utf-8?q?1763976868995112407?= From: Joshua Ashton Allow userspace to tell the kernel driver the input space and, therefore, uses correct predefined transfer function (TF) to delinearize content with or without LUT (using hardcoded curve caps). Signed-off-by: Joshua Ashton --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 9 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 5 ++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 7 +++++ .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 28 +++++++++++++++++++ 4 files changed, 49 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 996c9c3fd471..24595906dab1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1317,6 +1317,15 @@ amdgpu_display_create_color_properties(struct amdgpu_device *adev) return -ENOMEM; adev->mode_info.plane_degamma_lut_size_property = prop; + prop = drm_property_create_enum(adev_to_drm(adev), + DRM_MODE_PROP_ENUM, + "AMD_PLANE_DEGAMMA_TF", + drm_transfer_function_enum_list, + ARRAY_SIZE(drm_transfer_function_enum_list)); + if (!prop) + return -ENOMEM; + adev->mode_info.plane_degamma_tf_property = prop; + return 0; } #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index d4e609a8b67e..ab9ce6f26c90 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -382,6 +382,11 @@ struct amdgpu_mode_info { * size of degamma LUT as supported by the driver (read-only). */ struct drm_property *plane_degamma_lut_size_property; + /** + * @plane_degamma_tf_property: Predefined transfer function to + * linearize content with or without LUT. + */ + struct drm_property *plane_degamma_tf_property; #endif }; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index b1d0c65d821d..005632c1c9ec 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -729,6 +729,13 @@ struct dm_plane_state { * The blob (if not NULL) is an array of &struct drm_color_lut. */ struct drm_property_blob *degamma_lut; + /** + * @degamma_tf: + * + * Predefined transfer function to tell DC driver the input space to + * linearize. + */ + enum drm_transfer_function degamma_tf; #endif }; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 7b9d62c70b30..5b458cc0781c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1319,6 +1319,11 @@ static void dm_drm_plane_reset(struct drm_plane *plane) if (amdgpu_state) __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base); + +#ifdef CONFIG_STEAM_DECK + if (amdgpu_state) + amdgpu_state->degamma_tf = DRM_TRANSFER_FUNCTION_DEFAULT; +#endif } static struct drm_plane_state * @@ -1450,6 +1455,19 @@ amdgpu_dm_replace_property_blob_from_id(struct drm_device *dev, return 0; } +static const struct drm_prop_enum_list drm_transfer_function_enum_list[] = { + { DRM_TRANSFER_FUNCTION_DEFAULT, "Default" }, + { DRM_TRANSFER_FUNCTION_SRGB, "sRGB" }, + { DRM_TRANSFER_FUNCTION_BT709, "BT.709" }, + { DRM_TRANSFER_FUNCTION_PQ, "PQ (Perceptual Quantizer)" }, + { DRM_TRANSFER_FUNCTION_LINEAR, "Linear" }, + { DRM_TRANSFER_FUNCTION_UNITY, "Unity" }, + { DRM_TRANSFER_FUNCTION_HLG, "HLG (Hybrid Log Gamma)" }, + { DRM_TRANSFER_FUNCTION_GAMMA22, "Gamma 2.2" }, + { DRM_TRANSFER_FUNCTION_GAMMA24, "Gamma 2.4" }, + { DRM_TRANSFER_FUNCTION_GAMMA26, "Gamma 2.6" }, +}; + static void dm_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm, struct drm_plane *plane) @@ -1460,6 +1478,9 @@ dm_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm, drm_object_attach_property(&plane->base, dm->adev->mode_info.plane_degamma_lut_size_property, MAX_COLOR_LUT_ENTRIES); + drm_object_attach_property(&plane->base, + dm->adev->mode_info.plane_degamma_tf_property, + DRM_TRANSFER_FUNCTION_DEFAULT); } } @@ -1481,6 +1502,11 @@ dm_atomic_plane_set_property(struct drm_plane *plane, &replaced); dm_plane_state->base.color_mgmt_changed |= replaced; return ret; + } else if (property == adev->mode_info.plane_degamma_tf_property) { + if (dm_plane_state->degamma_tf != val) { + dm_plane_state->degamma_tf = val; + dm_plane_state->base.color_mgmt_changed = 1; + } } else { drm_dbg_atomic(plane->dev, "[PLANE:%d:%s] unknown property [PROP:%d:%s]]\n", @@ -1505,6 +1531,8 @@ dm_atomic_plane_get_property(struct drm_plane *plane, if (property == adev->mode_info.plane_degamma_lut_property) { *val = (dm_plane_state->degamma_lut) ? dm_plane_state->degamma_lut->base.id : 0; + } else if (property == adev->mode_info.plane_degamma_tf_property) { + *val = dm_plane_state->degamma_tf; } else { return -EINVAL; } From patchwork Sun Apr 23 14:10:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86753 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2231396vqo; Sun, 23 Apr 2023 07:48:55 -0700 (PDT) X-Google-Smtp-Source: AKy350a20PUuoRyLtQBgIrEKj0jJy3rvSkaHElDeV2Cy+etHRjUkPJ8r07+9XiHu3PvgK0tCryxA X-Received: by 2002:a17:90b:1bc1:b0:247:14ac:4d3a with SMTP id oa1-20020a17090b1bc100b0024714ac4d3amr12487135pjb.20.1682261334912; Sun, 23 Apr 2023 07:48:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682261334; cv=none; d=google.com; s=arc-20160816; b=cUIAKAUGfO0U6duyASX0d/+LPHzqIuoF21lrJfLNyucgaKj4zjtH5JgFAKt89+wlIn VzH0mrB623GryF+W2HkKOvwwITdO4m/wtfnNlp7llvc614YDii+lXYw3YE4o3tY+rcN8 OcBiKTeYFLHXdA7a07w2eo5DlGpzpPYcUbJ5NGYSPWbw+AYLt+XyxUif6Ar0unJgrgzS TiUO6fYjq3eXeUkJQBMQD8mwmOypnil5xCkk6T6iIt6VmqmSGeaAsMQdvVuPuSQ58y+A n9Q1vAbSmFeVUNviu+wEootKtcyAP4O/tfNJr3ActO323X8uQcZAvuVsYB3hjTOYgjtJ AGhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=mNxdNED6L3HES4VBefAtsG63OTHIZrslESDcQiiim+M=; b=BkSbTkhAqIlx8/0FN7d8HIh3hHkv27cLEVo0OzwMJXgQyE7t+mNI+a3Em5stVyg2P4 cOjPOSTHFGXWDnn9N927Jhs224NGIXsReqFteBAS8U7zU98Jcpdf3KKMjmJiUcp4WN0S 6GDgELcnpXE2Vq34i4P5B+ddbuwLEQGv6R/ZGd0VQwNOyuQ+rA8QDQKi3ITIExrxDciM sDPWBfc7zT7KDKbf/815nwllRSb7vnXy3fMcK8pr4pfzogpIVAfUJc9U4OaZ8WP+2lBL HbIrU7jIxgrmdkkE2+/oNs0PuPlbLTkiJPL8WG+fZSnWQVhCOZDT3i3FLxE+oLXuMqtV oSKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=gmOQ3q2n; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id h16-20020a17090acf1000b0024715c041c3si11694870pju.137.2023.04.23.07.48.40; Sun, 23 Apr 2023 07:48:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=gmOQ3q2n; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229493AbjDWOOE (ORCPT + 99 others); Sun, 23 Apr 2023 10:14:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33454 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229619AbjDWOOD (ORCPT ); Sun, 23 Apr 2023 10:14:03 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D355330FE for ; Sun, 23 Apr 2023 07:13:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=mNxdNED6L3HES4VBefAtsG63OTHIZrslESDcQiiim+M=; b=gmOQ3q2nfwj0Oz9By8BoODLpBY nlWFvAuX/nCjrsoRwqBnOvu2066ZTKBbV1SErilbIPPRLrxBtV/KWPbid0GMIyO0efOPS2r9whq0A zJStCM0vdyqfTIqe/n3FV9tKSV0Za4BhoTjefXnGciV3+7B4cIVtyUf4ZbL3mD5bi+9yctwQHIEfJ n9rskomfSRZN28dlPi6qFZPvlKXDWiYCorGwQblxgtaBjG22jhYjdJ3T/Y83k66Nf0wQ6tDd5VRv+ /WmFasbZZ6REAydvn3Edv4Yoeoc1HzxVBaY/iWeNkA2aCk9I39lVyGQ7bW1YmWLYStAvpVPKJJy65 k3LsJHwA==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaSA-00ANVs-GB; Sun, 23 Apr 2023 16:12:34 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 12/40] drm/amd/display: add plane HDR multiplier driver-private property Date: Sun, 23 Apr 2023 13:10:24 -0100 Message-Id: <20230423141051.702990-13-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763978861458876632?= X-GMAIL-MSGID: =?utf-8?q?1763978861458876632?= From: Joshua Ashton Multiplier to 'gain' the plane. When PQ is decoded using the fixed func transfer function to the internal FP16 fb, 1.0 -> 80 nits (on AMD at least) When sRGB is decoded, 1.0 -> 1.0. Therefore, 1.0 multiplier = 80 nits for SDR content. So if you want, 203 nits for SDR content, pass in (203.0 / 80.0). Co-developed-by: Melissa Wen Signed-off-by: Melissa Wen Signed-off-by: Joshua Ashton --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 6 +++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 4 +++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 12 +++++++++ .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 25 ++++++++++++++----- 4 files changed, 41 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 24595906dab1..dd658f162f6f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1326,6 +1326,12 @@ amdgpu_display_create_color_properties(struct amdgpu_device *adev) return -ENOMEM; adev->mode_info.plane_degamma_tf_property = prop; + prop = drm_property_create_range(adev_to_drm(adev), + 0, "AMD_PLANE_HDR_MULT", 0, UINT_MAX); + if (!prop) + return -ENOMEM; + adev->mode_info.plane_hdr_mult_property = prop; + return 0; } #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index ab9ce6f26c90..65a9d62ffbe4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -387,6 +387,10 @@ struct amdgpu_mode_info { * linearize content with or without LUT. */ struct drm_property *plane_degamma_tf_property; + /** + * @plane_hdr_mult_property: + */ + struct drm_property *plane_hdr_mult_property; #endif }; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 005632c1c9ec..bb7307b9cfd5 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -51,6 +51,7 @@ #define AMDGPU_DMUB_NOTIFICATION_MAX 5 +#define AMDGPU_HDR_MULT_DEFAULT (0x100000000LL) /* #include "include/amdgpu_dal_power_if.h" #include "amdgpu_dm_irq.h" @@ -736,6 +737,17 @@ struct dm_plane_state { * linearize. */ enum drm_transfer_function degamma_tf; + /** + * @hdr_mult: + * + * Multiplier to 'gain' the plane. When PQ is decoded using the fixed + * func transfer function to the internal FP16 fb, 1.0 -> 80 nits (on + * AMD at least). When sRGB is decoded, 1.0 -> 1.0, obviously. + * Therefore, 1.0 multiplier = 80 nits for SDR content. So if you + * want, 203 nits for SDR content, pass in (203.0 / 80.0). Format is + * S31.32 sign-magnitude. + */ + __u64 hdr_mult; #endif }; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 5b458cc0781c..57169dae8b3d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1321,8 +1321,10 @@ static void dm_drm_plane_reset(struct drm_plane *plane) __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base); #ifdef CONFIG_STEAM_DECK - if (amdgpu_state) + if (amdgpu_state) { amdgpu_state->degamma_tf = DRM_TRANSFER_FUNCTION_DEFAULT; + amdgpu_state->hdr_mult = AMDGPU_HDR_MULT_DEFAULT; + } #endif } @@ -1424,11 +1426,11 @@ static void dm_drm_plane_destroy_state(struct drm_plane *plane, #ifdef CONFIG_STEAM_DECK int amdgpu_dm_replace_property_blob_from_id(struct drm_device *dev, - struct drm_property_blob **blob, - uint64_t blob_id, - ssize_t expected_size, - ssize_t expected_elem_size, - bool *replaced) + struct drm_property_blob **blob, + uint64_t blob_id, + ssize_t expected_size, + ssize_t expected_elem_size, + bool *replaced) { struct drm_property_blob *new_blob = NULL; @@ -1482,6 +1484,10 @@ dm_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm, dm->adev->mode_info.plane_degamma_tf_property, DRM_TRANSFER_FUNCTION_DEFAULT); } + /* HDR MULT is always available */ + drm_object_attach_property(&plane->base, + dm->adev->mode_info.plane_hdr_mult_property, + AMDGPU_HDR_MULT_DEFAULT); } static int @@ -1507,6 +1513,11 @@ dm_atomic_plane_set_property(struct drm_plane *plane, dm_plane_state->degamma_tf = val; dm_plane_state->base.color_mgmt_changed = 1; } + } else if (property == adev->mode_info.plane_hdr_mult_property) { + if (dm_plane_state->hdr_mult != val) { + dm_plane_state->hdr_mult = val; + dm_plane_state->base.color_mgmt_changed = 1; + } } else { drm_dbg_atomic(plane->dev, "[PLANE:%d:%s] unknown property [PROP:%d:%s]]\n", @@ -1533,6 +1544,8 @@ dm_atomic_plane_get_property(struct drm_plane *plane, dm_plane_state->degamma_lut->base.id : 0; } else if (property == adev->mode_info.plane_degamma_tf_property) { *val = dm_plane_state->degamma_tf; + } else if (property == adev->mode_info.plane_hdr_mult_property) { + *val = dm_plane_state->hdr_mult; } else { return -EINVAL; } From patchwork Sun Apr 23 14:10:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86763 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2241815vqo; Sun, 23 Apr 2023 08:10:14 -0700 (PDT) X-Google-Smtp-Source: AKy350aJFqrQKj++GWpbzHlyF7Feh+DIttsDjTHWEpsmskGvINSvUeZegaxzzY14yY+5bVtvTLz/ X-Received: by 2002:a17:90a:408f:b0:246:b973:de35 with SMTP id l15-20020a17090a408f00b00246b973de35mr11504031pjg.4.1682262614686; Sun, 23 Apr 2023 08:10:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682262614; cv=none; d=google.com; s=arc-20160816; b=NC/4avDMjL9pm/2bxti+5ad7bcfn9mYAZ8LEhuB1fI/PolvgBlPJLkV1+rTH1SzK3P 2Pr22edyFiEdAcmgVj4n9tuuMKMZkLa3kgdejwK3qrRjdXS03KmSI2pEoThLkkVL4puU nxu6QTe4heydOWkKjKmmKYGHQt6I4pwU7vAUkKh93urJlwmdgs/OL4X6F2g2Jp2G9p10 4bo/tkrsF648lgKgb4l1u5dxUQ7m9wLi4JvlUke48LEP2c87OqcHdr9JGjAC9VP/dAZr +8v9AXtIBDPcvjKgAhg+E6KEQcP2DrZBpliMM3stjNnTGzAMMa9U4Kc7cmKOtAuWkGQ2 Rwfg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=XleRtpzB51Ir3Pboj9ghwngNAd/+A1lioslQSwoJ2AI=; b=bKBIcDZp/nFA3nQtkTmiVLnudIXXFcoi6v5Ms9m8ljFdIOxITyNtpeRb5mq+khGN1k c7JiuCGkeoYPDa99Rx1iwjL4x4YPbRNCYLsppoaUFbTNxD/hOcOQJt+cRhErRX5qKtj4 JRU1lwXJ7LYFMZ3IienkXdXG/TsITJzWFSD/QLZHcl17pBt7WgoLxsy1Xec2q/D3Mk2t yYGAC9bYZQFGnu97bYo06t3B6Maj4BAr9SIxiqE11U1ZlW7yjq585QjJyRfYb9VH3wDg 4PhpQ/+KYCdhmiFArjAI9kr3QqjQdKcMYw020yySPItCywI1U8ayd1na5GFhbG1ezhbA YbSQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=nB3+YRio; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id y3-20020a17090a154300b002340e454213si8840388pja.190.2023.04.23.08.10.00; Sun, 23 Apr 2023 08:10:14 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=nB3+YRio; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230419AbjDWOto (ORCPT + 99 others); Sun, 23 Apr 2023 10:49:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56032 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230239AbjDWOtn (ORCPT ); Sun, 23 Apr 2023 10:49:43 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 180221BE5 for ; Sun, 23 Apr 2023 07:49:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=XleRtpzB51Ir3Pboj9ghwngNAd/+A1lioslQSwoJ2AI=; b=nB3+YRio3j5L9kqpSuTn+k+r52 h88OqMdUI9lBq+LKN8jeTUo+3ZE5NDSNgAUJIK6BsePJbE8DCj4yQ29mvmXCw6JfdVH+es5zHRrV1 S9+k9CgCO9OOtW0XDhjT2Gw8U6ILT0rpTDrdyDsi00eaHo+maBrJiQoIk+U0pIYBkrajxBpEWpVGY +DZXDkAA8EnEckKEaVfjt/N6kgdpSdepGCl3U/m5BUWNH4p32u3u4O/gBilOnIn5lNRJR0DC7uc/8 j7G0jjng7h/Kq8CAQ1lcan7ue7ieW0xRZosJkAbZKMeBbTtJRru6NRL6w6yWtR5xD6ngvycvpg/P1 whC++FNw==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaSF-00ANVs-BW; Sun, 23 Apr 2023 16:12:39 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 13/40] drm/amd/display: add plane 3D LUT driver-private properties Date: Sun, 23 Apr 2023 13:10:25 -0100 Message-Id: <20230423141051.702990-14-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763980203388858883?= X-GMAIL-MSGID: =?utf-8?q?1763980203388858883?= Add 3D LUT property for plane gamma correction using a 3D lookup table. 3D LUT is more effective when applying in non-linear space, therefore, userpace may need one 1D LUT (shaper) before it to delinearize content and another 1D LUT after 3D LUT (blend) to linearize content again for blending. The next patches add these 1D LUTs to the plane color mgmt pipeline. Signed-off-by: Melissa Wen --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 14 +++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 10 ++++++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 5 ++++ .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 24 +++++++++++++++++++ 4 files changed, 53 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index dd658f162f6f..8d4726978c6e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1332,6 +1332,20 @@ amdgpu_display_create_color_properties(struct amdgpu_device *adev) return -ENOMEM; adev->mode_info.plane_hdr_mult_property = prop; + prop = drm_property_create(adev_to_drm(adev), + DRM_MODE_PROP_BLOB, + "AMD_PLANE_LUT3D", 0); + if (!prop) + return -ENOMEM; + adev->mode_info.plane_lut3d_property = prop; + + prop = drm_property_create_range(adev_to_drm(adev), + DRM_MODE_PROP_IMMUTABLE, + "AMD_PLANE_LUT3D_SIZE", 0, UINT_MAX); + if (!prop) + return -ENOMEM; + adev->mode_info.plane_lut3d_size_property = prop; + return 0; } #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 65a9d62ffbe4..9d9dac26edfc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -391,6 +391,16 @@ struct amdgpu_mode_info { * @plane_hdr_mult_property: */ struct drm_property *plane_hdr_mult_property; + /** + * @plane_lut3d_property: Plane property for gamma correction using a + * 3D LUT (pre-blending). + */ + struct drm_property *plane_lut3d_property; + /** + * @plane_degamma_lut_size_property: Plane property to define the max + * size of 3D LUT as supported by the driver (read-only). + */ + struct drm_property *plane_lut3d_size_property; #endif }; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index bb7307b9cfd5..b0ba0279dc25 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -748,6 +748,11 @@ struct dm_plane_state { * S31.32 sign-magnitude. */ __u64 hdr_mult; + /** + * @lut3d: 3D lookup table blob. The blob (if not NULL) is an array of + * &struct drm_color_lut. + */ + struct drm_property_blob *lut3d; #endif }; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 57169dae8b3d..0e418e161b0b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1347,7 +1347,10 @@ dm_drm_plane_duplicate_state(struct drm_plane *plane) #ifdef CONFIG_STEAM_DECK if (dm_plane_state->degamma_lut) drm_property_blob_get(dm_plane_state->degamma_lut); + if (dm_plane_state->lut3d) + drm_property_blob_get(dm_plane_state->lut3d); #endif + return &dm_plane_state->base; } @@ -1416,7 +1419,9 @@ static void dm_drm_plane_destroy_state(struct drm_plane *plane, struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); #ifdef CONFIG_STEAM_DECK drm_property_blob_put(dm_plane_state->degamma_lut); + drm_property_blob_put(dm_plane_state->lut3d); #endif + if (dm_plane_state->dc_state) dc_plane_state_release(dm_plane_state->dc_state); @@ -1488,6 +1493,14 @@ dm_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm, drm_object_attach_property(&plane->base, dm->adev->mode_info.plane_hdr_mult_property, AMDGPU_HDR_MULT_DEFAULT); + + if (dm->dc->caps.color.dpp.hw_3d_lut) { + drm_object_attach_property(&plane->base, + dm->adev->mode_info.plane_lut3d_property, 0); + drm_object_attach_property(&plane->base, + dm->adev->mode_info.plane_lut3d_size_property, + MAX_COLOR_3DLUT_ENTRIES); + } } static int @@ -1518,6 +1531,14 @@ dm_atomic_plane_set_property(struct drm_plane *plane, dm_plane_state->hdr_mult = val; dm_plane_state->base.color_mgmt_changed = 1; } + } else if (property == adev->mode_info.plane_lut3d_property) { + ret = amdgpu_dm_replace_property_blob_from_id(plane->dev, + &dm_plane_state->lut3d, + val, + -1, sizeof(struct drm_color_lut), + &replaced); + dm_plane_state->base.color_mgmt_changed |= replaced; + return ret; } else { drm_dbg_atomic(plane->dev, "[PLANE:%d:%s] unknown property [PROP:%d:%s]]\n", @@ -1546,6 +1567,9 @@ dm_atomic_plane_get_property(struct drm_plane *plane, *val = dm_plane_state->degamma_tf; } else if (property == adev->mode_info.plane_hdr_mult_property) { *val = dm_plane_state->hdr_mult; + } else if (property == adev->mode_info.plane_lut3d_property) { + *val = (dm_plane_state->lut3d) ? + dm_plane_state->lut3d->base.id : 0; } else { return -EINVAL; } From patchwork Sun Apr 23 14:10:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86775 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2253478vqo; Sun, 23 Apr 2023 08:38:09 -0700 (PDT) X-Google-Smtp-Source: AKy350bdRbZ1nC+U+VXgMyJg/lE9tPARurT7PlIFGmoank2Bos4D6Ag8Xpk5eT6POgUb9x2HSYIy X-Received: by 2002:a17:902:d591:b0:1a6:b2e3:5dc4 with SMTP id k17-20020a170902d59100b001a6b2e35dc4mr10465873plh.14.1682264289483; Sun, 23 Apr 2023 08:38:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682264289; cv=none; d=google.com; s=arc-20160816; b=vEP4mmOntq0BJJPblLYkuTGx0ro6QB2pXwFlpYOAz/+ItNZWUfpO0WQlTd06CZ4MH/ bieBu7iGwN+BYd3Oa3QGN9tEr9rRWaSB1P5ohgkInlZ5ft9PvRAFeo1fc0SgvhjecIF/ IRdt9L23KjDMY5OmxBlmr7m53XC+iPitphkrdNjI8NZrqkC0174AcIxP0+l+Hbiw35pq yW2iIAeERwcw4fyCfWNNz7pEiaYoIGFJXGyv2CoyH59BXsZC+GM82YZnefredCZo4Az0 NeCUClrgGexk+CQuPyRfYDapMdXkpW08pg083vP6KYq6WzP3wRU2jITnrwddA1BPN9Gg 7yeg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=6Ff9ArTJlhjOrz4Iyf2wgXUbGoNJsvmn8LGUWU50kvw=; b=Ee5/kytQ9Ez064GG5KxNiMoC3iWpD8+N7KAOqxJ1Igvmk+pjKKluZv/+8Pn9YxThmC 3JyqDJMlHcN1UmGRqlRr3r15Nhy8F23F6l/pFX6xaMO/yh8Hp8b32y4I2TiKejSCKxon GLd7IEo3jtaExBHBAYoOlActbyoLGmLjVLQP6FgzxMvw8zNonSHYgN8pHhxt0I/m2Rms hiXNswkpv0c9M2soX8fc8YVYFEneflB4oX4XyD5/lcWAuAtjyJjIq//HoPg+Mxxo2qfG ZoWEVuitDa37pHsyNcn7hXHAuCfGHGxdyz1lOucnZDPB/+OajFLnTlwOXdn9z7SN16Us KvcQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=kV82mWIj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id u17-20020a170903125100b001a6ce2cdb20si284568plh.244.2023.04.23.08.37.54; Sun, 23 Apr 2023 08:38:09 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=kV82mWIj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230250AbjDWOuD (ORCPT + 99 others); Sun, 23 Apr 2023 10:50:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230239AbjDWOt6 (ORCPT ); Sun, 23 Apr 2023 10:49:58 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F6F310E4 for ; Sun, 23 Apr 2023 07:49:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=6Ff9ArTJlhjOrz4Iyf2wgXUbGoNJsvmn8LGUWU50kvw=; b=kV82mWIjR+T/0TKTIHkNnso9y1 pj9TQUgP3KcKJTCLphT77F1zJ7XCv+tM2Ln5BULPV5hM/o+XqRkbY290rR5HQeg8QupGrJ5T9SOxp aNfGmJjQR/J3Pex79r/KaRVMGsMNh5jW2U+Kd5ui2gQ9VDDGyMqpKS0xmtlCpC6xaMAmdaggoZcLI mPZ4gVBBRNXQ7p72uO7m/mSBlsvcHHM4wDATqFzcQZc1Ax3Yi/fDQyNKfbFAQlcKPwvfLjhqNmneb yzAimWQG2DZaqeBAl0usp35JnkWNK2b7J1/wCocyiAlqss+4MLIuAvT9tLPKLZfICsRLbiC66PRjh GRpPLsLQ==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaSI-00ANVs-Vu; Sun, 23 Apr 2023 16:12:43 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 14/40] drm/amd/display: add plane shaper LUT driver-private properties Date: Sun, 23 Apr 2023 13:10:26 -0100 Message-Id: <20230423141051.702990-15-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763981959560249434?= X-GMAIL-MSGID: =?utf-8?q?1763981959560249434?= Shaper 1D LUT delinearizes content before applying 3D LUT so that, it comes before 3D LUT. It's an optional property and drivers should attach it according to HW caps. Signed-off-by: Melissa Wen --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 14 ++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 10 ++++++++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 5 +++++ .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 19 +++++++++++++++++++ 4 files changed, 48 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 8d4726978c6e..f41406ee96ad 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1332,6 +1332,20 @@ amdgpu_display_create_color_properties(struct amdgpu_device *adev) return -ENOMEM; adev->mode_info.plane_hdr_mult_property = prop; + prop = drm_property_create(adev_to_drm(adev), + DRM_MODE_PROP_BLOB, + "AMD_PLANE_SHAPER_LUT", 0); + if (!prop) + return -ENOMEM; + adev->mode_info.plane_shaper_lut_property = prop; + + prop = drm_property_create_range(adev_to_drm(adev), + DRM_MODE_PROP_IMMUTABLE, + "AMD_PLANE_SHAPER_LUT_SIZE", 0, UINT_MAX); + if (!prop) + return -ENOMEM; + adev->mode_info.plane_shaper_lut_size_property = prop; + prop = drm_property_create(adev_to_drm(adev), DRM_MODE_PROP_BLOB, "AMD_PLANE_LUT3D", 0); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 9d9dac26edfc..756d5f70be0a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -391,6 +391,16 @@ struct amdgpu_mode_info { * @plane_hdr_mult_property: */ struct drm_property *plane_hdr_mult_property; + /** + * @shaper_lut_property: Plane property to set pre-blending shaper LUT + * that converts color content before 3D LUT. + */ + struct drm_property *plane_shaper_lut_property; + /** + * @shaper_lut_size_property: Plane property for the size of + * pre-blending shaper LUT as supported by the driver (read-only). + */ + struct drm_property *plane_shaper_lut_size_property; /** * @plane_lut3d_property: Plane property for gamma correction using a * 3D LUT (pre-blending). diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index b0ba0279dc25..d3ecc73129ff 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -748,6 +748,11 @@ struct dm_plane_state { * S31.32 sign-magnitude. */ __u64 hdr_mult; + /** + * @shaper_lut: shaper lookup table blob. The blob (if not NULL) is an + * array of &struct drm_color_lut. + */ + struct drm_property_blob *shaper_lut; /** * @lut3d: 3D lookup table blob. The blob (if not NULL) is an array of * &struct drm_color_lut. diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 0e418e161b0b..69e2f1f86cce 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1347,6 +1347,8 @@ dm_drm_plane_duplicate_state(struct drm_plane *plane) #ifdef CONFIG_STEAM_DECK if (dm_plane_state->degamma_lut) drm_property_blob_get(dm_plane_state->degamma_lut); + if (dm_plane_state->shaper_lut) + drm_property_blob_get(dm_plane_state->shaper_lut); if (dm_plane_state->lut3d) drm_property_blob_get(dm_plane_state->lut3d); #endif @@ -1419,6 +1421,7 @@ static void dm_drm_plane_destroy_state(struct drm_plane *plane, struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); #ifdef CONFIG_STEAM_DECK drm_property_blob_put(dm_plane_state->degamma_lut); + drm_property_blob_put(dm_plane_state->shaper_lut); drm_property_blob_put(dm_plane_state->lut3d); #endif @@ -1495,6 +1498,11 @@ dm_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm, AMDGPU_HDR_MULT_DEFAULT); if (dm->dc->caps.color.dpp.hw_3d_lut) { + drm_object_attach_property(&plane->base, + dm->adev->mode_info.plane_shaper_lut_property, 0); + drm_object_attach_property(&plane->base, + dm->adev->mode_info.plane_shaper_lut_size_property, + MAX_COLOR_LUT_ENTRIES); drm_object_attach_property(&plane->base, dm->adev->mode_info.plane_lut3d_property, 0); drm_object_attach_property(&plane->base, @@ -1531,6 +1539,14 @@ dm_atomic_plane_set_property(struct drm_plane *plane, dm_plane_state->hdr_mult = val; dm_plane_state->base.color_mgmt_changed = 1; } + } else if (property == adev->mode_info.plane_shaper_lut_property) { + ret = amdgpu_dm_replace_property_blob_from_id(plane->dev, + &dm_plane_state->shaper_lut, + val, + -1, sizeof(struct drm_color_lut), + &replaced); + dm_plane_state->base.color_mgmt_changed |= replaced; + return ret; } else if (property == adev->mode_info.plane_lut3d_property) { ret = amdgpu_dm_replace_property_blob_from_id(plane->dev, &dm_plane_state->lut3d, @@ -1567,6 +1583,9 @@ dm_atomic_plane_get_property(struct drm_plane *plane, *val = dm_plane_state->degamma_tf; } else if (property == adev->mode_info.plane_hdr_mult_property) { *val = dm_plane_state->hdr_mult; + } else if (property == adev->mode_info.plane_shaper_lut_property) { + *val = (dm_plane_state->shaper_lut) ? + dm_plane_state->shaper_lut->base.id : 0; } else if (property == adev->mode_info.plane_lut3d_property) { *val = (dm_plane_state->lut3d) ? dm_plane_state->lut3d->base.id : 0; From patchwork Sun Apr 23 14:10:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86756 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2241179vqo; Sun, 23 Apr 2023 08:09:04 -0700 (PDT) X-Google-Smtp-Source: AKy350bDMRmuw3CTDNkNJpS3rH+2WuYmyUX1s2qKjtmKdNXH+zf/h3ebgZ7VLRH3qBbrEvBlIojS X-Received: by 2002:a17:90a:f00a:b0:246:61ae:2fbb with SMTP id bt10-20020a17090af00a00b0024661ae2fbbmr11383876pjb.41.1682262543837; Sun, 23 Apr 2023 08:09:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682262543; cv=none; d=google.com; s=arc-20160816; b=GP3ClbDuoPrAW9ZvVyx2h773HpEQFrF6tISHpwIwP+0ZqzuAq3whS1IYtFxyCw9MHQ jtIG4KDj7+O216SW+8nLuggLRZT9CdtQfRng/ZlGhz0C9cnEGW7isuJiCV+CoG+/FjMO sYcQ/BBAmbzIU9Vyvcy/0oNZgtILQ84z6b7DgDuIkCIuhQnsCaGcF/YOL3iiv2rlTTPo XwOGOq9K/BEcJQuv/xmyrNwdXu5mdMMoGQmi3tCs1DIbgOhV6yH5bWE3D9C74bUnjyeY Q1iU0JsYclBGvX2xg16svYn9rY9JyO2DqaK/pftz7UguEBtGXK88BIv3YrRR5VWNV2wH vybA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=KvhTbB+Kxd5FYe1aiUgkRyX7rJ0s9IuTtnkFeSJu+RY=; b=hwyiBNrZqCeBXh+pEFOA1Q5sytdg4ArYvraTEtXrG4YEN2H1u+v3rsVJh4bPkt4HFW dhXy9ID45wlh/WuOtlzML00o2nRFJZoOGuvxu2Akx5jqnhqYoMuofn9bdaxR3ATD34Nz M0gvvg8yzCIVjHWOv/zs7f/oIAP/fsT9WvFOp2vH6RT8KzKFyQK6Q5uc8BP73C1RDSVQ bzaagv2fIVUJ6KfaYKBYqnerqNmCgtpYAEFifnZKJMhaHdrLoJmQhPkVYnObNHhLxuaA dW2ycXAANr4Rh2zykUu9d7yC6IXWNgY25HnvQOTqh+zy2eP0LiHrWBZlR+ooB9S61vXf cTnQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=QToXh3jP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id v69-20020a638948000000b0050bfc85d989si9675498pgd.154.2023.04.23.08.08.48; Sun, 23 Apr 2023 08:09:03 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=QToXh3jP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230180AbjDWOsw (ORCPT + 99 others); Sun, 23 Apr 2023 10:48:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54806 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229836AbjDWOsr (ORCPT ); Sun, 23 Apr 2023 10:48:47 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C59F710F0 for ; Sun, 23 Apr 2023 07:48:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=KvhTbB+Kxd5FYe1aiUgkRyX7rJ0s9IuTtnkFeSJu+RY=; b=QToXh3jPx2EZMNZ2JLKAilJauf Jfd1Ns7DYII8MVMLpuyE4jT/HcukAegS+IN5ebTnSnEC6KiLu/URgl8YXFmo3W3dez9mqXM8Cr+Vv fkXwQ0nR1x3Gggw31jb+zqXIOgn8yCxFN4iiD7TMjOcwKSMU7fbgdpIRYOKiPFnbYKciAfo0EEpV9 Zhj5DMLLiqyFbX1Dmu1mbZZezZ4+DEI9we2JTYYxSwueqNdRZ4TNzVZXS46vTX+HgA+Pqe6vCKeSC SWKh4JDYBad2hzBBwLdRZzCYWs7EafdkPIDGRvfurG3gZsZ7ew4/dViGFMxHiyNFUpCkX8NlTBiKH I8Wa97Tw==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaSM-00ANVs-Kf; Sun, 23 Apr 2023 16:12:46 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 15/40] drm/amd/display: add plane shaper TF driver-private property Date: Sun, 23 Apr 2023 13:10:27 -0100 Message-Id: <20230423141051.702990-16-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763980128717377581?= X-GMAIL-MSGID: =?utf-8?q?1763980128717377581?= Add property to set predefined transfer function to enable delinearizing content with or without shaper LUT. Drivers should advertize this property acoording to HW caps. Signed-off-by: Melissa Wen --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 9 +++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 6 ++++++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 6 ++++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 11 +++++++++++ 4 files changed, 32 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index f41406ee96ad..2bf8b19feae4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1346,6 +1346,15 @@ amdgpu_display_create_color_properties(struct amdgpu_device *adev) return -ENOMEM; adev->mode_info.plane_shaper_lut_size_property = prop; + prop = drm_property_create_enum(adev_to_drm(adev), + DRM_MODE_PROP_ENUM, + "AMD_PLANE_SHAPER_TF", + drm_transfer_function_enum_list, + ARRAY_SIZE(drm_transfer_function_enum_list)); + if (!prop) + return -ENOMEM; + adev->mode_info.plane_shaper_tf_property = prop; + prop = drm_property_create(adev_to_drm(adev), DRM_MODE_PROP_BLOB, "AMD_PLANE_LUT3D", 0); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 756d5f70be0a..17c7669ad9ab 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -401,6 +401,12 @@ struct amdgpu_mode_info { * pre-blending shaper LUT as supported by the driver (read-only). */ struct drm_property *plane_shaper_lut_size_property; + /** + * @plane_shaper_tf_property: Plane property to set a predefined + * transfer function for pre-blending shaper (before applying 3D LUT) + * with or without LUT. + */ + struct drm_property *plane_shaper_tf_property; /** * @plane_lut3d_property: Plane property for gamma correction using a * 3D LUT (pre-blending). diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index d3ecc73129ff..8a425e7a7e89 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -753,6 +753,12 @@ struct dm_plane_state { * array of &struct drm_color_lut. */ struct drm_property_blob *shaper_lut; + /** + * @shaper_tf: + * + * Predefined transfer function to delinearize color space. + */ + enum drm_transfer_function shaper_tf; /** * @lut3d: 3D lookup table blob. The blob (if not NULL) is an array of * &struct drm_color_lut. diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 69e2f1f86cce..e4f28fbf6613 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1324,6 +1324,7 @@ static void dm_drm_plane_reset(struct drm_plane *plane) if (amdgpu_state) { amdgpu_state->degamma_tf = DRM_TRANSFER_FUNCTION_DEFAULT; amdgpu_state->hdr_mult = AMDGPU_HDR_MULT_DEFAULT; + amdgpu_state->shaper_tf = DRM_TRANSFER_FUNCTION_DEFAULT; } #endif } @@ -1503,6 +1504,9 @@ dm_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm, drm_object_attach_property(&plane->base, dm->adev->mode_info.plane_shaper_lut_size_property, MAX_COLOR_LUT_ENTRIES); + drm_object_attach_property(&plane->base, + dm->adev->mode_info.plane_shaper_tf_property, + DRM_TRANSFER_FUNCTION_DEFAULT); drm_object_attach_property(&plane->base, dm->adev->mode_info.plane_lut3d_property, 0); drm_object_attach_property(&plane->base, @@ -1547,6 +1551,11 @@ dm_atomic_plane_set_property(struct drm_plane *plane, &replaced); dm_plane_state->base.color_mgmt_changed |= replaced; return ret; + } else if (property == adev->mode_info.plane_shaper_tf_property) { + if (dm_plane_state->shaper_tf != val) { + dm_plane_state->shaper_tf = val; + dm_plane_state->base.color_mgmt_changed = 1; + } } else if (property == adev->mode_info.plane_lut3d_property) { ret = amdgpu_dm_replace_property_blob_from_id(plane->dev, &dm_plane_state->lut3d, @@ -1586,6 +1595,8 @@ dm_atomic_plane_get_property(struct drm_plane *plane, } else if (property == adev->mode_info.plane_shaper_lut_property) { *val = (dm_plane_state->shaper_lut) ? dm_plane_state->shaper_lut->base.id : 0; + } else if (property == adev->mode_info.plane_shaper_tf_property) { + *val = dm_plane_state->shaper_tf; } else if (property == adev->mode_info.plane_lut3d_property) { *val = (dm_plane_state->lut3d) ? dm_plane_state->lut3d->base.id : 0; From patchwork Sun Apr 23 14:10:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86757 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2241177vqo; Sun, 23 Apr 2023 08:09:04 -0700 (PDT) X-Google-Smtp-Source: AKy350ZrEzVZ0DrTfjwxtKgHm7AXt6BGiRE+nhWWQnMkUJYaE4aj5w6GO2JcO/OR2c+52KaZFkPI X-Received: by 2002:a05:6a21:1185:b0:ee:3824:664f with SMTP id oj5-20020a056a21118500b000ee3824664fmr11217037pzb.47.1682262543793; Sun, 23 Apr 2023 08:09:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682262543; cv=none; d=google.com; s=arc-20160816; b=A5PtalBhr60RUEzqDzlt+HuTJHIQ9+gGnDYZEggHq4vCCJy9y60xBcxrpqB0ZjVetZ J3fPU8xtbwadFD31RqO8sUHXYjAXayjnsGbYBJRi4tpywbVnSKktwcQZdFk2CzQCE3nn D0zoqRGP9Qy21Ua8BhNMaHdnQDT/TrDtBvC8ZYEPA71VvEfTeeeF1Hk3JFssVppsIqPL nhQfFhb0/VrqBrmdcGDHEYBvtyXAJu9fUPYR1ZO5kIvcFTPwdbgrNkHFLJ7aHze9xdsx P9xl3IO0yqDQn6B6T1F7v+f89++36Ih8eEQsPJHS0su8aCvjlCJV8UyuFDR7Qx7AmGPi pNIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=YuRvpsn5roC+eRUxTHLyKChKqQovXO5NGq7R4iJaNio=; b=R6P7VbNz4iueqkYdsOlOubnGTzdTDlhTIaFdH08P3kytcEixWJnYHAtZgOMUt53ftf PDpc0V+Z+3VOWQWSBINEFIdN/IFj3/1WFZyu6sxRKB1jLpyTuo7LBDjxwIa1UnN2Vynh mkcSt1EKn680VEv3kdYiz4OziwYeOghMZL1z+T8JsouTQ7dec3J26bzBoAsOa29bfcMk SI+qRgTFM/cRsx/GDxYxJ/fXon0y61yAlPOe4hL/lbf/0hGsMENEraB1ABnfn0V+5mNA 8M6c3gZr5cpyBvALLpZP0Zyp1BUKOEyI7pwEl6mQfR9Ths+ZzNGu/FvkvfTiXuEIrNP6 9cuQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=FNUSIzcp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id a8-20020aa78e88000000b0062d781f1f87si8940175pfr.355.2023.04.23.08.08.49; Sun, 23 Apr 2023 08:09:03 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=FNUSIzcp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229881AbjDWOqq (ORCPT + 99 others); Sun, 23 Apr 2023 10:46:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51784 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230388AbjDWOqj (ORCPT ); Sun, 23 Apr 2023 10:46:39 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 40C1E1701 for ; Sun, 23 Apr 2023 07:46:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=YuRvpsn5roC+eRUxTHLyKChKqQovXO5NGq7R4iJaNio=; b=FNUSIzcpPCB6FEpiH8zNLT8EVn FKHwSPuShGgq3xWnWZaDT3vF72WB3E+4l2s1M2C1c6QMBsRwUgFzuiVYUC/+/hBKWbDpCj4Sx3azm r5grGq3nR6ebdh67g1rIEj88WslocWkWQS0h0l4Su4LT5A7uziEHbR9+PLZwFZ2suBw4UlA+Kg7KZ ZNyVOWRBIJfGnuAmXCxcbrmXZz+aOdQbvrsGjJfUGx25Gcbs/93zjxsqDizmWncZzWYTYU/KUBmyk L8Rwi0hvAlQ97Rw8j1L1Xubxa9LNnpqJi4pPb+TL+Lz+iCHL8nUWUaWxMQXQ+8kmkvqeN8O4/8/p1 VOj7whEQ==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaSP-00ANVs-HQ; Sun, 23 Apr 2023 16:12:49 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , linux-kernel@vger.kernel.org Subject: [RFC PATCH 16/40] drm/amd/display: add plane blend LUT and TF driver-private properties Date: Sun, 23 Apr 2023 13:10:28 -0100 Message-Id: <20230423141051.702990-17-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763980128778757620?= X-GMAIL-MSGID: =?utf-8?q?1763980128778757620?= From: Joshua Ashton Blend 1D LUT or a predefined transfer function can be set to linearize content before blending, so that it's positioned just before blending planes, and after 3D LUT (non-linear space). Shaper and Blend LUTs are 1D LUTs that sandwich 3D LUT. Drivers should advertize blend properties according to HW caps. Signed-off-by: Joshua Ashton --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 23 +++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 18 ++++++++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 12 +++++++ .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 34 +++++++++++++++++++ 4 files changed, 87 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 2bf8b19feae4..0bcf0bc6baff 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1369,6 +1369,29 @@ amdgpu_display_create_color_properties(struct amdgpu_device *adev) return -ENOMEM; adev->mode_info.plane_lut3d_size_property = prop; + prop = drm_property_create(adev_to_drm(adev), + DRM_MODE_PROP_BLOB, + "AMD_PLANE_BLEND_LUT", 0); + if (!prop) + return -ENOMEM; + adev->mode_info.plane_blend_lut_property = prop; + + prop = drm_property_create_range(adev_to_drm(adev), + DRM_MODE_PROP_IMMUTABLE, + "AMD_PLANE_BLEND_LUT_SIZE", 0, UINT_MAX); + if (!prop) + return -ENOMEM; + adev->mode_info.plane_blend_lut_size_property = prop; + + prop = drm_property_create_enum(adev_to_drm(adev), + DRM_MODE_PROP_ENUM, + "AMD_PLANE_BLEND_TF", + drm_transfer_function_enum_list, + ARRAY_SIZE(drm_transfer_function_enum_list)); + if (!prop) + return -ENOMEM; + adev->mode_info.plane_blend_tf_property = prop; + return 0; } #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 17c7669ad9ab..f640dbd53b8c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -417,6 +417,24 @@ struct amdgpu_mode_info { * size of 3D LUT as supported by the driver (read-only). */ struct drm_property *plane_lut3d_size_property; + /** + * @plane_blend_lut_property: Plane property for output gamma before + * blending. Userspace set a blend LUT to convert colors after 3D LUT + * conversion. It works as a post-3D LUT 1D LUT, with shaper LUT, they + * are sandwiching 3D LUT with two 1D LUT. + */ + struct drm_property *plane_blend_lut_property; + /** + * @plane_blend_lut_size_property: Plane property to define the max + * size of blend LUT as supported by the driver (read-only). + */ + struct drm_property *plane_blend_lut_size_property; + /** + * @plane_blend_tf_property: Plane property to set a predefined + * transfer function for pre-blending blend (before applying 3D LUT) + * with or without LUT. + */ + struct drm_property *plane_blend_tf_property; #endif }; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 8a425e7a7e89..54121c3fa040 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -764,6 +764,18 @@ struct dm_plane_state { * &struct drm_color_lut. */ struct drm_property_blob *lut3d; + /** + * @blend_lut: blend lut lookup table blob. The blob (if not NULL) is an + * array of &struct drm_color_lut. + */ + struct drm_property_blob *blend_lut; + /** + * @blend_tf: + * + * Pre-defined transfer function for converting plane pixel data before + * applying blend LUT. + */ + enum drm_transfer_function blend_tf; #endif }; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index e4f28fbf6613..cdbd11f3be20 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1325,6 +1325,7 @@ static void dm_drm_plane_reset(struct drm_plane *plane) amdgpu_state->degamma_tf = DRM_TRANSFER_FUNCTION_DEFAULT; amdgpu_state->hdr_mult = AMDGPU_HDR_MULT_DEFAULT; amdgpu_state->shaper_tf = DRM_TRANSFER_FUNCTION_DEFAULT; + amdgpu_state->blend_tf = DRM_TRANSFER_FUNCTION_DEFAULT; } #endif } @@ -1352,6 +1353,8 @@ dm_drm_plane_duplicate_state(struct drm_plane *plane) drm_property_blob_get(dm_plane_state->shaper_lut); if (dm_plane_state->lut3d) drm_property_blob_get(dm_plane_state->lut3d); + if (dm_plane_state->blend_lut) + drm_property_blob_get(dm_plane_state->blend_lut); #endif return &dm_plane_state->base; @@ -1424,6 +1427,7 @@ static void dm_drm_plane_destroy_state(struct drm_plane *plane, drm_property_blob_put(dm_plane_state->degamma_lut); drm_property_blob_put(dm_plane_state->shaper_lut); drm_property_blob_put(dm_plane_state->lut3d); + drm_property_blob_put(dm_plane_state->blend_lut); #endif if (dm_plane_state->dc_state) @@ -1513,6 +1517,17 @@ dm_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm, dm->adev->mode_info.plane_lut3d_size_property, MAX_COLOR_3DLUT_ENTRIES); } + + if (dm->dc->caps.color.dpp.ogam_ram) { + drm_object_attach_property(&plane->base, + dm->adev->mode_info.plane_blend_lut_property, 0); + drm_object_attach_property(&plane->base, + dm->adev->mode_info.plane_blend_lut_size_property, + MAX_COLOR_LUT_ENTRIES); + drm_object_attach_property(&plane->base, + dm->adev->mode_info.plane_blend_tf_property, + DRM_TRANSFER_FUNCTION_DEFAULT); + } } static int @@ -1564,6 +1579,19 @@ dm_atomic_plane_set_property(struct drm_plane *plane, &replaced); dm_plane_state->base.color_mgmt_changed |= replaced; return ret; + } else if (property == adev->mode_info.plane_blend_lut_property) { + ret = amdgpu_dm_replace_property_blob_from_id(plane->dev, + &dm_plane_state->blend_lut, + val, + -1, sizeof(struct drm_color_lut), + &replaced); + dm_plane_state->base.color_mgmt_changed |= replaced; + return ret; + } else if (property == adev->mode_info.plane_blend_tf_property) { + if (dm_plane_state->blend_tf != val) { + dm_plane_state->blend_tf = val; + dm_plane_state->base.color_mgmt_changed = 1; + } } else { drm_dbg_atomic(plane->dev, "[PLANE:%d:%s] unknown property [PROP:%d:%s]]\n", @@ -1600,6 +1628,12 @@ dm_atomic_plane_get_property(struct drm_plane *plane, } else if (property == adev->mode_info.plane_lut3d_property) { *val = (dm_plane_state->lut3d) ? dm_plane_state->lut3d->base.id : 0; + } else if (property == adev->mode_info.plane_blend_lut_property) { + *val = (dm_plane_state->blend_lut) ? + dm_plane_state->blend_lut->base.id : 0; + } else if (property == adev->mode_info.plane_blend_tf_property) { + *val = dm_plane_state->blend_tf; + } else { return -EINVAL; } From patchwork Sun Apr 23 14:10:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86732 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2221330vqo; Sun, 23 Apr 2023 07:23:59 -0700 (PDT) X-Google-Smtp-Source: AKy350aa84s1naQZrmulR9NHAtFmF9yFc1V9qodzZu0ctXXVbHArKc43pYqc8iUjNQcEs9pAe2SW X-Received: by 2002:a05:6a20:a1a0:b0:de:247e:d1fe with SMTP id r32-20020a056a20a1a000b000de247ed1femr10258924pzk.1.1682259839334; Sun, 23 Apr 2023 07:23:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682259839; cv=none; d=google.com; s=arc-20160816; b=cR/SIDkexTZP58pceHcVN/6c2k3+4OH2W6fPUoK32+XStQz+WQM9ySCK7lsuW7PgKf rgKTbG75BCQX+W9OX3mXIGGBu8TtgG3FYylgEgf89UKYLg6WQzX6Ym/rrC95iDvnvpxv 9IJLGmhmXgEub/aeXpu8PDchHULdcYVvqex7Dw6M/rGXFzH9BD1p4WP0+ETW4xPizLAC q6Wg6aScOh5yhMWdiTVLNTPv9BMozuJnTWG4orj0TZ29Wx5PYJ6BqPudUQeSq85/PPA8 sj1Ewke8L90QfBK+jNVtBdrKSzchFFM+Nq8L12/jBtGQKXJvriJASmdCPzeVMsBhBk+s SHpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=K+6HAiokAFpNjOZfe6WgA9HAsgScvAWCci4ACm8KQN8=; b=p9r8+v/0uc721Pxodu0sSf3zXOQSDXYALH42LLxQ7UY3fcjFAkF96r4hYEITtE5Lf9 j4ACVuA38AjJic2rA17XdNl86VcWk+d2jEd6Tjg2OsOqlRpqALzy6x8f+/C92xxFgStS TeYeW5KICT6HSZyQBlUYyoaIfy+Dk6mKTQ+34oKHFLgwqB1QrinutAjEmViIEFRH4bS3 7Umhk/hIHiO6goySJY1TbHLk+qdGBPleFQocaB8gapx0q6Bat2Lpd6Du8A3nu79VWDTt 3RBS113139EXJ6l/m/ERrbIRYhfU70ubDeOdtI7+GNsnARhK6CHftCeEqXV2M+fFBJFm AqiA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=hx19W7o9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id o16-20020a635a10000000b0051b3d5543c3si8918177pgb.130.2023.04.23.07.23.44; Sun, 23 Apr 2023 07:23:59 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=hx19W7o9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230260AbjDWOOa (ORCPT + 99 others); Sun, 23 Apr 2023 10:14:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34000 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230231AbjDWOO1 (ORCPT ); Sun, 23 Apr 2023 10:14:27 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8BBDC30DB for ; Sun, 23 Apr 2023 07:13:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=K+6HAiokAFpNjOZfe6WgA9HAsgScvAWCci4ACm8KQN8=; b=hx19W7o99rbwOcYM34nXNbSSO2 wNL6y1AqnOcuv62B7tlO7cHm2Mamz7TFvnDOpoVdX4iSCqBDLy14RJJhCiu5e9fAAzMxhYCxxlaXl hySJDSRTL/Cv8+a33gH5aQIROjh5lQr06r9/8oQLXkcUXZ59HIWqAwXQnSLB9RRaKYYFb+Gs/qQyM PgNCnsEa34yModOd4L5BkD2Noo5QY4wFU+UvANqowu7JU7BehKBJnr4hxXkt4yPQWMWT4FZFDK1t6 UfbeEMnf8VkLNQVqDokT5RCPODHQYd5XKsjPOziSs/PvQev4t0yHiP0N/qayIdHHz940+zkg1PH0C JVIariXg==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaST-00ANVs-FW; Sun, 23 Apr 2023 16:12:53 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 17/40] drm/amd/display: add comments to describe DM crtc color mgmt behavior Date: Sun, 23 Apr 2023 13:10:29 -0100 Message-Id: <20230423141051.702990-18-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763977293076988503?= X-GMAIL-MSGID: =?utf-8?q?1763977293076988503?= Describe some expected behavior of the AMD DM color mgmt programming. Signed-off-by: Melissa Wen --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index a4cb23d059bd..fe779d10834e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -440,12 +440,23 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS; stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; + /* Note: although we pass has_rom as parameter here, we never + * actually use ROM because the color module only takes the ROM + * path if transfer_func->type == PREDEFINED. + * + * See more in mod_color_calculate_regamma_params() + */ r = __set_legacy_tf(stream->out_transfer_func, regamma_lut, regamma_size, has_rom); if (r) return r; } else if (has_regamma) { - /* If atomic regamma, CRTC RGM goes into RGM LUT. */ + /* CRTC RGM goes into RGM LUT. + * + * Note: there is no implicit sRGB regamma here. We are using + * degamma calculation from color module to calculate the curve + * from a linear base. + */ stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS; stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR; From patchwork Sun Apr 23 14:10:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86737 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2222320vqo; Sun, 23 Apr 2023 07:26:34 -0700 (PDT) X-Google-Smtp-Source: AKy350Z8aQ21drhedSrQ8OLa4ljScLjZWSCkJO3M3SKyoJLzQF9brs1olzjxjT8DFZvnRted8tP3 X-Received: by 2002:a17:903:228d:b0:1a8:1d1e:407b with SMTP id b13-20020a170903228d00b001a81d1e407bmr14266627plh.64.1682259993879; Sun, 23 Apr 2023 07:26:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682259993; cv=none; d=google.com; s=arc-20160816; b=JMtD7O/oSwmpXA1KzyGujJRNUCjE1ohEgpTjAY6jRJcQOhgv2A0B4hBiNzPu3HNkCg Gosw610iHEHpmu/Yzo9s3VFGQWyX/OjPGy3q0VvP8D3wCd6hN4AVbi6ceLAY6Z/uZOnR 4iJ5No3TsmskmM2SSlTRl2916F80ZzSYX2LTQs8kAod+57g4ZKOchpLoCLV2xWeFbgl0 8uH9JEbGabAf8YxpK5NMdMnKCH5wUs5kCFfkEFbRl8Pz7+xougRVVQmQsVLj2X1GTZxy D8JxE0sX3oiMUsHUu5g+UJAwcQD5mJ4FlJyz8KUWC2uSfAikjC8ujGiV7gB/gP+KIT8q BLGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=fshOS/phNnywqSBclNdRCFpkoMQdWZs7fr2IAut5ZT0=; b=tfh6gMqIRbR/HLO5EiQL92GDJCnaFC2phDp5ukHliMv2PE3GjYJBSjAtsL02egddAN ziQRAKMURrGPu4vpVsotp3MkRTb3vldY/OZv++MikwmKvJx0hFUZIg8lkBiq1l38j/N9 7CfrMP7k8z8SLPfZE/fR7N6pE6zPWRe7VfElIxHmAHIGfnUTnZs9j1P/aQ90hXXLey19 r2Mzca7mh/UXvc+9cUJrySBXzH8qc3eoA8Af41vBGbVj5mCAIdHQrtiDKn+doGVB2tXK CGr9Mc9TZvj9tbYrSbSjt7AG8DqPjPYW3VwabPE4keJoB7ZLILud40XNu1GuqTU1cPG+ eorQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=BtJ4pyax; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id f11-20020a170902ce8b00b001a6e5be610esi5542476plg.297.2023.04.23.07.26.19; Sun, 23 Apr 2023 07:26:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=BtJ4pyax; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230253AbjDWOO1 (ORCPT + 99 others); Sun, 23 Apr 2023 10:14:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33936 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229726AbjDWOOZ (ORCPT ); Sun, 23 Apr 2023 10:14:25 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7452F30CA for ; Sun, 23 Apr 2023 07:13:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=fshOS/phNnywqSBclNdRCFpkoMQdWZs7fr2IAut5ZT0=; b=BtJ4pyaxdSoPnTZ+6hrLdkGn3J ThaZJtL9jgfH3W46t0EickvaTV1RcRBbRBtFLcIqmLXEO4cH/9wHo0uF/7TRv7xq02rBwYs38JVRI cRKqfACjAfjuzlRMHgFE6eJ4clTF0oU9e9wGD7U51lS6ePdh+ml8cARhCzFbMiu2pAFK8E1e2JTA0 6vH7lFIcUzwkeebvagpq38nIzFanGIUMwHbezSCvXbvcQ+djPBX+CR78NQ43bdGLb6P4kcV/tqcem fsJd568OQ7gjqkc+45X47JkDUimkGeK1dBnwBoOp/tXIuIIMhM8m9t7moV0apFxk95KjWNou7/qze qddg1PuQ==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaSW-00ANVs-Bb; Sun, 23 Apr 2023 16:12:56 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 18/40] drm/amd/display: encapsulate atomic regamma operation Date: Sun, 23 Apr 2023 13:10:30 -0100 Message-Id: <20230423141051.702990-19-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763977455194475662?= X-GMAIL-MSGID: =?utf-8?q?1763977455194475662?= We are introducing DRM 3D LUT property to DM color pipeline in the next patch, but so far, only for atomic interface. By checking set_output_transfer_func in DC drivers with MPC 3D LUT support, we can verify that regamma is only programmed when 3D LUT programming fails. As a groundwork to introduce 3D LUT programming and better understand each step, detach atomic regamma programming from the crtc colocr updating code. Signed-off-by: Melissa Wen --- .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 52 ++++++++++++------- 1 file changed, 33 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index fe779d10834e..f1885e9c614d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -303,6 +303,35 @@ static int __set_output_tf(struct dc_transfer_func *func, return res ? 0 : -ENOMEM; } +static int amdgpu_dm_set_atomic_regamma(struct dc_stream_state *stream, + const struct drm_color_lut *regamma_lut, + uint32_t regamma_size, bool has_rom) +{ + int ret = 0; + if (regamma_size) { + /* CRTC RGM goes into RGM LUT. + * + * Note: there is no implicit sRGB regamma here. We are using + * degamma calculation from color module to calculate the curve + * from a linear base. + */ + stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS; + stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR; + + ret = __set_output_tf(stream->out_transfer_func, + regamma_lut, regamma_size, has_rom); + } else { + /* + * No CRTC RGM means we can just put the block into bypass + * since we don't have any plane level adjustments using it. + */ + stream->out_transfer_func->type = TF_TYPE_BYPASS; + stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR; + } + + return ret; +} + /** * __set_input_tf - calculates the input transfer function based on expected * input space. @@ -450,27 +479,12 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) regamma_size, has_rom); if (r) return r; - } else if (has_regamma) { - /* CRTC RGM goes into RGM LUT. - * - * Note: there is no implicit sRGB regamma here. We are using - * degamma calculation from color module to calculate the curve - * from a linear base. - */ - stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS; - stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR; - - r = __set_output_tf(stream->out_transfer_func, regamma_lut, - regamma_size, has_rom); + } else { + regamma_size = has_regamma ? regamma_size : 0; + r = amdgpu_dm_set_atomic_regamma(stream, regamma_lut, + regamma_size, has_rom); if (r) return r; - } else { - /* - * No CRTC RGM means we can just put the block into bypass - * since we don't have any plane level adjustments using it. - */ - stream->out_transfer_func->type = TF_TYPE_BYPASS; - stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR; } /* From patchwork Sun Apr 23 14:10:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86731 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2221215vqo; Sun, 23 Apr 2023 07:23:37 -0700 (PDT) X-Google-Smtp-Source: AKy350ZRjI/0EXHQBamDs1SgCtqxiMlOUF0WHJ79m6G6t7tXu7tKGk7mMfXTfqSnQbwIkFlHQ4lZ X-Received: by 2002:a17:902:d10b:b0:1a6:4016:8974 with SMTP id w11-20020a170902d10b00b001a640168974mr10446620plw.31.1682259817366; Sun, 23 Apr 2023 07:23:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682259817; cv=none; d=google.com; s=arc-20160816; b=HcmpzMW6AgVY4ohKc8f/Q9dmhiHK5Hss1paej7uT754iKp6FPeEdsR+u/mThTQexY/ VMYlS030bLeT2oPsMrb3GBoF0AIg4sjH6IrdX7Hzry42JvprvLfiE2oyH4nAqB60insp 5Lx0IPQEM3LoxH2gdLfZEEdeMfpn7KoBbAKXW5N/pXhataVhXyDSaKJXcMNrZ/yu2tT/ wzEn2UJZ/O4iqVHY0IYB2QFEleKubV5acPT+tQWE2vFd78c3UesJMlk0i9SNQp8mxzHU yXJeYeFLUQBT7CsxMPO4NAuGMTCFs8g4MqlXPJ48KzkVBR/qJq986MZYfzzcZbdEsaN6 aDqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ZM4LRZ9R6oIPI6RNCnBj4XwAXqnDA6bTH1zIbaUH8Yk=; b=uzhvdNdIZYwRfgqXVKFXPp6/WpQ0RdZvYEz5q43UKi9f0A3PzHjzUL5X1gR+3NvpDp yylV/RftxThO1+VIg+ATO0hSuLoq04WY1rm00qYBvTQH5gFtfvdu2TCHXoiHJ07vSsCb hZVQG77x3Uudirpyb5wzMcoBAWJAZ/PCFJbiCMkE7ihmo2K52c4EbxZ8PuGlwUekOOSs miStzRsS5uWUeAsMIH49GLYh/sp8faPXtDPgvP9AZS4oRkBVtJWucb5YENr+u4kxz54q SD3YmkR1XSgYDbyT8u24fa/d5OO350IRnr//tJVv8FGw9DNuRDK+S9pHaQnIOGbbZ909 EZ7A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=McvxyZbQ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Melissa Wen --- drivers/gpu/drm/amd/display/dc/core/dc.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index e65ba87ee2c5..9230c122d77e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2581,7 +2581,7 @@ static enum surface_update_type check_update_surfaces_for_stream( stream_update->integer_scaling_update) su_flags->bits.scaling = 1; - if (stream_update->out_transfer_func) + if (stream_update->out_transfer_func || stream_update->lut3d_func) su_flags->bits.out_tf = 1; if (stream_update->abm_level) @@ -2936,6 +2936,14 @@ static void copy_stream_update_to_stream(struct dc *dc, sizeof(struct dc_transfer_func_distributed_points)); } + if (update->func_shaper && + stream->func_shaper != update->func_shaper) + stream->func_shaper = update->func_shaper; + + if (update->lut3d_func && + stream->lut3d_func != update->lut3d_func) + stream->lut3d_func = update->lut3d_func; + if (update->hdr_static_metadata) stream->hdr_static_metadata = *update->hdr_static_metadata; From patchwork Sun Apr 23 14:10:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86741 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2223069vqo; Sun, 23 Apr 2023 07:28:41 -0700 (PDT) X-Google-Smtp-Source: AKy350b5vDyVDYsIKIjPqOO7OoLZPv4aGTnlXFB9R/rgOirwMN11dTrl2Ic+sTeGBwmhFwPdx/Om X-Received: by 2002:a05:6a20:4394:b0:f0:2501:349b with SMTP id i20-20020a056a20439400b000f02501349bmr13379487pzl.25.1682260121386; Sun, 23 Apr 2023 07:28:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682260121; cv=none; d=google.com; s=arc-20160816; b=iIICSkKitmWCQ9mjS3+KmvWFniPL55Equ8JtQpqsULWPybrDRtF31qonR3w9IUtGkf hwpgVn+WAswGtGIQu/GKCxSEGTdUGUDfzvVAaki393NP0s9S0GumuEOaVNZh+yNEuSbi xE2Tgx4GIlUCaSrZzoX+okuf/LXcvH3T6JrxBPws0yo2M0iKbSrSs0W561UUegi8p2// Af6RyeinFek6mMk4U8jaMid25XuJTiooX6bTTmDwka4vnXwX/5A2XBN3Oxz5ZjdHwlEQ DxLbFAGpCF6UcBuG8LDUL6kRgF9VlZ3yGfAUiomGHHr/BDksT/fUo2LB76EiXP0rMyKu oH+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=3ClD7dV5VuRi0yBxsEkJ52hVcmkeVavwfEKm0GzWXV0=; b=CoDwixcS9KTQf/tSs+od5qJZQq2RAarw/XmIY35xjZeXp9r+tmJUjjEBTGfuTQ+M4o CBKp5c5z6NuIscEOqrlLAPvg7dF9XS1tuYlvqot7vhDnuOA0PG3+VH9jA/gP35SVTy58 8zkWM4YYDPzwfKW2acaMRtxz/yIWsawzXsoxAd/SRc4cKENL26hgm/PcrsUz5zPw9Rbt YyOumJWVo9mhTmxk2CebqqkvOMs3BLype0wqfXOclHyMTwJAf8eBD5q+fFss2T/E0v8Z 1hOKUQF771mpVgIS9Z2f4aYSyg+Ch1mWTsuNpecRf6W3V1OfQhRovDA3qHX4P7CkLEVI 27fg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=Mscy7EO0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id u15-20020a63470f000000b005143d5f9ff0si8795553pga.357.2023.04.23.07.28.27; Sun, 23 Apr 2023 07:28:41 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=Mscy7EO0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230315AbjDWOOo (ORCPT + 99 others); Sun, 23 Apr 2023 10:14:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34248 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230292AbjDWOOh (ORCPT ); Sun, 23 Apr 2023 10:14:37 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D70C530F5 for ; Sun, 23 Apr 2023 07:14:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=3ClD7dV5VuRi0yBxsEkJ52hVcmkeVavwfEKm0GzWXV0=; b=Mscy7EO0gkStGjDQNcsCg5zVyN bq0TY2LHRPFrZ5GtBwNl/y2RthYAcEZ59rjOzdOUOUefA/FIqb5t2v7onqNismXpG1YPDQvFLxjiw T3Nc1vBouF+pTUlS2Fk5rHr0JVJRf0R0B5W0UVtbCv1Vj4qtKtDF9Q7F9AQbMxXM2EO4exvqtzK6M eDinz8eY/E9pc8Tu+09q4Vzb8yx2ZJ+JJR1ScWienqUfoAXo5r1u5XwQoQ6xF25b+W5oCt2UVP1b9 rJaHLeqPxbrkXXbdYvDUYNge1oyHQqOFnra1cnW5te9wf7+zQf0Xyo+5px76pAmT99ugIB37dbr6J /k+hqfYg==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaSd-00ANVs-8i; Sun, 23 Apr 2023 16:13:03 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 20/40] drm/amd/display: copy 3D LUT settings from crtc state to stream_update Date: Sun, 23 Apr 2023 13:10:32 -0100 Message-Id: <20230423141051.702990-21-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763977588995401700?= X-GMAIL-MSGID: =?utf-8?q?1763977588995401700?= From: Joshua Ashton When commiting planes, we copy color mgmt resources to the stream state. Do the same for shaper and 3D LUTs. Co-developed-by: Melissa Wen Signed-off-by: Melissa Wen Signed-off-by: Joshua Ashton --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 76a776fd8437..729e37fa1873 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8190,6 +8190,10 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, &acrtc_state->stream->csc_color_matrix; bundle->stream_update.out_transfer_func = acrtc_state->stream->out_transfer_func; + bundle->stream_update.lut3d_func = + (struct dc_3dlut *) acrtc_state->stream->lut3d_func; + bundle->stream_update.func_shaper = + (struct dc_transfer_func *) acrtc_state->stream->func_shaper; } acrtc_state->stream->abm_level = acrtc_state->abm_level; From patchwork Sun Apr 23 14:10:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86743 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2224599vqo; Sun, 23 Apr 2023 07:31:48 -0700 (PDT) X-Google-Smtp-Source: AKy350apmPHWoPM6xJbGksPlAjQp1LOuzPFUvyRPZFl0uMuGwr8Ur9NCybauMjyawsnEXi1espSs X-Received: by 2002:a05:6a00:1582:b0:63d:4142:1a1b with SMTP id u2-20020a056a00158200b0063d41421a1bmr16008569pfk.18.1682260308486; Sun, 23 Apr 2023 07:31:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682260308; cv=none; d=google.com; s=arc-20160816; b=w3Lt1/TNn+JUpW1Qeu++aYMLDgqOAwEA9a8x2M7xuGhg5sJK5fyxGJ4Hdhx+vwiqH0 y2ltBIqmIXBekN5jPSRLrKqfO/q5l3V24EbUHtEAX6RCZrI6uHhZWOrf8U5zlb8ozvS9 iFT0Q7IJ2Stn6wbNZQpThSnlBw/uC9HXRs6x4CWpCVJjv70/D8w6EAMk/fKfoUHeYvrf Uv4yL0aE08i/4wym2sRet/qJ2Gy5XkCwTxGQd0fAF+KpV2JQ5ooUhhcvGlsyL2FnD+mr 4qL6F0chaP4jmWkSRIOQlb7zbEKyQM7Aa12hQAFwHe32D1KIaiecMdXqI5USYfQMA2f8 +PTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=1pDv9ml0fMW1552wzaK0WkxguQ7efaI2g4W2c2iLaSQ=; b=URJpIgKKY2x3rsnXORYbB4VQE+cMGBNKT4wPcmUZiqBUcksN2cErAWEsK35q3+hP8i gD0uZurUg0X0QWZAdI1tHZin8ut6RXLdW6P//pyezJm4Q0kpD/ZiFdT3mwV3H+PpOo50 y+3WhI9EByMiCw/hFjNDLARk93oQF/VuBcuifPTmFyA428EeX/Issofav6cnp+HQguTa ndb1lxVve/0/WxUf2zwVreSnG7jJQAdwh++NfBRB0ITYYzA7waaOuORSYkptHjmBF8fL nXJIKN+alwO8Rk8RZUaR2HE9qtB0ljjzj/PdkQ2qx3Ag9+88dNoKgKB3KAU1fq8Cv7NX VIIQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=Eox+XIAf; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id k27-20020a63561b000000b0051b52bacc82si8549729pgb.243.2023.04.23.07.31.33; Sun, 23 Apr 2023 07:31:48 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=Eox+XIAf; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230347AbjDWOPe (ORCPT + 99 others); Sun, 23 Apr 2023 10:15:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230358AbjDWOPY (ORCPT ); Sun, 23 Apr 2023 10:15:24 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 78996273A for ; Sun, 23 Apr 2023 07:14:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=1pDv9ml0fMW1552wzaK0WkxguQ7efaI2g4W2c2iLaSQ=; b=Eox+XIAfqqBlMEmXETYlxVXbEh JHMNZPiMHotm9iHBFLCgTg0eMle01wIqFJm4RqTCF4aAo33wH93VNrc75eNg9GhToaQQ8MZR10sVS VVcU/Ad/u2MW3uASchmgY0rh/ZmfaZ2M0uPRWalgkOBjLFHWxJtajKLCq7TTFWO3KxZiHb/hsg7vB lm7esmn/xAWZc5vjeCb7V5QRcsbOCl8FLRoDuqvkvkMTTq9sRIXEff+iMavZKHEIa39gNBNpgOTDG 0V1X62DnqJA3REts/k7ijvTFdNinuGn+fMbGrnxYflTLiqHR+qSut+0U8lXTcgUikMRUGJoXot13l iqFJGnhw==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaSf-00ANVs-T7; Sun, 23 Apr 2023 16:13:06 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 21/40] drm/amd/display: allow BYPASS 3D LUT but keep shaper LUT settings Date: Sun, 23 Apr 2023 13:10:33 -0100 Message-Id: <20230423141051.702990-22-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763977784956762175?= X-GMAIL-MSGID: =?utf-8?q?1763977784956762175?= HW allows us to program shaper LUT without 3D LUT settings and it is also good for testing shaper LUT behavior, therefore, DC driver should allow acquiring both 3D and shaper LUT, but programing shaper LUT without 3D LUT (not initialized). Signed-off-by: Melissa Wen --- drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c index 3303c9aae068..bacb0a001d68 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c @@ -113,7 +113,6 @@ static bool dcn30_set_mpc_shaper_3dlut(struct pipe_ctx *pipe_ctx, } if (stream->lut3d_func && - stream->lut3d_func->state.bits.initialized == 1 && stream->lut3d_func->state.bits.rmu_idx_valid == 1) { if (stream->lut3d_func->state.bits.rmu_mux_num == 0) mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu0_mux; @@ -131,8 +130,12 @@ static bool dcn30_set_mpc_shaper_3dlut(struct pipe_ctx *pipe_ctx, if (acquired_rmu != stream->lut3d_func->state.bits.rmu_mux_num) BREAK_TO_DEBUGGER(); - result = mpc->funcs->program_3dlut(mpc, &stream->lut3d_func->lut_3d, - stream->lut3d_func->state.bits.rmu_mux_num); + if (stream->lut3d_func->state.bits.initialized == 1) + result = mpc->funcs->program_3dlut(mpc, &stream->lut3d_func->lut_3d, + stream->lut3d_func->state.bits.rmu_mux_num); + else + result = mpc->funcs->program_3dlut(mpc, NULL, + stream->lut3d_func->state.bits.rmu_mux_num); result = mpc->funcs->program_shaper(mpc, shaper_lut, stream->lut3d_func->state.bits.rmu_mux_num); } else { From patchwork Sun Apr 23 14:10:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86729 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2219514vqo; Sun, 23 Apr 2023 07:19:23 -0700 (PDT) X-Google-Smtp-Source: AKy350biznqpVAkSKFdbCzJfbZSnpD7G2EBkAhfTCFZKBJZr1mF5wPNLT9/3jbDWiHkVkfD68Eon X-Received: by 2002:a05:6a00:1911:b0:63b:599b:a2e6 with SMTP id y17-20020a056a00191100b0063b599ba2e6mr15434534pfi.27.1682259562976; Sun, 23 Apr 2023 07:19:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682259562; cv=none; d=google.com; s=arc-20160816; b=lvb+Twxl+WBvTN40jcGtmMgBjeaMHNzyAaqMNu6C29JX2/64tY+jEpLtsuNIUl91hC Y0yf+hhrnAN6zDCbbrOQZyDcRkZDpypicYWCsF1u1i0gWDEwEdXNLGPin7QcP19yLnu6 WyEJXxqdfw7kpA+2JsjP3941QsRur5BML4egUUPTHN+K0W/ELw15ajng7P5jEAmKdFbN KT56yaXXHYanGrLgUTl1t7jn1ZylR7Co3pu12LzcIQTg71/Wm7iQMfcrUW5g5sdEJMOV GaUlUae7L8jjJuPPWWiqmUX5c1XTxeBGoBWqKwp36yuxKQ9+dCb9LMwIisnayNLw9+mN LEqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=S9VKUbO7MAPqhVMypvggSCZtQux9ThB4FE1T0I3nB9M=; b=0c0fR/KDhhTUWctjTitSKuKDdGAy+CAAfJZ9n5RsyAVAFS3yzyRM98VRUyyetUGJgM IeNX8YdHbKOEDrBJpsXgs2d+a6DYpwIcdKZ6P0sNuGG6fktvwwOEneZxlhQ1z5QKwILI H8ha4ZKQr6QuTnvdQ+utav0Wgi4i4YTMUXXYDx6Su/EjO/EDZRGDUnp3FRZHLSjEee2G d9cJOBz2Y0mvP5oBjXJLcLz0Aqi9EirZK05Lhhj7SKoPXa4KzQszJ9WdN8TlfwErwaFB gMDkCXdelnRUyHI0HYPHNeBPyUvoWRIeoXiqcsHuJHEYtMPf3p0gJXIa15bt+Mg3iAqR k1qQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=K+L2mEiC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id b9-20020aa78ec9000000b0063b8935bcbasi8727736pfr.310.2023.04.23.07.19.08; Sun, 23 Apr 2023 07:19:22 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=K+L2mEiC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230264AbjDWOOr (ORCPT + 99 others); Sun, 23 Apr 2023 10:14:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34256 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230297AbjDWOOh (ORCPT ); Sun, 23 Apr 2023 10:14:37 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BFEA230FC for ; Sun, 23 Apr 2023 07:14:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=S9VKUbO7MAPqhVMypvggSCZtQux9ThB4FE1T0I3nB9M=; b=K+L2mEiCcTRSWLNvjIWK7/xizd RT3sUnpGTVNFcJfIhaMk04c0H0X6XV3kedOP9m0QG+RJJZvUJ4B5qsVWXGAVRE3DKf6YcUXjbv/8n UoBhv1MQY3GsiHKiU0tBzvvhd/MQkovROYklwtrA17K9Tljdtqqzq7cDGxfoV37Sv9ZaYPXJU+6K+ KtuWR7QZPdEOX0gBz/VCMLdYh77DDOn1AcbOG471uRt/tNB8FXPG1MWViY5jtmtfoiUKpDBgd4Nxl CDhkArhDBuTHc7CXO6irwad2t7x3LGTsmaXyqplZ4pFcuxlVXty5gqR9Xdyj87a6llYK+pDvi0XnL ZkyHfi5w==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaSm-00ANVs-8B; Sun, 23 Apr 2023 16:13:12 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 22/40] drm/amd/display: handle MPC 3D LUT resources for a given context Date: Sun, 23 Apr 2023 13:10:34 -0100 Message-Id: <20230423141051.702990-23-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763977003485892228?= X-GMAIL-MSGID: =?utf-8?q?1763977003485892228?= In the original dc_acquire_release_mpc_3dlut(), only current ctx is considered, which doesn't fit the steps for atomic checking new ctx. Therefore, create a function to handle 3D LUT resource for a given context, so that we can check resources availability in atomic_check time and handle failures properly. Signed-off-by: Melissa Wen --- drivers/gpu/drm/amd/display/dc/core/dc.c | 39 ++++++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dc.h | 8 +++++ 2 files changed, 47 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 9230c122d77e..ee3fe4eae22e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2101,6 +2101,45 @@ bool dc_acquire_release_mpc_3dlut( return ret; } +bool +dc_acquire_release_mpc_3dlut_for_ctx(struct dc *dc, + bool acquire, + struct dc_state *state, + struct dc_stream_state *stream, + struct dc_3dlut **lut, + struct dc_transfer_func **shaper) +{ + int pipe_idx; + bool ret = false; + bool found_pipe_idx = false; + const struct resource_pool *pool = dc->res_pool; + struct resource_context *res_ctx = &state->res_ctx; + int mpcc_id = 0; + + if (pool && res_ctx) { + if (acquire) { + /*find pipe idx for the given stream*/ + for (pipe_idx = 0; pipe_idx < pool->pipe_count; pipe_idx++) { + if (res_ctx->pipe_ctx[pipe_idx].stream == stream) { + found_pipe_idx = true; + mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst; + break; + } + } + } else + found_pipe_idx = true;/*for release pipe_idx is not required*/ + + if (found_pipe_idx) { + if (acquire && pool->funcs->acquire_post_bldn_3dlut) + ret = pool->funcs->acquire_post_bldn_3dlut(res_ctx, pool, mpcc_id, lut, shaper); + else if (!acquire && pool->funcs->release_post_bldn_3dlut) + ret = pool->funcs->release_post_bldn_3dlut(res_ctx, pool, lut, shaper); + } + } + return ret; +} + + static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context) { int i; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index b45974a2dec3..7fdb0bbb2df9 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1350,6 +1350,14 @@ bool dc_acquire_release_mpc_3dlut( struct dc_3dlut **lut, struct dc_transfer_func **shaper); +bool +dc_acquire_release_mpc_3dlut_for_ctx(struct dc *dc, + bool acquire, + struct dc_state *state, + struct dc_stream_state *stream, + struct dc_3dlut **lut, + struct dc_transfer_func **shaper); + void dc_resource_state_copy_construct( const struct dc_state *src_ctx, struct dc_state *dst_ctx); From patchwork Sun Apr 23 14:10:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86745 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2230709vqo; Sun, 23 Apr 2023 07:46:55 -0700 (PDT) X-Google-Smtp-Source: AKy350bK4UAHdGb1ntWGFQhDs9YjbeOX1eRtg+BXFPqC20ROzfhfbirj+XyeBXBzgzNktb1BivI8 X-Received: by 2002:a17:90a:fb51:b0:247:173c:ba26 with SMTP id iq17-20020a17090afb5100b00247173cba26mr11583151pjb.19.1682261215365; Sun, 23 Apr 2023 07:46:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682261215; cv=none; d=google.com; s=arc-20160816; b=fFBF7CLB87jYyBLErX358QSKcdphJSf65kto9oDX9HdT360egDoTl1ilX5zTXJAeCn +PEE4ZzRHpn9MP55CGn+l7J8OINzIg8YJW7/EY1joe3+7rHVWOLB0pMH2H2MUF5hsKQo xNQ/UTj1ROp9oHRQ0405Q9o0TeadwJYUmFZZQzKgdeKU2H/iLTvfa7dTBT2E7j+3h7b+ /QgIYIyGPVFFahWzg52RUMcpdQ2eB9cRVAihVdJ/4x8BKZCPIPE97cUHORVJK9RipEQk GAmOY3oh68J4jb686zUcJ3NFe1XIN3tj2fSAYNE634t2Y5QJZcZ06z3ss3Vp2+6J+YXz O8ww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=9Gkkzg/ODcJu0BrE41sPuO2jmfVJw6XTbAb54/DnoP4=; b=l4FcRjs82klBKAcA+UyO+6PDzB+3p/p6LJMffR5+/5aIBf28k94lcOV+MezA3KBEL+ KzPlK9D+YuEcVfHHtVQQ+JxWcDQo3J+zkwS0b3UliNo0PXYTbUHDtgcy+dZtW0lHnVgb lN8fqth4Q+icZ2LGIOJ7KgiK7LvttTGZRXU7+JuU+RH8/7KlbvOuWvnp/SjkM+gCj/xD Mjgipjs8JO1Zfom6Lpu6PwOFulgsx2vZbIZopK2iY1NaoY8kl6HhnguKD9t6RF0WXNY1 VnbwdZyps3zMN6a10/ZT8DiNuvBcUnGV8TnIQ5tsNJgisQWZnrpQMMPP7TyOG47oNXgZ 8qjg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b="s5/3j2a1"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id nv5-20020a17090b1b4500b00247871edcdasi10340687pjb.96.2023.04.23.07.46.41; Sun, 23 Apr 2023 07:46:55 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b="s5/3j2a1"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229526AbjDWOPD (ORCPT + 99 others); Sun, 23 Apr 2023 10:15:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230269AbjDWOOp (ORCPT ); Sun, 23 Apr 2023 10:14:45 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F2F9E3594 for ; Sun, 23 Apr 2023 07:14:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=9Gkkzg/ODcJu0BrE41sPuO2jmfVJw6XTbAb54/DnoP4=; b=s5/3j2a1x5SnRnokVpZrpPtoII Uy+KWIdhizMHi3O8/BDg6IVgeFnD170Ek9iPTEEcbXMSqoXF7MW9bVC8m6NUHTECEj5wRrU0iSPGe lV+0Gwx18v0+XhETC/yXxqg1E1aUhcbAH9CPqfzAnR+m7j84gEknDElhZuDLaCLptaa3Hgh1BB2Yo ICwZiz5BsnHAUvqjo7LhyAD2V3+E/kI8YL2vCD08nuRqek/QQtum5aYyYM93IoSt1M/i3puYhzicM av83P4dJjzPqPlxHwS40vaz5d87yotMhd/0Khtpy7KhDiNRZA1IU4BBUQVZ6ErhljH86fzzpCHJUQ oeJEsofw==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaSp-00ANVs-O1; Sun, 23 Apr 2023 16:13:15 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 23/40] drm/amd/display: dynamically acquire 3DLUT resources for color changes Date: Sun, 23 Apr 2023 13:10:35 -0100 Message-Id: <20230423141051.702990-24-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763978736463129352?= X-GMAIL-MSGID: =?utf-8?q?1763978736463129352?= From: Joshua Ashton dc_acquire_release_mpc_3dlut_for_ctx initializes the bits required to program 3DLUT in DC MPC hw block, applied in set_output_transfer_func(). Since acquire/release can fail, we should check resources availability during atomic check considering the new context created. We dynamically acquire 3D LUT resources when we actually use them, so we don't limit ourselves with the stream count. Co-developed-by: Melissa Wen Signed-off-by: Melissa Wen Signed-off-by: Joshua Ashton --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 ++- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 3 +- .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 55 ++++++++++++++++++- .../amd/display/dc/dcn301/dcn301_resource.c | 26 ++++++++- 4 files changed, 87 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 729e37fa1873..6b40e17892e5 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -9380,7 +9380,12 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, */ if (dm_new_crtc_state->base.color_mgmt_changed || drm_atomic_crtc_needs_modeset(new_crtc_state)) { - ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); + if (!dm_state) { + ret = dm_atomic_get_state(state, &dm_state); + if (ret) + goto fail; + } + ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state, dm_state->context); if (ret) goto fail; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 54121c3fa040..5faf4fc87701 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -904,7 +904,8 @@ void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); void amdgpu_dm_init_color_mod(void); int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state); -int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); +int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc, + struct dc_state *ctx); int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, struct dc_plane_state *dc_plane_state); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index f1885e9c614d..99b1738c98d3 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -332,6 +332,49 @@ static int amdgpu_dm_set_atomic_regamma(struct dc_stream_state *stream, return ret; } +/* amdgpu_dm_atomic_shaper_lut3d - set DRM CRTC shaper LUT and 3D LUT to DC + * interface + * @dc: Display Core control structure + * @ctx: + * @stream: DC stream state to set shaper LUT and 3D LUT + * @drm_shaper_lut: DRM CRTC (user) shaper LUT + * @drm_shaper_size: size of shaper LUT + * @drm_lut3d: DRM CRTC (user) 3D LUT + * @drm_lut3d_size: size of 3D LUT + * + * Returns: + * 0 on success. + */ +static int amdgpu_dm_atomic_shaper_lut3d(struct dc *dc, + struct dc_state *ctx, + struct dc_stream_state *stream, + const struct drm_color_lut *drm_shaper_lut, + uint32_t drm_shaper_size, + const struct drm_color_lut *drm_lut3d, + uint32_t drm_lut3d_size) +{ + struct dc_3dlut *lut3d_func; + struct dc_transfer_func *func_shaper; + bool acquire = drm_shaper_size && drm_lut3d_size; + + lut3d_func = (struct dc_3dlut *)stream->lut3d_func; + func_shaper = (struct dc_transfer_func *)stream->func_shaper; + + ASSERT((lut3d_func && func_shaper) || (!lut3d_func && !func_shaper)); + if ((acquire && !lut3d_func && !func_shaper) || + (!acquire && lut3d_func && func_shaper)) + { + if (!dc_acquire_release_mpc_3dlut_for_ctx(dc, acquire, ctx, stream, + &lut3d_func, &func_shaper)) + return DC_ERROR_UNEXPECTED; + } + + stream->lut3d_func = lut3d_func; + stream->func_shaper = func_shaper; + + return 0; +} + /** * __set_input_tf - calculates the input transfer function based on expected * input space. @@ -402,6 +445,7 @@ int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state) /** * amdgpu_dm_update_crtc_color_mgmt: Maps DRM color management to DC stream. * @crtc: amdgpu_dm crtc state + * @ctx: * * With no plane level color management properties we're free to use any * of the HW blocks as long as the CRTC CTM always comes before the @@ -421,7 +465,8 @@ int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state) * Returns: * 0 on success. Error code if setup fails. */ -int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) +int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc, + struct dc_state *ctx) { struct dc_stream_state *stream = crtc->stream; struct amdgpu_device *adev = drm_to_adev(crtc->base.state->dev); @@ -480,6 +525,14 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) if (r) return r; } else { + r = amdgpu_dm_atomic_shaper_lut3d(adev->dm.dc, ctx, stream, + NULL, 0, NULL, 0); + if (r) + return r; + /* Note: OGAM is disabled if 3D LUT is successfully programmed. + * See params and set_output_gamma in + * dcn30_set_output_transfer_func() + */ regamma_size = has_regamma ? regamma_size : 0; r = amdgpu_dm_set_atomic_regamma(stream, regamma_lut, regamma_size, has_rom); diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c index 5ac2a272c380..a6d6fcaaca1c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c @@ -1258,6 +1258,30 @@ static struct display_stream_compressor *dcn301_dsc_create( return &dsc->base; } +static enum dc_status +dcn301_remove_stream_from_ctx(struct dc *dc, + struct dc_state *new_ctx, + struct dc_stream_state *dc_stream) +{ + struct dc_3dlut *lut3d_func; + struct dc_transfer_func *func_shaper; + + lut3d_func = (struct dc_3dlut *)dc_stream->lut3d_func; + func_shaper = (struct dc_transfer_func *)dc_stream->func_shaper; + + ASSERT((lut3d_func && func_shaper) || (!lut3d_func && !func_shaper)); + if (lut3d_func && func_shaper) + { + if (!dc_acquire_release_mpc_3dlut_for_ctx(dc, false, new_ctx, dc_stream, + &lut3d_func, &func_shaper)) + return DC_ERROR_UNEXPECTED; + } + + dc_stream->lut3d_func = lut3d_func; + dc_stream->func_shaper = func_shaper; + + return dcn20_remove_stream_from_ctx(dc, new_ctx, dc_stream); +} static void dcn301_destroy_resource_pool(struct resource_pool **pool) { @@ -1406,7 +1430,7 @@ static struct resource_funcs dcn301_res_pool_funcs = { .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, .add_stream_to_ctx = dcn30_add_stream_to_ctx, .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, - .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, + .remove_stream_from_ctx = dcn301_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, From patchwork Sun Apr 23 14:10:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86728 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2219232vqo; Sun, 23 Apr 2023 07:18:35 -0700 (PDT) X-Google-Smtp-Source: AKy350bCCdjeVzU8MhDOw8FQwizz0V93tji1uZVb0X8XUuL7oxXA9mWv3WdZxwiTC7N5vWOF5HQb X-Received: by 2002:a17:903:2281:b0:1a1:b174:836c with SMTP id b1-20020a170903228100b001a1b174836cmr15101233plh.16.1682259514865; Sun, 23 Apr 2023 07:18:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682259514; cv=none; d=google.com; s=arc-20160816; b=T/Sz9yPlPKUdPB/k7Fz7zFH7Lghi+hk2W9bxQKcxfhbIO9UwBvgGGlH8QXDYQwgdql DXwHO8OWNTD1yvY7FV+OzakngzL17X+VTpjkhFz6uS6wUFCxut9jq1tnntF4bA95zv4w A4lHFrri00RKSKK9dH4OnwKLFu19YOtXsGuUnJ0ASqe4l2zBlqBwOCwoH/SRvuvg3Bf+ E7GwDlT+5o9kCPY4yHtSDfFDfLD7rsXfktl8w4nz3ooICbQdhG4eaTFp3SGlUVaWtWAg HjOnFZb2561xTz2LBF6sbv+ZA+wRb/nrndXqUuFiqhdbrnIlID59I7BMILLQhYx1F5Hj L0Gw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=TkoBdE0X3JiudIF9hpBBDC0wbNFTzIx5OXQ++chrLeo=; b=KxFedH6RGKufoNZQtk84V9FeLMxwqx1zA7p8/FzVoDpqNLlMifsG0LW1q7p8uQFd8w e6Zk9P76yZFl6uMVMJKaDI+QKNj6RWetEJH6OYh0LVkl4o75gC3nUVJJcXkC4CnHUGaz 82SXFGAjpOiD+x27jBulCFXnf0fw8MmKnPcUJVw8SZE3XDeUaUOpDygYoHdnVo5E9caf mUmg+alMiGFfQ8KayDwKuXvzlo8tNgWR6utr05DEsHm7MXrxfhbPI+n6ylazh7unz75m Vbll25l+JNPm/JL0RwLfsHmfhJ2PeNH2hN4/2RxV3GlYtuYNyODieHgYH09WVg6dy82e NkvA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=K7t8DRab; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id t3-20020a1709027fc300b001a9770780b3si586592plb.258.2023.04.23.07.18.20; Sun, 23 Apr 2023 07:18:34 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=K7t8DRab; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230324AbjDWOPH (ORCPT + 99 others); Sun, 23 Apr 2023 10:15:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230305AbjDWOOr (ORCPT ); Sun, 23 Apr 2023 10:14:47 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 007C7359E for ; Sun, 23 Apr 2023 07:14:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=TkoBdE0X3JiudIF9hpBBDC0wbNFTzIx5OXQ++chrLeo=; b=K7t8DRab4ba2O6sQ8flMCap/jg MbIBrWb2oJRrYL+zIaN6wsWzQKvFw3XPIMbWoR+ft1KLS8AC16xbBEVtcZqZ29N3ACQz29GOCaSr8 XibuFKF/stNWtQ8BBdo8HQXPcdOtOMuQu3W4Fkaf4s8WD5Iob0R3wZaMn8UeTQz0I7qRWFI0ILxZw 5UtY8Onr6TcbCuX2HPs0tPcGSh08858GNfxfXTvuzmNzV2unIuLOtpMdZ4b9IY2Zks5SFvAY1HKb2 ulgAF8P7luDZi6fvelSzxi3nAhfFnS+LTAVRSUUzFsUI/BARCZtZgageWILE2q46M1/xc3T6Ry2OY m7Z23uWA==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaSt-00ANVs-1f; Sun, 23 Apr 2023 16:13:19 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 24/40] drm/amd/display: add CRTC 3D LUT support to amd color pipeline Date: Sun, 23 Apr 2023 13:10:36 -0100 Message-Id: <20230423141051.702990-25-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763976952600383965?= X-GMAIL-MSGID: =?utf-8?q?1763976952600383965?= Map DRM CRTC 3D LUT in the atomic color mgmt pipeline to DC (post-blending). 3D LUT works better in a non-linear color space, therefore using a degamma to linearize the input space may produce unexpected results. The next patch introduces shaper LUT support that can be used to delinearize the color space before applying 3D LUT conversion. Signed-off-by: Melissa Wen --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 +- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 5 + .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 185 +++++++++++++++--- 3 files changed, 174 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 6b40e17892e5..760080e4a4da 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -9945,7 +9945,13 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n"); goto fail; } - +#ifdef CONFIG_STEAM_DECK + ret = amdgpu_dm_verify_lut3d_size(adev, new_crtc_state); + if (ret) { + DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n"); + goto fail; + } +#endif if (!new_crtc_state->enable) continue; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 5faf4fc87701..b9840c1f3cdf 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -894,9 +894,14 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); +#ifdef CONFIG_STEAM_DECK /* 3D LUT max size is 17x17x17 */ #define MAX_COLOR_3DLUT_ENTRIES 4913 #define MAX_COLOR_3DLUT_BITDEPTH 12 +int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev, + const struct drm_crtc_state *crtc_state); +#endif + /* 1D LUT degamma, regamma and shaper*/ #define MAX_COLOR_LUT_ENTRIES 4096 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 99b1738c98d3..25010fa19bc8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -332,6 +332,117 @@ static int amdgpu_dm_set_atomic_regamma(struct dc_stream_state *stream, return ret; } +/** + * __set_input_tf - calculates the input transfer function based on expected + * input space. + * @func: transfer function + * @lut: lookup table that defines the color space + * @lut_size: size of respective lut. + * + * Returns: + * 0 in case of success. -ENOMEM if fails. + */ +static int __set_input_tf(struct dc_transfer_func *func, + const struct drm_color_lut *lut, uint32_t lut_size) +{ + struct dc_gamma *gamma = NULL; + bool res; + + gamma = dc_create_gamma(); + if (!gamma) + return -ENOMEM; + + gamma->type = GAMMA_CUSTOM; + gamma->num_entries = lut_size; + + __drm_lut_to_dc_gamma(lut, gamma, false); + + res = mod_color_calculate_degamma_params(NULL, func, gamma, true); + dc_gamma_release(&gamma); + + return res ? 0 : -ENOMEM; +} + +#ifdef CONFIG_STEAM_DECK +static void __to_dc_lut3d_color(struct dc_rgb *rgb, + const struct drm_color_lut lut, + int bit_precision) +{ + rgb->red = drm_color_lut_extract(lut.red, bit_precision); + rgb->green = drm_color_lut_extract(lut.green, bit_precision); + rgb->blue = drm_color_lut_extract(lut.blue, bit_precision); +} + +static void __drm_3dlut_to_dc_3dlut(const struct drm_color_lut *lut, + uint32_t lut3d_size, + struct tetrahedral_params *params, + bool use_tetrahedral_9, + int bit_depth) +{ + struct dc_rgb *lut0; + struct dc_rgb *lut1; + struct dc_rgb *lut2; + struct dc_rgb *lut3; + int lut_i, i; + + + if (use_tetrahedral_9) { + lut0 = params->tetrahedral_9.lut0; + lut1 = params->tetrahedral_9.lut1; + lut2 = params->tetrahedral_9.lut2; + lut3 = params->tetrahedral_9.lut3; + } else { + lut0 = params->tetrahedral_17.lut0; + lut1 = params->tetrahedral_17.lut1; + lut2 = params->tetrahedral_17.lut2; + lut3 = params->tetrahedral_17.lut3; + } + + for (lut_i = 0, i = 0; i < lut3d_size - 4; lut_i++, i += 4) { + /* We should consider the 3dlut RGB values are distributed + * along four arrays lut0-3 where the first sizes 1229 and the + * other 1228. The bit depth supported for 3dlut channel is + * 12-bit, but DC also supports 10-bit. + * + * TODO: improve color pipeline API to enable the userspace set + * bit depth and 3D LUT size/stride, as specified by VA-API. + */ + __to_dc_lut3d_color(&lut0[lut_i], lut[i], bit_depth); + __to_dc_lut3d_color(&lut1[lut_i], lut[i + 1], bit_depth); + __to_dc_lut3d_color(&lut2[lut_i], lut[i + 2], bit_depth); + __to_dc_lut3d_color(&lut3[lut_i], lut[i + 3], bit_depth); + } + /* lut0 has 1229 points (lut_size/4 + 1) */ + __to_dc_lut3d_color(&lut0[lut_i], lut[i], bit_depth); +} + +/* amdgpu_dm_atomic_lut3d - set DRM 3D LUT to DC stream + * @drm_lut3d: DRM CRTC (user) 3D LUT + * @drm_lut3d_size: size of 3D LUT + * @lut3d: DC 3D LUT + * + * Map DRM CRTC 3D LUT to DC 3D LUT and all necessary bits to program it + * on DCN MPC accordingly. + */ +static void amdgpu_dm_atomic_lut3d(const struct drm_color_lut *drm_lut, + uint32_t drm_lut3d_size, + struct dc_3dlut *lut) +{ + if (!drm_lut3d_size) { + lut->state.bits.initialized = 0; + } else { + /* Stride and bit depth are not programmable by API yet. + * Therefore, only supports 17x17x17 3D LUT (12-bit). + */ + lut->lut_3d.use_tetrahedral_9 = false; + lut->lut_3d.use_12bits = true; + lut->state.bits.initialized = 1; + __drm_3dlut_to_dc_3dlut(drm_lut, drm_lut3d_size, &lut->lut_3d, + lut->lut_3d.use_tetrahedral_9, + MAX_COLOR_3DLUT_BITDEPTH); + } +} + /* amdgpu_dm_atomic_shaper_lut3d - set DRM CRTC shaper LUT and 3D LUT to DC * interface * @dc: Display Core control structure @@ -355,7 +466,7 @@ static int amdgpu_dm_atomic_shaper_lut3d(struct dc *dc, { struct dc_3dlut *lut3d_func; struct dc_transfer_func *func_shaper; - bool acquire = drm_shaper_size && drm_lut3d_size; + bool acquire = drm_shaper_size || drm_lut3d_size; lut3d_func = (struct dc_3dlut *)stream->lut3d_func; func_shaper = (struct dc_transfer_func *)stream->func_shaper; @@ -369,42 +480,56 @@ static int amdgpu_dm_atomic_shaper_lut3d(struct dc *dc, return DC_ERROR_UNEXPECTED; } - stream->lut3d_func = lut3d_func; stream->func_shaper = func_shaper; + stream->lut3d_func = lut3d_func; + + if (!acquire) + return 0; + + /* We don't get DRM shaper LUT yet. We assume the input color + * space is already delinearized, so we don't need a shaper LUT + * and we can just BYPASS. + */ + func_shaper->type = TF_TYPE_BYPASS; + func_shaper->tf = TRANSFER_FUNCTION_LINEAR; + amdgpu_dm_atomic_lut3d(drm_lut3d, drm_lut3d_size, lut3d_func); return 0; } /** - * __set_input_tf - calculates the input transfer function based on expected - * input space. - * @func: transfer function - * @lut: lookup table that defines the color space - * @lut_size: size of respective lut. + * amdgpu_dm_verify_lut3d_size - verifies if 3D LUT is supported and if DRM 3D + * LUT matches the hw supported size + * @adev: amdgpu device + * @crtc_state: the DRM CRTC state + * + * Verifies if post-blending (MPC) 3D LUT is supported by the HW (DCN 3.0 or + * newer) and if the DRM 3D LUT matches the supported size. * * Returns: - * 0 in case of success. -ENOMEM if fails. + * 0 on success. -EINVAL if lut size are invalid. */ -static int __set_input_tf(struct dc_transfer_func *func, - const struct drm_color_lut *lut, uint32_t lut_size) +int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev, + const struct drm_crtc_state *crtc_state) { - struct dc_gamma *gamma = NULL; - bool res; + const struct drm_color_lut *lut3d = NULL; + struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc_state); + uint32_t exp_size, size; - gamma = dc_create_gamma(); - if (!gamma) - return -ENOMEM; + exp_size = adev->dm.dc->caps.color.mpc.num_3dluts ? + MAX_COLOR_3DLUT_ENTRIES : 0; - gamma->type = GAMMA_CUSTOM; - gamma->num_entries = lut_size; - - __drm_lut_to_dc_gamma(lut, gamma, false); + lut3d = __extract_blob_lut(acrtc_state->lut3d, &size); - res = mod_color_calculate_degamma_params(NULL, func, gamma, true); - dc_gamma_release(&gamma); + if (lut3d && size != exp_size) { + DRM_DEBUG_DRIVER("Invalid Gamma 3D LUT size. Should be %u but got %u.\n", + exp_size, size); + return -EINVAL; + } - return res ? 0 : -ENOMEM; + return 0; } +#endif /** * amdgpu_dm_verify_lut_sizes - verifies if DRM luts match the hw supported sizes @@ -477,6 +602,16 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc, bool has_regamma, has_degamma; bool is_legacy; int r; +#ifdef CONFIG_STEAM_DECK + const struct drm_color_lut *lut3d; + uint32_t lut3d_size; + + r = amdgpu_dm_verify_lut3d_size(adev, &crtc->base); + if (r) + return r; + + lut3d = __extract_blob_lut(crtc->lut3d, &lut3d_size); +#endif r = amdgpu_dm_verify_lut_sizes(&crtc->base); if (r) @@ -525,10 +660,14 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc, if (r) return r; } else { +#ifdef CONFIG_STEAM_DECK + lut3d_size = lut3d != NULL ? lut3d_size : 0; r = amdgpu_dm_atomic_shaper_lut3d(adev->dm.dc, ctx, stream, - NULL, 0, NULL, 0); + NULL, 0, + lut3d, lut3d_size); if (r) return r; +#endif /* Note: OGAM is disabled if 3D LUT is successfully programmed. * See params and set_output_gamma in * dcn30_set_output_transfer_func() From patchwork Sun Apr 23 14:10:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86758 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2241208vqo; Sun, 23 Apr 2023 08:09:06 -0700 (PDT) X-Google-Smtp-Source: AKy350bhiZWj6mg/ewDeU2/Q2FvzzDRnpNBhFlima1DswKhm23TkrTZjzuEJ15vxSRkrc/uWX5o5 X-Received: by 2002:a05:6a00:23c4:b0:626:29ed:941f with SMTP id g4-20020a056a0023c400b0062629ed941fmr15849013pfc.5.1682262546258; Sun, 23 Apr 2023 08:09:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682262546; cv=none; d=google.com; s=arc-20160816; b=ut03e5FY5h9jJh1gQjP9DRA0GPIWonePQrU90BpedUZxVzjtmEW3w2BQDG9zpaquv5 q6cxeO1dBcJCE1qLrRBTO1aYOLSPB8HwhDpgjCou7QJtauiGgnJcjiwdRwii/TWrOzMe ixH6MDJqNsXKrcrIIdi+8l7ljETX1EKkCrTDIBIEaZzghGCkWdEf2J1mWhl10UqVcOGP 9h03PvDJuFIQlzWxTdDknZuwuvYpRPu05TXnfilye84iCNHznAaHLez6RvoQhRuQ35Tu Ih2hUnsJIzrwXdXBPUl0nIAo8zv95oula18mVhO8lmNgkCOFbrdDm8L+qPagD3L18RhE 75Yw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=T0QU+rn3vH/vhCGh2w+pB+FknzjEXDis7z0wQd69Ucg=; b=iK1LnMRpGRGIFaPVNaGPx5RF+Q4FzA5t0PE0zvFJ/zFd/7iLZwl/JCmfSG6+b6hsPe 2BPPfPLPYO1TWdjbGYDnjqDVJrt+ecJyOX9f5BZcTPrn66d1EBcPz/LgCLptAymIIeqf EtV5q8sVbCxqchAPKnw4hqN1rvtYIBFqZPq4opogCcPur/SpyG1lR/6XsoK0w40PkzoG x8pKBs3PiEIw6nD0cQuFmO/U5VaPM7w+tGXNSChGSPaCXm89hk6oioSAAzXnK11jZYgA dOvn59at6iL1pBFBiXNqP17yg4LL+cRs6AfnyvojcPlpgO3tIdqE3grVSU1/ZxoxspRo mWJA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=KsvdnIDg; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id b11-20020aa7950b000000b0063b843131b1si8882349pfp.324.2023.04.23.08.08.51; Sun, 23 Apr 2023 08:09:06 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=KsvdnIDg; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229604AbjDWOuL (ORCPT + 99 others); Sun, 23 Apr 2023 10:50:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230403AbjDWOuG (ORCPT ); Sun, 23 Apr 2023 10:50:06 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C092110FD for ; Sun, 23 Apr 2023 07:49:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=T0QU+rn3vH/vhCGh2w+pB+FknzjEXDis7z0wQd69Ucg=; b=KsvdnIDgtkN+mFU1/LngtyfA5d lPyshycpBtzRBocFDJHhbU6OKz0Nx9xNY/ss/256mIatnlh/+QjyHXA9VflaBhksFTaB2+LLTNqim nY/ibVox19zMD8loxRtvUGRZJ9OmAHZB6PpRd14AlUdYZnCthOWrN0HzO/DI563ikaSL5km9038kP bTpMqgm8XDDlxswpF2w5R38RZmWCbU0z4qhDSPA5IA19gP2siJ375VQ+1wex5YCQejDPDOOSxHJgf 6Er7CXzS621K2NtHFnotO0C0hgoJ62h2XqZsQH1BPurnaIyuhT93Yc9EJq/YbCDGaCyB8S46zZYh/ oqFL8WPg==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaSv-00ANVs-J8; Sun, 23 Apr 2023 16:13:21 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 25/40] drm/amd/display: decouple steps to reuse in CRTC shaper LUT support Date: Sun, 23 Apr 2023 13:10:37 -0100 Message-Id: <20230423141051.702990-26-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763980131391630899?= X-GMAIL-MSGID: =?utf-8?q?1763980131391630899?= Decouple steps of post-blending shaper LUT setup and LUT size validation according to HW caps as a preparation for DRM CRTC shaper LUT support. Signed-off-by: Melissa Wen --- .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 67 ++++++++++++++++--- 1 file changed, 58 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 25010fa19bc8..672ca5e9e59c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -443,6 +443,48 @@ static void amdgpu_dm_atomic_lut3d(const struct drm_color_lut *drm_lut, } } +/** + * __set_input_tf - calculates the input transfer function based on expected + * input space. + * @func: transfer function + * @lut: lookup table that defines the color space + * @lut_size: size of respective lut. + * + * Returns: + * 0 in case of success. -ENOMEM if fails. + */ +static int __set_input_tf(struct dc_transfer_func *func, + const struct drm_color_lut *lut, uint32_t lut_size) +{ + struct dc_gamma *gamma = NULL; + bool res; + + gamma = dc_create_gamma(); + if (!gamma) + return -ENOMEM; + + gamma->type = GAMMA_CUSTOM; + gamma->num_entries = lut_size; + + __drm_lut_to_dc_gamma(lut, gamma, false); + + res = mod_color_calculate_degamma_params(NULL, func, gamma, true); + dc_gamma_release(&gamma); + + return res ? 0 : -ENOMEM; +} + +static int amdgpu_dm_atomic_shaper_lut(struct dc_transfer_func *func_shaper) +{ + /* We don't get DRM shaper LUT yet. We assume the input color space is already + * delinearized, so we don't need a shaper LUT and we can just BYPASS + */ + func_shaper->type = TF_TYPE_BYPASS; + func_shaper->tf = TRANSFER_FUNCTION_LINEAR; + + return 0; +} + /* amdgpu_dm_atomic_shaper_lut3d - set DRM CRTC shaper LUT and 3D LUT to DC * interface * @dc: Display Core control structure @@ -486,15 +528,23 @@ static int amdgpu_dm_atomic_shaper_lut3d(struct dc *dc, if (!acquire) return 0; - /* We don't get DRM shaper LUT yet. We assume the input color - * space is already delinearized, so we don't need a shaper LUT - * and we can just BYPASS. - */ - func_shaper->type = TF_TYPE_BYPASS; - func_shaper->tf = TRANSFER_FUNCTION_LINEAR; amdgpu_dm_atomic_lut3d(drm_lut3d, drm_lut3d_size, lut3d_func); - return 0; + return amdgpu_dm_atomic_shaper_lut(func_shaper); +} + +/** + * amdgpu_dm_lut3d_size - get expected size according to hw color caps + * @adev: amdgpu device + * @lut_size: default size + * + * Return: + * lut_size if DC 3D LUT is supported, zero otherwise. + */ +static uint32_t amdgpu_dm_get_lut3d_size(struct amdgpu_device *adev, + uint32_t lut_size) +{ + return adev->dm.dc->caps.color.mpc.num_3dluts ? lut_size : 0; } /** @@ -516,8 +566,7 @@ int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev, struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc_state); uint32_t exp_size, size; - exp_size = adev->dm.dc->caps.color.mpc.num_3dluts ? - MAX_COLOR_3DLUT_ENTRIES : 0; + exp_size = amdgpu_dm_get_lut3d_size(adev, MAX_COLOR_3DLUT_ENTRIES); lut3d = __extract_blob_lut(acrtc_state->lut3d, &size); From patchwork Sun Apr 23 14:10:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86766 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2242098vqo; Sun, 23 Apr 2023 08:10:54 -0700 (PDT) X-Google-Smtp-Source: AKy350ad8tgi99SDPyASFgsb/y+LshzrPfe8mp433vz+W0qzOs/3WO9l1NPfPEeM7Owb1JCmkDel X-Received: by 2002:a05:6a00:1496:b0:63d:4407:b6c with SMTP id v22-20020a056a00149600b0063d44070b6cmr15784910pfu.7.1682262654463; Sun, 23 Apr 2023 08:10:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682262654; cv=none; d=google.com; s=arc-20160816; b=Vt1Ca7HNnuwKI6vmpbeNoyFVHFPFCyI48z2tD+4wjveHKWae79J9juwbAKz7crYob5 LrDrMCtLW5kQGF7C5r1hRqnyZpSt7erH+GMGOUkh2ibkj/et8rA9dRbq73HB1CHgehZc DfKBJiQqC2q8m82OuYuQaMAr0lAmpnKeKE3JsZpVD+oUTKDAEsgekR+CpTB0VoQWXWb5 QVI2R5/rL7xMO+bjwv/W4WuSsS94Iq0hvXSq/XAV/zrIf1KTBQnRDbr0hGWYBflLfAeQ pxOpX9+7UdK67il0Nb9OkXufZq3H1mHgDpL8/znVv81iVk01zp+7x0IhksZgGMblop3v 1Mqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Muyaau4YvOlEED9C4uAM8ak2NdSxTNzeXN9VmH4gVg8=; b=EprT+W/7cH7PDRYMUZywMOULjlsmXUAuiCYqp0w+ypINNkrK25Pd9nMEXzl36GitEA 2JkgNvPH2BD4mp2RLOEBdO8Q6HS3+RHc6QbVD12dq/OAUu0EHnhgQcYFSeGPHJhpAjk/ tx8tL/fNCp0PkP/vrrhYlgeyqfOdBDo9TDNiQQqZGseRg/dmy7e90tGRpJQBgb4scCkX ofQ9/R8hTKFpR96T+lywQToHZdmGMLotxY63RzBy/2SMP7qd17SdTL1GzUvUqXlLqOQ9 r9ZI01ylrP93H0yBtX/N7MzvIMY9sSY9pma1S3OZYnX/YFfXqvKnSHjObQxznJqGAQTe carQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b="RIi/I6X7"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id b11-20020aa7950b000000b0063b843131b1si8882349pfp.324.2023.04.23.08.10.39; Sun, 23 Apr 2023 08:10:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b="RIi/I6X7"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229694AbjDWOt2 (ORCPT + 99 others); Sun, 23 Apr 2023 10:49:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55326 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230325AbjDWOtX (ORCPT ); Sun, 23 Apr 2023 10:49:23 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 57FE82D50 for ; Sun, 23 Apr 2023 07:49:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=Muyaau4YvOlEED9C4uAM8ak2NdSxTNzeXN9VmH4gVg8=; b=RIi/I6X7R9U2EXTQ/46iYBOgt/ Q16kxpKaEe9OCsrh6q1xeW46Kdite61TIWCNgJO7BP2xVORvhdoAlVp/FPTGO1UEsL0YSP6HvsX6v 3DVGj2y8myl1uSjUAxLlH3PWtJPvmgwJQts9Jk9zsMX/3ZhuXm5nEupcNFflaIaSy/aL6UNK4x0/n PHuvrrunJQIMhtBoZovf0grLgxPWY1blvEKTahV9ca8F1GuZkloaqyjbURld8CZJ7A5l+AYaeFDzd nrjgbi5Uuf6UaEvPqJKVA/r8qHHpGLEnnXsh2aub327MWsVnlW/v5DIy0yOLKtwbrayNuePqlougm yQArAa1g==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaSy-00ANVs-8n; Sun, 23 Apr 2023 16:13:24 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 26/40] drm/amd/display: add CRTC shaper LUT support to amd color pipeline Date: Sun, 23 Apr 2023 13:10:38 -0100 Message-Id: <20230423141051.702990-27-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763980245107457388?= X-GMAIL-MSGID: =?utf-8?q?1763980245107457388?= Now, we can use DRM CRTC shaper LUT to delinearize and/or normalize the color space for a more efficient 3D LUT support (so far, only for DRM atomic color mgmt). If a degamma 1D LUT is passed to linearize the color space, a custom shaper 1D LUT can be used before applying 3D LUT. NOTE: although DRM CRTC shaper and 3D LUTs are optional properties, from our tests, AMD HW doesn't allow 3D LUT when shaper LUT is set to BYPASS (without user shaper LUT) Signed-off-by: Melissa Wen --- .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 81 +++++++++---------- 1 file changed, 38 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 672ca5e9e59c..ff29be3929af 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -443,46 +443,26 @@ static void amdgpu_dm_atomic_lut3d(const struct drm_color_lut *drm_lut, } } -/** - * __set_input_tf - calculates the input transfer function based on expected - * input space. - * @func: transfer function - * @lut: lookup table that defines the color space - * @lut_size: size of respective lut. - * - * Returns: - * 0 in case of success. -ENOMEM if fails. - */ -static int __set_input_tf(struct dc_transfer_func *func, - const struct drm_color_lut *lut, uint32_t lut_size) +static int amdgpu_dm_atomic_shaper_lut(const struct drm_color_lut *shaper_lut, + uint32_t shaper_size, + struct dc_transfer_func *func_shaper) { - struct dc_gamma *gamma = NULL; - bool res; - - gamma = dc_create_gamma(); - if (!gamma) - return -ENOMEM; - - gamma->type = GAMMA_CUSTOM; - gamma->num_entries = lut_size; - - __drm_lut_to_dc_gamma(lut, gamma, false); - - res = mod_color_calculate_degamma_params(NULL, func, gamma, true); - dc_gamma_release(&gamma); + int ret = 0; - return res ? 0 : -ENOMEM; -} + if (shaper_size) { + /* If DRM shaper LUT is set, we assume a linear color space + * (linearized by DRM degamma 1D LUT or not) + */ + func_shaper->type = TF_TYPE_DISTRIBUTED_POINTS; + func_shaper->tf = TRANSFER_FUNCTION_LINEAR; -static int amdgpu_dm_atomic_shaper_lut(struct dc_transfer_func *func_shaper) -{ - /* We don't get DRM shaper LUT yet. We assume the input color space is already - * delinearized, so we don't need a shaper LUT and we can just BYPASS - */ - func_shaper->type = TF_TYPE_BYPASS; - func_shaper->tf = TRANSFER_FUNCTION_LINEAR; + ret = __set_output_tf(func_shaper, shaper_lut, shaper_size, false); + } else { + func_shaper->type = TF_TYPE_BYPASS; + func_shaper->tf = TRANSFER_FUNCTION_LINEAR; + } - return 0; + return ret; } /* amdgpu_dm_atomic_shaper_lut3d - set DRM CRTC shaper LUT and 3D LUT to DC @@ -530,7 +510,8 @@ static int amdgpu_dm_atomic_shaper_lut3d(struct dc *dc, amdgpu_dm_atomic_lut3d(drm_lut3d, drm_lut3d_size, lut3d_func); - return amdgpu_dm_atomic_shaper_lut(func_shaper); + return amdgpu_dm_atomic_shaper_lut(drm_shaper_lut, + drm_shaper_size, func_shaper); } /** @@ -562,12 +543,22 @@ static uint32_t amdgpu_dm_get_lut3d_size(struct amdgpu_device *adev, int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev, const struct drm_crtc_state *crtc_state) { - const struct drm_color_lut *lut3d = NULL; struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc_state); + const struct drm_color_lut *shaper = NULL, *lut3d = NULL; uint32_t exp_size, size; - exp_size = amdgpu_dm_get_lut3d_size(adev, MAX_COLOR_3DLUT_ENTRIES); + /* shaper LUT is only available if 3D LUT color caps*/ + exp_size = amdgpu_dm_get_lut3d_size(adev, MAX_COLOR_LUT_ENTRIES); + shaper = __extract_blob_lut(acrtc_state->shaper_lut, &size); + if (shaper && size != exp_size) { + DRM_DEBUG_DRIVER( + "Invalid Shaper LUT size. Should be %u but got %u.\n", + exp_size, size); + return -EINVAL; + } + + exp_size = amdgpu_dm_get_lut3d_size(adev, MAX_COLOR_3DLUT_ENTRIES); lut3d = __extract_blob_lut(acrtc_state->lut3d, &size); if (lut3d && size != exp_size) { @@ -652,14 +643,15 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc, bool is_legacy; int r; #ifdef CONFIG_STEAM_DECK - const struct drm_color_lut *lut3d; - uint32_t lut3d_size; + const struct drm_color_lut *shaper_lut, *lut3d; + uint32_t shaper_size, lut3d_size; r = amdgpu_dm_verify_lut3d_size(adev, &crtc->base); if (r) return r; lut3d = __extract_blob_lut(crtc->lut3d, &lut3d_size); + shaper_lut = __extract_blob_lut(crtc->shaper_lut, &shaper_size); #endif r = amdgpu_dm_verify_lut_sizes(&crtc->base); @@ -711,11 +703,14 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc, } else { #ifdef CONFIG_STEAM_DECK lut3d_size = lut3d != NULL ? lut3d_size : 0; + shaper_size = shaper_lut != NULL ? shaper_size : 0; r = amdgpu_dm_atomic_shaper_lut3d(adev->dm.dc, ctx, stream, - NULL, 0, + shaper_lut, shaper_size, lut3d, lut3d_size); - if (r) + if (r) { + DRM_DEBUG_DRIVER("Failed on shaper/3D LUTs setup\n"); return r; + } #endif /* Note: OGAM is disabled if 3D LUT is successfully programmed. * See params and set_output_gamma in From patchwork Sun Apr 23 14:10:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86734 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2221844vqo; Sun, 23 Apr 2023 07:25:15 -0700 (PDT) X-Google-Smtp-Source: AKy350b8WZBxsBqtMRjj3pLulvNmRZ/eH6LqoUAjik2SUVv2MD2IOusESeG29b8/itoiCm8E+M3O X-Received: by 2002:a05:6a00:248f:b0:63b:6933:a30d with SMTP id c15-20020a056a00248f00b0063b6933a30dmr15061116pfv.25.1682259914829; Sun, 23 Apr 2023 07:25:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682259914; cv=none; d=google.com; s=arc-20160816; b=NGGQukT1OOLiDAcwqwgG1flSiQFwtj4alkLmX7rIwaov7495Kwry6kAUBEPRvCFvIe GYid6r5jkczW1osrX9lcLLgoYAWWqdfjOlKxetQe9FlNsYppd4u5UEgwXMvFWF7s/+RQ D/TAa4vp1iWMPyN8mbW+K/RXnc8GvMKzfxflz3ZJP0p3YqjErA0WPdVOrAVJS8e8Qj6k a3tyogYejnZiY3OaLp5JO1kpnEjyOAOY1ykCEHg8K4jMxGeGq8W9Jr/9HFY+qfyQ9l3y T2BXJI8Njpk5xF2T5CllFornYMmFuchxTNFz6jiAFne3vRURV/dgLCyc4V0J4+unkdhM a93A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Hj+41OAGChCkaIi9YXRqlEYXZ5g/+UsZBvfDycRkUvs=; b=sEUUKJ9aRSHj0heqxM3HuhZncbYSSUSnNpgcC/iFD6QIe6OJKSaX4MFZYsbeefczJ4 iYcpAhll6VVi/ROqWgNmg3dKeTpXbVqJoqbr+8UlJP10dJqpcPMeEl7pVWiUIyxZMKGh JFXAOY0uRJyiSu/GdojsJ29OZDyHhhn1M7vbBj/3RwZ0nauKCaLDWQnDdW7k59L7rZYk lfzml9uFmyciy0m4wFq8dEhB0AGyK4YXe3Uq5d5IYsV+or/Obdo0f+B4bK0zYHP+9eTE qR4SFSzwlWbgXYNEFrfkezkZpNoCPzG+HviOrl6n3aLjybpaInvkxg7/kzLTXwgZyIDL ZN6Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=AQBnmpqH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id z22-20020aa79f96000000b0063b506e148asi6588380pfr.90.2023.04.23.07.25.00; Sun, 23 Apr 2023 07:25:14 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=AQBnmpqH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230326AbjDWOP3 (ORCPT + 99 others); Sun, 23 Apr 2023 10:15:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34360 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230342AbjDWOPV (ORCPT ); Sun, 23 Apr 2023 10:15:21 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6751330F5 for ; Sun, 23 Apr 2023 07:14:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=Hj+41OAGChCkaIi9YXRqlEYXZ5g/+UsZBvfDycRkUvs=; b=AQBnmpqHLmaGWXY8B+vvIMQ5fI FsT0iFt+CjslQ7cEGoxl5K2M+FTdDpUAE464kVGnbtKcrwodU4Fa3RwE1+wj2mUDdr0Ata/aqt1OG ie1fkBpZFsFebdeOabZum2K/5ateXqXV+un/E5r6SmgwKPbpYAbotaH4PPQfti7K5bbrrQmoIqK1+ bL+Uh06UrTyrUCWImEsm4bsY6cXMPU3w3cmksPrJB3QaDazsTdT7Qiq3X8IK1RtU0MNhFKuDlcWnF nbgWCSheuGPQaW2ADYc7XKBg2xwcq384WVArUiI0qhWKruD79KY/RKvcuPwLyhNvPR0rVyz8DA6Cz QXAsGmPg==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaT1-00ANVs-I6; Sun, 23 Apr 2023 16:13:27 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , linux-kernel@vger.kernel.org Subject: [RFC PATCH 27/40] drm/amd/display: add CRTC regamma TF support Date: Sun, 23 Apr 2023 13:10:39 -0100 Message-Id: <20230423141051.702990-28-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763977372402686528?= X-GMAIL-MSGID: =?utf-8?q?1763977372402686528?= From: Joshua Ashton Add predefined transfer function programming. There is no out gamma ROM, but we can use AMD color modules to program LUT parameters from a predefined TF and an empty regamma LUT (or power LUT parameters with predefined TF setup). Signed-off-by: Joshua Ashton --- .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 60 ++++++++++++++----- 1 file changed, 44 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index ff29be3929af..55aa876a5008 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -268,16 +268,18 @@ static int __set_output_tf(struct dc_transfer_func *func, struct calculate_buffer cal_buffer = {0}; bool res; - ASSERT(lut && lut_size == MAX_COLOR_LUT_ENTRIES); - cal_buffer.buffer_index = -1; - gamma = dc_create_gamma(); - if (!gamma) - return -ENOMEM; + if (lut_size) { + ASSERT(lut && lut_size == MAX_COLOR_LUT_ENTRIES); - gamma->num_entries = lut_size; - __drm_lut_to_dc_gamma(lut, gamma, false); + gamma = dc_create_gamma(); + if (!gamma) + return -ENOMEM; + + gamma->num_entries = lut_size; + __drm_lut_to_dc_gamma(lut, gamma, false); + } if (func->tf == TRANSFER_FUNCTION_LINEAR) { /* @@ -285,30 +287,34 @@ static int __set_output_tf(struct dc_transfer_func *func, * on top of a linear input. But degamma params can be used * instead to simulate this. */ - gamma->type = GAMMA_CUSTOM; + if (gamma) + gamma->type = GAMMA_CUSTOM; res = mod_color_calculate_degamma_params(NULL, func, - gamma, true); + gamma, gamma != NULL); } else { /* * Assume sRGB. The actual mapping will depend on whether the * input was legacy or not. */ - gamma->type = GAMMA_CS_TFM_1D; - res = mod_color_calculate_regamma_params(func, gamma, false, + if (gamma) + gamma->type = GAMMA_CS_TFM_1D; + res = mod_color_calculate_regamma_params(func, gamma, gamma != NULL, has_rom, NULL, &cal_buffer); } - dc_gamma_release(&gamma); + if (gamma) + dc_gamma_release(&gamma); return res ? 0 : -ENOMEM; } static int amdgpu_dm_set_atomic_regamma(struct dc_stream_state *stream, const struct drm_color_lut *regamma_lut, - uint32_t regamma_size, bool has_rom) + uint32_t regamma_size, bool has_rom, + enum dc_transfer_func_predefined tf) { int ret = 0; - if (regamma_size) { + if (regamma_size || tf != TRANSFER_FUNCTION_LINEAR) { /* CRTC RGM goes into RGM LUT. * * Note: there is no implicit sRGB regamma here. We are using @@ -316,7 +322,7 @@ static int amdgpu_dm_set_atomic_regamma(struct dc_stream_state *stream, * from a linear base. */ stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS; - stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR; + stream->out_transfer_func->tf = tf; ret = __set_output_tf(stream->out_transfer_func, regamma_lut, regamma_size, has_rom); @@ -364,6 +370,25 @@ static int __set_input_tf(struct dc_transfer_func *func, } #ifdef CONFIG_STEAM_DECK +static enum dc_transfer_func_predefined drm_tf_to_dc_tf(enum drm_transfer_function drm_tf) +{ + switch (drm_tf) + { + default: + case DRM_TRANSFER_FUNCTION_DEFAULT: return TRANSFER_FUNCTION_LINEAR; + case DRM_TRANSFER_FUNCTION_SRGB: return TRANSFER_FUNCTION_SRGB; + + case DRM_TRANSFER_FUNCTION_BT709: return TRANSFER_FUNCTION_BT709; + case DRM_TRANSFER_FUNCTION_PQ: return TRANSFER_FUNCTION_PQ; + case DRM_TRANSFER_FUNCTION_LINEAR: return TRANSFER_FUNCTION_LINEAR; + case DRM_TRANSFER_FUNCTION_UNITY: return TRANSFER_FUNCTION_UNITY; + case DRM_TRANSFER_FUNCTION_HLG: return TRANSFER_FUNCTION_HLG; + case DRM_TRANSFER_FUNCTION_GAMMA22: return TRANSFER_FUNCTION_GAMMA22; + case DRM_TRANSFER_FUNCTION_GAMMA24: return TRANSFER_FUNCTION_GAMMA24; + case DRM_TRANSFER_FUNCTION_GAMMA26: return TRANSFER_FUNCTION_GAMMA26; + } +} + static void __to_dc_lut3d_color(struct dc_rgb *rgb, const struct drm_color_lut lut, int bit_precision) @@ -640,6 +665,7 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc, const struct drm_color_lut *degamma_lut, *regamma_lut; uint32_t degamma_size, regamma_size; bool has_regamma, has_degamma; + enum dc_transfer_func_predefined tf = TRANSFER_FUNCTION_LINEAR; bool is_legacy; int r; #ifdef CONFIG_STEAM_DECK @@ -652,6 +678,8 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc, lut3d = __extract_blob_lut(crtc->lut3d, &lut3d_size); shaper_lut = __extract_blob_lut(crtc->shaper_lut, &shaper_size); + + tf = drm_tf_to_dc_tf(crtc->gamma_tf); #endif r = amdgpu_dm_verify_lut_sizes(&crtc->base); @@ -718,7 +746,7 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc, */ regamma_size = has_regamma ? regamma_size : 0; r = amdgpu_dm_set_atomic_regamma(stream, regamma_lut, - regamma_size, has_rom); + regamma_size, has_rom, tf); if (r) return r; } From patchwork Sun Apr 23 14:10:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86761 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2241776vqo; Sun, 23 Apr 2023 08:10:09 -0700 (PDT) X-Google-Smtp-Source: AKy350bUvS2od7ZK58y6b2sap3OI3MbMus/n9Aqieh6lxSguaJnfzib6N3nH2QS7E2W/vBOv4lse X-Received: by 2002:a17:90a:ff0e:b0:249:78bb:2bea with SMTP id ce14-20020a17090aff0e00b0024978bb2beamr10734400pjb.32.1682262609139; Sun, 23 Apr 2023 08:10:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682262609; cv=none; d=google.com; s=arc-20160816; b=LiWM/RnA2F6xiAkZ2A5XWkbuVGMBED9Hhk32YTJnnVLViqG2s8bp4btrvgBO9pa2cg XASQ5J5NUNMjzgBiF2WSZLV+AQ22r+dPB8Dt3vw2VSTAieTjmUrG3rhMHb51YFYxg2Po sPBFYeaFcnKLOjItNK46JP2FVtbhKxbNF5cZwxevuPRjaspr/H2rjWPe+7Qcu2hFojOd tvZMgis8ozmthbNzHkhNapIjGAXv/K6DwvZd2MVb3mk/aUOdEJTobOnWRKLWeQ3bsM7x o0O8ttbII/SnpvVWIxjaLSun2mfw7N/H1i9yatK4cSndH5EVI3qgt6jx35FM+S7tQcgT ykiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=8bT2ob0F8OaOVr4E4QYrwsso9uTEpOktmlUklSt8S/Q=; b=l+sTlG4qnbRbkqML7zPj3SiBuvSABJbkSsdwPeaRNsbJ6t/EdiLd8LCbLGrN9ZWVdz SwxXZ+qbxIxgKSJISCaBilgzfMVHxJnCea7MjgZYtoDy9aedx1f25mDNrsBbQQ7uE8mZ J7DhdLa6Z74kzItN+LhAhmeOUA1p7WiAZm7Ct8sazgahU1XHLMJkKsJgk5Uzb/Q+Q3Mb yuVoevRkZXCFGn4CSuoZO0/g4bX2HuPOF7v4c0szBSMXoqs3ozTYtOzvjbaJ5aafEY44 SehW5f1842+q1LFbvKTc46aRtLRLMU0JTQ8A9sMHYeSXO0a2fLfhvSdKCzUeRgLShL65 pC+w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=H0v1vztI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id a8-20020a17090a854800b0024785ccbc3csi9418299pjw.131.2023.04.23.08.09.54; Sun, 23 Apr 2023 08:10:09 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=H0v1vztI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230431AbjDWOqt (ORCPT + 99 others); Sun, 23 Apr 2023 10:46:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51972 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230418AbjDWOqo (ORCPT ); Sun, 23 Apr 2023 10:46:44 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 90F7EE7C for ; Sun, 23 Apr 2023 07:46:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=8bT2ob0F8OaOVr4E4QYrwsso9uTEpOktmlUklSt8S/Q=; b=H0v1vztIlXOcj+FbNVovVSfxmS uLfgMVTH0Tki6M+t52HV7T8tsXMELFNbTc3nzcvA7RlIaoHnDJeegiil6v16jjibd/nQz/9L4qMJX wauTFprY5PTOrGaOSGSplXdDZUyQUHu/vGwbL5lwB5tGqmIzoNlOQ1NkmE70Gpmj03LNksO09AYX9 SFNmhLnRr9IPKs7Y1KiMqzrJ5wiKkpi3BPbmThmETI5lrb9MWUwiO+Kfg/WLQK6+/mnmQlqbRTsnJ ySloYFH2oXHJLsYK4stG70OUmDEi48Tw/b30wioMj19hLgbrzLZAJZenJGrDWEFhh9qdIze1upjSW HO2SnzWQ==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaT4-00ANVs-5O; Sun, 23 Apr 2023 16:13:30 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , linux-kernel@vger.kernel.org Subject: [RFC PATCH 28/40] drm/amd/display: set sdr_ref_white_level to 80 for out_transfer_func Date: Sun, 23 Apr 2023 13:10:40 -0100 Message-Id: <20230423141051.702990-29-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763980197582408054?= X-GMAIL-MSGID: =?utf-8?q?1763980197582408054?= From: Joshua Ashton Otherwise this is just initialized to 0. This needs to actually have a value so that compute_curve can work for PQ EOTF. Signed-off-by: Joshua Ashton --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 55aa876a5008..6e7271065a56 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -323,6 +323,7 @@ static int amdgpu_dm_set_atomic_regamma(struct dc_stream_state *stream, */ stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS; stream->out_transfer_func->tf = tf; + stream->out_transfer_func->sdr_ref_white_level = 80; ret = __set_output_tf(stream->out_transfer_func, regamma_lut, regamma_size, has_rom); From patchwork Sun Apr 23 14:10:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86774 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2252433vqo; Sun, 23 Apr 2023 08:35:24 -0700 (PDT) X-Google-Smtp-Source: AKy350YymFwvBoScYJp7O1qTlGwnQ3323gjTvkBPLTXZ/tYL/IdxUGKWdqt48Gdn0tpEpP8F75am X-Received: by 2002:a17:902:e74e:b0:1a5:309e:d209 with SMTP id p14-20020a170902e74e00b001a5309ed209mr4941875plf.42.1682264124066; Sun, 23 Apr 2023 08:35:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682264124; cv=none; d=google.com; s=arc-20160816; b=aj44NbVvj+wSxduYGQNeDaei9bq9NotqdewQU39iQ5E1b5nnVkgxtgqTgr/4OllFhU HON4GAaH2bh5VaIVFunXjndBvd957sA2H8H9O1jBM/2TBDiJmXRQmM9APdMbKbaSaVlp SZqWxcF0YG5atTZLo9dHcS7FhuMFweYedBjf5QoJDmclYeexJeegeNdjeTCGR/TW1dbQ UD9VlVdLEzQmFntIz6Ccwu3ss2qAHTIn73qYdQ2u8CmGIOnZ9lsnItYAib9J5kDQ61+c 6ykET4O0TG2h97+GcqQg1FlIa6CjTSMa79XF61Eyv9NhX+zlpSfhFB72mODe6EeL+NU2 hmSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=lxN4o+4K+4Z4seUWpOvL7AAr75VVAUYJY+xnqLiCvUc=; b=w404huhT21Kfez2IedzN4M01WGnAZ07U867A6m9WncwK993Qufk+adKfGPzHVq7fzE 9JRq9JXHfVDiaLOrhHhsSPQBhdWN1KAlWHGvkV4fq6CSYjPZN7Z3VQxGHDh0XJ+0r6o/ FMN1xmLlDWIn90H133KcJk9ho3nDqmKaP21IbikC2fGpPmfMWyX2WM8snspN6xXImhQI Ei/RJom5gHjB9CrPhahOrCT7BXmeYaUfDisZAyKpbtT2jNgv3K3FlRmqnQIHjxAwbGxV 8uhuUKQ9vz7xudo6/6SdZwOtppZe97+zzq7rnyCHQIqt11qo6/J4/3WzerUOHNAbIE6K 2NOA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=ldnqTfdy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id u17-20020a170903125100b001a6ce2cdb20si284568plh.244.2023.04.23.08.35.08; Sun, 23 Apr 2023 08:35:24 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=ldnqTfdy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230347AbjDWOqi (ORCPT + 99 others); Sun, 23 Apr 2023 10:46:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230326AbjDWOqg (ORCPT ); Sun, 23 Apr 2023 10:46:36 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24AF1E77 for ; Sun, 23 Apr 2023 07:46:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=lxN4o+4K+4Z4seUWpOvL7AAr75VVAUYJY+xnqLiCvUc=; b=ldnqTfdyEMGI4mbqShp9tr/liM YQTTbJw6WaTPud7IYSxZwA15m0J2bA8x23c73MjMq3kNtQd0Jt3KBobOZIBCzCb2XLvELGfbF/Qt7 eGDG9ZbCwoCkHFAKeP6qIoASRP+4hAHQqHkrEP+cEHDHNFSYvhmXDThVVCXcHMnApgb+tjAxqBGo6 6WAksnjMAdCXgRzIOxcu8T1hxp4gNNFaOl7PEijhMtUOop4Ao5ZSPsvN+N3pCUvbL17vhApJQ1xAn D+OXavQ94QlAL5RXXZVKQ6pgFQJoDRp+jeu2lzhWn/8vXDnUSLOqizYX5SuVqIKCsMhsokaJmtKSw DGzMjzdQ==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaT7-00ANVs-0P; Sun, 23 Apr 2023 16:13:33 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 29/40] drm/amd/display: add CRTC shaper TF support Date: Sun, 23 Apr 2023 13:10:41 -0100 Message-Id: <20230423141051.702990-30-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763981786365718967?= X-GMAIL-MSGID: =?utf-8?q?1763981786365718967?= Inspired by regamma TF, follow similar steps to add TF + 1D LUT for shaper func. Reuse gamma_tf property, since the driver doesn't support shaper and out gamma at the same time. We could rename gamma_tf, if necessary to avoid misunderstandings, or add a specific property for shaper lut. Signed-off-by: Melissa Wen --- .../drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 6e7271065a56..6a233380f284 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -470,19 +470,22 @@ static void amdgpu_dm_atomic_lut3d(const struct drm_color_lut *drm_lut, } static int amdgpu_dm_atomic_shaper_lut(const struct drm_color_lut *shaper_lut, + bool has_rom, + enum dc_transfer_func_predefined tf, uint32_t shaper_size, struct dc_transfer_func *func_shaper) { int ret = 0; - if (shaper_size) { + if (shaper_size || tf != TRANSFER_FUNCTION_LINEAR) { /* If DRM shaper LUT is set, we assume a linear color space * (linearized by DRM degamma 1D LUT or not) */ func_shaper->type = TF_TYPE_DISTRIBUTED_POINTS; - func_shaper->tf = TRANSFER_FUNCTION_LINEAR; + func_shaper->tf = tf; + func_shaper->sdr_ref_white_level = 80; /* hardcoded for now */ - ret = __set_output_tf(func_shaper, shaper_lut, shaper_size, false); + ret = __set_output_tf(func_shaper, shaper_lut, shaper_size, has_rom); } else { func_shaper->type = TF_TYPE_BYPASS; func_shaper->tf = TRANSFER_FUNCTION_LINEAR; @@ -509,12 +512,14 @@ static int amdgpu_dm_atomic_shaper_lut3d(struct dc *dc, struct dc_stream_state *stream, const struct drm_color_lut *drm_shaper_lut, uint32_t drm_shaper_size, + bool has_rom, + enum dc_transfer_func_predefined tf, const struct drm_color_lut *drm_lut3d, uint32_t drm_lut3d_size) { struct dc_3dlut *lut3d_func; struct dc_transfer_func *func_shaper; - bool acquire = drm_shaper_size || drm_lut3d_size; + bool acquire = drm_shaper_size || drm_lut3d_size || tf != TRANSFER_FUNCTION_LINEAR; lut3d_func = (struct dc_3dlut *)stream->lut3d_func; func_shaper = (struct dc_transfer_func *)stream->func_shaper; @@ -536,7 +541,7 @@ static int amdgpu_dm_atomic_shaper_lut3d(struct dc *dc, amdgpu_dm_atomic_lut3d(drm_lut3d, drm_lut3d_size, lut3d_func); - return amdgpu_dm_atomic_shaper_lut(drm_shaper_lut, + return amdgpu_dm_atomic_shaper_lut(drm_shaper_lut, has_rom, tf, drm_shaper_size, func_shaper); } @@ -735,6 +740,7 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc, shaper_size = shaper_lut != NULL ? shaper_size : 0; r = amdgpu_dm_atomic_shaper_lut3d(adev->dm.dc, ctx, stream, shaper_lut, shaper_size, + has_rom, tf, lut3d, lut3d_size); if (r) { DRM_DEBUG_DRIVER("Failed on shaper/3D LUTs setup\n"); From patchwork Sun Apr 23 14:10:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86768 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2242881vqo; Sun, 23 Apr 2023 08:12:34 -0700 (PDT) X-Google-Smtp-Source: AKy350ZxIkps77J9c1+26PPMg6Z/CSIwqpCTqbo+FXUYmeE+pk5G1ntsbuufeoFiFcJ6YAYP2kur X-Received: by 2002:a05:6a20:3d10:b0:f2:c7a5:26d8 with SMTP id y16-20020a056a203d1000b000f2c7a526d8mr9220737pzi.11.1682262753922; Sun, 23 Apr 2023 08:12:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682262753; cv=none; d=google.com; s=arc-20160816; b=tuzkHim9D1DZR4oUt3yrkEZbSv9RXqt8jCI6/nOteUTwXAXdw0+IRFhRBEyAR+jRaq vYVMmXPPPQm8w8W8F9aXRAayKSiSI+XJ1AEAaT101gt78bQnqwLNAy3QteXbDcNNOuqT eQSNvMVhZ5y9T6BuxUfcKjzz3yzTg7twJAkE/NPRzk8F5bkxNfOC9Svd7tXG+Nlcf/s3 grQ9pslrAuy5zLFfA/qvMXa506abWyssVCd1GS+mRFuYM8BGV11CVeZ0gLUp+QjSK+JY Fa7hjoOXSCQE1LufXVbWDkGsxew8Y7cUGTdrRuUs6VVH+vnSuTyJ3+6baH1wO5LYayLO qUTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=uJMJ+NQtZ0XpbgcU5B6V/mq7bccUXUSsHINPFl3Guj4=; b=BeWXWAbCo8vXu7a1/PxV3QK6khDrvAv1Efj+y6i/F5QrM61RVY1fsVv/pyHotOAYKk dPlmo1lD9ppkLTHLaIN8xuVdvWPavdLZCczlQABMQeDW6/UREMGe3WDeJv0q3ok2jcK9 nvpPkHX6x0KK1zXQlLD6SrdbWKAmHBLCxzOYsBxSXiVTP6fwiB76JhlM67JTEjsUjf/3 chqLtIUt1pBKCyE0cghQbJsSjLV6qrl6mGzFZIU2BuW+NtdPBj5yRd/k4tIp3068MWCP 0e9FqEgwkAv5hNM7bLJkyIPIIqLg1mD1c0hHixEvV1M/A/0plLudt0AssydKLOe5Zycj jqeA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=IhYMosca; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Here we can use the status of `plane->color_mgmt_changed` to detect when a plane color property changed and recreate the plane accordingly. Co-developed-by: Joshua Ashton Signed-off-by: Joshua Ashton Signed-off-by: Melissa Wen --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 760080e4a4da..1dac311cab67 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -9441,6 +9441,9 @@ static bool should_reset_plane(struct drm_atomic_state *state, if (drm_atomic_crtc_needs_modeset(new_crtc_state)) return true; + if (new_plane_state->color_mgmt_changed) + return true; + /* * If there are any new primary or overlay planes being added or * removed then the z-order can potentially change. To ensure From patchwork Sun Apr 23 14:10:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86764 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2241864vqo; Sun, 23 Apr 2023 08:10:21 -0700 (PDT) X-Google-Smtp-Source: AKy350YaOYAtq921ui/KzCT9EtxXkFmcQQlduSdKyQ6ct5gaPbc+gITDoVZedwc0IDo18wr/U91k X-Received: by 2002:a05:6a20:a696:b0:f1:b3c1:82f2 with SMTP id ba22-20020a056a20a69600b000f1b3c182f2mr12160420pzb.38.1682262621113; Sun, 23 Apr 2023 08:10:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682262621; cv=none; d=google.com; s=arc-20160816; b=IP9mECwIHvEDPC3Vu0aEdTXH8arXkoqRRuMfVmx32JFS4O1Su8LPhBqaHV3JQXEq1z EbliZLBs5UrGvi1OMfYqL2Z61b3RafmokkhdzmCgl5dtD7yAHFDUzD2vw9r4c+qKpP3L MI8fVbZhhqV1dknl9hB1eOxI/w+wuQadzHBZmPals+h3OZILjHLJA3IWQ5c321tvIb5M NGlhF5iz5OFmX59iJ6ZnxkK7rwuwUMr8zGM1kuFZmYmdrfZ/ih1PaLIYTyjq5cYUs12K HbFTsc8Spq2wudrCuveSRC0DJQoCZKhFMNqj7cMOS7ovAPBCCS9fhT5EIFIL3fZfdCHU DvkQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=QwuSO2LNJ+LJ1+yrvEcZOrqAYwcz+YFmvLiCu9u3lbQ=; b=NWEfYYjN1KYeGA5Vsma+m0VYPrxY8Fgopy0Izb9dA2A7E037XhUOHJ8wCpl/tQsbLw yFaAFheAtSNgSveEwEMiylVffLLljem86QPiJIyhlwM3+1To2pmOtqoSH9ET7NTCz87Y TFqDhfcFTv2fd2BAxOwpb7aq2+qIfAgMm0BTSOE1u/SqIrzXeMT4qpeQKzJs/0Jo6nWa CWBQjTbBnfiry+tXO3FE2K/2nm9jGe3KFTVkmVJx9jQUELvDHIaIpHmALTgwpIREadGS IQo7kRab5qurULLROJFVfwrIuWIGPy5s6dS3qRe+E3dgiQfreNTxLgA2GA215HA9FPGr PkDA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=mORa53lO; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id v69-20020a638948000000b0050bfc85d989si9675498pgd.154.2023.04.23.08.10.06; Sun, 23 Apr 2023 08:10:21 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=mORa53lO; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230402AbjDWOtK (ORCPT + 99 others); Sun, 23 Apr 2023 10:49:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55148 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230170AbjDWOtF (ORCPT ); Sun, 23 Apr 2023 10:49:05 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E541B1FD8 for ; Sun, 23 Apr 2023 07:48:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=QwuSO2LNJ+LJ1+yrvEcZOrqAYwcz+YFmvLiCu9u3lbQ=; b=mORa53lOjf6BQPulDyK5c+ctGp 7OS8D5hV+ZI9NRVY0Ypu6IY6WqiF0u0PogOM0YVPNCTSHAZv21TK2yltFeu/NOinJ5+GZDwCB8sIE XA2LN+prpg73D38iJoWmtLIxa5fZEQvsITh/jOLw7H43mP2xHOClrJnhXK8nwhrSnZlA7jJiRxwMo AcSCwp8ShKkdKEEZeFf0qUdetr2sbbhPccegDIUB1NCLhEWKf/hNebglaABOnRm6OA+ylqMCgVas3 VvKi5XzfLqcTNLiddrsRsJYHNLCQl/x982gL31yJZNkebLSzsCoJKFm5A1IFgEq6EuGdTydUlVViZ WfDpbpnQ==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaTD-00ANVs-Ax; Sun, 23 Apr 2023 16:13:39 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 31/40] drm/amd/display: decouple steps for mapping CRTC degamma to DC plane Date: Sun, 23 Apr 2023 13:10:43 -0100 Message-Id: <20230423141051.702990-32-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763980210179598887?= X-GMAIL-MSGID: =?utf-8?q?1763980210179598887?= The next patch adds pre-blending degamma to AMD color mgmt pipeline, but pre-blending degamma caps (DPP) is currently in use to provide DRM CRTC atomic degamma or implict degamma on legacy gamma. Detach degamma usage regarging CRTC color properties to manage plane and CRTC color correction combinations. Signed-off-by: Melissa Wen --- .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 55 +++++++++++++------ 1 file changed, 38 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 6a233380f284..518082222fff 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -791,20 +791,8 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc, return 0; } -/** - * amdgpu_dm_update_plane_color_mgmt: Maps DRM color management to DC plane. - * @crtc: amdgpu_dm crtc state - * @dc_plane_state: target DC surface - * - * Update the underlying dc_stream_state's input transfer function (ITF) in - * preparation for hardware commit. The transfer function used depends on - * the preparation done on the stream for color management. - * - * Returns: - * 0 on success. -ENOMEM if mem allocation fails. - */ -int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, - struct dc_plane_state *dc_plane_state) +static int map_crtc_degamma_to_dc_plane(struct dm_crtc_state *crtc, + struct dc_plane_state *dc_plane_state) { const struct drm_color_lut *degamma_lut; enum dc_transfer_func_predefined tf = TRANSFER_FUNCTION_SRGB; @@ -827,8 +815,7 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, °amma_size); ASSERT(degamma_size == MAX_COLOR_LUT_ENTRIES); - dc_plane_state->in_transfer_func->type = - TF_TYPE_DISTRIBUTED_POINTS; + dc_plane_state->in_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS; /* * This case isn't fully correct, but also fairly @@ -864,7 +851,7 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, degamma_lut, degamma_size); if (r) return r; - } else if (crtc->cm_is_degamma_srgb) { + } else { /* * For legacy gamma support we need the regamma input * in linear space. Assume that the input is sRGB. @@ -876,6 +863,40 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, !mod_color_calculate_degamma_params(NULL, dc_plane_state->in_transfer_func, NULL, false)) return -ENOMEM; + } + + return 0; +} + +/** + * amdgpu_dm_update_plane_color_mgmt: Maps DRM color management to DC plane. + * @crtc: amdgpu_dm crtc state + * @dc_plane_state: target DC surface + * + * Update the underlying dc_stream_state's input transfer function (ITF) in + * preparation for hardware commit. The transfer function used depends on + * the preparation done on the stream for color management. + * + * Returns: + * 0 on success. -ENOMEM if mem allocation fails. + */ +int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, + struct dc_plane_state *dc_plane_state) +{ + bool has_crtc_cm_degamma; + int ret; + + has_crtc_cm_degamma = (crtc->cm_has_degamma || crtc->cm_is_degamma_srgb); + if (has_crtc_cm_degamma){ + /* AMD HW doesn't have post-blending degamma caps. When DRM + * CRTC atomic degamma is set, we maps it to DPP degamma block + * (pre-blending) or, on legacy gamma, we use DPP degamma to + * linearize (implicit degamma) from sRGB/BT709 according to + * the input space. + */ + ret = map_crtc_degamma_to_dc_plane(crtc, dc_plane_state); + if (ret) + return ret; } else { /* ...Otherwise we can just bypass the DGM block. */ dc_plane_state->in_transfer_func->type = TF_TYPE_BYPASS; From patchwork Sun Apr 23 14:10:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86755 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2231949vqo; Sun, 23 Apr 2023 07:50:22 -0700 (PDT) X-Google-Smtp-Source: AKy350ZINCfnl2HkXCJHsJGV1BZjCT3vRKzStBOVUYe64MOfxp6gBJlIipSNreGbrNJUzG49eVdb X-Received: by 2002:a05:6a00:a09:b0:63f:21e:5b0e with SMTP id p9-20020a056a000a0900b0063f021e5b0emr14106558pfh.4.1682261422146; Sun, 23 Apr 2023 07:50:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682261422; cv=none; d=google.com; s=arc-20160816; b=PTc61plPxSc6tksOWA6q70JCW3B97NQJETPKnhPXCeG9ZGGVMGo2ZsWAmMYo4oHyEJ j/yNTf/sxqGC3n+RI9B6jqQ42Eip9i/5jIUYg4ls5gBIw2LZdYKF9fiDAfEOVzFlLNiO Ny+eJQKSvcBj/FomeG6aPZK91bGoXNWno25s3X4nDZG3Gvt15jO9w5ArSuVMEqH1TR3D HuI+0s8BMsxxAZ0AiXhdd1kjg3l19GdCyP++ZvxyoMVveuutIPKZatJ/Sbgi30zdPn+f SR9PEizGo8Z37yp8hzcWlN8wXH1sDY7PT11+ZwFO/kswpa7hydBo3fHqrjbZVCBOiCAQ bu8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=/W4Otev8naKI+sTtsOTBF0+9f4KzatyGi8o5pO95DCc=; b=ZCa9MivvU3RoN4hInDDgS7cab5+lco7AjS0deuePZRoPCBtp/2HcTpcoYxKw67RxC4 G5XEBUiXii0CJ2LOkUXeIpyrbEWvJ251na0LpEcO4d5eOV3qQv2/M3cUNKTwnIF2vzYg D3lIJthMpLssd0iF84uH4SpL89trL1FQRrB0vuu2v93/VPb+DIs7bJnZECQMLaul8Gtt qG9h39pYiPo9FkA8r55sIx81QojVlrrenv3NqDAr8RwAnx4PIremKHSeAE4YQf4bGMsj JRlWeCAJBzGtQ2E+S/OMVYtRiOYOLSWESYmpSBkKC16fematOcmkadZI+eKlMqE0zJjr 2DIA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=pccns+OH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 137-20020a63078f000000b00513a68ca71asi4508689pgh.742.2023.04.23.07.50.08; Sun, 23 Apr 2023 07:50:22 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=pccns+OH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230272AbjDWOr6 (ORCPT + 99 others); Sun, 23 Apr 2023 10:47:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53788 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229948AbjDWOrz (ORCPT ); Sun, 23 Apr 2023 10:47:55 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 74CCF2D57 for ; Sun, 23 Apr 2023 07:47:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=/W4Otev8naKI+sTtsOTBF0+9f4KzatyGi8o5pO95DCc=; b=pccns+OHh+ISutnzDBzunpavg5 2jNNXAWTA3OhX/+/uK59iGeX89oRWnewx768uhx1o6BKUrJNxIjW+b1a+DtS5ZSKCUWFtEKnX21f1 SPVY/Hghr7FjxlcNuYexPZuiSIop9McU/7Z1LmdCQGfdY/ZK1ime3A/8vefdoZeTtQckJlJ4TuywT JVEScpNQqXPJDmxkUW9sHzVxVtasQzZTOkKZ0aBtfY7qAZtDXkb6Q0nYEOQ3GCNgJJMgdnpSd1KVU PNWQQ7FD7BxUqH8cbfKv73KTbY9ZIpVecTnoQqQzqcRxLjEqGTWe5rjpdmnnKjP9p7/bwo0+905e+ +cS9yeaw==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaTI-00ANVs-GJ; Sun, 23 Apr 2023 16:13:44 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , linux-kernel@vger.kernel.org Subject: [RFC PATCH 32/40] drm/amd/display: add support for plane degamma TF and LUT properties Date: Sun, 23 Apr 2023 13:10:44 -0100 Message-Id: <20230423141051.702990-33-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763978953322159577?= X-GMAIL-MSGID: =?utf-8?q?1763978953322159577?= From: Joshua Ashton We only set CRTC degamma if we don't have plane degamma LUT or TF to configure. We return -EINVAL if we don't have plane degamma settings, so we can continue and check CRTC degamma. Signed-off-by: Joshua Ashton --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 + .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 71 +++++++++++++++++-- 3 files changed, 70 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 1dac311cab67..c0321272c129 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5043,7 +5043,9 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev, * Always set input transfer function, since plane state is refreshed * every time. */ - ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state); + ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, + plane_state, + dc_plane_state); if (ret) return ret; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index b9840c1f3cdf..bcf74b7391c9 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -912,6 +912,7 @@ int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state); int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc, struct dc_state *ctx); int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, + struct drm_plane_state *plane_state, struct dc_plane_state *dc_plane_state); void amdgpu_dm_update_connector_after_detect( diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 518082222fff..693168cc1d9c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -868,9 +868,59 @@ static int map_crtc_degamma_to_dc_plane(struct dm_crtc_state *crtc, return 0; } +#ifdef CONFIG_STEAM_DECK +static int +__set_dm_plane_degamma(struct drm_plane_state *plane_state, + struct dc_plane_state *dc_plane_state) +{ + struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state); + const struct drm_color_lut *degamma_lut; + enum drm_transfer_function drm_tf = DRM_TRANSFER_FUNCTION_DEFAULT; + uint32_t degamma_size; + bool has_degamma_lut; + int ret; + + degamma_lut = __extract_blob_lut(dm_plane_state->degamma_lut, °amma_size); + + has_degamma_lut = degamma_lut && + !__is_lut_linear(degamma_lut, degamma_size); + + drm_tf = dm_plane_state->degamma_tf; + + /* If we don't have plane degamma LUT nor TF to set on DC, we have + * nothing to do here, return. + */ + if (!has_degamma_lut && drm_tf == DRM_TRANSFER_FUNCTION_DEFAULT) + return -EINVAL; + + dc_plane_state->in_transfer_func->tf = drm_tf_to_dc_tf(drm_tf); + + if (has_degamma_lut) { + ASSERT(degamma_size == MAX_COLOR_LUT_ENTRIES); + + dc_plane_state->in_transfer_func->type = + TF_TYPE_DISTRIBUTED_POINTS; + + ret = __set_input_tf(dc_plane_state->in_transfer_func, + degamma_lut, degamma_size); + if (ret) + return ret; + } else { + dc_plane_state->in_transfer_func->type = + TF_TYPE_PREDEFINED; + + if (!mod_color_calculate_degamma_params(NULL, + dc_plane_state->in_transfer_func, NULL, false)) + return -ENOMEM; + } + return 0; +} +#endif + /** * amdgpu_dm_update_plane_color_mgmt: Maps DRM color management to DC plane. * @crtc: amdgpu_dm crtc state + * @plane_state: DRM plane state * @dc_plane_state: target DC surface * * Update the underlying dc_stream_state's input transfer function (ITF) in @@ -881,13 +931,28 @@ static int map_crtc_degamma_to_dc_plane(struct dm_crtc_state *crtc, * 0 on success. -ENOMEM if mem allocation fails. */ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, + struct drm_plane_state *plane_state, struct dc_plane_state *dc_plane_state) { bool has_crtc_cm_degamma; int ret; + /* Initially, we can just bypass the DGM block. */ + dc_plane_state->in_transfer_func->type = TF_TYPE_BYPASS; + dc_plane_state->in_transfer_func->tf = TRANSFER_FUNCTION_LINEAR; + + /* After, we start to update values according to color props */ has_crtc_cm_degamma = (crtc->cm_has_degamma || crtc->cm_is_degamma_srgb); - if (has_crtc_cm_degamma){ + +#ifdef CONFIG_STEAM_DECK + ret = __set_dm_plane_degamma(plane_state, dc_plane_state); + if (ret != -EINVAL) + return ret; + + /* As we don't have plane degamma, check if we have CRTC degamma + * waiting for mapping to pre-blending degamma block */ +#endif + if (has_crtc_cm_degamma) { /* AMD HW doesn't have post-blending degamma caps. When DRM * CRTC atomic degamma is set, we maps it to DPP degamma block * (pre-blending) or, on legacy gamma, we use DPP degamma to @@ -897,10 +962,6 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, ret = map_crtc_degamma_to_dc_plane(crtc, dc_plane_state); if (ret) return ret; - } else { - /* ...Otherwise we can just bypass the DGM block. */ - dc_plane_state->in_transfer_func->type = TF_TYPE_BYPASS; - dc_plane_state->in_transfer_func->tf = TRANSFER_FUNCTION_LINEAR; } return 0; From patchwork Sun Apr 23 14:10:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86739 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2222381vqo; Sun, 23 Apr 2023 07:26:44 -0700 (PDT) X-Google-Smtp-Source: AKy350ZqP7XFCS3dxdwg//6cSollqHBNLFebxg348Pt73Zp737b7QCaQvDkntmD6aE7MjrzBoYs/ X-Received: by 2002:a05:6a20:c901:b0:cc:a5d4:c334 with SMTP id gx1-20020a056a20c90100b000cca5d4c334mr12653633pzb.10.1682260003915; Sun, 23 Apr 2023 07:26:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682260003; cv=none; d=google.com; s=arc-20160816; b=KQ1x4RdZSP25HK1OuCyHtusztesY8wd4bKpHZiopr46+rTDtXbQcVeA+lkutn0hW5Z Rc7sWyHMuJ3Jd+jy25vGhmCB6JG3+Q1d1fuAGkYu7oCqbeJmM67Fk+7/w3K6isGa57yd cU1MugYYSMx/Xq3jgRBUmmWIw++jwwYIj7G1OMSKJ11EK/8PaCaP4GjnXXZ7k1AXvXF4 N1K+1x8cwid7TUoh+2eRN146x6YjxeaXWJnRxW+IWNUT0OmRPXdoy2rDlXAlkG35o+xE Gu9IoAcBITuyvbo+36fvLx79fyF9Mk9V5aTlxm5vI5PO6idDuqeWEaxgc5sfQoX15pMd Vtsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=4GQm73N05wdyDPvLOueAQrdj1CPYaUCZeKkaAs7VjXY=; b=aPYI8/vq5rW7hEDrLcW1j3a5mU1dcZs/s9FAYdJ1+HBEuiuwh0DAAqUkUAWO2SsIix 9MzbtiBQorV1EEa8nYV3ejBs4217lbqS71on3+4tDzhqzL48a7D2hs4HJ9CWIqahyXAw veRvQj1OCpMJHmrMEIK1NyBuSngWjVVlLKDPEC87QOjVdnFMtpSVcFUAW9dvabvjxJY7 Z7R7StM/I5WODdUVSFDVTjqKSmfF3aQ+fiDrQvVoVCyyCfcNupkNeLsGtUYxF2quGhQ6 4GyJaTqvuhLNjJ8GSlmg552i76HSkccsJy9yPuoC0zw77G7zFXhRPl0cW8r1qgHpA+3v W0tg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=h2ixzavp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id u15-20020a63470f000000b005143d5f9ff0si8795553pga.357.2023.04.23.07.26.29; Sun, 23 Apr 2023 07:26:43 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=h2ixzavp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230328AbjDWOPv (ORCPT + 99 others); Sun, 23 Apr 2023 10:15:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35044 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230348AbjDWOPe (ORCPT ); Sun, 23 Apr 2023 10:15:34 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BBFC73C0A for ; Sun, 23 Apr 2023 07:15:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=4GQm73N05wdyDPvLOueAQrdj1CPYaUCZeKkaAs7VjXY=; b=h2ixzavpfQLRZTKkPcsvUCerpa LoWyHwwWnSdmYYg+hC/Hnz4QMtMT7U68Rvz7ux818FUzfSWXCVmsN8eWeKnzaILchgmSYHg2gwph+ ke043JYgzHR+pr+v5CcOeYqNdOt7qZFyhmctCzqoPOV6hkqIHC7As5ZjpgZ+obUKlh1VhUKyKiRw1 cI1EU41E+TYX6+B2QSNH7eFjttLv/ar2/wHCjT/hoNPLcnheUAxZp7BcSmRvGuQc/jwdRgoUnrkni PdtbyQbeh6ROOvboSKntvevX6ke1BEKqEjBabV0BoivARn+hynJAbfVGHPYXXmlTiYLSqRthR6Dfi 2ghFpcpA==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaTL-00ANVs-Dv; Sun, 23 Apr 2023 16:13:47 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 33/40] drm/amd/display: reject atomic commit if setting both plane and CRTC degamma Date: Sun, 23 Apr 2023 13:10:45 -0100 Message-Id: <20230423141051.702990-34-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763977466180314448?= X-GMAIL-MSGID: =?utf-8?q?1763977466180314448?= DC only has pre-blending degamma caps (pre-blending/DPP) that is currently in use for CRTC/post-blending degamma, so that we don't have HW caps to perform plane and CRTC degamma at the same time. Reject atomic updates when serspace sets both plane and CRTC degamma properties. Signed-off-by: Melissa Wen --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 693168cc1d9c..07303c9f3618 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -949,6 +949,17 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, if (ret != -EINVAL) return ret; + /* We only have one degamma block available (pre-blending) for the + * whole color correction pipeline, so that we can't actually perform + * plane and CRTC degamma at the same time. Reject atomic updates when + * userspace sets both plane and CRTC degamma properties. + */ + if (has_crtc_cm_degamma && ret == -EINVAL){ + drm_dbg_kms(crtc->base.crtc->dev, + "doesn't support plane and CRTC degamma at the same time\n"); + return -EINVAL; + } + /* As we don't have plane degamma, check if we have CRTC degamma * waiting for mapping to pre-blending degamma block */ #endif From patchwork Sun Apr 23 14:10:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86765 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2241995vqo; Sun, 23 Apr 2023 08:10:41 -0700 (PDT) X-Google-Smtp-Source: AKy350ao07iMFDSu5CRhe5JeJRdpPXrzEB5SDjvSgBv4udXdM+yxoQZWFgcl4m/m6Xcz8Ne5hN+i X-Received: by 2002:a05:6a00:1a55:b0:63d:4446:18ab with SMTP id h21-20020a056a001a5500b0063d444618abmr15084056pfv.23.1682262641030; Sun, 23 Apr 2023 08:10:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682262641; cv=none; d=google.com; s=arc-20160816; b=boBqTJzraTKNHQVPR4R0Jo1gYc8URDfI8Q4ii7ae6eeFwHI4nidowGfkXEN6Sn7AZV OLw+Xem0DtVXC1f0ae658NEAkOpx/PzNhwF0YMOm2OQ4YLsjF6/EawKNrfxPWrCELsJo s0y9I0HU3ekJa7vVZwkZblfvWvcg9qjwSRKV0EI3cuMQIv84rJgywBqz4xGSxOGv8BR6 F/bKwE9XCvBeqaHatsHjnUex9C3dwcNc+oUEHCreqL9XPM0opgWdc3ssh6oODNi7VS5W +pQsqMVeHDSf08IU4oiSH9U1w1IK7fHkFC9Ffs/DLPXuyZtmo739wrZMrUwCHGwxtSSu EXkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=P4ZXpKFMtoIv2GHYDm0O+bIMEiRHVdDFlzSdVRRjl+4=; b=N7bAahJ94a0a154B/OmiLO58903JKClileCV3a7XzD1nPRVWjPTmpNTlvRVrpNGRBZ fm+8xikf1rgitdLCsbrS0TkJxTaIlWs9860a197SLwJaL6aHclR8gaAp++yP0OZZ2nY1 ZrKGVq0SHff75Lvfub1iWwCYyRPYfC+frbnRbrnXDHaIOjXoY4zfU3fKO7L1IYa7lh9C 1wIpvWa4IoaZSmD9SZRRTzm1WZ4kAZ/xodj6J/AcZTefNo+1HBDw2IbQeGsQCBonr9LN e+k9RcXQnE20Rb/X6I0psrH+PSSUHOi1e83htvV5pvRakYS8tKt1qr3kkpXk7iwZWjqm uZHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=Xf5xbFUl; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id a12-20020aa7970c000000b0063bba11c4a0si9313829pfg.59.2023.04.23.08.10.26; Sun, 23 Apr 2023 08:10:41 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=Xf5xbFUl; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229453AbjDWOrK (ORCPT + 99 others); Sun, 23 Apr 2023 10:47:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51958 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230256AbjDWOrF (ORCPT ); Sun, 23 Apr 2023 10:47:05 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8EBC62700 for ; Sun, 23 Apr 2023 07:46:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=P4ZXpKFMtoIv2GHYDm0O+bIMEiRHVdDFlzSdVRRjl+4=; b=Xf5xbFUlVRcMeEfF92pKTWXigX R9y7r3VyMhFpJTzPExO/MEwG3xN9AyhwDWtZ+WGoZe8rbS3sdSGEV77TDsmVhg2icLCNnhOqq/nZq C94uECAkNCXMFTBXeOewYKAf3EFwNxYGTW+54d9UbLXWJkzvXXMvDYEDMY6JWdZI3UuFi1R/PW7yj Tj6FFfM6mOlk6Uz1yKXlU+iE+uuhNX59b6Q9G3mElUuCEDTy67bzM3TKt8//1H7bEjJsGJYcuqvdB rjmy50QlYBUT/bHPct4NQfoVfgJsbb5dW5VB8BZCE7LdtB78DNXJFGVC8sjgEQWkwzlmiQy7qFtJx UHH6t3+A==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaTO-00ANVs-Pv; Sun, 23 Apr 2023 16:13:50 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , linux-kernel@vger.kernel.org Subject: [RFC PATCH 34/40] drm/amd/display: add dc_fixpt_from_s3132 helper Date: Sun, 23 Apr 2023 13:10:46 -0100 Message-Id: <20230423141051.702990-35-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763980230872114799?= X-GMAIL-MSGID: =?utf-8?q?1763980230872114799?= From: Joshua Ashton Detach value translation from CTM to reuse it for programming HDR multiplier property. Signed-off-by: Joshua Ashton --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 8 +------- drivers/gpu/drm/amd/display/include/fixed31_32.h | 12 ++++++++++++ 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 07303c9f3618..d714728ca143 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -182,7 +182,6 @@ static void __drm_lut_to_dc_gamma(const struct drm_color_lut *lut, static void __drm_ctm_to_dc_matrix(const struct drm_color_ctm *ctm, struct fixed31_32 *matrix) { - int64_t val; int i; /* @@ -201,12 +200,7 @@ static void __drm_ctm_to_dc_matrix(const struct drm_color_ctm *ctm, } /* gamut_remap_matrix[i] = ctm[i - floor(i/4)] */ - val = ctm->matrix[i - (i / 4)]; - /* If negative, convert to 2's complement. */ - if (val & (1ULL << 63)) - val = -(val & ~(1ULL << 63)); - - matrix[i].value = val; + matrix[i] = dc_fixpt_from_s3132(ctm->matrix[i - (i / 4)]); } } diff --git a/drivers/gpu/drm/amd/display/include/fixed31_32.h b/drivers/gpu/drm/amd/display/include/fixed31_32.h index ece97ae0e826..f4cc7f97329f 100644 --- a/drivers/gpu/drm/amd/display/include/fixed31_32.h +++ b/drivers/gpu/drm/amd/display/include/fixed31_32.h @@ -69,6 +69,18 @@ static const struct fixed31_32 dc_fixpt_epsilon = { 1LL }; static const struct fixed31_32 dc_fixpt_half = { 0x80000000LL }; static const struct fixed31_32 dc_fixpt_one = { 0x100000000LL }; +static inline struct fixed31_32 dc_fixpt_from_s3132(__u64 x) +{ + struct fixed31_32 val; + + /* If negative, convert to 2's complement. */ + if (x & (1ULL << 63)) + x = -(x & ~(1ULL << 63)); + + val.value = x; + return val; +} + /* * @brief * Initialization routines From patchwork Sun Apr 23 14:10:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86760 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2241774vqo; Sun, 23 Apr 2023 08:10:09 -0700 (PDT) X-Google-Smtp-Source: AKy350ameGhpj17B9ysTouTVgd3O7KB5aov2A8fRQIcHNp5gPz87BB0nbKdm6r2WHYylogL6VtRe X-Received: by 2002:a05:6a20:428c:b0:f4:ec49:b83b with SMTP id o12-20020a056a20428c00b000f4ec49b83bmr1698938pzj.15.1682262608783; Sun, 23 Apr 2023 08:10:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682262608; cv=none; d=google.com; s=arc-20160816; b=MUWzrzLovJuj/QSOIVpLtOpHt0Lv5H8oGjW1Y8yVvNW2EhXTNxsJ2wY5WqPeA1yoc1 /pkCqaR7Gu2vId1Ys/ADT+TvC+s2BrS5oHGu1+nc5GF7pWn130ZRhKvj2VKxQUgtNH4T HNajnFdtBab73r50dyWZfKhAGY7C4sg926hmJTuXL8D9brycauXXgRDrW4bkRNOBxNlc Md10+On2ZWMLwO7wS6XsVRfcekdZnPpRr6P/O4RGYstnILeu+bm/Q7hAgLrqU0RJvwTG Htx9GfCdiEDONoLVORz3olWeF4dV5ceRalSMnCPlIv4iu0ZxvmqqEjViG0RoliJ69oIq ZI5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=av8LLs8d/qgSpvCdtPWbCDxJo/b1Zt+to8SoXN3tsd4=; b=Qse843TuvAtyyBoMY+w7vXo5rhjGsxTaf8guAyY5oYU4yqCf1o0Oi6NCkrPW6J1RLP AmVFezSgnpKNosLlSHGfBz0zvgpWXztE7DiBcZwanEiZtjVrRjKzBRam0Q2QeC5c/VEy 7F326zqMmjsTkKBbGPtY0LXaeJGerL2On6dimRW0utL3mnL7c+LA864255+4yE8UH0Qj 5GLhkqZ7IXJDBXVp8IbTKgvsjwvKcGou3oezIPGbBiBjCIJbyy7huO+XQjVeChn7g7Ig tzldELgmFkh3RmLAgOlBPo5PcWgT5tvIi8YyonRL4VqLAh2XGJOTOCudPmpohhlSZzKf 3FOw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=Wc6qM5pM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Joshua Ashton --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index c0321272c129..0e3b6d414ec4 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7991,6 +7991,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction; bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func; bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix; + bundle->surface_updates[planes_count].hdr_mult = dc_plane->hdr_mult; } amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index d714728ca143..854510b05194 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -939,6 +939,8 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, has_crtc_cm_degamma = (crtc->cm_has_degamma || crtc->cm_is_degamma_srgb); #ifdef CONFIG_STEAM_DECK + dc_plane_state->hdr_mult = dc_fixpt_from_s3132(dm_plane_state->hdr_mult); + ret = __set_dm_plane_degamma(plane_state, dc_plane_state); if (ret != -EINVAL) return ret; @@ -969,5 +971,6 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, return ret; } + return 0; } From patchwork Sun Apr 23 14:10:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86762 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2241813vqo; Sun, 23 Apr 2023 08:10:14 -0700 (PDT) X-Google-Smtp-Source: AKy350Zk4kxxsxYkZ75YmSxenIR5GnR4aK77oBfOOenW6t/uEXfnpMscSTsGzZH38xOL4LBNUxFC X-Received: by 2002:a05:6a00:1309:b0:63b:23b0:a72e with SMTP id j9-20020a056a00130900b0063b23b0a72emr11889400pfu.15.1682262614407; Sun, 23 Apr 2023 08:10:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682262614; cv=none; d=google.com; s=arc-20160816; b=Q9dTpkZWV56/wxigIkeoND7JZgIef27oT/f45ASNamtckJTlTJNB+iGnc4+j4tf9kn gKoxKBEFHThAdXRFb6TJ7WPCPNyKsrL8svO3LONvLkKEarurVRvoSdH1A884a9PSf1dT F0itJGf88JtH0rlqX/xJ0kYn2ZmPZJShzESuaHcXrnOJfKJYpjzdZqwAU3LPnCCyNdp4 pX3gXL3jNKhCuREtJQBceKhJGzjuTdYUNOXm4nDlWsdwhBVG/YobFoSch8c6Y1Kh+A4Y lQcsNTdSV0WAHJ12fzl4rR45HOOu0jClTasY1FVYSBTM9cTFtcreDGmT/4Tuer2kLboF Ge3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=j3/12jxSdcW585zS5aTXAW8FYxDjDH8xTDC6oGODNZ4=; b=HLex/zakCnPh5gsuJ5BRi2cogyncMVp/0nGPFWo/faS6oV+B7L/0uVIAaEDJokMKzL an/QzzpWjCaMytkA8GnLGWiEc73J2TonW9FlNAk7erJJtoUc0JICB1xozR7oaET26JJi ybQQg0wKnLW83Gc67EyZOinNuf/1p9PSbmQfW5qjqy8PKozGbmbs/IaGTcltCopTpn6B p9srn32p2b8yiTvAKbvYi0SLVfRK1p5wV6nT0oaJJHBXbsT/ozNce2v8y/4eRcx1EfoV eXgvv9mLKrvE60HZVeWqEDwHXunuavOG4hyAtU1XQyiseHjKInBqoRpwGmhYpfvaEomF mbaw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=gGPYg1jP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id a12-20020aa7970c000000b0063bba11c4a0si9313829pfg.59.2023.04.23.08.09.59; Sun, 23 Apr 2023 08:10:14 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=gGPYg1jP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230252AbjDWOsX (ORCPT + 99 others); Sun, 23 Apr 2023 10:48:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229587AbjDWOsV (ORCPT ); Sun, 23 Apr 2023 10:48:21 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 96D5610F0 for ; Sun, 23 Apr 2023 07:47:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=j3/12jxSdcW585zS5aTXAW8FYxDjDH8xTDC6oGODNZ4=; b=gGPYg1jP8KMZzxXdI1YyTRkYWD ZOSsJyEWVsUa4GnVoAhvsXfQe5MwF/3xExwFTIXBkBhDy26yZagqaIfPPwFlbEkrrNcPp3NBd7CBE cKO/cuBPRttDjjstSCMeNkP6/A7WLmMcJoClGtyLVXAtwsZga4YDQHji8U8a1HHhz6hienUN4W++V g3vS9eYtpHFvmFYUtrlL8GLh2d9et+g2dxLs6Bzn1Ewt/J7yqREVBcR/w9pFXOxaMg5xpSPow0Sfi 02XeYziyiJQbR9xryPVYgY113jjbSkCgryI/9m2MC3TEQVdXp7BXUzlfxY8tzz68AwJZFnQMRyu1g VY7vcTog==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaTZ-00ANVs-0W; Sun, 23 Apr 2023 16:14:01 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 36/40] drm/amd/display: add plane shaper/3D LUT and shaper TF support Date: Sun, 23 Apr 2023 13:10:48 -0100 Message-Id: <20230423141051.702990-37-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763980202863551730?= X-GMAIL-MSGID: =?utf-8?q?1763980202863551730?= We already have the steps to program post-blending shaper/3D LUT on AMD display driver, so that we can reuse them and map plane properties to DC plane for pre-blending (plane) shaper/3D LUT setup. Signed-off-by: Melissa Wen --- .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 34 +++++++++++++++++-- .../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 5 +-- 2 files changed, 35 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 854510b05194..e17141fc8d12 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -909,6 +909,35 @@ __set_dm_plane_degamma(struct drm_plane_state *plane_state, } return 0; } + +static int +amdgpu_dm_plane_set_color_properties(struct drm_plane_state *plane_state, + struct dc_plane_state *dc_plane_state) +{ + struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state); + enum drm_transfer_function shaper_tf = DRM_TRANSFER_FUNCTION_DEFAULT; + const struct drm_color_lut *shaper_lut, *lut3d; + uint32_t lut3d_size, shaper_size; + + /* We have nothing to do here, return */ + if (!plane_state->color_mgmt_changed) + return 0; + + dc_plane_state->hdr_mult = dc_fixpt_from_s3132(dm_plane_state->hdr_mult); + + shaper_tf = dm_plane_state->shaper_tf; + shaper_lut = __extract_blob_lut(dm_plane_state->shaper_lut, &shaper_size); + lut3d = __extract_blob_lut(dm_plane_state->lut3d, &lut3d_size); + lut3d_size = lut3d != NULL ? lut3d_size : 0; + shaper_size = shaper_lut != NULL ? shaper_size : 0; + + amdgpu_dm_atomic_lut3d(lut3d, lut3d_size, dc_plane_state->lut3d_func); + ret = amdgpu_dm_atomic_shaper_lut(shaper_lut, false, + drm_tf_to_dc_tf(shaper_tf), + shaper_size, dc_plane_state->in_shaper_func); + + return ret; +} #endif /** @@ -939,7 +968,9 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, has_crtc_cm_degamma = (crtc->cm_has_degamma || crtc->cm_is_degamma_srgb); #ifdef CONFIG_STEAM_DECK - dc_plane_state->hdr_mult = dc_fixpt_from_s3132(dm_plane_state->hdr_mult); + ret = amdgpu_dm_plane_set_color_properties(plane_state, dc_plane_state); + if(ret) + return ret; ret = __set_dm_plane_degamma(plane_state, dc_plane_state); if (ret != -EINVAL) @@ -971,6 +1002,5 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, return ret; } - return 0; } diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index 5800acf6aae1..91fee60410f4 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -1759,8 +1759,9 @@ static void dcn20_program_pipe( hws->funcs.set_hdr_multiplier(pipe_ctx); if (pipe_ctx->update_flags.bits.enable || - pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || - pipe_ctx->plane_state->update_flags.bits.gamma_change) + pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || + pipe_ctx->plane_state->update_flags.bits.gamma_change || + pipe_ctx->plane_state->update_flags.bits.lut_3d) hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); /* dcn10_translate_regamma_to_hw_format takes 750us to finish From patchwork Sun Apr 23 14:10:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86733 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2221672vqo; Sun, 23 Apr 2023 07:24:48 -0700 (PDT) X-Google-Smtp-Source: AKy350ZG+GZMV+wYfj2nu9owv0zaa1L6KClT1ASwvcBYYdn/6FeEROJ6NLk9mMesV+MLrX6d54WP X-Received: by 2002:a05:6a00:2487:b0:63d:368b:76b4 with SMTP id c7-20020a056a00248700b0063d368b76b4mr16739965pfv.17.1682259887743; Sun, 23 Apr 2023 07:24:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682259887; cv=none; d=google.com; s=arc-20160816; b=hlYcDExHnyVZU/Cif9Alcw046Pl85riuFWJn/seWq5YKT4AxW1MdGfukhi49QbIbpy Azg3WP/kAD8lSYIRq1K5E2aCowSEf4cFrVyO4cqp6MO0Y4pz6u9krfjWcf/sNdG3Rjft 7xITY60l0IiMe66azlo3TnHMnIbhjUB0RJ7dsOWm3yefbEQHaw2H2ntCoTIAizMfTzH0 NZ/QdipkNPSvKAGtNyNxlGMwZzAX2V2coqTUcuMM6KtocVV7Ikik2jirlMXODpeklN7N jxxwMhcZ9mBeGMNFTwRFsNhcjK6EBSJPHCftYgKGPScmlwkx9dImRAM0A0IRQEfl7b2L mKxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=cUSOYLuQjdiS9Ja6dEexWHo4C4Y5Ft7LRX3bN1lCnPA=; b=c0lp1sPo3pUHNz0XIkbCBuyhcRriO73RE4HIQ7CcrJqcDIzAjO8R5cafHgaTw3aBhE MeWn3642AL+BtBHZTTsP9gyBk4/dsg4B9ix1PefdRJaIbtdySarFalLOF0gv99LFLrDO cwDW2Z2KWt9N7G1CETcRflEnHmR2ovdDCtB309FRSM9uurRhJ0rCzx+zds/ZPxUvNCVG 1lUY43nrG9/LS1qU6lybaVmimm6ccDx3m7ZzBG3rQkW/2Oahy9uJYoWuQvM7+bnqM/C6 odFlkGCgyaBoRRrtBzWDpxVeSPb2zG5adyteuRexF8DMg/hdzSBCihUsJDeivHnicxWy KEHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=Hb2Dt82V; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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The regular degamma path doesn't hit this. Signed-off-by: Joshua Ashton --- .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 21 ++++++++++++------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index e17141fc8d12..baa7fea9ebae 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -349,21 +349,26 @@ static int __set_input_tf(struct dc_transfer_func *func, struct dc_gamma *gamma = NULL; bool res; - gamma = dc_create_gamma(); - if (!gamma) - return -ENOMEM; + if (lut_size) { + gamma = dc_create_gamma(); + if (!gamma) + return -ENOMEM; - gamma->type = GAMMA_CUSTOM; - gamma->num_entries = lut_size; + gamma->type = GAMMA_CUSTOM; + gamma->num_entries = lut_size; - __drm_lut_to_dc_gamma(lut, gamma, false); + __drm_lut_to_dc_gamma(lut, gamma, false); + } - res = mod_color_calculate_degamma_params(NULL, func, gamma, true); - dc_gamma_release(&gamma); + res = mod_color_calculate_degamma_params(NULL, func, gamma, gamma != NULL); + + if (gamma) + dc_gamma_release(&gamma); return res ? 0 : -ENOMEM; } + #ifdef CONFIG_STEAM_DECK static enum dc_transfer_func_predefined drm_tf_to_dc_tf(enum drm_transfer_function drm_tf) { From patchwork Sun Apr 23 14:10:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86769 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2243331vqo; Sun, 23 Apr 2023 08:13:30 -0700 (PDT) X-Google-Smtp-Source: AKy350bsJBLg2kC/Sff6CSbREpU1ivxqF4gE3eLDDIXmDmUEo7LyZ1rXPggNPVutc0Utml4zXOBy X-Received: by 2002:a05:6a20:549a:b0:f5:55a3:67d3 with SMTP id i26-20020a056a20549a00b000f555a367d3mr546446pzk.13.1682262809849; Sun, 23 Apr 2023 08:13:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682262809; cv=none; d=google.com; s=arc-20160816; b=rJnqZTOWHv0csu3PbF1y5lWNPtYwUb1sOZa8gTArX4vej/IkE9BOE+6Va0x1UkKVyk rBsijBPjU7sOGanjRHEBencpyfzoBvjS7JwIJftZZk6tzIOx7+2Wnk7pWQZ2okIBZleT VboQFJJcqKiKYwGXUoKCwYv/U7OpZVN1AgVk91chtbQLkh6P5+crpBWhxMOrlykrkl9r Udz3sRlLxblJsgUYPFe2t3cVcFLB2nx/KRtGVckFqUjUXMaTSRMpsng7K1Uz/ydPhnSJ 2ZkzEiBf6lK2muM6XqKvkHqFhJ6XMAXuOEE5Rfy7s06R9+Idm/NrbKxsQGxcIlwSL6nJ yL8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=566kXB93gduhO2pKotI8dq2ueeNQbJHEXFmIOVEzq10=; b=EM7VNCHDxneERT67OEnKHbJMbNv9yzDCH90Vu6/kPUQQtUwlLWIbGeFmydLmr8Zo9U aNdytBrYK/dO2BZyskfp8yNRsHIzbamStny33CHc4lg6P2dyi05uJFUfpVTZyRJ9Sr9C zosHLVt2EZjy2v0GjCkyh7Kn8RN7InSjQB2Yxnj/BKG1zeZfBkRMIGpWK+SaAikESb11 1vScySV32AislVxXtyjMg4+ZTmOAqyB23jB4rJvfzuU2BB69aOANuJh/SYPg8th5YAZo C6dEslJtUAxq38mMB2Zu5DBXXdtsZsvhVmhKdt5kDh5ReQcqcEetOvEtSKJEitjL1mGR Im8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=FJPh6Phj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id v69-20020a638948000000b0050bfc85d989si9675498pgd.154.2023.04.23.08.13.15; Sun, 23 Apr 2023 08:13:29 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=FJPh6Phj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230328AbjDWOqg (ORCPT + 99 others); Sun, 23 Apr 2023 10:46:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51696 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229501AbjDWOqe (ORCPT ); Sun, 23 Apr 2023 10:46:34 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33EDBE79 for ; Sun, 23 Apr 2023 07:46:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=566kXB93gduhO2pKotI8dq2ueeNQbJHEXFmIOVEzq10=; b=FJPh6PhjvOZATxzA+xct5dbVc7 gvsyJq189sn9N+Sx8/b9V6/F8OeScwhlxwajOaTzJvKBQnCNtyZ+iM7bAPOTmI8wsDKons2orsKLg /LWoGEFqE+GwbFxo8YTX1W/W4nPqxZnaFQTQ7yN+8uFphqOhYLY6upDlZo1wFnu4ydap/J1htHOx1 ElZWZnaBcH19SMPD+XsHcuc+xXBL1MJlatgLUu1s4BcNufr4b8EfZk1FrYPnBxbRXMNmCFitoeLc0 3Sj1JESKDWFQTgypjuGrJMcSMfIko5ngJRmWOzro7uRcaVm0fvU318+tQz7TI3dbXMiWAAYJIj4Zl U/HVg21Q==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaTg-00ANVs-Do; Sun, 23 Apr 2023 16:14:08 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , linux-kernel@vger.kernel.org Subject: [RFC PATCH 38/40] drm/amd/display: add DRM plane blend LUT and TF support Date: Sun, 23 Apr 2023 13:10:50 -0100 Message-Id: <20230423141051.702990-39-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763980408294014940?= X-GMAIL-MSGID: =?utf-8?q?1763980408294014940?= From: Joshua Ashton Map DRM plane blend properties to DPP blend gamma. Plane blend is a post-3D LUT curve that linearizes color space for blending. It may be defined by a user-blob LUT and/or predefined transfer function. As hardcoded curve (ROM) is not supported on blend gamma, we use AMD color module to fill parameters when setting non-linear TF with empty LUT. Signed-off-by: Joshua Ashton --- .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 60 +++++++++++++++++-- 1 file changed, 56 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index baa7fea9ebae..a034c0c0d383 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -493,6 +493,34 @@ static int amdgpu_dm_atomic_shaper_lut(const struct drm_color_lut *shaper_lut, return ret; } +static int amdgpu_dm_atomic_blend_lut(const struct drm_color_lut *blend_lut, + bool has_rom, + enum dc_transfer_func_predefined tf, + uint32_t blend_size, + struct dc_transfer_func *func_blend) +{ + int ret = 0; + + if (blend_size || tf != TRANSFER_FUNCTION_LINEAR) { + /* DRM plane gamma LUT or TF means we are linearizing color + * space before blending (similar to degamma programming). As + * we don't have hardcoded curve support, or we use AMD color + * module to fill the parameters that will be translated to HW + * points. + */ + func_blend->type = TF_TYPE_DISTRIBUTED_POINTS; + func_blend->tf = tf; + func_blend->sdr_ref_white_level = 80; /* hardcoded for now */ + + ret = __set_input_tf(func_blend, blend_lut, blend_size); + } else { + func_blend->type = TF_TYPE_BYPASS; + func_blend->tf = TRANSFER_FUNCTION_LINEAR; + } + + return ret; +} + /* amdgpu_dm_atomic_shaper_lut3d - set DRM CRTC shaper LUT and 3D LUT to DC * interface * @dc: Display Core control structure @@ -921,9 +949,11 @@ amdgpu_dm_plane_set_color_properties(struct drm_plane_state *plane_state, { struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state); enum drm_transfer_function shaper_tf = DRM_TRANSFER_FUNCTION_DEFAULT; - const struct drm_color_lut *shaper_lut, *lut3d; - uint32_t lut3d_size, shaper_size; - + enum drm_transfer_function blend_tf = DRM_TRANSFER_FUNCTION_DEFAULT; + const struct drm_color_lut *shaper_lut, *lut3d, *blend_lut; + uint32_t lut3d_size, shaper_size, blend_size; + int ret; + /* We have nothing to do here, return */ if (!plane_state->color_mgmt_changed) return 0; @@ -940,8 +970,30 @@ amdgpu_dm_plane_set_color_properties(struct drm_plane_state *plane_state, ret = amdgpu_dm_atomic_shaper_lut(shaper_lut, false, drm_tf_to_dc_tf(shaper_tf), shaper_size, dc_plane_state->in_shaper_func); + if (ret) { + drm_dbg_kms(plane_state->plane->dev, + "setting plane %d shaper/3d lut failed.\n", + plane_state->plane->index); - return ret; + return ret; + } + + blend_tf = dm_plane_state->blend_tf; + blend_lut = __extract_blob_lut(dm_plane_state->blend_lut, &blend_size); + blend_size = blend_lut != NULL ? blend_size : 0; + + ret = amdgpu_dm_atomic_blend_lut(blend_lut, false, + drm_tf_to_dc_tf(blend_tf), + blend_size, dc_plane_state->blend_tf); + if (ret) { + drm_dbg_kms(plane_state->plane->dev, + "setting plane %d gamma lut failed.\n", + plane_state->plane->index); + + return ret; + } + + return 0; } #endif From patchwork Sun Apr 23 14:10:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86738 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2222322vqo; Sun, 23 Apr 2023 07:26:34 -0700 (PDT) X-Google-Smtp-Source: AKy350ZbHBnRJPg+vm38CJL+aiO68Fiwa5G5JuzlgVicr8SB2N3wwVhzfKrJVawJplw/Wim+LTLj X-Received: by 2002:a05:6a20:1583:b0:f0:a283:4854 with SMTP id h3-20020a056a20158300b000f0a2834854mr11911567pzj.13.1682259994016; Sun, 23 Apr 2023 07:26:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682259994; cv=none; d=google.com; s=arc-20160816; b=Z4rhT/OK5vydy/aXzwyW6gX7qR0gftiSiEw7J7ylI4wo2D0+uQwWfUZBpGZyXxkE2V WNJ2SHQykywomikmk4hPtBN9pb6GvjiI6enbjXPoiscrgMlgHlLHMGLdjm/jKD14Ma/p jXEne3m1dRinQH9icXZE3oiu7/mL+OR3g5dFnaznWXHkBBVdpzuh1ygzhcl/tvYJm+kP vUkqrBdbUs8uRdus1gnXnBAfMK9KBzxFw363lRQJf3N1L7di5kDqSJJAt/4mev6A22O3 rE96JqGQw7j2LXbjzCGZ7AR+G2HibUYKsXh2ToKa3H+HD/dLzka75GoQWCmNVTSb6f6y 6AGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ThKpXKa9g7weqsnCPtd4OEDTst1upZkxiTxtrVaNrZo=; b=WxgyWeHwFKzRG5TqICvLgbtvDLLQlW5bqjCFMRLurq/0UMp6kDM4BiO28kgH2FRoxt Y50SjEi5jB8t3DNA+M6LmrdqNCcEeGvUdWYtjw8XwLsnSDMOzI7rnA5Od5XmAjBJ5jPa UoOVuXYpxIyPHCSNgdcGw7eyNFHmANunwt7JcPxkKUZF7ftIZ1hiLwkuNnZIEIpGVLjd 9ef/4LPer9Lz1cJrEaXvp8IQIn2+ZXcdQizEhoxZJF5zI2f/Ss6eI9oPAWI3xA3fbUXE ys7W7+9PrXvnxEoWctMg7/4qbSBMB8NP5mbmAiLTZ4lVUx7sA+ZYijmAwXc11zKqOMWU oNaA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=l3NFJXyr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id b10-20020aa7950a000000b0063b7f1093e1si9050032pfp.110.2023.04.23.07.26.19; Sun, 23 Apr 2023 07:26:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=l3NFJXyr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230256AbjDWOQ4 (ORCPT + 99 others); Sun, 23 Apr 2023 10:16:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37150 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230319AbjDWOQx (ORCPT ); Sun, 23 Apr 2023 10:16:53 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F013612B for ; Sun, 23 Apr 2023 07:16:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=ThKpXKa9g7weqsnCPtd4OEDTst1upZkxiTxtrVaNrZo=; b=l3NFJXyryB+V2jHF63KnKZh7N/ tqMOm8AWuWPKzrRUTZoIBRHuAMeYCCdGt3zyZhG8lML4Y4SbyiSeH4cgsnk+PuIHTh1QUAq9CvWs8 9z5T3W/S83PXwvDRmBsw5p/3CC7voRayxUW6LM3tY/7iQFnurh1IFNvRcJW89Jv2R14jgU8YusFOz 9r6QKI6UIOXsTGJFnns4kA2D8gMZ4Tu42j75bvDum/zMJmIYYFepEvGgw7YIgis1VI2M1RSmzDLN6 jxDKMmxcfaZ2ljNRocczsja39KWG2iEr8Ljvto2RTcqBnHTRuBw0EDa3ENcgkboVvVAlSIqvKZ2gO 4Xx/7DWw==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaTi-00ANVs-Ti; Sun, 23 Apr 2023 16:14:11 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 39/40] drm/amd/display: copy dc_plane color settings to surface_updates Date: Sun, 23 Apr 2023 13:10:51 -0100 Message-Id: <20230423141051.702990-40-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763977455247190933?= X-GMAIL-MSGID: =?utf-8?q?1763977455247190933?= As per previous code, copy shaper, 3d and blend settings from dc_plane to surface_updates before commit. Signed-off-by: Melissa Wen --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 0e3b6d414ec4..cdaaec1b2a3a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7987,11 +7987,13 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, continue; bundle->surface_updates[planes_count].surface = dc_plane; - if (new_pcrtc_state->color_mgmt_changed) { + if (new_pcrtc_state->color_mgmt_changed || new_plane_state->color_mgmt_changed) { bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction; bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func; bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix; bundle->surface_updates[planes_count].hdr_mult = dc_plane->hdr_mult; + bundle->surface_updates[planes_count].func_shaper = dc_plane->in_shaper_func; + bundle->surface_updates[planes_count].lut3d_func = dc_plane->lut3d_func; } amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state, From patchwork Sun Apr 23 14:10:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86746 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2230763vqo; Sun, 23 Apr 2023 07:47:05 -0700 (PDT) X-Google-Smtp-Source: AKy350YACG2qM+nVh2aSxYRDJRIP1eNFsPTBrFWw62lZP85XwRubGgMNhSiPboeM9nL54XROewGw X-Received: by 2002:a05:6a20:d906:b0:ef:bd:38 with SMTP id jd6-20020a056a20d90600b000ef00bd0038mr12551550pzb.55.1682261225387; Sun, 23 Apr 2023 07:47:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682261225; cv=none; d=google.com; s=arc-20160816; b=Kf5uE3vgbFmrGe05PGyiTHkp3cRO2Evda3On1ukC8jVT60xvGilhkmgUJwANPPWAGM LMd6fvFnHV9/RjVlcc4qmGve4TLH2OhtpX/YFAzxumCRwVHX1UTXXhaK/1v4SzLD2/XD 1Tp9u9xOpH0MEAgJ5HX5HkRRxAi0bRA8ziWxEHEnKKgPhBW0g/eyBFK8J2qtynj8flnx bxUpE+3K4wGouZKZe5gSwnHT3M7OrDDX/osjXJ1BYFzCw4MXnLCMHm4VmBIjnXEHfRcT 51TxHKEVzPETYXQ1vDVgrt3zzjnhqFMPkndhzl/9FE7ThyLdACDTl3uugf34jlHeEC3Z TVFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=DSe48vE9nywjx4G3xnygTop+WxvlePBvLA+a/JHlHUc=; b=sgR8Phbv+bWQ11O6K+jedzEopkyki+L+pT4mpgDaGI15qlMXT0tvICkqz+4CSpahKw RCXj6PNbpSK5VflxRfPHe/v8UkY5Ua1K359su94LqIKh8fHZpi5cmUZqWB+KGLMqxb+s z+LGYPYFwhhle/z+dvYvhZp/dTSGwuL3cFZUVcRrfNvPcyBmubzI0jHEdL5x9ejUK9sw uD6TcSEirXbZO9xnOHuWRi4LNFsoRYUUaxBzNdjf0mAB5sFsY1w4xftvJrwRNFOYazdh GdkalsDeuLxOtvZ31X8Zyp4glFxdGIlLm7htk9qWHCCXrWCBsFJbzzLYoBnOo05s3BUP rm1g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=JIxgWWwN; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id i7-20020a654847000000b0051b1542d6efsi8920567pgs.213.2023.04.23.07.46.50; Sun, 23 Apr 2023 07:47:05 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=JIxgWWwN; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230385AbjDWOPl (ORCPT + 99 others); Sun, 23 Apr 2023 10:15:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230331AbjDWOP3 (ORCPT ); Sun, 23 Apr 2023 10:15:29 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2D7412D46 for ; Sun, 23 Apr 2023 07:15:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=DSe48vE9nywjx4G3xnygTop+WxvlePBvLA+a/JHlHUc=; b=JIxgWWwNV5I9b+JeGqYfWNgjd/ 8rdv1Drcdv9QZIxwJVANyd5HLbtCLyJJIETXuvP3ivC1Y+Us68jrlyzzfufTze/73gCrizVxU9123 opcPsg0fkAlNGppOPlNtzSPq2SYKd2lWiMnd3ZnN9T2pEo7lItOuqSSAdCqwC2kHLj0F9uDSgdqSV td0yVqEI81iD3lVIlbco7S03v3nAe1rBELF/dPEimmtFKifIBVZt+URe014F5pQ8kWa0kCbQC6Kpr C5K9Ke68c/8CTe677l0PGaTwnXYZmlBm4JVOkhN8HCgMmbvHNUtn8LyQ9bWi9+he4fShwiR1rd6GQ 9jsCqjeQ==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaTl-00ANVs-MW; Sun, 23 Apr 2023 16:14:13 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , linux-kernel@vger.kernel.org Subject: [RFC PATCH 40/40] drm/amd/display: allow newer DC hardware to use degamma ROM for PQ/HLG Date: Sun, 23 Apr 2023 13:10:52 -0100 Message-Id: <20230423141051.702990-41-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763978746362590979?= X-GMAIL-MSGID: =?utf-8?q?1763978746362590979?= From: Joshua Ashton Need to funnel the color caps through to these functions so it can check that the hardware is capable. Signed-off-by: Joshua Ashton --- .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 34 ++++++++++++------- 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index a034c0c0d383..f0b5f09b9146 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -336,6 +336,7 @@ static int amdgpu_dm_set_atomic_regamma(struct dc_stream_state *stream, /** * __set_input_tf - calculates the input transfer function based on expected * input space. + * @caps: dc color capabilities * @func: transfer function * @lut: lookup table that defines the color space * @lut_size: size of respective lut. @@ -343,7 +344,7 @@ static int amdgpu_dm_set_atomic_regamma(struct dc_stream_state *stream, * Returns: * 0 in case of success. -ENOMEM if fails. */ -static int __set_input_tf(struct dc_transfer_func *func, +static int __set_input_tf(struct dc_color_caps *caps, struct dc_transfer_func *func, const struct drm_color_lut *lut, uint32_t lut_size) { struct dc_gamma *gamma = NULL; @@ -360,7 +361,7 @@ static int __set_input_tf(struct dc_transfer_func *func, __drm_lut_to_dc_gamma(lut, gamma, false); } - res = mod_color_calculate_degamma_params(NULL, func, gamma, gamma != NULL); + res = mod_color_calculate_degamma_params(caps, func, gamma, gamma != NULL); if (gamma) dc_gamma_release(&gamma); @@ -512,7 +513,7 @@ static int amdgpu_dm_atomic_blend_lut(const struct drm_color_lut *blend_lut, func_blend->tf = tf; func_blend->sdr_ref_white_level = 80; /* hardcoded for now */ - ret = __set_input_tf(func_blend, blend_lut, blend_size); + ret = __set_input_tf(NULL, func_blend, blend_lut, blend_size); } else { func_blend->type = TF_TYPE_BYPASS; func_blend->tf = TRANSFER_FUNCTION_LINEAR; @@ -819,7 +820,8 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc, } static int map_crtc_degamma_to_dc_plane(struct dm_crtc_state *crtc, - struct dc_plane_state *dc_plane_state) + struct dc_plane_state *dc_plane_state, + struct dc_color_caps *caps) { const struct drm_color_lut *degamma_lut; enum dc_transfer_func_predefined tf = TRANSFER_FUNCTION_SRGB; @@ -874,7 +876,7 @@ static int map_crtc_degamma_to_dc_plane(struct dm_crtc_state *crtc, dc_plane_state->in_transfer_func->tf = TRANSFER_FUNCTION_LINEAR; - r = __set_input_tf(dc_plane_state->in_transfer_func, + r = __set_input_tf(caps, dc_plane_state->in_transfer_func, degamma_lut, degamma_size); if (r) return r; @@ -887,7 +889,7 @@ static int map_crtc_degamma_to_dc_plane(struct dm_crtc_state *crtc, dc_plane_state->in_transfer_func->tf = tf; if (tf != TRANSFER_FUNCTION_SRGB && - !mod_color_calculate_degamma_params(NULL, + !mod_color_calculate_degamma_params(caps, dc_plane_state->in_transfer_func, NULL, false)) return -ENOMEM; } @@ -898,7 +900,8 @@ static int map_crtc_degamma_to_dc_plane(struct dm_crtc_state *crtc, #ifdef CONFIG_STEAM_DECK static int __set_dm_plane_degamma(struct drm_plane_state *plane_state, - struct dc_plane_state *dc_plane_state) + struct dc_plane_state *dc_plane_state, + struct dc_color_caps *color_caps) { struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state); const struct drm_color_lut *degamma_lut; @@ -907,6 +910,9 @@ __set_dm_plane_degamma(struct drm_plane_state *plane_state, bool has_degamma_lut; int ret; + if (dc_plane_state->ctx && dc_plane_state->ctx->dc) + color_caps = &dc_plane_state->ctx->dc->caps.color; + degamma_lut = __extract_blob_lut(dm_plane_state->degamma_lut, °amma_size); has_degamma_lut = degamma_lut && @@ -928,8 +934,8 @@ __set_dm_plane_degamma(struct drm_plane_state *plane_state, dc_plane_state->in_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS; - ret = __set_input_tf(dc_plane_state->in_transfer_func, - degamma_lut, degamma_size); + ret = __set_input_tf(color_caps, dc_plane_state->in_transfer_func, + degamma_lut, degamma_size); if (ret) return ret; } else { @@ -945,7 +951,8 @@ __set_dm_plane_degamma(struct drm_plane_state *plane_state, static int amdgpu_dm_plane_set_color_properties(struct drm_plane_state *plane_state, - struct dc_plane_state *dc_plane_state) + struct dc_plane_state *dc_plane_state, + struct dc_color_caps *color_caps) { struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state); enum drm_transfer_function shaper_tf = DRM_TRANSFER_FUNCTION_DEFAULT; @@ -1014,6 +1021,7 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, struct drm_plane_state *plane_state, struct dc_plane_state *dc_plane_state) { + struct dc_color_caps *color_caps = NULL; bool has_crtc_cm_degamma; int ret; @@ -1025,11 +1033,11 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, has_crtc_cm_degamma = (crtc->cm_has_degamma || crtc->cm_is_degamma_srgb); #ifdef CONFIG_STEAM_DECK - ret = amdgpu_dm_plane_set_color_properties(plane_state, dc_plane_state); + ret = amdgpu_dm_plane_set_color_properties(plane_state, dc_plane_state, color_caps); if(ret) return ret; - ret = __set_dm_plane_degamma(plane_state, dc_plane_state); + ret = __set_dm_plane_degamma(plane_state, dc_plane_state, color_caps); if (ret != -EINVAL) return ret; @@ -1054,7 +1062,7 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, * linearize (implicit degamma) from sRGB/BT709 according to * the input space. */ - ret = map_crtc_degamma_to_dc_plane(crtc, dc_plane_state); + ret = map_crtc_degamma_to_dc_plane(crtc, dc_plane_state, color_caps); if (ret) return ret; }