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[8.43.85.97]) by mx.google.com with ESMTPS id x26-20020a1709065ada00b0094f06597eeesi6401864ejs.108.2023.04.23.05.18.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 05:18:55 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 13F223857353 for ; Sun, 23 Apr 2023 12:18:49 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgau1.qq.com (smtpbgau1.qq.com [54.206.16.166]) by sourceware.org (Postfix) with ESMTPS id B0CE23858D35 for ; Sun, 23 Apr 2023 12:18:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B0CE23858D35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp71t1682252294tcchl85d Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Sun, 23 Apr 2023 20:18:13 +0800 (CST) X-QQ-SSF: 01400000000000F0P000000A0000000 X-QQ-FEAT: rGm7xzoh3hkiQNnlU3HeO9YwYoXy/je9atwuL6JJ1vHtDmUw8ELZjFpAN1dh/ JsqNDIihMoSqncwgJ5C5Csu2l0qGcNTIYxxLH6wgQMNtQBTo50AuVBTyJKdE4vwtxnR+3B9 XYJxVj5GDFlOcoFNCq9hyi1oJw0ZbZZuSxFDZQxabPv0br07vdYjijEgV7j/vwn1UfyCjjF To+S1KU/EGoga6LSCqe87DeVbR4/Csp4FIJyiPAcHtKSHm4Gw75w2Q7xjad7/eAPLyYWpGk 1qE4qcKzPe63rbJCqyKVmkDhTdEJrtkhWBaJXcy1ARtQj6upZJFBpKi6cvRE0RfjD6eT29o o+QFUzU80g9XziMaifq/FLxM55D+zWnwxQcX8bjNl199dKYKl0gtocof8fWWNqF3x3ZwDx0 svwDctOMLfM= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 10081467234652817861 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, jeffreyalaw@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Eliminate redundant vsetvli for duplicate AVL def Date: Sun, 23 Apr 2023 20:18:12 +0800 Message-Id: <20230423121812.95392-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763969424983773128?= X-GMAIL-MSGID: =?utf-8?q?1763969424983773128?= From: Juzhe-Zhong This patch is the V2 patch:https://patchwork.sourceware.org/project/gcc/patch/20230328010124.235703-1-juzhe.zhong@rivai.ai/ Address comments from Jeff. Add comments for all_avail_in_compatible_p and refine comments of codes. gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (vector_infos_manager::all_avail_in_compatible_p): New function. (pass_vsetvl::refine_vsetvls): Optimize vsetvls. * config/riscv/riscv-vsetvl.h: New function. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/avl_single-102.c: New test. --- gcc/config/riscv/riscv-vsetvl.cc | 44 +++++++++++++++++-- gcc/config/riscv/riscv-vsetvl.h | 1 + .../riscv/rvv/vsetvl/avl_single-102.c | 16 +++++++ 3 files changed, 58 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index fa68b8a0462..89a45a428a4 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -2446,6 +2446,26 @@ vector_infos_manager::all_same_ratio_p (sbitmap bitdata) const return true; } +/* Return TRUE if the incoming vector configuration state + to CFG_BB is compatible with the vector configuration + state in CFG_BB, FALSE otherwise. */ +bool +vector_infos_manager::all_avail_in_compatible_p (const basic_block cfg_bb) const +{ + const auto &info = vector_block_infos[cfg_bb->index].local_dem; + sbitmap avin = vector_avin[cfg_bb->index]; + unsigned int bb_index; + sbitmap_iterator sbi; + EXECUTE_IF_SET_IN_BITMAP (avin, 0, bb_index, sbi) + { + const auto &avin_info + = static_cast (*vector_exprs[bb_index]); + if (!info.compatible_p (avin_info)) + return false; + } + return true; +} + bool vector_infos_manager::all_same_avl_p (const basic_block cfg_bb, sbitmap bitdata) const @@ -3816,9 +3836,27 @@ pass_vsetvl::refine_vsetvls (void) const m_vector_manager->to_refine_vsetvls.add (rinsn); continue; } - rinsn = PREV_INSN (rinsn); - rtx new_pat = gen_vsetvl_pat (VSETVL_VTYPE_CHANGE_ONLY, info, NULL_RTX); - change_insn (rinsn, new_pat); + + /* If all incoming edges to a block have a vector state that is compatbile + with the block. In such a case we need not emit a vsetvl in the current + block. */ + + gcc_assert (has_vtype_op (insn->rtl ())); + rinsn = PREV_INSN (insn->rtl ()); + gcc_assert (vector_config_insn_p (PREV_INSN (insn->rtl ()))); + if (m_vector_manager->all_avail_in_compatible_p (cfg_bb)) + { + size_t id = m_vector_manager->get_expr_id (info); + if (bitmap_bit_p (m_vector_manager->vector_del[cfg_bb->index], id)) + continue; + eliminate_insn (rinsn); + } + else + { + rtx new_pat + = gen_vsetvl_pat (VSETVL_VTYPE_CHANGE_ONLY, info, NULL_RTX); + change_insn (rinsn, new_pat); + } } } diff --git a/gcc/config/riscv/riscv-vsetvl.h b/gcc/config/riscv/riscv-vsetvl.h index 9041eee1281..d7a6c14e931 100644 --- a/gcc/config/riscv/riscv-vsetvl.h +++ b/gcc/config/riscv/riscv-vsetvl.h @@ -452,6 +452,7 @@ public: bool all_same_ratio_p (sbitmap) const; bool all_empty_predecessor_p (const basic_block) const; + bool all_avail_in_compatible_p (const basic_block) const; void release (void); void create_bitmap_vectors (void); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c new file mode 100644 index 00000000000..8236d4e7f18 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */ + +#include "riscv_vector.h" + +void f (int8_t* base1,int8_t* base2,int8_t* out,int n) +{ + vint8mf4_t v = __riscv_vle8_v_i8mf4 (base1, 32); + for (int i = 0; i < n; i++){ + v = __riscv_vor_vx_i8mf4 (v, 101, 32); + v = __riscv_vle8_v_i8mf4_tu (v, base2, 32); + } + __riscv_vse8_v_i8mf4 (out, v, 32); +} + +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */