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[37.212.18.133]) by smtp.gmail.com with ESMTPSA id u11-20020adff88b000000b0022e2eaa2bdcsm21310581wrp.98.2022.10.22.08.13.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:13:00 -0700 (PDT) From: Siarhei Volkau Cc: Siarhei Volkau , Krzysztof Kozlowski , Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Paul Cercueil , Jiri Slaby , linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v2 1/2] dt-bindings: serial: ingenic: Add support for the JZ4750/55 SoCs Date: Sat, 22 Oct 2022 18:12:23 +0300 Message-Id: <20221022151224.4000238-2-lis8215@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221022151224.4000238-1-lis8215@gmail.com> References: <20221022151224.4000238-1-lis8215@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747401437958611036?= X-GMAIL-MSGID: =?utf-8?q?1747401437958611036?= These SoCs UART block are the same as JZ4725b' one, the difference is outside of the block - it is in the clock generation unit (CGU). The difference requires to make a quirk for early console init. Acked-by: Krzysztof Kozlowski Signed-off-by: Siarhei Volkau --- Documentation/devicetree/bindings/serial/ingenic,uart.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/ingenic,uart.yaml b/Documentation/devicetree/bindings/serial/ingenic,uart.yaml index 9ca7a18ec..315ceb722 100644 --- a/Documentation/devicetree/bindings/serial/ingenic,uart.yaml +++ b/Documentation/devicetree/bindings/serial/ingenic,uart.yaml @@ -20,6 +20,7 @@ properties: oneOf: - enum: - ingenic,jz4740-uart + - ingenic,jz4750-uart - ingenic,jz4760-uart - ingenic,jz4780-uart - ingenic,x1000-uart @@ -31,6 +32,9 @@ properties: - items: - const: ingenic,jz4725b-uart - const: ingenic,jz4740-uart + - items: + - const: ingenic,jz4755-uart + - const: ingenic,jz4750-uart reg: maxItems: 1 From patchwork Sat Oct 22 15:12:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siarhei Volkau X-Patchwork-Id: 7895 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4242:0:0:0:0:0 with SMTP id s2csp1247206wrr; Sat, 22 Oct 2022 08:16:19 -0700 (PDT) X-Google-Smtp-Source: AMsMyM41ujEwQvPg9PR1SrwW9tuAsHdt0hnEGOK8I/0BF2ZfrWIM7ic8R95Z5EBikpvyn6J/ruOi X-Received: by 2002:a50:fb0f:0:b0:458:df03:c3aa with SMTP id d15-20020a50fb0f000000b00458df03c3aamr22005705edq.83.1666451778908; Sat, 22 Oct 2022 08:16:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666451778; cv=none; d=google.com; s=arc-20160816; b=h+rdHK8Z7adz9WbSBPCo81ImaY0yPEOQrEnFew37hrHSYQPxGFNPVNaYRdQJN6ok79 cODaIVY/ehNE5HNlGmKuKxNZ7lyo/u19OFScSpuHBZiJwtqycbC1n3wNnn3y7/kGOTXg g4hEdK3EpxhFduLB/fSBjxe/iCzY830RhEgemXNHdeO3xgT079HGdMKzuEHq6WMz8usy rNENnSXfGCNkkgEBLfSyuMI06/6c6g3d3wTaBQnwx7RjSAIj2MtV9FL/cAlYT9fATPxY Zrf9Nr5V1r+kAyoxJeC+KYz5aciBHghPYPO2FR8ZpiIlB58ukVFwnGHiNgaVYqG1Lk9w k/HA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:to:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:from :dkim-signature; bh=/tn9ME0TL0Y61oMWgSDpk8x/grA5ek9OA4zh/3kmEPY=; b=bZwC+bTbWEIWCjOmTTRFyRY15OjdgQjsNRqSAzEGuEbQhOKFJNh05Zbawx6ZTmlX81 wT3nSGNeJ4b591scuPqR9sL3XMMnr9DViLo2sxSWR96pvUvmPKHC2syfMKR746j0nxXY 5h2/uqNuuJZcr9kE2URU+7DQKeX/fQtW4+yJPH2TvX1F3lyD7TdmJWeyTM9ITYo2FmM8 mYNq5DnF3k3r0L/SGEQOJNUiFzx4qxZ8lzpR5MaTtOLkJK5QMX/cH/jVyZvFinokgdaJ DyqeSOWbqBbwCstiuB4YfV3ZZWXdUKlilCUaKmWXU0014dTAPLpoZdNh5+bStvvUD7QP awzw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20210112 header.b="GW6/l8Ui"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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[37.212.18.133]) by smtp.gmail.com with ESMTPSA id u11-20020adff88b000000b0022e2eaa2bdcsm21310581wrp.98.2022.10.22.08.13.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:13:02 -0700 (PDT) From: Siarhei Volkau Cc: Siarhei Volkau , Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Paul Cercueil , Jiri Slaby , linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v2 2/2] serial: 8250/ingenic: Add support for the JZ4750/JZ4755 Date: Sat, 22 Oct 2022 18:12:24 +0300 Message-Id: <20221022151224.4000238-3-lis8215@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221022151224.4000238-1-lis8215@gmail.com> References: <20221022151224.4000238-1-lis8215@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747401340462118847?= X-GMAIL-MSGID: =?utf-8?q?1747401340462118847?= JZ4750/55/60 (but not JZ4760b) have an extra divisor in between extclk and peripheral clock, called CPCCR.ECS, the driver can't figure out the real state of the divisor without dirty hack - peek CGU CPCCR register. However, we can rely on a vendor's bootloader (u-boot 1.1.6) behavior: if (extclk > 16MHz) the divisor is enabled, so the UART driving clock is extclk/2. This behavior relies on hardware differences: most boards (if not all) with those SoCs have 12 or 24 MHz oscillators but many peripherals want 12Mhz to operate properly (AIC and USB-PHY at least). The patch doesn't affect JZ4760's behavior as it is subject for another patchset with re-classification of all supported ingenic UARTs. Link: https://github.com/carlos-wong/uboot_jz4755/blob/master/cpu/mips/jz_serial.c#L158 Signed-off-by: Siarhei Volkau --- drivers/tty/serial/8250/8250_ingenic.c | 50 ++++++++++++++++++++++---- 1 file changed, 43 insertions(+), 7 deletions(-) diff --git a/drivers/tty/serial/8250/8250_ingenic.c b/drivers/tty/serial/8250/8250_ingenic.c index 2b2f5d8d2..3ffa6b722 100644 --- a/drivers/tty/serial/8250/8250_ingenic.c +++ b/drivers/tty/serial/8250/8250_ingenic.c @@ -87,24 +87,19 @@ static void __init ingenic_early_console_setup_clock(struct earlycon_device *dev dev->port.uartclk = be32_to_cpup(prop); } -static int __init ingenic_early_console_setup(struct earlycon_device *dev, - const char *opt) +static int __init ingenic_earlycon_setup_tail(struct earlycon_device *dev, + const char *opt) { struct uart_port *port = &dev->port; unsigned int divisor; int baud = 115200; - if (!dev->port.membase) - return -ENODEV; - if (opt) { unsigned int parity, bits, flow; /* unused for now */ uart_parse_options(opt, &baud, &parity, &bits, &flow); } - ingenic_early_console_setup_clock(dev); - if (dev->baud) baud = dev->baud; divisor = DIV_ROUND_CLOSEST(port->uartclk, 16 * baud); @@ -129,9 +124,49 @@ static int __init ingenic_early_console_setup(struct earlycon_device *dev, return 0; } +static int __init ingenic_early_console_setup(struct earlycon_device *dev, + const char *opt) +{ + if (!dev->port.membase) + return -ENODEV; + + ingenic_early_console_setup_clock(dev); + + ingenic_earlycon_setup_tail(dev, opt); +} + +static int __init jz4750_early_console_setup(struct earlycon_device *dev, + const char *opt) +{ + if (!dev->port.membase) + return -ENODEV; + + /* + * JZ4750/55/60 (not JZ4760b) have an extra divisor + * between extclk and peripheral clock, the + * driver can't figure out the real state of the + * divisor without dirty hacks (peek CGU register). + * However, we can rely on a vendor's behavior: + * if (extclk > 16MHz) + * the divisor is enabled. + * This behavior relies on hardware differences: + * most boards with those SoCs have 12 or 24 MHz + * oscillators but many peripherals want 12Mhz + * to operate properly (AIC and USB-phy at least). + */ + ingenic_early_console_setup_clock(dev); + if (dev->port.uartclk > 16000000) + dev->port.uartclk /= 2; + + ingenic_earlycon_setup_tail(dev, opt); +} + OF_EARLYCON_DECLARE(jz4740_uart, "ingenic,jz4740-uart", ingenic_early_console_setup); +OF_EARLYCON_DECLARE(jz4750_uart, "ingenic,jz4750-uart", + jz4750_early_console_setup); + OF_EARLYCON_DECLARE(jz4770_uart, "ingenic,jz4770-uart", ingenic_early_console_setup); @@ -328,6 +363,7 @@ static const struct ingenic_uart_config x1000_uart_config = { static const struct of_device_id of_match[] = { { .compatible = "ingenic,jz4740-uart", .data = &jz4740_uart_config }, + { .compatible = "ingenic,jz4750-uart", .data = &jz4760_uart_config }, { .compatible = "ingenic,jz4760-uart", .data = &jz4760_uart_config }, { .compatible = "ingenic,jz4770-uart", .data = &jz4760_uart_config }, { .compatible = "ingenic,jz4775-uart", .data = &jz4760_uart_config },