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[2620:137:e000::1:20]) by mx.google.com with ESMTP id k15-20020a170902c40f00b001a52ce30cc2si6079847plk.420.2023.04.21.15.52.01; Fri, 21 Apr 2023 15:52:16 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=TWG0uska; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233329AbjDUWrq (ORCPT + 99 others); Fri, 21 Apr 2023 18:47:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47800 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232094AbjDUWro (ORCPT ); Fri, 21 Apr 2023 18:47:44 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BF300F2; Fri, 21 Apr 2023 15:47:38 -0700 (PDT) Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 33LMXdPV013531; Fri, 21 Apr 2023 22:47:32 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=7jtwcQ2eXKaXKxxSOLLQ1U76nRkqnQcOBDX6LutvMJw=; b=TWG0uska9j4xGrq/MCUngN4uluxi+DQZtiBulQYF7MbWxZnqZieVieek6K1yEtuJF2xE i69Ud8OOuoeGurHSbSn0Vqs+DhLwWnIt+j9z6LApZc4I2kDPjIRJXuGomMzexwXMzOoy kLdi6kgCzKzgAZ4VCOrSNMOBTM5ORrCJj3/nww6aqGLr3JRMb4elSQe7vfr4oz3i7EVy 8w/0D9w76gJIVXbbI7FDz6tn1InW9oQP8U898uUdx1Wra9fIFpopjVZGh1sDrimuj81g yrMBPUwNCqiYuqxoW9mK5SyB5EudfgT04wPS3TiY9dGUWz5n85AKCzy1Ep1s5HYzLmIk qQ== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3q3thds8jt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 21 Apr 2023 22:47:32 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 33LMlVeM021444 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 21 Apr 2023 22:47:31 GMT Received: from abhinavk-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Fri, 21 Apr 2023 15:47:30 -0700 From: Abhinav Kumar To: , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter CC: , , , , Subject: [PATCH 1/2] drm/msm/dpu: remove DPU_DSPP_GC handling in dspp flush Date: Fri, 21 Apr 2023 15:47:19 -0700 Message-ID: <20230421224721.12738-1-quic_abhinavk@quicinc.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: zYwcGwWxVyblow5OQOQRT_NVx4JjwbyW X-Proofpoint-GUID: zYwcGwWxVyblow5OQOQRT_NVx4JjwbyW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-21_08,2023-04-21_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 mlxlogscore=853 mlxscore=0 impostorscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304210199 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763828078216640250?= X-GMAIL-MSGID: =?utf-8?q?1763828078216640250?= Gamma correction blocks (GC) are not used today so lets remove the usage of DPU_DSPP_GC in the dspp flush to make it easier to remove GC from the catalog. We can add this back when GC is properly supported in DPU with one of the standard DRM properties. Signed-off-by: Abhinav Kumar Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index bbdc95ce374a..57adaebab563 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -336,9 +336,6 @@ static void dpu_hw_ctl_update_pending_flush_dspp_sub_blocks( case DPU_DSPP_PCC: ctx->pending_dspp_flush_mask[dspp - DSPP_0] |= BIT(4); break; - case DPU_DSPP_GC: - ctx->pending_dspp_flush_mask[dspp - DSPP_0] |= BIT(5); - break; default: return; } From patchwork Fri Apr 21 22:47:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhinav Kumar X-Patchwork-Id: 86537 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1383719vqo; Fri, 21 Apr 2023 15:52:25 -0700 (PDT) X-Google-Smtp-Source: AKy350Z1oIzsgfpuxKCdQu+Y1Sp/Nlk+IW8d715UOiyOOjhK1R5J8Ggr5DAWf77w1+DuG+VU1qI2 X-Received: by 2002:a05:6a20:9591:b0:ef:a31b:af8e with SMTP id iu17-20020a056a20959100b000efa31baf8emr8184994pzb.25.1682117545216; Fri, 21 Apr 2023 15:52:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682117545; cv=none; d=google.com; s=arc-20160816; b=oNruRg9xJd1nKvicAN9V4wP9swQX0QpQoSdKLpO/FKSChlDkTYsb+m30UUGERhmg35 WfLLq64jXzHexmGXFpPUmVTAbMaIB3ZBEZLdECmeUP/tTS3BSmPScghudQ781ME2dT6a aVDHc/KuGDuzgQMEwBZVWEq247BIdvM+fMcU0AAa04Uz9XyOuKjnJRAzf7/qfjJrJTNq +WM76m8iEdDOVixtSNrFzokk3T+RyT1mZLmzTmfUCY+/g5N8WmfmVDK/jqYxm5Auln2K 5LR/BooUnTfl+lqFggDrNlUsv2VbKmsbYmPa3jLFoOS3RFpNgbsiqQrIC1gXHgN6RohV oO2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=8EE8timcjGGxQsm//IdKVah5+CYhJ5HJN8lauwDkGgc=; b=XDy1BtLwMU0y6lq4Aoga+WBVC8CnwCaLgfOSjhLQKCAguDpDzjITFiWkoKqwZi9N7K vDBuQ//FMflcNdQYrjZweAlOQ7R75sofcpLc34ah9pyqVDi1FeuFVNyw1K8l/3KBaQx5 fdmoBhgbCR3FhLMPJQo5VuY8liXm2loK+Pz0h0Vhsyxmmgdxz1+2qyG75P1KC0Mjl34b +wgaHQAjszMgkwc29R/WKY0/atMj1byfbWbarvP4+wfaKEni6qN2ba1Q3Rkuovw8oEEG JudL9tD7f5xsdMJFvrd4UKF0dPdLGzb/dzuVcp8ddzhCkoQkqn5N+DSMGRoGc1vHpRSC rDEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=pKe6sDCs; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Abhinav Kumar Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 4 +--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 6 ------ 2 files changed, 1 insertion(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 03f162af1a50..badfc3680485 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -91,7 +91,7 @@ #define MERGE_3D_SM8150_MASK (0) -#define DSPP_MSM8998_MASK BIT(DPU_DSPP_PCC) | BIT(DPU_DSPP_GC) +#define DSPP_MSM8998_MASK BIT(DPU_DSPP_PCC) #define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC) @@ -449,8 +449,6 @@ static const struct dpu_lm_sub_blks qcm2290_lm_sblk = { static const struct dpu_dspp_sub_blks msm8998_dspp_sblk = { .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700, .len = 0x90, .version = 0x10007}, - .gc = { .id = DPU_DSPP_GC, .base = 0x17c0, - .len = 0x90, .version = 0x10007}, }; static const struct dpu_dspp_sub_blks sc7180_dspp_sblk = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 71584cd56fd7..e0dcef04bc61 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -127,12 +127,10 @@ enum { /** * DSPP sub-blocks * @DPU_DSPP_PCC Panel color correction block - * @DPU_DSPP_GC Gamma correction block * @DPU_DSPP_IGC Inverse gamma correction block */ enum { DPU_DSPP_PCC = 0x1, - DPU_DSPP_GC, DPU_DSPP_IGC, DPU_DSPP_MAX }; @@ -433,22 +431,18 @@ struct dpu_sspp_sub_blks { * @maxwidth: Max pixel width supported by this mixer * @maxblendstages: Max number of blend-stages supported * @blendstage_base: Blend-stage register base offset - * @gc: gamma correction block */ struct dpu_lm_sub_blks { u32 maxwidth; u32 maxblendstages; u32 blendstage_base[MAX_BLOCKS]; - struct dpu_pp_blk gc; }; /** * struct dpu_dspp_sub_blks: Information of DSPP block - * @gc : gamma correction block * @pcc: pixel color correction block */ struct dpu_dspp_sub_blks { - struct dpu_pp_blk gc; struct dpu_pp_blk pcc; };