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[2620:137:e000::1:20]) by mx.google.com with ESMTP id j69-20020a638048000000b00518af507f3asi2865287pgd.10.2023.04.20.16.34.03; Thu, 20 Apr 2023 16:34:15 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231234AbjDTXW7 (ORCPT + 99 others); Thu, 20 Apr 2023 19:22:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54396 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231504AbjDTXW5 (ORCPT ); Thu, 20 Apr 2023 19:22:57 -0400 Received: from fudo.makrotopia.org (fudo.makrotopia.org [IPv6:2a07:2ec0:3002::71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D2EC2697; Thu, 20 Apr 2023 16:22:56 -0700 (PDT) Received: from local by fudo.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.96) (envelope-from ) id 1ppdc6-0003XL-1R; Fri, 21 Apr 2023 01:22:54 +0200 Date: Fri, 21 Apr 2023 00:22:49 +0100 From: Daniel Golle To: devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Thierry Reding , Uwe =?iso-8859-1?q?Kleine-K=F6ni?= =?iso-8859-1?q?g?= , Matthias Brugger , AngeloGioacchino Del Regno , John Crispin Subject: [PATCH v3 1/2] dt-bindings: pwm: mediatek: Add mediatek,mt7981 compatible Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763740122389738484?= X-GMAIL-MSGID: =?utf-8?q?1763740122389738484?= Add compatible string for the PWM unit found of the MediaTek MT7981 SoC. This is in preparation to adding support in the pwm-mediatek.c driver. Signed-off-by: Daniel Golle Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pwm/mediatek,mt2712-pwm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pwm/mediatek,mt2712-pwm.yaml b/Documentation/devicetree/bindings/pwm/mediatek,mt2712-pwm.yaml index 8e176ba7a525f..0fbe8a6469eb2 100644 --- a/Documentation/devicetree/bindings/pwm/mediatek,mt2712-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/mediatek,mt2712-pwm.yaml @@ -22,6 +22,7 @@ properties: - mediatek,mt7623-pwm - mediatek,mt7628-pwm - mediatek,mt7629-pwm + - mediatek,mt7981-pwm - mediatek,mt7986-pwm - mediatek,mt8183-pwm - mediatek,mt8365-pwm From patchwork Thu Apr 20 23:23:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Golle X-Patchwork-Id: 86084 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp685915vqo; Thu, 20 Apr 2023 16:25:51 -0700 (PDT) X-Google-Smtp-Source: AKy350ZkEZlyxtiRZZYhTN35Y3CijYdHEtYZhtsGCp7smGffHAeBrUu26B+5r9S9LZuaEz3OM30T X-Received: by 2002:a05:6a21:3286:b0:f1:fa94:ee65 with SMTP id yt6-20020a056a21328600b000f1fa94ee65mr4431983pzb.4.1682033150986; Thu, 20 Apr 2023 16:25:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682033150; cv=none; d=google.com; s=arc-20160816; b=nAjX8RuwmRYrgXwXpHnmXcwhb3gXEwx4AjygW/09k0ocqFbI3dZVpyysjzGHDSvLNu Micw2tW3ELaFRKj8ohM0/DFcrG6jz1r1Q69diNX+pbikPDdMSywSvQ68idw2JqUNJfBb HUkt/yGArFvYmPdVYRihh/J0ntAgxFClMedgfqSqWNySmmhgQDwv0+0IKKwGRFu6JA0d qWX2KGOzjfgy72rPgqqrboPJwUoI025c/TSEd8s28XT+TyBdTOp/YmtM3stnQefPmrH6 55WpNeTQu/ceJHqdS1ExPWNyHOWytA66K9m/RiFBHLCybnhlNhINNuHnz6iuKTk2D5ns 36KQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:in-reply-to:content-disposition:mime-version :references:message-id:subject:to:from:date; bh=UWSwbFCxnvo9VEXfgZz9RfV2StvwzWiOoWNBXRuQrbc=; b=nYCj/3Sj280cYvbr9pxOQ7kkPmaoe7WOS3/d89AB4bJXRqdXHuQSPeLkJ9sSJQywom RXG2axCtBN+nDBoSmEZX3fWd1K1LEiNxXNXKHRdXHKCVcLyhIckvjToCfvQ/Nz6HWG9B 6BTtMwR6A68IonYVSCG9X4gMULbkCu2sAJz0gVcXKMkoK1ITFyeRbyiopXc/jH0hQ/yE 43XFZPsCPvtxbP1i7o+meHSlIdLw7w5pCn5wZ483FjAHSrX7A5Z+GCY2MDUdSA2kTJNu tzeyLgtM5pRjXzTBUSBziZG6CBNMbmJBDn/SK3zhBrE2hImhlzKVD+zQw9uuxxSKkiDV NtgA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id s23-20020a632c17000000b0051b32aa267asi2957650pgs.671.2023.04.20.16.25.36; Thu, 20 Apr 2023 16:25:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231504AbjDTXXf (ORCPT + 99 others); Thu, 20 Apr 2023 19:23:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54924 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232984AbjDTXXc (ORCPT ); Thu, 20 Apr 2023 19:23:32 -0400 Received: from fudo.makrotopia.org (fudo.makrotopia.org [IPv6:2a07:2ec0:3002::71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA37B61B3; Thu, 20 Apr 2023 16:23:28 -0700 (PDT) Received: from local by fudo.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.96) (envelope-from ) id 1ppdcd-0003Xr-0q; Fri, 21 Apr 2023 01:23:27 +0200 Date: Fri, 21 Apr 2023 00:23:21 +0100 From: Daniel Golle To: linux-pwm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Thierry Reding , Uwe =?iso-8859-1?q?Kleine-K=F6ni?= =?iso-8859-1?q?g?= , Matthias Brugger , AngeloGioacchino Del Regno , John Crispin Subject: [PATCH v3 2/2] pwm: mediatek: Add support for MT7981 Message-ID: <7f404164337a2e06a6026c5c7e066e0cfba1fb32.1682007088.git.daniel@makrotopia.org> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763739593020136746?= X-GMAIL-MSGID: =?utf-8?q?1763739593020136746?= The PWM unit on MT7981 uses different register offsets than previous MediaTek PWM units. Add support for these new offsets and add support for PWM on MT7981 which has 3 PWM channels, one of them is typically used for a temperature controlled fan. While at it, also reorder pwm_mediatek_of_data entries to restore alphabetic order. Signed-off-by: Daniel Golle Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger --- drivers/pwm/pwm-mediatek.c | 39 ++++++++++++++++++++++++++++++-------- 1 file changed, 31 insertions(+), 8 deletions(-) diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c index 5b5eeaff35da6..7a51d210a8778 100644 --- a/drivers/pwm/pwm-mediatek.c +++ b/drivers/pwm/pwm-mediatek.c @@ -38,6 +38,7 @@ struct pwm_mediatek_of_data { unsigned int num_pwms; bool pwm45_fixup; bool has_ck_26m_sel; + const unsigned int *reg_offset; }; /** @@ -59,10 +60,14 @@ struct pwm_mediatek_chip { const struct pwm_mediatek_of_data *soc; }; -static const unsigned int pwm_mediatek_reg_offset[] = { +static const unsigned int mtk_pwm_reg_offset_v1[] = { 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220 }; +static const unsigned int mtk_pwm_reg_offset_v2[] = { + 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240 +}; + static inline struct pwm_mediatek_chip * to_pwm_mediatek_chip(struct pwm_chip *chip) { @@ -111,7 +116,7 @@ static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip, unsigned int num, unsigned int offset, u32 value) { - writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset); + writel(value, chip->regs + chip->soc->reg_offset[num] + offset); } static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm, @@ -285,60 +290,77 @@ static const struct pwm_mediatek_of_data mt2712_pwm_data = { .num_pwms = 8, .pwm45_fixup = false, .has_ck_26m_sel = false, + .reg_offset = mtk_pwm_reg_offset_v1, }; static const struct pwm_mediatek_of_data mt6795_pwm_data = { .num_pwms = 7, .pwm45_fixup = false, .has_ck_26m_sel = false, + .reg_offset = mtk_pwm_reg_offset_v1, }; static const struct pwm_mediatek_of_data mt7622_pwm_data = { .num_pwms = 6, .pwm45_fixup = false, .has_ck_26m_sel = true, + .reg_offset = mtk_pwm_reg_offset_v1, }; static const struct pwm_mediatek_of_data mt7623_pwm_data = { .num_pwms = 5, .pwm45_fixup = true, .has_ck_26m_sel = false, + .reg_offset = mtk_pwm_reg_offset_v1, }; static const struct pwm_mediatek_of_data mt7628_pwm_data = { .num_pwms = 4, .pwm45_fixup = true, .has_ck_26m_sel = false, + .reg_offset = mtk_pwm_reg_offset_v1, }; static const struct pwm_mediatek_of_data mt7629_pwm_data = { .num_pwms = 1, .pwm45_fixup = false, .has_ck_26m_sel = false, + .reg_offset = mtk_pwm_reg_offset_v1, }; -static const struct pwm_mediatek_of_data mt8183_pwm_data = { - .num_pwms = 4, +static const struct pwm_mediatek_of_data mt7981_pwm_data = { + .num_pwms = 3, .pwm45_fixup = false, .has_ck_26m_sel = true, + .reg_offset = mtk_pwm_reg_offset_v2, }; -static const struct pwm_mediatek_of_data mt8365_pwm_data = { - .num_pwms = 3, +static const struct pwm_mediatek_of_data mt7986_pwm_data = { + .num_pwms = 2, .pwm45_fixup = false, .has_ck_26m_sel = true, + .reg_offset = mtk_pwm_reg_offset_v1, }; -static const struct pwm_mediatek_of_data mt7986_pwm_data = { - .num_pwms = 2, +static const struct pwm_mediatek_of_data mt8183_pwm_data = { + .num_pwms = 4, + .pwm45_fixup = false, + .has_ck_26m_sel = true, + .reg_offset = mtk_pwm_reg_offset_v1, +}; + +static const struct pwm_mediatek_of_data mt8365_pwm_data = { + .num_pwms = 3, .pwm45_fixup = false, .has_ck_26m_sel = true, + .reg_offset = mtk_pwm_reg_offset_v1, }; static const struct pwm_mediatek_of_data mt8516_pwm_data = { .num_pwms = 5, .pwm45_fixup = false, .has_ck_26m_sel = true, + .reg_offset = mtk_pwm_reg_offset_v1, }; static const struct of_device_id pwm_mediatek_of_match[] = { @@ -348,6 +370,7 @@ static const struct of_device_id pwm_mediatek_of_match[] = { { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data }, { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data }, { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data }, + { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data }, { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data }, { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data }, { .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data },