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Wysocki" , linux-arm-kernel@lists.infradead.org, Stephen Boyd , Lecopzer Chen , Thomas Gleixner , linux-perf-users@vger.kernel.org, Masayoshi Mizuma , Douglas Anderson , Andrey Konovalov , Joey Gouly , Masahiro Yamada , linux-kernel@vger.kernel.org Subject: [PATCH v8 01/10] arm64: Add framework to turn IPI as NMI Date: Wed, 19 Apr 2023 15:55:55 -0700 Message-ID: <20230419155341.v8.1.Ie6c132b96ebbbcddbf6954b9469ed40a6960343c@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419225604.21204-1-dianders@chromium.org> References: <20230419225604.21204-1-dianders@chromium.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763649036709119512?= X-GMAIL-MSGID: =?utf-8?q?1763649036709119512?= From: Sumit Garg Introduce framework to turn an IPI as NMI using pseudo NMIs. The main motivation for this feature is to have an IPI that can be leveraged to invoke NMI functions on other CPUs. And current prospective users are NMI backtrace and KGDB CPUs round-up whose support is added via future patches. Signed-off-by: Sumit Garg Reviewed-by: Masayoshi Mizuma Tested-by: Chen-Yu Tsai Signed-off-by: Douglas Anderson --- Changes in v8: - dynamic_ipi_setup() and dynamic_ipi_teardown() no longer take cpu param arch/arm64/include/asm/nmi.h | 17 ++++++++++ arch/arm64/kernel/Makefile | 2 +- arch/arm64/kernel/ipi_nmi.c | 65 ++++++++++++++++++++++++++++++++++++ 3 files changed, 83 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/include/asm/nmi.h create mode 100644 arch/arm64/kernel/ipi_nmi.c diff --git a/arch/arm64/include/asm/nmi.h b/arch/arm64/include/asm/nmi.h new file mode 100644 index 000000000000..2cc4b4d4090e --- /dev/null +++ b/arch/arm64/include/asm/nmi.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_NMI_H +#define __ASM_NMI_H + +#ifndef __ASSEMBLER__ + +#include + +extern bool arm64_supports_nmi(void); +extern void arm64_send_nmi(cpumask_t *mask); + +void set_smp_dynamic_ipi(int ipi); +void dynamic_ipi_setup(void); +void dynamic_ipi_teardown(void); + +#endif /* !__ASSEMBLER__ */ +#endif diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index ceba6792f5b3..d57c8f99ca69 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -34,7 +34,7 @@ obj-y := debug-monitors.o entry.o irq.o fpsimd.o \ cpufeature.o alternative.o cacheinfo.o \ smp.o smp_spin_table.o topology.o smccc-call.o \ syscall.o proton-pack.o idreg-override.o idle.o \ - patching.o + patching.o ipi_nmi.o obj-$(CONFIG_COMPAT) += sys32.o signal32.o \ sys_compat.o diff --git a/arch/arm64/kernel/ipi_nmi.c b/arch/arm64/kernel/ipi_nmi.c new file mode 100644 index 000000000000..712411eed949 --- /dev/null +++ b/arch/arm64/kernel/ipi_nmi.c @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * NMI support for IPIs + * + * Copyright (C) 2020 Linaro Limited + * Author: Sumit Garg + */ + +#include +#include +#include + +#include + +static struct irq_desc *ipi_nmi_desc __read_mostly; +static int ipi_nmi_id __read_mostly; + +bool arm64_supports_nmi(void) +{ + if (ipi_nmi_desc) + return true; + + return false; +} + +void arm64_send_nmi(cpumask_t *mask) +{ + if (WARN_ON_ONCE(!ipi_nmi_desc)) + return; + + __ipi_send_mask(ipi_nmi_desc, mask); +} + +static irqreturn_t ipi_nmi_handler(int irq, void *data) +{ + /* nop, NMI handlers for special features can be added here. */ + + return IRQ_NONE; +} + +void dynamic_ipi_setup(void) +{ + if (!ipi_nmi_desc) + return; + + if (!prepare_percpu_nmi(ipi_nmi_id)) + enable_percpu_nmi(ipi_nmi_id, IRQ_TYPE_NONE); +} + +void dynamic_ipi_teardown(void) +{ + if (!ipi_nmi_desc) + return; + + disable_percpu_nmi(ipi_nmi_id); + teardown_percpu_nmi(ipi_nmi_id); +} + +void __init set_smp_dynamic_ipi(int ipi) +{ + if (!request_percpu_nmi(ipi, ipi_nmi_handler, "IPI", &cpu_number)) { + ipi_nmi_desc = irq_to_desc(ipi); + ipi_nmi_id = ipi; + } +} From patchwork Wed Apr 19 22:55:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 85643 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp723070vqo; Wed, 19 Apr 2023 16:12:17 -0700 (PDT) X-Google-Smtp-Source: AKy350ZNSuQ4lzRPsfAYGuTR1vtmxzxWsAdSKJWJJha36sD7uOotGEphaaXjphTtTtZdZmKAeVqQ X-Received: by 2002:a05:6a20:2590:b0:f0:dedb:83b7 with SMTP id k16-20020a056a20259000b000f0dedb83b7mr116485pzd.60.1681945936771; Wed, 19 Apr 2023 16:12:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681945936; cv=none; d=google.com; s=arc-20160816; b=N7/NTJXyCMmGoNqI6YHskDEY2WEci9rBqyxwboIJizr/DFrhgNxYVkU/A66vB7bniq fPnFYqTyzPygWd+QGKdHvP8QYDCUTiR5fn8ZzcKswqDUb7dsRX6K9IoISleaXvOGVWb0 Izbn2mkX4TMpzT/masxH0MlEVyHMz5tq5xthmBLwV7dlioJKelDr9f5ANRSojskWnYQW D6Q/f29gzrZAoJ/9YvUnCINk6i43jeRy/ND85ZgW0PX6Zns/epd4/bSCTxjBtjNN7FNB daCeGtACNZQQ51qqMcKSuunCDteRk4F53TJWuam6BgPAOz4jO1iujRqsiOu1y20iOF79 mCMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Yg6b8cGZHL+pVn4pi0Hug3H2RUvB+6MRfIbO+7gLzcE=; b=bNchwy89F7MUEBU8FNZ8/oWzyRk+E7L+r+nTsaW2f7bHmJ+4OpxkpsIhPNnQcws+K3 yHUj83IA98stM7SlU9Zo/chJbBVND/7PmvgyRkyo/7GBclsR/+/Bmto4lWLBOo4iW+VQ wrsggabwnOruAEKq1MDVAJ4QNfZvcNA4kBfiLT2puX8EUgroBdK58W2qzCcX89a4lYQ6 c7BcNt0fIPn7Rf2zjqcHCH6+GhlucmCetPmwTWN+hzPkOhkGqjUZnFatvWKUdLDSkrwF puhc2eK65WV7JJ/fmA3FhvwjVAt2I7WdyrrZTHKRuIsECUyUNAMTU5NPBWGKdq/igSCm yXOw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=jml0A+YB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , linux-arm-kernel@lists.infradead.org, Stephen Boyd , Lecopzer Chen , Thomas Gleixner , linux-perf-users@vger.kernel.org, Masayoshi Mizuma , Douglas Anderson , linux-kernel@vger.kernel.org Subject: [PATCH v8 02/10] irqchip/gic-v3: Enable support for SGIs to act as NMIs Date: Wed, 19 Apr 2023 15:55:56 -0700 Message-ID: <20230419155341.v8.2.I1223c11c88937bd0cbd9b086d4ef216985797302@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419225604.21204-1-dianders@chromium.org> References: <20230419225604.21204-1-dianders@chromium.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763648142377069630?= X-GMAIL-MSGID: =?utf-8?q?1763648142377069630?= From: Sumit Garg Add support to handle SGIs as pseudo NMIs. As SGIs or IPIs default to a special flow handler: handle_percpu_devid_fasteoi_ipi(), so skip NMI handler update in case of SGIs. Also, enable NMI support prior to gic_smp_init() as allocation of SGIs as IRQs/NMIs happen as part of this routine. Signed-off-by: Sumit Garg Reviewed-by: Masayoshi Mizuma Tested-by: Chen-Yu Tsai Signed-off-by: Douglas Anderson --- (no changes since v1) drivers/irqchip/irq-gic-v3.c | 29 +++++++++++++++++++++-------- 1 file changed, 21 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index fd134e1f481a..b402a81fea59 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -482,6 +482,7 @@ static u32 gic_get_ppi_index(struct irq_data *d) static int gic_irq_nmi_setup(struct irq_data *d) { struct irq_desc *desc = irq_to_desc(d->irq); + u32 idx; if (!gic_supports_nmi()) return -EINVAL; @@ -499,16 +500,22 @@ static int gic_irq_nmi_setup(struct irq_data *d) return -EINVAL; /* desc lock should already be held */ - if (gic_irq_in_rdist(d)) { - u32 idx = gic_get_ppi_index(d); + switch (get_intid_range(d)) { + case SGI_RANGE: + break; + case PPI_RANGE: + case EPPI_RANGE: + idx = gic_get_ppi_index(d); /* Setting up PPI as NMI, only switch handler for first NMI */ if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) { refcount_set(&ppi_nmi_refs[idx], 1); desc->handle_irq = handle_percpu_devid_fasteoi_nmi; } - } else { + break; + default: desc->handle_irq = handle_fasteoi_nmi; + break; } gic_irq_set_prio(d, GICD_INT_NMI_PRI); @@ -519,6 +526,7 @@ static int gic_irq_nmi_setup(struct irq_data *d) static void gic_irq_nmi_teardown(struct irq_data *d) { struct irq_desc *desc = irq_to_desc(d->irq); + u32 idx; if (WARN_ON(!gic_supports_nmi())) return; @@ -536,14 +544,20 @@ static void gic_irq_nmi_teardown(struct irq_data *d) return; /* desc lock should already be held */ - if (gic_irq_in_rdist(d)) { - u32 idx = gic_get_ppi_index(d); + switch (get_intid_range(d)) { + case SGI_RANGE: + break; + case PPI_RANGE: + case EPPI_RANGE: + idx = gic_get_ppi_index(d); /* Tearing down NMI, only switch handler for last NMI */ if (refcount_dec_and_test(&ppi_nmi_refs[idx])) desc->handle_irq = handle_percpu_devid_irq; - } else { + break; + default: desc->handle_irq = handle_fasteoi_irq; + break; } gic_irq_set_prio(d, GICD_INT_DEF_PRI); @@ -1867,6 +1881,7 @@ static int __init gic_init_bases(void __iomem *dist_base, gic_dist_init(); gic_cpu_init(); + gic_enable_nmi_support(); gic_smp_init(); gic_cpu_pm_init(); @@ -1879,8 +1894,6 @@ static int __init gic_init_bases(void __iomem *dist_base, gicv2m_init(handle, gic_data.domain); } - gic_enable_nmi_support(); - return 0; out_free: From patchwork Wed Apr 19 22:55:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 85646 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp723647vqo; Wed, 19 Apr 2023 16:13:26 -0700 (PDT) X-Google-Smtp-Source: AKy350ZIj8oO4YFHjyeSnO3S9jCUtQQX4EXR/7FuDsbXeKWYAwZhfG46HbXmivJ4RMfAqH1c8FlY X-Received: by 2002:a05:6a20:3c86:b0:f1:bf92:51d4 with SMTP id b6-20020a056a203c8600b000f1bf9251d4mr211259pzj.45.1681946006358; Wed, 19 Apr 2023 16:13:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681946006; cv=none; d=google.com; s=arc-20160816; b=YJXbJYULf/sc5mwTzyOyghaq2MEwB96drLX3YgcokPPlQIwWzY68XF8ABkPjYUthSV lnevHHybM715AV1/xWfJHPe+x+Y4dKphadi5XwYGON4CV3tPcSB6ROzC5K8mk6ah4gr3 DYzsD+H/SkuUhQQbi7EzPmmm515TMMO+t/pziRoBsYgS5CatWrerdO1e20QGEbM8IKBT 19YFucVELxi8IT9EVqrBz5p/0BpQIAl2D/8xJaqEJsAJQedvY3OpQDRV05RWD+QC/fC9 mz6h/NdacVJukKIOtmYBsG4+FbslhN8dOdpIOs8VrFZlfFW9XXVgUhwgXouLy2Q611jL HtIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=I4TtHmnmxTTT3fwHdqQt/qizkftz4ebAquvrklnKCnk=; b=mDFr9I7gG5gMQ0vwudJQmDdP1oGr8ZkuhQJ5gCqbKOjp2zhcbqcNedx4QwEDeoe+Yy zz4f1iVgokxKHW7aDNjzjsIxNEI6XEABguNDmE7gfZ6BZIJf7ffG6QCcgg3C9kocKlGo q8LDJgHo1UTs0L0TlaEcWySGLqVpI88S53LP2g+I3EC1EZGrIIktl16MHip2tW+QhTpI LMGQKNDGsfjjcC/cgB/QQjwleef//01UvRplCuyG/71CIB0tDo1rRaB0NiJxmx9EKmf1 wqNJvUKRZ+5tLEcT9SkkWRVw7nnt9aI+RxkBuI04UPAG3OcEDl7XS4Fp6WeKeduOuw9g 5Viw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=Mhapfz67; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , linux-arm-kernel@lists.infradead.org, Stephen Boyd , Lecopzer Chen , Thomas Gleixner , linux-perf-users@vger.kernel.org, Masayoshi Mizuma , Douglas Anderson , Ben Dooks , Pierre Gondois , linux-kernel@vger.kernel.org Subject: [PATCH v8 03/10] arm64: smp: Assign and setup an IPI as NMI Date: Wed, 19 Apr 2023 15:55:57 -0700 Message-ID: <20230419155341.v8.3.I6d7f7d5fa0aa293c8c3374194947254b93114d37@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419225604.21204-1-dianders@chromium.org> References: <20230419225604.21204-1-dianders@chromium.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763648215551085095?= X-GMAIL-MSGID: =?utf-8?q?1763648215551085095?= From: Sumit Garg Assign an unused IPI which can be turned as NMI using ipi_nmi framework. Also, invoke corresponding dynamic IPI setup/teardown APIs. Signed-off-by: Sumit Garg Reviewed-by: Masayoshi Mizuma Tested-by: Chen-Yu Tsai Signed-off-by: Douglas Anderson --- Changes in v8: - dynamic_ipi_setup() and dynamic_ipi_teardown() no longer take cpu param arch/arm64/kernel/smp.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 4e8327264255..94ff063527c6 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -43,6 +43,7 @@ #include #include #include +#include #include #include #include @@ -938,6 +939,8 @@ static void ipi_setup(int cpu) for (i = 0; i < nr_ipi; i++) enable_percpu_irq(ipi_irq_base + i, 0); + + dynamic_ipi_setup(); } #ifdef CONFIG_HOTPLUG_CPU @@ -950,6 +953,8 @@ static void ipi_teardown(int cpu) for (i = 0; i < nr_ipi; i++) disable_percpu_irq(ipi_irq_base + i); + + dynamic_ipi_teardown(); } #endif @@ -971,6 +976,9 @@ void __init set_smp_ipi_range(int ipi_base, int n) irq_set_status_flags(ipi_base + i, IRQ_HIDDEN); } + if (n > nr_ipi) + set_smp_dynamic_ipi(ipi_base + nr_ipi); + ipi_irq_base = ipi_base; /* Setup the boot CPU immediately */ From patchwork Wed Apr 19 22:55:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 85649 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp725842vqo; Wed, 19 Apr 2023 16:17:47 -0700 (PDT) X-Google-Smtp-Source: AKy350bCEYqa2hSDmrnYkuTIXQ78Mlq2c7kXh9ho6/2DXtGX2ZyCbeQdVmbCVanv2eN96dVwZywl X-Received: by 2002:a05:6a21:1693:b0:f0:916:e62 with SMTP id np19-20020a056a21169300b000f009160e62mr119891pzb.60.1681946266753; Wed, 19 Apr 2023 16:17:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681946266; cv=none; d=google.com; s=arc-20160816; b=yT4joso+6OVow/rrEsOvohY4fMbQhQ3VU3oKZQ6wDKEi4ul+JlgDbdMrAoFYIz+3n4 Ryx1e2970N+Ib7Dxnw05jrepcVHM4zZqOd/uUIh+PeBzgvMtNEpg8S6Tlq6qgTNyXcQx jI+3irrM238R86VCMflmCVtcRUQwnCufYPU4ArrMqxlpPLE7GWsMC2xEcnY0UiK5h2AE OsC2cnMwm7PowW/8fRJNhxsFP42LyTTCotIsR1OmmDTcg7qbD4HZ0XtR4p8d1RzVC/Hz jeRRdGjG3n7zEpHtz6mq1XXGux6fsCREf518+28g143X3tvcCie6lTZmHtaEoPDxQvG0 PgRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Yb6/i5wvA5aqg7D8OxOUWOO0Hm18poXHV7fpSzZnAys=; b=0uKx+2WIx510QA6ZtIOz7qRecTkMUdRjpbZsCCnXq/PHT4HxwmGPG47ZETYn55azdW C+VbRWbeq0w4cNAlqQO9o52JcwwXJfhUXyP7TjcwA2LAB2oNFZhP1tFdcEbOHBSBuMUi 5xDqpR9V78ZbjsMvS8ufClQkv6P9sBoptlpmgmLOHBDKdwaQ+opY9GYUP4/F5W5awePJ 7fsiFzQ1X+bNs4zf1KQ76V0ocY977rErRBOWGNndz7ZlwyUi7tMDqkpa7goRR6Knwm8x 7HODpbWE+J2feVUEfvrIUqiWWK/n+dOj/4tXtlmWt2rpRyA3sqP72dKsbXNlkAHvCwRa eJgg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b="f/keZsFs"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , linux-arm-kernel@lists.infradead.org, Stephen Boyd , Lecopzer Chen , Thomas Gleixner , linux-perf-users@vger.kernel.org, Douglas Anderson , Ben Dooks , Borislav Petkov , Christophe Leroy , "Darrick J. Wong" , Dave Hansen , "David S. Miller" , "Eric W. Biederman" , Gaosheng Cui , "Gautham R. Shenoy" , Greg Kroah-Hartman , "Guilherme G. Piccoli" , Guo Ren , "H. Peter Anvin" , Huacai Chen , Ingo Molnar , "Jason A. Donenfeld" , Jianmin Lv , Jiaxun Yang , Jinyang He , Kees Cook , Laurent Dufour , Michael Ellerman , Nicholas Piggin , "Paul E. McKenney" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Qing Zhang , "Russell King (Oracle)" , Russell King , Thomas Bogendoerfer , Ulf Hansson , WANG Xuerui , linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, loongarch@lists.linux.dev, sparclinux@vger.kernel.org, x86@kernel.org Subject: [PATCH v8 04/10] nmi: backtrace: Allow runtime arch specific override Date: Wed, 19 Apr 2023 15:55:58 -0700 Message-ID: <20230419155341.v8.4.I3929b13cb2fab48772537aa308cd89e6f8a6753c@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419225604.21204-1-dianders@chromium.org> References: <20230419225604.21204-1-dianders@chromium.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763648488513708540?= X-GMAIL-MSGID: =?utf-8?q?1763648488513708540?= From: Sumit Garg Add a boolean return to arch_trigger_cpumask_backtrace() to support a use-case where a particular architecture detects at runtime if it supports NMI backtrace or it would like to fallback to default implementation using SMP cross-calls. Currently such an architecture example is arm64 supporting pseudo NMIs feature which is only available on platforms which have support for GICv3 or later version. Signed-off-by: Sumit Garg Tested-by: Chen-Yu Tsai Signed-off-by: Douglas Anderson --- Changes in v8: - Add loongarch support, too arch/arm/include/asm/irq.h | 2 +- arch/arm/kernel/smp.c | 3 ++- arch/loongarch/include/asm/irq.h | 2 +- arch/loongarch/kernel/process.c | 3 ++- arch/mips/include/asm/irq.h | 2 +- arch/mips/kernel/process.c | 3 ++- arch/powerpc/include/asm/nmi.h | 2 +- arch/powerpc/kernel/stacktrace.c | 3 ++- arch/sparc/include/asm/irq_64.h | 2 +- arch/sparc/kernel/process_64.c | 4 +++- arch/x86/include/asm/irq.h | 2 +- arch/x86/kernel/apic/hw_nmi.c | 3 ++- include/linux/nmi.h | 12 ++++-------- 13 files changed, 23 insertions(+), 20 deletions(-) diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h index a7c2337b0c7d..e6b62c7d6f0e 100644 --- a/arch/arm/include/asm/irq.h +++ b/arch/arm/include/asm/irq.h @@ -32,7 +32,7 @@ void init_IRQ(void); #ifdef CONFIG_SMP #include -extern void arch_trigger_cpumask_backtrace(const cpumask_t *mask, +extern bool arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self); #define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace #endif diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 0b8c25763adc..acb97d9219b1 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -849,7 +849,8 @@ static void raise_nmi(cpumask_t *mask) __ipi_send_mask(ipi_desc[IPI_CPU_BACKTRACE], mask); } -void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self) +bool arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self) { nmi_trigger_cpumask_backtrace(mask, exclude_self, raise_nmi); + return true; } diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h index a115e8999c69..c7a152d6bf0c 100644 --- a/arch/loongarch/include/asm/irq.h +++ b/arch/loongarch/include/asm/irq.h @@ -40,7 +40,7 @@ void spurious_interrupt(void); #define NR_IRQS_LEGACY 16 #define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace -void arch_trigger_cpumask_backtrace(const struct cpumask *mask, bool exclude_self); +bool arch_trigger_cpumask_backtrace(const struct cpumask *mask, bool exclude_self); #define MAX_IO_PICS 2 #define NR_IRQS (64 + (256 * MAX_IO_PICS)) diff --git a/arch/loongarch/kernel/process.c b/arch/loongarch/kernel/process.c index fa2443c7afb2..8f7f818f5c4e 100644 --- a/arch/loongarch/kernel/process.c +++ b/arch/loongarch/kernel/process.c @@ -339,9 +339,10 @@ static void raise_backtrace(cpumask_t *mask) } } -void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self) +bool arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self) { nmi_trigger_cpumask_backtrace(mask, exclude_self, raise_backtrace); + return true; } #ifdef CONFIG_64BIT diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h index 44f9824c1d8c..daf16173486a 100644 --- a/arch/mips/include/asm/irq.h +++ b/arch/mips/include/asm/irq.h @@ -77,7 +77,7 @@ extern int cp0_fdc_irq; extern int get_c0_fdc_int(void); -void arch_trigger_cpumask_backtrace(const struct cpumask *mask, +bool arch_trigger_cpumask_backtrace(const struct cpumask *mask, bool exclude_self); #define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index 093dbbd6b843..7d538571830a 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -750,9 +750,10 @@ static void raise_backtrace(cpumask_t *mask) } } -void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self) +bool arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self) { nmi_trigger_cpumask_backtrace(mask, exclude_self, raise_backtrace); + return true; } int mips_get_process_fp_mode(struct task_struct *task) diff --git a/arch/powerpc/include/asm/nmi.h b/arch/powerpc/include/asm/nmi.h index c3c7adef74de..135f65adcf63 100644 --- a/arch/powerpc/include/asm/nmi.h +++ b/arch/powerpc/include/asm/nmi.h @@ -12,7 +12,7 @@ static inline void watchdog_nmi_set_timeout_pct(u64 pct) {} #endif #ifdef CONFIG_NMI_IPI -extern void arch_trigger_cpumask_backtrace(const cpumask_t *mask, +extern bool arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self); #define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace #endif diff --git a/arch/powerpc/kernel/stacktrace.c b/arch/powerpc/kernel/stacktrace.c index 5de8597eaab8..0fee4bded7ba 100644 --- a/arch/powerpc/kernel/stacktrace.c +++ b/arch/powerpc/kernel/stacktrace.c @@ -221,8 +221,9 @@ static void raise_backtrace_ipi(cpumask_t *mask) } } -void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self) +bool arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self) { nmi_trigger_cpumask_backtrace(mask, exclude_self, raise_backtrace_ipi); + return true; } #endif /* defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_NMI_IPI) */ diff --git a/arch/sparc/include/asm/irq_64.h b/arch/sparc/include/asm/irq_64.h index 154df2cf19f4..00a0051a9da0 100644 --- a/arch/sparc/include/asm/irq_64.h +++ b/arch/sparc/include/asm/irq_64.h @@ -87,7 +87,7 @@ static inline unsigned long get_softint(void) return retval; } -void arch_trigger_cpumask_backtrace(const struct cpumask *mask, +bool arch_trigger_cpumask_backtrace(const struct cpumask *mask, bool exclude_self); #define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace diff --git a/arch/sparc/kernel/process_64.c b/arch/sparc/kernel/process_64.c index 91c2b8124527..f9aea1df3adf 100644 --- a/arch/sparc/kernel/process_64.c +++ b/arch/sparc/kernel/process_64.c @@ -236,7 +236,7 @@ static void __global_reg_poll(struct global_reg_snapshot *gp) } } -void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self) +bool arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self) { struct thread_info *tp = current_thread_info(); struct pt_regs *regs = get_irq_regs(); @@ -291,6 +291,8 @@ void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self) memset(global_cpu_snapshot, 0, sizeof(global_cpu_snapshot)); spin_unlock_irqrestore(&global_cpu_snapshot_lock, flags); + + return true; } #ifdef CONFIG_MAGIC_SYSRQ diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h index 768aa234cbb4..f731638cc38e 100644 --- a/arch/x86/include/asm/irq.h +++ b/arch/x86/include/asm/irq.h @@ -43,7 +43,7 @@ extern void init_ISA_irqs(void); extern void __init init_IRQ(void); #ifdef CONFIG_X86_LOCAL_APIC -void arch_trigger_cpumask_backtrace(const struct cpumask *mask, +bool arch_trigger_cpumask_backtrace(const struct cpumask *mask, bool exclude_self); #define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace diff --git a/arch/x86/kernel/apic/hw_nmi.c b/arch/x86/kernel/apic/hw_nmi.c index 34a992e275ef..e7dcd28bc824 100644 --- a/arch/x86/kernel/apic/hw_nmi.c +++ b/arch/x86/kernel/apic/hw_nmi.c @@ -34,10 +34,11 @@ static void nmi_raise_cpu_backtrace(cpumask_t *mask) apic->send_IPI_mask(mask, NMI_VECTOR); } -void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self) +bool arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self) { nmi_trigger_cpumask_backtrace(mask, exclude_self, nmi_raise_cpu_backtrace); + return true; } static int nmi_cpu_backtrace_handler(unsigned int cmd, struct pt_regs *regs) diff --git a/include/linux/nmi.h b/include/linux/nmi.h index 048c0b9aa623..7d8a77cd1e03 100644 --- a/include/linux/nmi.h +++ b/include/linux/nmi.h @@ -145,26 +145,22 @@ static inline void touch_nmi_watchdog(void) #ifdef arch_trigger_cpumask_backtrace static inline bool trigger_all_cpu_backtrace(void) { - arch_trigger_cpumask_backtrace(cpu_online_mask, false); - return true; + return arch_trigger_cpumask_backtrace(cpu_online_mask, false); } static inline bool trigger_allbutself_cpu_backtrace(void) { - arch_trigger_cpumask_backtrace(cpu_online_mask, true); - return true; + return arch_trigger_cpumask_backtrace(cpu_online_mask, true); } static inline bool trigger_cpumask_backtrace(struct cpumask *mask) { - arch_trigger_cpumask_backtrace(mask, false); - return true; + return arch_trigger_cpumask_backtrace(mask, false); } static inline bool trigger_single_cpu_backtrace(int cpu) { - arch_trigger_cpumask_backtrace(cpumask_of(cpu), false); - return true; + return arch_trigger_cpumask_backtrace(cpumask_of(cpu), false); } /* generic implementation */ From patchwork Wed Apr 19 22:55:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 85651 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp726315vqo; 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Wysocki" , linux-arm-kernel@lists.infradead.org, Stephen Boyd , Lecopzer Chen , Thomas Gleixner , linux-perf-users@vger.kernel.org, Masayoshi Mizuma , Douglas Anderson , linux-kernel@vger.kernel.org Subject: [PATCH v8 05/10] arm64: ipi_nmi: Add support for NMI backtrace Date: Wed, 19 Apr 2023 15:55:59 -0700 Message-ID: <20230419155341.v8.5.I65981105e1f62550b0316625dd1e599deaf9e1aa@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419225604.21204-1-dianders@chromium.org> References: <20230419225604.21204-1-dianders@chromium.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763648549368593507?= X-GMAIL-MSGID: =?utf-8?q?1763648549368593507?= From: Sumit Garg Enable NMI backtrace support on arm64 using IPI turned as an NMI leveraging pseudo NMIs support. It is now possible for users to get a backtrace of a CPU stuck in hard-lockup using magic SYSRQ. Signed-off-by: Sumit Garg Tested-by: Masayoshi Mizuma Tested-by: Chen-Yu Tsai Signed-off-by: Douglas Anderson --- Changes in v8: - Removed "#ifdef CONFIG_SMP" since arm64 is always SMP arch/arm64/include/asm/irq.h | 4 ++++ arch/arm64/kernel/ipi_nmi.c | 18 ++++++++++++++++-- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/irq.h b/arch/arm64/include/asm/irq.h index fac08e18bcd5..dc35b9d23a81 100644 --- a/arch/arm64/include/asm/irq.h +++ b/arch/arm64/include/asm/irq.h @@ -6,6 +6,10 @@ #include +extern bool arch_trigger_cpumask_backtrace(const cpumask_t *mask, + bool exclude_self); +#define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace + struct pt_regs; int set_handle_irq(void (*handle_irq)(struct pt_regs *)); diff --git a/arch/arm64/kernel/ipi_nmi.c b/arch/arm64/kernel/ipi_nmi.c index 712411eed949..c592e92b8cbf 100644 --- a/arch/arm64/kernel/ipi_nmi.c +++ b/arch/arm64/kernel/ipi_nmi.c @@ -8,6 +8,7 @@ #include #include +#include #include #include @@ -31,11 +32,24 @@ void arm64_send_nmi(cpumask_t *mask) __ipi_send_mask(ipi_nmi_desc, mask); } +bool arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self) +{ + if (!ipi_nmi_desc) + return false; + + nmi_trigger_cpumask_backtrace(mask, exclude_self, arm64_send_nmi); + + return true; +} + static irqreturn_t ipi_nmi_handler(int irq, void *data) { - /* nop, NMI handlers for special features can be added here. */ + irqreturn_t ret = IRQ_NONE; + + if (nmi_cpu_backtrace(get_irq_regs())) + ret = IRQ_HANDLED; - return IRQ_NONE; + return ret; } void dynamic_ipi_setup(void) From patchwork Wed Apr 19 22:56:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 85657 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp729559vqo; Wed, 19 Apr 2023 16:25:51 -0700 (PDT) X-Google-Smtp-Source: AKy350Y4N6WvfmvP+MIL/Y9h3xGnJ1z4ECxKqGhtvzzN8xex2jaKK2MpR8czkoM5HQTW7awc6AAw X-Received: by 2002:a05:6a00:1945:b0:63d:2910:5c8b with SMTP id s5-20020a056a00194500b0063d29105c8bmr4580571pfk.29.1681946751390; Wed, 19 Apr 2023 16:25:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681946751; cv=none; d=google.com; s=arc-20160816; b=UwKLROY90YnJAFB2e5SacyXgIGsZv+SjIoNjvIch9CE2kWnBdIy50JsKv5M6wlZjwV EmFWdRiO0Xue5WPHm41jftxD9+jghl5VtpH7AakVmmCEpMJciV1rXPgWvm1h07tR4fwi adMZiZy3vm5NM9en9FllrxQ1qwLys+ykZ5SEV72kPgz6RdN8foN92eKyPbzWtg0THTeS lRJqINBwxCF72Tj+FtLKqHYCOL1glZgxxJgtaeE5nUt0nqFvwtONPmdr11pgG0qKrqpN qSjR9DkGpodkflUl0NKKkquD3QjRMgH4GI8HUS3mOUI6eFNlfK3ROCEe5vlBGmTrUqU9 qG5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=LAvgM/34n0JSYhh4m4RBiwXsllZsYs4Vm4Z5FlxDAmU=; b=zMIMU33H+iGpiQ7zDTk4CYRFLtMqi0JA5bD+0H5/OGX4E/u6FWQtdkPVujUju30mYX GFAQmq2pwxiYj9YunXkKLhkKVCe494KmKuzrF0Y/y9Kt4kKzVtf/kiBaiZRzLp5OYskh WvX7WuUGjv60gVOmFk84DFv3Es7vIcmLs3rGPTSxgIBrZKvBsxf3jYgM0C0Mmm5wOBtt qdwd8jHFXJ80z6K/myCqmkXj3sB2fN3vPj8Ov4Il3UZxvXUo0UgitXd29u3X/BKW0mlV Wd5Nnen/tj1Nj+evnHIsDpHMMKCT7uNVv7C/2SRLcEyCUH3lBU9Z0LIlVI8/LHLC8HSL tsmQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=na1XodKz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , linux-arm-kernel@lists.infradead.org, Stephen Boyd , Lecopzer Chen , Thomas Gleixner , linux-perf-users@vger.kernel.org, Douglas Anderson , Frederic Weisbecker , "Gautham R. Shenoy" , Ingo Molnar , linux-kernel@vger.kernel.org Subject: [PATCH v8 06/10] arm64: idle: Tag the arm64 idle functions as __cpuidle Date: Wed, 19 Apr 2023 15:56:00 -0700 Message-ID: <20230419155341.v8.6.I4baba13e220bdd24d11400c67f137c35f07f82c7@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419225604.21204-1-dianders@chromium.org> References: <20230419225604.21204-1-dianders@chromium.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763648996658286331?= X-GMAIL-MSGID: =?utf-8?q?1763648996658286331?= As per the (somewhat recent) comment before the definition of `__cpuidle`, the tag is like `noinstr` but also marks a function so it can be identified by cpu_in_idle(). Let'a add this. After doing this then when we dump stack traces of all processors using nmi_cpu_backtrace() then instead of getting useless backtraces we get things like: NMI backtrace for cpu N skipped: idling at cpu_do_idle+0x94/0x98 Signed-off-by: Douglas Anderson --- Changes in v8: - "Tag the arm64 idle functions as __cpuidle" new for v8 arch/arm64/kernel/idle.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kernel/idle.c b/arch/arm64/kernel/idle.c index c1125753fe9b..05cfb347ec26 100644 --- a/arch/arm64/kernel/idle.c +++ b/arch/arm64/kernel/idle.c @@ -20,7 +20,7 @@ * ensure that interrupts are not masked at the PMR (because the core will * not wake up if we block the wake up signal in the interrupt controller). */ -void noinstr cpu_do_idle(void) +void __cpuidle cpu_do_idle(void) { struct arm_cpuidle_irq_context context; @@ -35,7 +35,7 @@ void noinstr cpu_do_idle(void) /* * This is our default idle handler. */ -void noinstr arch_cpu_idle(void) +void __cpuidle arch_cpu_idle(void) { /* * This should do all the clock switching and wait for interrupt From patchwork Wed Apr 19 22:56:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 85637 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp715577vqo; Wed, 19 Apr 2023 15:58:58 -0700 (PDT) X-Google-Smtp-Source: AKy350YzQkIHQFQBge94L09zaVDtpOPwE+tU4saz6dEHbbCA+7fFVTb+Fv/iYHdR2Q2tvRLCmmGf X-Received: by 2002:a05:6a21:788d:b0:f0:9e73:c77b with SMTP id bf13-20020a056a21788d00b000f09e73c77bmr216557pzc.20.1681945138637; Wed, 19 Apr 2023 15:58:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681945138; cv=none; d=google.com; s=arc-20160816; b=QXPJJmlXOm11iKcklxzO+U/+lCNKuo7YdnvF7hSmpbErhF035PKTdaeD7dIWAsWfmq +0HLrFXon2ta17/pNCpY0fPFpMuIRncZt72oVuX5Ss7WpASSToHqbJZAc+79N+o8b89p 6RWM7hHCsHHjdCwGwXSObUUtqCybe+wB7FrBcSv4HEdMe5B+KYmDzCIQdmHik+i9xcmC DZl+u2oSKLmf4X+MNiZL2oiEii2Ez+u7ofZgnQwedZNHe2Gyu/w64NKFlfnU3Zq0+lKb FLKqMV+ZY/PUUpPeR9wZftqCiYAyfsCk9D/6W9I14P+YvLKwptKs02BMWZ7eMWAFppKa KOFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=g22FS7H3jiae+Nq35iKba9yRyiXUFZk5tjGcb2Ngrro=; b=ZLdply2eRAO6aVEAvOw2HfLNUP18IyjpLfanjRJfH8gjAQa5LxQBgzmooqdqZlH1LV APYAhZ/F6AxjzW8ARo5/Yk3SG2QlsKStcnTxhrP1opDsVqb7WIDaFw1X02om/hje0oXo /S/FF9xDHa0S0Jig9zS3fsHMRQKmO7Me94LRSGA8BWPUk328OtZzh75n6/sccoNdqFcN dq59iOwRo5dqQaL8FV5O0r0MYnld5M9D4TgB1Zhva/oYhhMYJL2uK+QrRwQ6f2Rllmkn 0tz7Sh22L+zPCwU36mn0o3GFuJ79EcIYAcAts+az7Me9WTQhzulcxn/PY7wuP/M0Aou7 sh0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=I12V15zv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , linux-arm-kernel@lists.infradead.org, Stephen Boyd , Lecopzer Chen , Thomas Gleixner , linux-perf-users@vger.kernel.org, Douglas Anderson , Jason Wessel , linux-kernel@vger.kernel.org Subject: [PATCH v8 07/10] kgdb: Expose default CPUs roundup fallback mechanism Date: Wed, 19 Apr 2023 15:56:01 -0700 Message-ID: <20230419155341.v8.7.I21d92f8974c8e4001a5982fea6c98da1bed33ef5@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419225604.21204-1-dianders@chromium.org> References: <20230419225604.21204-1-dianders@chromium.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763647305383403758?= X-GMAIL-MSGID: =?utf-8?q?1763647305383403758?= From: Sumit Garg Add a new API kgdb_smp_call_nmi_hook() to expose default CPUs roundup mechanism to a particular archichecture as a runtime fallback if it detects to not support NMI roundup. Currently such an architecture example is arm64 supporting pseudo NMIs feature which is only available on platforms which have support for GICv3 or later version. Signed-off-by: Sumit Garg Tested-by: Chen-Yu Tsai Signed-off-by: Douglas Anderson --- (no changes since v1) include/linux/kgdb.h | 12 ++++++++++++ kernel/debug/debug_core.c | 8 +++++++- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/include/linux/kgdb.h b/include/linux/kgdb.h index 258cdde8d356..87713bd390f3 100644 --- a/include/linux/kgdb.h +++ b/include/linux/kgdb.h @@ -199,6 +199,18 @@ kgdb_arch_handle_qxfer_pkt(char *remcom_in_buffer, extern void kgdb_call_nmi_hook(void *ignored); +/** + * kgdb_smp_call_nmi_hook - Provide default fallback mechanism to + * round-up CPUs + * + * If you're using the default implementation of kgdb_roundup_cpus() + * this function will be called. And if an arch detects at runtime to + * not support NMI based roundup then it can fallback to default + * mechanism using this API. + */ + +extern void kgdb_smp_call_nmi_hook(void); + /** * kgdb_roundup_cpus - Get other CPUs into a holding pattern * diff --git a/kernel/debug/debug_core.c b/kernel/debug/debug_core.c index d5e9ccde3ab8..14d40a7d6a4b 100644 --- a/kernel/debug/debug_core.c +++ b/kernel/debug/debug_core.c @@ -238,7 +238,7 @@ NOKPROBE_SYMBOL(kgdb_call_nmi_hook); static DEFINE_PER_CPU(call_single_data_t, kgdb_roundup_csd) = CSD_INIT(kgdb_call_nmi_hook, NULL); -void __weak kgdb_roundup_cpus(void) +void kgdb_smp_call_nmi_hook(void) { call_single_data_t *csd; int this_cpu = raw_smp_processor_id(); @@ -269,6 +269,12 @@ void __weak kgdb_roundup_cpus(void) kgdb_info[cpu].rounding_up = false; } } +NOKPROBE_SYMBOL(kgdb_smp_call_nmi_hook); + +void __weak kgdb_roundup_cpus(void) +{ + kgdb_smp_call_nmi_hook(); +} NOKPROBE_SYMBOL(kgdb_roundup_cpus); #endif From patchwork Wed Apr 19 22:56:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 85645 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp723454vqo; Wed, 19 Apr 2023 16:13:02 -0700 (PDT) X-Google-Smtp-Source: AKy350YbUHW4gKangseqcJdLXEJ7f3xlUdF06cIIR3E//+9F6xfDzmTxaO5nY7wdPUMwP4lc3h/W X-Received: by 2002:a05:6a20:1583:b0:f0:558b:8fbb with SMTP id h3-20020a056a20158300b000f0558b8fbbmr254018pzj.34.1681945982013; Wed, 19 Apr 2023 16:13:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681945981; cv=none; d=google.com; s=arc-20160816; b=1J8kwUyaZFN2wZVc6tOQHFqIaTYTQ/zqkhPsvjzpdswkXUXD0b4TNd4bf7EkE2hd65 OTr8nd1dl94KsMmxoAIAwMyWLsaNzU9qss25AjUPn8+Clh3nnA5L9BmYWRhzOQ2JYhXl Xgq+DhQjmkr5V3GdeHSLu1te7e0NRm6Um1mF5IqFnl3yP36wKt4MDJUZ7tCP09wYPb2t j4m3clNnkM9/lcWCxncFKSS3G18H6z9vf2619UGAcym9KXZ2jfkr9FQeCDu2DWpX9OV6 2FmKJbe0Enx3Yfsg5Ea30wFVQYtSyCBbT19YMq6F0ID411vgEQkjrWis2ZE/M6xC1ecc w5YQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=4J3L1PRmmJQLOwITbbf3gVcO1wn/5q5E8+agGJxBWhk=; b=QsQwuOJ4mA3hRUp2FAuIJfEOw0iHBajAfIz+Xv/eUcb4xGfbqvVpAn4JMxIwRjgaAy vd25kG3yzLI+vZvwkwRnPtAr13hSyZhePwPympzattZ6c/UrpR9d1hggmiW0kGprYD54 8eqi+20TOzd7YSaseaoj+z72+F/S4PNKmQjpuLdylgbem26zYPSVXhHilM6Aw7Zv/M5m 6S0WzKGNy5vZ/VjkWHaUWsIiXGTSM/8s+Tf1Uuy0m9hJIHyEiaJY7HVoxfQ0/rj9N+NR EL2Z8sseiMhRUyhs2RIKQu7FIhwPbx14Ov7eX4iWJmh+Dt4ikjkkaW7J3uiQsP6hohMq SXOA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=E5o6owHA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , linux-arm-kernel@lists.infradead.org, Stephen Boyd , Lecopzer Chen , Thomas Gleixner , linux-perf-users@vger.kernel.org, Douglas Anderson , Jason Wessel , linux-kernel@vger.kernel.org Subject: [PATCH v8 08/10] kgdb: Provide a stub kgdb_nmicallback() if !CONFIG_KGDB Date: Wed, 19 Apr 2023 15:56:02 -0700 Message-ID: <20230419155341.v8.8.Ia3aeac89bb6751b682237e76e5ba594318e4b1aa@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419225604.21204-1-dianders@chromium.org> References: <20230419225604.21204-1-dianders@chromium.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763648190160136055?= X-GMAIL-MSGID: =?utf-8?q?1763648190160136055?= To save architectures from needing to wrap the call in #ifdefs, add a stub no-op version of kgdb_nmicallback(), which returns 1 if it didn't handle anything. Signed-off-by: Douglas Anderson Reviewed-by: Daniel Thompson --- Changes in v8: - "Provide a stub kgdb_nmicallback() if !CONFIG_KGDB" new for v8 include/linux/kgdb.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/kgdb.h b/include/linux/kgdb.h index 87713bd390f3..9ce628ee47cc 100644 --- a/include/linux/kgdb.h +++ b/include/linux/kgdb.h @@ -377,5 +377,6 @@ extern void kgdb_free_init_mem(void); #define dbg_late_init() static inline void kgdb_panic(const char *msg) {} static inline void kgdb_free_init_mem(void) { } +static int kgdb_nmicallback(int cpu, void *regs) { return 1; } #endif /* ! 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Wysocki" , linux-arm-kernel@lists.infradead.org, Stephen Boyd , Lecopzer Chen , Thomas Gleixner , linux-perf-users@vger.kernel.org, Douglas Anderson , Alexandru Elisei , Masayoshi Mizuma , linux-kernel@vger.kernel.org Subject: [PATCH v8 09/10] arm64: kgdb: Roundup cpus using IPI as NMI Date: Wed, 19 Apr 2023 15:56:03 -0700 Message-ID: <20230419155341.v8.9.I2ef26d1b3bfbed2d10a281942b0da7d9854de05e@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419225604.21204-1-dianders@chromium.org> References: <20230419225604.21204-1-dianders@chromium.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763648743230407435?= X-GMAIL-MSGID: =?utf-8?q?1763648743230407435?= From: Sumit Garg arm64 platforms with GICv3 or later supports pseudo NMIs which can be leveraged to roundup CPUs which are stuck in hard lockup state with interrupts disabled that wouldn't be possible with a normal IPI. So instead switch to roundup CPUs using IPI turned as NMI. And in case a particular arm64 platform doesn't supports pseudo NMIs, it will switch back to default kgdb CPUs roundup mechanism. Signed-off-by: Sumit Garg Tested-by: Chen-Yu Tsai Signed-off-by: Douglas Anderson --- (no changes since v1) arch/arm64/kernel/ipi_nmi.c | 5 +++++ arch/arm64/kernel/kgdb.c | 18 ++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/arch/arm64/kernel/ipi_nmi.c b/arch/arm64/kernel/ipi_nmi.c index c592e92b8cbf..2adaaf1519e5 100644 --- a/arch/arm64/kernel/ipi_nmi.c +++ b/arch/arm64/kernel/ipi_nmi.c @@ -8,6 +8,7 @@ #include #include +#include #include #include @@ -45,10 +46,14 @@ bool arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self) static irqreturn_t ipi_nmi_handler(int irq, void *data) { irqreturn_t ret = IRQ_NONE; + unsigned int cpu = smp_processor_id(); if (nmi_cpu_backtrace(get_irq_regs())) ret = IRQ_HANDLED; + if (!kgdb_nmicallback(cpu, get_irq_regs())) + ret = IRQ_HANDLED; + return ret; } diff --git a/arch/arm64/kernel/kgdb.c b/arch/arm64/kernel/kgdb.c index cda9c1e9864f..2c85bc1df013 100644 --- a/arch/arm64/kernel/kgdb.c +++ b/arch/arm64/kernel/kgdb.c @@ -17,6 +17,7 @@ #include #include +#include #include #include @@ -354,3 +355,20 @@ int kgdb_arch_remove_breakpoint(struct kgdb_bkpt *bpt) return aarch64_insn_write((void *)bpt->bpt_addr, *(u32 *)bpt->saved_instr); } + +void kgdb_roundup_cpus(void) +{ + struct cpumask mask; + + if (!arm64_supports_nmi()) { + kgdb_smp_call_nmi_hook(); + return; + } + + cpumask_copy(&mask, cpu_online_mask); + cpumask_clear_cpu(raw_smp_processor_id(), &mask); + if (cpumask_empty(&mask)) + return; + + arm64_send_nmi(&mask); +} From patchwork Wed Apr 19 22:56:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 85644 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp723428vqo; Wed, 19 Apr 2023 16:13:00 -0700 (PDT) X-Google-Smtp-Source: AKy350bK32fvcXMI8Uidhac4QyMoyxuZ16zPmzaykN6r3pvp7mr43dCq0KPyRT8xzLZyZZxdEH1R X-Received: by 2002:a05:6a00:1954:b0:63c:1be4:50a0 with SMTP id s20-20020a056a00195400b0063c1be450a0mr6168953pfk.8.1681945979682; Wed, 19 Apr 2023 16:12:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681945979; cv=none; d=google.com; s=arc-20160816; b=jhoHRIY3wfD+D4V5tD88m8kEalfBfsorkjVk8rwRkFpM2aF4mNl+2O73ZdWKBmeGRV wKLLEScz14scNAFVlMoD0anKAOven0sU1cFcdqqAiRgwj4BFIcVzDvkTlX68hOoN+sqZ MY/EdY+jd8HtGAfV8YHc4tbtAF7ilGnH/TFcRl01EkxKcGXASDTFoO3dbosbSrOyYiJE eRvyWw1o87cbFnZGN1FYJ9AM/GFg3NovqA5SiGMTvP8mclNlmrVwZoEpF9sliWcccP/N 8E56ya3lapmleRwkBZFcSSCdF0BNqX+16IG7TpPjpoH8RRiycclwmxhdFSkFlOaWY/HA lBQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=E4z5GDt+xM87DteGPLwbziaQRjegx46K8N8SblpggcI=; b=U0nyI45R8eKK9bmpp5aZLsbYBE5bjnfB7uICV25kG630H9yUQohq8/IAeq2yB+n5cG rTFVe1KyduImBfY4GVDD/LxPJhefGVZcdI71j32VvX6PSHwPkDiUstb0xsMXV8wIN6WJ +CwaoUbvQqWbtL/rOryqekQHaN7f2AVYHMJ25PP2MQQKhkFQUNruWhODfGHqR4Z4nd/H uc/rNTx6pPlVjir4/x+ooCajFFSPbg3Ez+8iitgDfvb3EeDdO3hOKxEcrbjSJSnplei0 ER5BZovdVTlRRkImgAD2SLjMGY3iu/g+TL3L6wR5eCjM3Yo07sBmWTJSuHeVUe15IhA4 SvpA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b="lc6v/s63"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , linux-arm-kernel@lists.infradead.org, Stephen Boyd , Lecopzer Chen , Thomas Gleixner , linux-perf-users@vger.kernel.org, Douglas Anderson , Masayoshi Mizuma , linux-kernel@vger.kernel.org Subject: [PATCH v8 10/10] arm64: ipi_nmi: Fallback to a regular IPI if NMI isn't enabled Date: Wed, 19 Apr 2023 15:56:04 -0700 Message-ID: <20230419155341.v8.10.Ic3659997d6243139d0522fc3afcdfd88d7a5f030@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419225604.21204-1-dianders@chromium.org> References: <20230419225604.21204-1-dianders@chromium.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763648187398597641?= X-GMAIL-MSGID: =?utf-8?q?1763648187398597641?= The current ipi_nmi implementation relies on the arm64 pseudo-NMI support. This needs to be enabled in both the kernel config with CONFIG_ARM64_PSEUDO_NMI and on the kernel command line with "irqchip.gicv3_pseudo_nmi=1". Let's add a fallback of using a regular IPI if the NMI isn't enabled. The fallback mechanism of using a regular IPI matches what arm32 does all the time since there is no NMI there. The reason for doing this is to make the trigger_all_cpu_backtrace() class of functions work. While those functions all return a bool indicating that the caller should try a fallback upon failure, an inspection of the callers shows that nearly nobody implements a fallback. It's better to at least provide something here. Signed-off-by: Douglas Anderson --- I dunno what people think of this patch. If it's great, we could actually drop some of the patches out of this series since some of them are to account for the fact that we might not be able to register an "ipi_nmi". If it's awful, it could simply be dropped. Changes in v8: - "Fallback to a regular IPI if NMI isn't enabled" new for v8 arch/arm64/kernel/ipi_nmi.c | 31 +++++++++++++++++++++++++------ 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/arch/arm64/kernel/ipi_nmi.c b/arch/arm64/kernel/ipi_nmi.c index 2adaaf1519e5..02868752845c 100644 --- a/arch/arm64/kernel/ipi_nmi.c +++ b/arch/arm64/kernel/ipi_nmi.c @@ -16,6 +16,7 @@ static struct irq_desc *ipi_nmi_desc __read_mostly; static int ipi_nmi_id __read_mostly; +static bool is_nmi; bool arm64_supports_nmi(void) { @@ -62,8 +63,12 @@ void dynamic_ipi_setup(void) if (!ipi_nmi_desc) return; - if (!prepare_percpu_nmi(ipi_nmi_id)) - enable_percpu_nmi(ipi_nmi_id, IRQ_TYPE_NONE); + if (is_nmi) { + if (!prepare_percpu_nmi(ipi_nmi_id)) + enable_percpu_nmi(ipi_nmi_id, IRQ_TYPE_NONE); + } else { + enable_percpu_irq(ipi_nmi_id, IRQ_TYPE_NONE); + } } void dynamic_ipi_teardown(void) @@ -71,14 +76,28 @@ void dynamic_ipi_teardown(void) if (!ipi_nmi_desc) return; - disable_percpu_nmi(ipi_nmi_id); - teardown_percpu_nmi(ipi_nmi_id); + if (is_nmi) { + disable_percpu_nmi(ipi_nmi_id); + teardown_percpu_nmi(ipi_nmi_id); + } else { + disable_percpu_irq(ipi_nmi_id); + } } void __init set_smp_dynamic_ipi(int ipi) { + int err; + if (!request_percpu_nmi(ipi, ipi_nmi_handler, "IPI", &cpu_number)) { - ipi_nmi_desc = irq_to_desc(ipi); - ipi_nmi_id = ipi; + is_nmi = true; + } else { + err = request_percpu_irq(ipi, ipi_nmi_handler, "IPI", &cpu_number); + if (WARN_ON(err)) + return; + + irq_set_status_flags(ipi, IRQ_HIDDEN); } + + ipi_nmi_desc = irq_to_desc(ipi); + ipi_nmi_id = ipi; }