From patchwork Wed Apr 19 22:33:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Judith Mendez X-Patchwork-Id: 85655 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp727942vqo; Wed, 19 Apr 2023 16:22:16 -0700 (PDT) X-Google-Smtp-Source: AKy350awUKBBBL5E4hTkuXKsgQJzTGeUSWUaI9QmHxGJfqB8NLfscy/LqTV9Ftw8lARmTr2TkK5w X-Received: by 2002:a05:6a00:1884:b0:63b:8df5:f8d with SMTP id x4-20020a056a00188400b0063b8df50f8dmr6971539pfh.3.1681946535839; Wed, 19 Apr 2023 16:22:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681946535; cv=none; d=google.com; s=arc-20160816; b=ys243SXDR45/wJBua3j+wVQPh1Smba3PidzsKiBEHpTu2Zo6V0Y8B8bDDLZ0Q+cWh4 I5C186yoaYIdKUbFusYYz6qeZVZ6NK0zhiY4U4ZsKux5qQ/Vl03N3B5N6Rx41RAUFFfZ KImgO+gw4SAeeGJtZyR8uX2mTH9Gz1suzpaGOZn2fcHTPVyB0Atab5lN6aaz4SOY0UBV 4c3oDaevQJ+ZrA76fzjGF447c34oc36NgUN1D9xUO0PXdyvQVhn4ktRMmNJhyQInOeir eGPetdyj7ismUXF7WZvc7nLagUC+V0ag81cpEec0TfavIjc7Xbdx6kXwDCMe29rfyHFn odkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=+0GoZhNulQJ5to302kKOEYuwOpVd4qY+OKEXXTzt2gs=; b=bvPBXytr0PizXotiq6Kw0UMAA2SUS2PwWptu9Kb71L1Teuq35fjZ1hKRHAAoZve1qN LWOYpuGlMMjTFoa0IeDsnA1Rei2rOVp7mSIdShm1asEXt1vXNAdTVbwglqIEwZudS2xQ DQJHfOuRXDbqxZ1fS/UG+ZNAkAtnXgTzpb+6XbM7cA2dzMMQya10UV6T7erSsdCcg1Nj haceiF0Wq/vxYw1rT7JRlj4oif1SJE3YKGb+GFq0XyyfbdppG+eUR6lh7CuZsTwoyoUi dP6DtdC4JmhNRwcR6G6j5qWCSczol7EfdeaQje9UhZsJ06T7Cg6tPV9cOTjsY9VcuW5m XK+A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=AEnDSCjU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id e13-20020a056a0000cd00b0063d1f93cc4fsi7900554pfj.291.2023.04.19.16.22.01; Wed, 19 Apr 2023 16:22:15 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=AEnDSCjU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232503AbjDSW4Q (ORCPT + 99 others); Wed, 19 Apr 2023 18:56:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56498 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229610AbjDSW4O (ORCPT ); Wed, 19 Apr 2023 18:56:14 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8931113; Wed, 19 Apr 2023 15:56:12 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 33JMXOWl117876; Wed, 19 Apr 2023 17:33:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1681943604; bh=+0GoZhNulQJ5to302kKOEYuwOpVd4qY+OKEXXTzt2gs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=AEnDSCjU1YevQKm6vSblyj0zz13b0JtUg70o9nr7Rd3QjO+enGPd4pw7Lx6Axl2hD WtGTyC+XSJ0IdtLW6iBjB7fi/9TUFoNyjxbsbCTzuybqC41RkAyioWtTgqTYpe9Sym spPnJJbHGgsNdn7/ZK3tRRQzdUV3EyPuJ/ztIM58= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 33JMXONe102532 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 19 Apr 2023 17:33:24 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 19 Apr 2023 17:33:23 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 19 Apr 2023 17:33:23 -0500 Received: from a0498204.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 33JMXNLW015736; Wed, 19 Apr 2023 17:33:23 -0500 From: Judith Mendez To: Chandrasekar Ramakrishnan , Wolfgang Grandegger , Marc Kleine-Budde CC: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Schuyler Patton , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Oliver Hartkopp , Judith Mendez , , , , , Subject: [PATCH 1/4] can: m_can: Add hrtimer to generate software interrupt Date: Wed, 19 Apr 2023 17:33:20 -0500 Message-ID: <20230419223323.20384-2-jm@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230419223323.20384-1-jm@ti.com> References: <20230419223323.20384-1-jm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763648770813784001?= X-GMAIL-MSGID: =?utf-8?q?1763648770813784001?= Add an hrtimer to MCAN struct. Each MCAN will have its own hrtimer instantiated if there is no hardware interrupt found. The hrtimer will generate a software interrupt every 1 ms. In hrtimer callback, we check if there is a transaction pending by reading a register, then process by calling the isr if there is. Signed-off-by: Judith Mendez --- drivers/net/can/m_can/m_can.c | 30 ++++++++++++++++++++++++-- drivers/net/can/m_can/m_can.h | 3 +++ drivers/net/can/m_can/m_can_platform.c | 13 +++++++++-- 3 files changed, 42 insertions(+), 4 deletions(-) diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c index a5003435802b..8784bdea300a 100644 --- a/drivers/net/can/m_can/m_can.c +++ b/drivers/net/can/m_can/m_can.c @@ -23,6 +23,7 @@ #include #include #include +#include #include "m_can.h" @@ -1587,6 +1588,11 @@ static int m_can_close(struct net_device *dev) if (!cdev->is_peripheral) napi_disable(&cdev->napi); + if (dev->irq < 0) { + dev_dbg(cdev->dev, "Disabling the hrtimer\n"); + hrtimer_cancel(&cdev->hrtimer); + } + m_can_stop(dev); m_can_clk_stop(cdev); free_irq(dev->irq, dev); @@ -1793,6 +1799,18 @@ static netdev_tx_t m_can_start_xmit(struct sk_buff *skb, return NETDEV_TX_OK; } +enum hrtimer_restart hrtimer_callback(struct hrtimer *timer) +{ + struct m_can_classdev *cdev = + container_of(timer, struct m_can_classdev, hrtimer); + + m_can_isr(0, cdev->net); + + hrtimer_forward_now(timer, ms_to_ktime(1)); + + return HRTIMER_RESTART; +} + static int m_can_open(struct net_device *dev) { struct m_can_classdev *cdev = netdev_priv(dev); @@ -1827,13 +1845,21 @@ static int m_can_open(struct net_device *dev) } INIT_WORK(&cdev->tx_work, m_can_tx_work_queue); - err = request_threaded_irq(dev->irq, NULL, m_can_isr, IRQF_ONESHOT, dev->name, dev); + } else { - err = request_irq(dev->irq, m_can_isr, IRQF_SHARED, dev->name, + if (dev->irq > 0) { + err = request_irq(dev->irq, m_can_isr, IRQF_SHARED, dev->name, dev); + } + + else { + dev_dbg(cdev->dev, "Enabling the hrtimer\n"); + cdev->hrtimer.function = &hrtimer_callback; + hrtimer_start(&cdev->hrtimer, ns_to_ktime(0), HRTIMER_MODE_REL_PINNED); + } } if (err < 0) { diff --git a/drivers/net/can/m_can/m_can.h b/drivers/net/can/m_can/m_can.h index a839dc71dc9b..ed046d77fdb9 100644 --- a/drivers/net/can/m_can/m_can.h +++ b/drivers/net/can/m_can/m_can.h @@ -28,6 +28,7 @@ #include #include #include +#include /* m_can lec values */ enum m_can_lec_type { @@ -93,6 +94,8 @@ struct m_can_classdev { int is_peripheral; struct mram_cfg mcfg[MRAM_CFG_NUM]; + + struct hrtimer hrtimer; }; struct m_can_classdev *m_can_class_allocate_dev(struct device *dev, int sizeof_priv); diff --git a/drivers/net/can/m_can/m_can_platform.c b/drivers/net/can/m_can/m_can_platform.c index 9c1dcf838006..7540db74b7d0 100644 --- a/drivers/net/can/m_can/m_can_platform.c +++ b/drivers/net/can/m_can/m_can_platform.c @@ -7,6 +7,7 @@ #include #include +#include #include "m_can.h" @@ -98,8 +99,16 @@ static int m_can_plat_probe(struct platform_device *pdev) addr = devm_platform_ioremap_resource_byname(pdev, "m_can"); irq = platform_get_irq_byname(pdev, "int0"); if (IS_ERR(addr) || irq < 0) { - ret = -EINVAL; - goto probe_fail; + if (irq == -EPROBE_DEFER) { + ret = -EPROBE_DEFER; + goto probe_fail; + } + if (IS_ERR(addr)) { + ret = PTR_ERR(addr); + goto probe_fail; + } + dev_dbg(mcan_class->dev, "Failed to get irq, initialize hrtimer\n"); + hrtimer_init(&mcan_class->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL_PINNED); } /* message ram could be shared */ From patchwork Wed Apr 19 22:33:21 2023 Content-Type: text/plain; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Schuyler Patton , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Oliver Hartkopp , Judith Mendez , , , , , Subject: [PATCH 2/4] dt-bindings: net: can: Make interrupt attributes optional for MCAN Date: Wed, 19 Apr 2023 17:33:21 -0500 Message-ID: <20230419223323.20384-3-jm@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230419223323.20384-1-jm@ti.com> References: <20230419223323.20384-1-jm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763647051169609275?= X-GMAIL-MSGID: =?utf-8?q?1763647051169609275?= For MCAN, remove interrupt and interrupt names from the required section. On AM62x SoC, MCANs on MCU domain do not have hardware interrupt routed to A53 Linux, instead they will use software interrupt by hrtimer. Make interrupt attributes optional in MCAN node by removing from required section. Signed-off-by: Judith Mendez Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/net/can/bosch,m_can.yaml | 2 -- 1 file changed, 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml index 67879aab623b..43f1aa9addc0 100644 --- a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml +++ b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml @@ -122,8 +122,6 @@ required: - compatible - reg - reg-names - - interrupts - - interrupt-names - clocks - clock-names - bosch,mram-cfg From patchwork Wed Apr 19 22:33:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Judith Mendez X-Patchwork-Id: 85656 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp728407vqo; Wed, 19 Apr 2023 16:23:11 -0700 (PDT) X-Google-Smtp-Source: AKy350ZNUKsrAVDGZ68pJNtMFNZz5QT5yGUvUlpVYztvk6CA0S3alf8AmNFv8vN51tscT2Ia2zWX X-Received: by 2002:a17:903:7d0:b0:1a6:7510:170a with SMTP id ko16-20020a17090307d000b001a67510170amr5737376plb.11.1681946591421; Wed, 19 Apr 2023 16:23:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681946591; cv=none; d=google.com; s=arc-20160816; b=wVzmW9keaPnfDnyHJvMDmk6XtZdmLPXJTgFbDpGGuOMrDZ3g0SbHJqdik0baK3g5K7 BHXVyCrPYoS2cySlf2yLMNXd7YNDT5V1D/TWauM4+F2g7nhkyyeU8KcJbb6bu8ClFrMc jCq3YDZvM/w5PYoTYWHv+TcfLwYqjpofTWd/FJO78MoaU9Ug9TDA60PqSJPA7dw8O69I wGgyavoDLbH2Tirs5yiaBX3AuaLg/orZ80HkEcvxNeLm4qHznC7WY9BG6vbwNe1t+XPy mf0ZDIq/M7lEqoHeN6O19uabG1KTnVyAO96StCYbd6z1g6swGreYv1xS2NBl1g5qfHL7 IJzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=OrWMLGnqJwjHMR2zESshsELG2IHJFL0T+AwlGIO3pco=; b=t6zXcMSiXqnCL9p4WSTxNl8MgKcQYRhmTOwoVjPMmmg9MOuuDrM06zeHIQY06iNJc1 1c/J8PpTcuoP4LZFwgC/e8xaAOam1dbT7Gq7QnTMByzs0Mwi/xXqkwOZbk7mUzDEv2sS ql2HSLvFg5aZjfLv5jQ7Yl8NnvIhdBZFld2jLcHrFHKyNkcIjtj3Fm/paA0qeiJjj+x5 8G+RoA6YmdRYe3B6CZ6zVnUfoOVd1lu4ak9jUeoQ79M29bRrUw6p7Zii0a/ja3tpjZm1 3xRDZyeNs1mS3PbXtoIbpQItGLSJ5RQPw0Hx8cYv5S/gvu+Adh/leS78D5v8DyeOxuA7 tTUg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=FQbPTeoy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Schuyler Patton , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Oliver Hartkopp , Judith Mendez , , , , , Subject: [PATCH 3/4] DO_NOT_MERGE arm64: dts: ti: Add AM62x MCAN MAIN domain transceiver overlay Date: Wed, 19 Apr 2023 17:33:22 -0500 Message-ID: <20230419223323.20384-4-jm@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230419223323.20384-1-jm@ti.com> References: <20230419223323.20384-1-jm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763648829090340689?= X-GMAIL-MSGID: =?utf-8?q?1763648829090340689?= Add an overlay for main domain MCAN on AM62x SK. The AM62x SK board does not have on-board CAN transceiver so instead of changing the DTB permanently, add an overlay to enable MAIN domain MCAN and support for 1 CAN transceiver. Signed-off-by: Judith Mendez --- arch/arm64/boot/dts/ti/Makefile | 2 ++ .../boot/dts/ti/k3-am625-sk-mcan-main.dtso | 35 +++++++++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-sk-mcan-main.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index c83c9d772b81..abe15e76b614 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -9,8 +9,10 @@ # alphabetically. # Boards with AM62x SoC +k3-am625-sk-mcan-dtbs := k3-am625-sk.dtb k3-am625-sk-mcan-main.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-sk-mcan.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb # Boards with AM62Ax SoC diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk-mcan-main.dtso b/arch/arm64/boot/dts/ti/k3-am625-sk-mcan-main.dtso new file mode 100644 index 000000000000..72b68fd51121 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-sk-mcan-main.dtso @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT overlay for MCAN transceiver in main domain on AM625 SK + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + transceiver1: can-phy0 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; +}; + +&main_pmx0 { + main_mcan0_pins_default: main-mcan0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1dc, PIN_INPUT, 0) /* (E15) MCAN0_RX */ + AM62X_IOPAD(0x1d8, PIN_OUTPUT, 0) /* (C15) MCAN0_TX */ + >; + }; +}; + +&main_mcan0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan0_pins_default>; + phys = <&transceiver1>; +}; From patchwork Wed Apr 19 22:33:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Judith Mendez X-Patchwork-Id: 85636 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp715192vqo; Wed, 19 Apr 2023 15:57:49 -0700 (PDT) X-Google-Smtp-Source: AKy350Z46PcdC1GVVrYPBFb6n/G1dLWL3t9TdqL/kuVd6+ZDZewdkRaSd9qFs/2Il3IrYVjVzIVY X-Received: by 2002:a05:6a00:14cb:b0:63b:8afe:a4dc with SMTP id w11-20020a056a0014cb00b0063b8afea4dcmr5954869pfu.30.1681945068998; Wed, 19 Apr 2023 15:57:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681945068; cv=none; d=google.com; s=arc-20160816; b=DHPbIg7se6z5eJFT9dbHZNlK1YcmxuQxurR+huNw07OkhpTjvUR19zfAiX752CXWFS MCbBnskzmB6xx+BJ/Rz9VVVfNs276prleIeNMxBxtV1KQi9rmrm173bt7P5g6LplHIZw px5RHtcgEHxY/Okq5arAg+P+1VtXawG1+srFiervH0aa7s1va39b+fzjAWHNrf+W/XHs zcucFFY77LvJ+hJ5XouG5xLLi6ecreqlIxRdph3CKT8nE/Hyissy4LNxYSsbXa/kSCfZ GMkh7N/FNd9kl//cxB+tDl6jhh80f6hsOnKuCbhDTfksVsvWFw+DQXS2tIRoOljQsQq/ qJfg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=Vd+9lvCfIptjFTjditm9bjPRq0iklMSeR+Ui3p22p0k=; b=PiHD+gEiSWiXEa6MiB5wX9TN8V0SorXvoeezfE3WftoyrjSWrdH4SgIEOMUSMHFOyo fzY1d1vSHHeYjJNt+d4XjLhHYbIwoMAGY28XpANCyOWsf/YxjIOAi1yLLSna7HvQeQQO 2ZMtqQ+zUpTol/hnsxw21EBTHovSWQd+HWzR7RwfxW6WUbqY09SivjydyVF8kNCQGbP3 3ckQ3aU9t0iSay9pC0WgMfNz+hOJxY2yvTX35LvlNjUIRzvC5J7hpbq5qaxBdzgAi50a e3IELepB58+LKHRawQB8RuD4yJ5SBlE7ZQfiFut1yI8GpESZLbtovK7q4lJ4E05RpWEM GIMw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=pYWeYTar; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Schuyler Patton , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Oliver Hartkopp , Judith Mendez , , , , , Subject: [PATCH 4/4] DO_NOT_MERGE arm64: dts: ti: Enable MCU MCANs for AM62x Date: Wed, 19 Apr 2023 17:33:23 -0500 Message-ID: <20230419223323.20384-5-jm@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230419223323.20384-1-jm@ti.com> References: <20230419223323.20384-1-jm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763647232610052076?= X-GMAIL-MSGID: =?utf-8?q?1763647232610052076?= On AM62x there are no hardware interrupts routed to GIC interrupt controller for MCU MCAN IP, A53 Linux cannot receive hardware interrupts. Since an hrtimer will be used to generate software interrupts, add MCU MCAN nodes to dtsi and default to disabled. AM62x does not carry on-board CAN transceivers, so instead of changing DTB permanently use an overlay to enable MCU MCANs and to add CAN transceiver nodes. If an hrtimer is used to generate software interrupts, the two required interrupt attributes in the MCAN node do not have to be included. Signed-off-by: Judith Mendez --- arch/arm64/boot/dts/ti/Makefile | 2 +- arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi | 24 ++++++++ .../boot/dts/ti/k3-am625-sk-mcan-mcu.dtso | 55 +++++++++++++++++++ 3 files changed, 80 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-sk-mcan-mcu.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index abe15e76b614..c76be3888e4d 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -9,7 +9,7 @@ # alphabetically. # Boards with AM62x SoC -k3-am625-sk-mcan-dtbs := k3-am625-sk.dtb k3-am625-sk-mcan-main.dtbo +k3-am625-sk-mcan-dtbs := k3-am625-sk.dtb k3-am625-sk-mcan-main.dtbo k3-am625-sk-mcan-mcu.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk-mcan.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi index 076601a41e84..20462f457643 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi @@ -141,4 +141,28 @@ /* Tightly coupled to M4F */ status = "reserved"; }; + + mcu_mcan1: can@4e00000 { + compatible = "bosch,m_can"; + reg = <0x00 0x4e00000 0x00 0x8000>, + <0x00 0x4e08000 0x00 0x200>; + reg-names = "message_ram", "m_can"; + power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 188 6>, <&k3_clks 188 1>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + mcu_mcan2: can@4e10000 { + compatible = "bosch,m_can"; + reg = <0x00 0x4e10000 0x00 0x8000>, + <0x00 0x4e18000 0x00 0x200>; + reg-names = "message_ram", "m_can"; + power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 189 6>, <&k3_clks 189 1>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk-mcan-mcu.dtso b/arch/arm64/boot/dts/ti/k3-am625-sk-mcan-mcu.dtso new file mode 100644 index 000000000000..7a527fdd4981 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-sk-mcan-mcu.dtso @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT overlay for MCAN in MCU domain on AM625 SK + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + transceiver2: can-phy1 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver3: can-phy2 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; +}; + +&mcu_pmx0 { + mcu_mcan1_pins_default: mcu-mcan1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x038, PIN_INPUT, 0) /* (B3) MCU_MCAN0_RX */ + AM62X_IOPAD(0x034, PIN_OUTPUT, 0) /* (D6) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan2_pins_default: mcu-mcan2-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x040, PIN_INPUT, 0) /* (D4) MCU_MCAN1_RX */ + AM62X_IOPAD(0x03C, PIN_OUTPUT, 0) /* (E5) MCU_MCAN1_TX */ + >; + }; +}; + +&mcu_mcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_pins_default>; + phys = <&transceiver2>; + status = "okay"; +}; + +&mcu_mcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan2_pins_default>; + phys = <&transceiver3>; + status = "okay"; +};