From patchwork Wed Apr 19 19:24:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Golle X-Patchwork-Id: 85536 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp623398vqo; Wed, 19 Apr 2023 12:39:24 -0700 (PDT) X-Google-Smtp-Source: AKy350Yc3o0wfGxc90xvg8LhUfTNKsaFLGO1zdoGQXjbrdhS2MXQhML1dFX87KFaqDztdX5I6sM+ X-Received: by 2002:a17:90a:f195:b0:24b:2ef6:64d5 with SMTP id bv21-20020a17090af19500b0024b2ef664d5mr1362081pjb.47.1681933164371; Wed, 19 Apr 2023 12:39:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681933164; cv=none; d=google.com; s=arc-20160816; b=RJNGq2/hjPClLf4E0B7BVDLdXpy9fsZmoGlAUxN6Y6K2a4D88RT1BogMK/Ltoa9gDL YuwrBlAmfE0hWEtEfaGIjbaeufRB1lKLU6ZSbgqC/UxHJQ8QNsusGst2gBM0bLCfvGAY g/Wb/w0ZVKun/C6otczfcYJvCz3yk16FLCCrZjujtwGd9sUIo4LAooY2PpZuDE9YBnPR hrKA6PC/jUsLJfzJsLYhtZ/dcNBrzKpJbOQsTl5Fc6uCrEbChzV8rmIWRJuzhyrwQE6U 2wncsbH4Ns/kp8C9RChA3bgk+TNnKlOAteR2dfI1j75OpbYW7iOHgIIoZxGXJjmzzmu0 eK7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:in-reply-to:content-disposition:mime-version :references:message-id:subject:to:from:date; bh=wp2SeUxNWu+iAzfNSBaY0iQyEGHgUGw6zP/njsRpzhU=; b=tEue9FnNR12mX1/Yrwws7rrLfDtt5te058kGCueDoI2rfzSqGGEkpukJRMX2PyTAzE oTUysl3qWNj2D3DXqa8Sw9ViQQD0iPDcT5BKmvGaGP3lk9CmnDjAk2R+o/0QNKH8zago AibyNsDJF2u/15EfyHAr+AyT3XUfsLgtToaNt8jyEYbKDlTTsmwwqAEBHCTt1u1FyhTT miE/AbwwCe3wHPPEYwvTHkpS/6O5KCtA3DjPIJq735C/fpTzuvuQlGdJpKLrneUPjV3h sx9DxpuOEvC8ClY0AIgO2r0Hr990jCaoTqe4oypMO7v7kOgNKIbfed5TiVAq9tpRrluz olsQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id v5-20020a632f05000000b0050f83aa181esi17102174pgv.698.2023.04.19.12.39.12; Wed, 19 Apr 2023 12:39:24 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230049AbjDSTZO (ORCPT + 99 others); Wed, 19 Apr 2023 15:25:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40584 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229872AbjDSTZM (ORCPT ); Wed, 19 Apr 2023 15:25:12 -0400 Received: from fudo.makrotopia.org (fudo.makrotopia.org [IPv6:2a07:2ec0:3002::71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E1CDF6A5B; Wed, 19 Apr 2023 12:25:03 -0700 (PDT) Received: from local by fudo.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.96) (envelope-from ) id 1ppDQM-0003x2-0p; Wed, 19 Apr 2023 21:25:02 +0200 Date: Wed, 19 Apr 2023 20:24:57 +0100 From: Daniel Golle To: devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Thierry Reding , Uwe =?iso-8859-1?q?Kleine-K=F6ni?= =?iso-8859-1?q?g?= , Matthias Brugger , AngeloGioacchino Del Regno , John Crispin Subject: [PATCH 1/2] dt-bindings: pwm: mediatek: Add mediatek,mt7981 compatible Message-ID: <4877689269af862ea9ddd199d8aa96b2d7fcf6fe.1681932165.git.daniel@makrotopia.org> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763634749545140545?= X-GMAIL-MSGID: =?utf-8?q?1763634749545140545?= Add compatible string for the PWM unit found of the MediaTek MT7981 SoC. This is in preparation to adding support in the pwm-mediatek.c driver. Signed-off-by: Daniel Golle Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pwm/mediatek,mt2712-pwm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pwm/mediatek,mt2712-pwm.yaml b/Documentation/devicetree/bindings/pwm/mediatek,mt2712-pwm.yaml index 8e176ba7a525f..0fbe8a6469eb2 100644 --- a/Documentation/devicetree/bindings/pwm/mediatek,mt2712-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/mediatek,mt2712-pwm.yaml @@ -22,6 +22,7 @@ properties: - mediatek,mt7623-pwm - mediatek,mt7628-pwm - mediatek,mt7629-pwm + - mediatek,mt7981-pwm - mediatek,mt7986-pwm - mediatek,mt8183-pwm - mediatek,mt8365-pwm From patchwork Wed Apr 19 19:25:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Golle X-Patchwork-Id: 85538 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp626345vqo; Wed, 19 Apr 2023 12:45:51 -0700 (PDT) X-Google-Smtp-Source: AKy350bUfxzM8N7rENVZz19/h6s5Viea9rt2iJjOPIBDuiL6TdZEudm3Hn24ht1S1avRNDTy0nIP X-Received: by 2002:a17:902:7b95:b0:1a1:ad5e:bdbb with SMTP id w21-20020a1709027b9500b001a1ad5ebdbbmr5905901pll.36.1681933550987; Wed, 19 Apr 2023 12:45:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681933550; cv=none; d=google.com; s=arc-20160816; b=zZTx40DEDm+G/y4IuLQleVwKWM6O8GCsnfxCSEXBHTIsQELMII6I/zIjNY4nIIT9Yo RXNRYhc/WETfdRvDIm7jhJw+ApFX4cu0mTlEPcyFUmCCI+cg4hxpSfLJySly3crdZt5j BSmA00uOFWNnV6Q9JoAcLTrBwFFgMloA+//MuDxg9Tsoa3zK0TqzUabDf4weQxnhX0gb MK3elfj0Ca6wK2iQS/2ua3vhuZVt5tCFVhdzjpM1iG9KmU98v5+qfpfTpNC2QrthYIu5 Mj4+PZE2Aa0TLDROJYtn3SJKTOBC097ma8d52GWwpwkxgWst+Gzwxn1V8HFO5i7l0ybN jPuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:in-reply-to:content-disposition:mime-version :references:message-id:subject:to:from:date; bh=oqPFLO+AVaKo1E1p6za4vyYX+tIhZ1uK9BaVGfdpMxo=; b=aIxuSbgDmImAD9a0l3S/U638P3FS0yFMgtnG3jMbHS9rxu2+RW/eSIGiPG+Y5QUZve xc2gk7dmMkA96iwZPBMcqOb7JeTFkATwdvalYD/dS64n7U7DsOQ3MEjqVRbqHXNV5QhJ KSaThICIq63BAfCEby5WMpb+QhHJT91xeZ+urHipoHui/myaR5BGAeHUU3rEpcW18qws i/pBLiv2icLfaDS79N3y5BPlKLIsAi5hH1sE1kiTULeDmKQPzaf/NhgFnqsEL6UAitwK RT8TeUUU8z47jMXt/K6tFeHov92WS/nPfffwAi0eIIXgya6905hFTq+o6QmaN2Dbu+QF 41bA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id n12-20020a170903110c00b0019ccffb3fd3si17947616plh.509.2023.04.19.12.45.37; Wed, 19 Apr 2023 12:45:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231273AbjDST0F (ORCPT + 99 others); Wed, 19 Apr 2023 15:26:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41408 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230163AbjDST0A (ORCPT ); Wed, 19 Apr 2023 15:26:00 -0400 Received: from fudo.makrotopia.org (fudo.makrotopia.org [IPv6:2a07:2ec0:3002::71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 289586E85; Wed, 19 Apr 2023 12:25:59 -0700 (PDT) Received: from local by fudo.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.96) (envelope-from ) id 1ppDRF-0003xn-1W; Wed, 19 Apr 2023 21:25:57 +0200 Date: Wed, 19 Apr 2023 20:25:51 +0100 From: Daniel Golle To: linux-pwm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Thierry Reding , Uwe =?iso-8859-1?q?Kleine-K=F6ni?= =?iso-8859-1?q?g?= , Matthias Brugger , AngeloGioacchino Del Regno , John Crispin Subject: [PATCH 2/2] pwm: mediatek: Add support for MT7981 Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763635154892537234?= X-GMAIL-MSGID: =?utf-8?q?1763635154892537234?= The PWM unit on MT7981 uses different register offsets than previous MediaTek PWM units. Add support for these new offsets and add support for PWM on MT7981 which has 3 PWM channels, one of them is typically used for a temperature controlled fan. Signed-off-by: Daniel Golle --- drivers/pwm/pwm-mediatek.c | 54 ++++++++++++++++++++++++++++++++------ 1 file changed, 46 insertions(+), 8 deletions(-) diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c index 5b5eeaff35da6..2bfb5bedf570b 100644 --- a/drivers/pwm/pwm-mediatek.c +++ b/drivers/pwm/pwm-mediatek.c @@ -34,10 +34,14 @@ #define PWM_CLK_DIV_MAX 7 +#define REG_V1 1 +#define REG_V2 2 + struct pwm_mediatek_of_data { unsigned int num_pwms; bool pwm45_fixup; bool has_ck_26m_sel; + u8 reg_ver; }; /** @@ -59,10 +63,14 @@ struct pwm_mediatek_chip { const struct pwm_mediatek_of_data *soc; }; -static const unsigned int pwm_mediatek_reg_offset[] = { +static const unsigned int mtk_pwm_reg_offset_v1[] = { 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220 }; +static const unsigned int mtk_pwm_reg_offset_v2[] = { + 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x1c0, 0x200, 0x0240 +}; + static inline struct pwm_mediatek_chip * to_pwm_mediatek_chip(struct pwm_chip *chip) { @@ -111,7 +119,19 @@ static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip, unsigned int num, unsigned int offset, u32 value) { - writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset); + u32 pwm_offset; + + switch (chip->soc->reg_ver) { + case REG_V2: + pwm_offset = mtk_pwm_reg_offset_v2[num]; + break; + + case REG_V1: + default: + pwm_offset = mtk_pwm_reg_offset_v1[num]; + } + + writel(value, chip->regs + pwm_offset + offset); } static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm, @@ -285,60 +305,77 @@ static const struct pwm_mediatek_of_data mt2712_pwm_data = { .num_pwms = 8, .pwm45_fixup = false, .has_ck_26m_sel = false, + .reg_ver = REG_V1, }; static const struct pwm_mediatek_of_data mt6795_pwm_data = { .num_pwms = 7, .pwm45_fixup = false, .has_ck_26m_sel = false, + .reg_ver = REG_V1, }; static const struct pwm_mediatek_of_data mt7622_pwm_data = { .num_pwms = 6, .pwm45_fixup = false, .has_ck_26m_sel = true, + .reg_ver = REG_V1, }; static const struct pwm_mediatek_of_data mt7623_pwm_data = { .num_pwms = 5, .pwm45_fixup = true, .has_ck_26m_sel = false, + .reg_ver = REG_V1, }; static const struct pwm_mediatek_of_data mt7628_pwm_data = { .num_pwms = 4, .pwm45_fixup = true, .has_ck_26m_sel = false, + .reg_ver = REG_V1, }; static const struct pwm_mediatek_of_data mt7629_pwm_data = { .num_pwms = 1, .pwm45_fixup = false, .has_ck_26m_sel = false, + .reg_ver = REG_V1, }; -static const struct pwm_mediatek_of_data mt8183_pwm_data = { - .num_pwms = 4, +static const struct pwm_mediatek_of_data mt7981_pwm_data = { + .num_pwms = 3, .pwm45_fixup = false, .has_ck_26m_sel = true, + .reg_ver = REG_V2, }; -static const struct pwm_mediatek_of_data mt8365_pwm_data = { - .num_pwms = 3, +static const struct pwm_mediatek_of_data mt7986_pwm_data = { + .num_pwms = 2, .pwm45_fixup = false, .has_ck_26m_sel = true, + .reg_ver = REG_V1, }; -static const struct pwm_mediatek_of_data mt7986_pwm_data = { - .num_pwms = 2, +static const struct pwm_mediatek_of_data mt8183_pwm_data = { + .num_pwms = 4, + .pwm45_fixup = false, + .has_ck_26m_sel = true, + .reg_ver = REG_V1, +}; + +static const struct pwm_mediatek_of_data mt8365_pwm_data = { + .num_pwms = 3, .pwm45_fixup = false, .has_ck_26m_sel = true, + .reg_ver = REG_V1, }; static const struct pwm_mediatek_of_data mt8516_pwm_data = { .num_pwms = 5, .pwm45_fixup = false, .has_ck_26m_sel = true, + .reg_ver = REG_V1, }; static const struct of_device_id pwm_mediatek_of_match[] = { @@ -348,6 +385,7 @@ static const struct of_device_id pwm_mediatek_of_match[] = { { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data }, { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data }, { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data }, + { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data }, { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data }, { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data }, { .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data },