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[8.43.85.97]) by mx.google.com with ESMTPS id n22-20020aa7db56000000b005048bfe57f1si14999807edt.28.2023.04.19.09.40.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 09:40:58 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1A7D23856DD6 for ; Wed, 19 Apr 2023 16:37:59 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg151.qq.com (smtpbg151.qq.com [18.169.211.239]) by sourceware.org (Postfix) with ESMTPS id 70599385773D for ; Wed, 19 Apr 2023 16:36:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 70599385773D Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp62t1681922204t2mku30d Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 20 Apr 2023 00:36:43 +0800 (CST) X-QQ-SSF: 01400000000000F0P000000A0000000 X-QQ-FEAT: 7L1V3dHhUFP/gxWihu1DKT15kGSFmJJRCsJz9p0k4PTdhg5E0VGjHwQkMMWgp S9yguXgivkukCwacxcM+IIPb8tMe+UkcSTqOhhKHQFdsmKaOPDbjKOKOARCZ3EzMLHqp9yW l6alhCWeQ8VmE3wRbhMv4WRV2rSqHQBpOvTMOCdpKp1+FecrXZqH40uusEfC9Ahh5IeDA1I +KIMRENIbkbdELcCBXIY1rl/ITTMFr21zUDPg9TBUBT/xazV/88WzvGpHYCbatCH90flQUA 7l0z7S6DnqbGXgzuHjkL0dB1W9tY1ZMaJz6iQU3xxT8vnDDwsYCEZ9KoyXzVnRgGza6ipKx +e+E+TmgF2XTSQw9enU42Fdbob/MZNHlOabtOw7GWLxkB+/Rqx3knJc21c9ig== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 17097081136364726819 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, jeffreyalaw@gmail.com, Ju-Zhe Zhong Subject: [PATCH 2/3] RISC-V: Enable basic auto-vectorization for RVV Date: Thu, 20 Apr 2023 00:36:33 +0800 Message-Id: <20230419163634.1030144-3-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 In-Reply-To: <20230419163634.1030144-1-juzhe.zhong@rivai.ai> References: <20230419163634.1030144-1-juzhe.zhong@rivai.ai> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763623523695212957?= X-GMAIL-MSGID: =?utf-8?q?1763623523695212957?= From: Ju-Zhe Zhong This patch enables auto-vectorization accurately according to '-march' And add len_load/len_store pattern. For example, for -march=rv32gc_zve32x, we should allow SEW = 64 RVV auto-vectorization. gcc/ChangeLog: * config/riscv/riscv-protos.h (preferred_simd_mode): Enable basic auto-vectorization support. * config/riscv/riscv-v.cc (autovec_use_vlmax_p): New function. (preferred_simd_mode): Ditto. * config/riscv/riscv.cc (riscv_convert_vector_bits): Enable basic auto-vectorization support. (riscv_preferred_simd_mode): New function. (TARGET_VECTORIZE_PREFERRED_SIMD_MODE): New target hook. * config/riscv/vector.md: include autovec.md * config/riscv/autovec.md: New file. --- gcc/config/riscv/autovec.md | 49 ++++++++++++++++++++++++++++++ gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv-v.cc | 53 +++++++++++++++++++++++++++++++++ gcc/config/riscv/riscv.cc | 24 ++++++++++++++- gcc/config/riscv/vector.md | 4 ++- 5 files changed, 129 insertions(+), 2 deletions(-) create mode 100644 gcc/config/riscv/autovec.md diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md new file mode 100644 index 00000000000..b5d46ff57ab --- /dev/null +++ b/gcc/config/riscv/autovec.md @@ -0,0 +1,49 @@ +;; Machine description for auto-vectorization using RVV for GNU compiler. +;; Copyright (C) 2023 Free Software Foundation, Inc. +;; Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +;; ========================================================================= +;; == Loads/Stores +;; ========================================================================= + +;; len_load/len_store is a sub-optimal pattern for RVV auto-vectorization support. +;; We will replace them when len_maskload/len_maskstore is supported in loop vectorizer. +(define_expand "len_load_" + [(match_operand:V 0 "register_operand") + (match_operand:V 1 "memory_operand") + (match_operand 2 "vector_length_operand") + (match_operand 3 "const_0_operand")] + "TARGET_VECTOR" +{ + riscv_vector::emit_nonvlmax_op (code_for_pred_mov (mode), operands[0], + operands[1], operands[2], mode); + DONE; +}) + +(define_expand "len_store_" + [(match_operand:V 0 "memory_operand") + (match_operand:V 1 "register_operand") + (match_operand 2 "vector_length_operand") + (match_operand 3 "const_0_operand")] + "TARGET_VECTOR" +{ + riscv_vector::emit_nonvlmax_op (code_for_pred_mov (mode), operands[0], + operands[1], operands[2], mode); + DONE; +}) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 5244e8dcbf0..2de9d40be46 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -207,6 +207,7 @@ enum vlen_enum bool slide1_sew64_helper (int, machine_mode, machine_mode, machine_mode, rtx *); rtx gen_avl_for_scalar_move (rtx); +machine_mode preferred_simd_mode (scalar_mode); } /* We classify builtin types into two classes: diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 99c414cc910..5e69427ac54 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -43,6 +43,7 @@ #include "optabs.h" #include "tm-constrs.h" #include "rtx-vector-builder.h" +#include "targhooks.h" using namespace riscv_vector; @@ -742,4 +743,56 @@ gen_avl_for_scalar_move (rtx avl) } } +/* SCALABLE means that the vector-length is agnostic (run-time invariant and + compile-time unknown). FIXED meands that the vector-length is specific + (compile-time known). Both RVV_SCALABLE and RVV_FIXED_VLMAX are doing + auto-vectorization using VLMAX vsetvl configuration. */ +static bool +autovec_use_vlmax_p (void) +{ + return riscv_autovec_preference == RVV_SCALABLE + || riscv_autovec_preference == RVV_FIXED_VLMAX; +} + +/* Return the vectorization machine mode for RVV according to LMUL. */ +machine_mode +preferred_simd_mode (scalar_mode mode) +{ + /* We only enable auto-vectorization when TARGET_MIN_VLEN >= 128 + which is -march=rv64gcv. Since GCC loop vectorizer report ICE + when we enable -march=rv64gc_zve32* and -march=rv32gc_zve64*. + in the 'can_duplicate_and_interleave_p' of tree-vect-slp.cc. Since we have + VNx1SImode in -march=*zve32* and VNx1DImode in -march=*zve64*, they are + enabled in targetm. vector_mode_supported_p and SLP vectorizer will try to + use them. Currently, we can support auto-vectorization in + -march=rv32_zve32x_zvl128b. Wheras, -march=rv32_zve32x_zvl32b or + -march=rv32_zve32x_zvl64b are disabled. + */ + if (autovec_use_vlmax_p ()) + { + /* If TARGET_MIN_VLEN < 128, we don't allow LMUL < 2 + auto-vectorization since Loop Vectorizer may use VNx1SImode or + VNx1DImode to vectorize which will create ICE in the + 'can_duplicate_and_interleave_p' of tree-vect-slp.cc. */ + if (TARGET_MIN_VLEN < 128 && riscv_autovec_lmul < RVV_M2) + return word_mode; + /* We use LMUL = 1 as base bytesize which is BYTES_PER_RISCV_VECTOR and + riscv_autovec_lmul as multiply factor to calculate the the NUNITS to + get the auto-vectorization mode. */ + poly_uint64 nunits; + poly_uint64 vector_size + = BYTES_PER_RISCV_VECTOR * ((int) riscv_autovec_lmul); + poly_uint64 scalar_size = GET_MODE_SIZE (mode); + if (!multiple_p (vector_size, scalar_size, &nunits)) + return word_mode; + machine_mode rvv_mode; + if (get_vector_mode (mode, nunits).exists (&rvv_mode)) + return rvv_mode; + } + /* TODO: We will support minimum length VLS auto-vectorization in the future. + */ + return word_mode; +} + + } // namespace riscv_vector diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 5d2550871c7..c601389b540 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -6228,7 +6228,15 @@ riscv_convert_vector_bits (void) to set RVV mode size. The RVV machine modes size are run-time constant if TARGET_VECTOR is enabled. The RVV machine modes size remains default compile-time constant if TARGET_VECTOR is disabled. */ - return TARGET_VECTOR ? poly_uint16 (1, 1) : 1; + if (TARGET_VECTOR) + { + if (riscv_autovec_preference == RVV_FIXED_VLMAX) + return (int) TARGET_MIN_VLEN / (riscv_bytes_per_vector_chunk * 8); + else + return poly_uint16 (1, 1); + } + else + return 1; } /* Implement TARGET_OPTION_OVERRIDE. */ @@ -7158,6 +7166,17 @@ riscv_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) & ~zeroed_hardregs); } +/* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */ + +static machine_mode +riscv_preferred_simd_mode (scalar_mode mode) +{ + if (TARGET_VECTOR) + return riscv_vector::preferred_simd_mode (mode); + + return word_mode; +} + /* Initialize the GCC target structure. */ #undef TARGET_ASM_ALIGNED_HI_OP #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" @@ -7412,6 +7431,9 @@ riscv_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) #undef TARGET_ZERO_CALL_USED_REGS #define TARGET_ZERO_CALL_USED_REGS riscv_zero_call_used_regs +#undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE +#define TARGET_VECTORIZE_PREFERRED_SIMD_MODE riscv_preferred_simd_mode + struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-riscv.h" diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 0fda11ed67d..3f06ab574c1 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -23,7 +23,7 @@ ;; This file include : ;; ;; - Intrinsics (https://github.com/riscv/rvv-intrinsic-doc) -;; - Auto-vectorization (TBD) +;; - Auto-vectorization (autovec.md) ;; - Combine optimization (TBD) (include "vector-iterators.md") @@ -7419,3 +7419,5 @@ "vleff.v\t%0,%3%p1" [(set_attr "type" "vldff") (set_attr "mode" "")]) + +(include "autovec.md") From patchwork Wed Apr 19 16:36:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 85499 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp523926vqo; Wed, 19 Apr 2023 09:42:42 -0700 (PDT) X-Google-Smtp-Source: AKy350Z37I/LqQpBgYnSkgICnXPOWQOvomqOHj9mb5LhYHqwPZL07ZI1WSPLb4OqzTG76TZ94eV0 X-Received: by 2002:a17:906:6dc4:b0:94f:ab46:77f9 with SMTP id j4-20020a1709066dc400b0094fab4677f9mr9829478ejt.15.1681922562106; Wed, 19 Apr 2023 09:42:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681922562; cv=none; d=google.com; s=arc-20160816; b=BZRYw+wOd7MedkOJ5A0KfGEEFfPmOw/axYDZ49wJvfbkdf+j6WIcl/W4uG9lWg4S9S Oo7/zQEVFi5X81OunZQhClnyn+57gCiLbyYWH2zMiN7w55e1lDyHlSs/MbfHq1hRlWZf UYXosW6QEyRQ3/hBSQj6cBXyCoYr2E2Bpf7gTslKy7bRh9V7DDb5uFZbAJzeL8bK6Q/E pM6LW8K8TA7rGO9EvA6zBqlA/XL7/HQb2QMBlj8JnmOuVEXV2YrXu85O+m/hvoskqiNC bq2eG6tVLIOctljDSznvKSYOaI0Ph0Zd2eeoXS+Jrzq4gX4I3TKnBbOCoJFaYBtsLKBe K4eQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:feedback-id :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dmarc-filter:delivered-to; bh=hhttlB67u6yf2ChX0uj/Ngnw7IzBhIu0b1UqKBD17Tw=; b=iUurZgGsl4xJo4NBLx8ePqq38GmyWPTuR/pq7K3pt/ij09JNfb6w+rQ7zF/rSxuHhe 9BWiSBFQ5Em8tDF0ZxfRYAPGWJ145dtV4znVvazV4mKYhNEDChT6DW2WFEmswPSORaZk vU7bnzUednDr1cUtBZtEbT0dtI4VtVfH2+xMbi8CrHfyzNsvG7dFGQSA76DAQesIgWa4 0HQH1QQNUtohSEwVdOk+vyPf3lFdGRB7v0PYSA5QUm6T7IVyCKz8thXApWutE+iccCzI otnLYyz6WTq4lynj0qaxtN+x83IaZNQ9WENYVv1Zz7W4yCQgGFjpoiH6//Q+4ENyUqgw kzDg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id ex20-20020a170907955400b0094f31b7d288si8325522ejc.307.2023.04.19.09.42.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 09:42:42 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3589E3896C05 for ; Wed, 19 Apr 2023 16:38:29 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg156.qq.com (smtpbg156.qq.com [15.184.82.18]) by sourceware.org (Postfix) with ESMTPS id 49806385356C for ; Wed, 19 Apr 2023 16:36:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 49806385356C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp62t1681922208ti085215 Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 20 Apr 2023 00:36:47 +0800 (CST) X-QQ-SSF: 01400000000000F0P000000A0000000 X-QQ-FEAT: UFnPsJu4LV/CvwEYd72oswajo9zMCh/JCXY41xKaH2yPFizWtquzx4CaCrSWV 7pUcH1BoYBG3Uy1jboIn/BmNSg79S6UL5fElBCuZrCmwAkaE8hbqMD84RKSBCjSqR4nWCrE KAX9LzkHsKAA8D+thSYXexG2wXG3rO1IS936qeJdReX0gP71Xg4xUWE7+yc5DkFlGNJu8IG 6UK4CbNT3JNU3cr+1uIwYbtRS1ruoaa6X3EmpxStOE/KmZBIxjy5+DivHlZeU4slLmTH61I c2nzMfLEG9HCegczgXbeeCZE0gCZX9JxIzFJm/82zIKgT+FlrHm3Qsc7uP6e5vl5GaDTmJz 4azUrM5yn8YCS74AnGSF5O1H+kY48xKEe+o4zPDm/GAIPYBIYfCzp9MwLvrQg== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 12647861614867816459 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, jeffreyalaw@gmail.com, Ju-Zhe Zhong Subject: [PATCH 3/3] RISC-V: Add sanity testcases for RVV auto-vectorization Date: Thu, 20 Apr 2023 00:36:34 +0800 Message-Id: <20230419163634.1030144-4-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 In-Reply-To: <20230419163634.1030144-1-juzhe.zhong@rivai.ai> References: <20230419163634.1030144-1-juzhe.zhong@rivai.ai> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763623632840838256?= X-GMAIL-MSGID: =?utf-8?q?1763623632840838256?= From: Ju-Zhe Zhong This patch adds sanity tests for basic enabling auto-vectorization. We should make sure compiler enable auto-vectorization strictly according to '-march' For example, '-march=rv32gc_zve32x' can not allow INT64 auto-vectorization. Since SEW = 64 RVV instructions are illegal instructions in this situation. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/rvv.exp: Add auto-vectorization tests. * gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c: New test. * gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.h: New test. * gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c: New test. * gcc.target/riscv/rvv/autovec/template-1.h: New test. * gcc.target/riscv/rvv/autovec/v-1.c: New test. * gcc.target/riscv/rvv/autovec/v-2.c: New test. * gcc.target/riscv/rvv/autovec/zve32f-1.c: New test. * gcc.target/riscv/rvv/autovec/zve32f-2.c: New test. * gcc.target/riscv/rvv/autovec/zve32f-3.c: New test. * gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c: New test. * gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c: New test. * gcc.target/riscv/rvv/autovec/zve32x-1.c: New test. * gcc.target/riscv/rvv/autovec/zve32x-2.c: New test. * gcc.target/riscv/rvv/autovec/zve32x-3.c: New test. * gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c: New test. * gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c: New test. * gcc.target/riscv/rvv/autovec/zve64d-1.c: New test. * gcc.target/riscv/rvv/autovec/zve64d-2.c: New test. * gcc.target/riscv/rvv/autovec/zve64d-3.c: New test. * gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c: New test. * gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c: New test. * gcc.target/riscv/rvv/autovec/zve64f-1.c: New test. * gcc.target/riscv/rvv/autovec/zve64f-2.c: New test. * gcc.target/riscv/rvv/autovec/zve64f-3.c: New test. * gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c: New test. * gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c: New test. * gcc.target/riscv/rvv/autovec/zve64x-1.c: New test. * gcc.target/riscv/rvv/autovec/zve64x-2.c: New test. * gcc.target/riscv/rvv/autovec/zve64x-3.c: New test. * gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c: New test. * gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c: New test. --- .../rvv/autovec/partial/single_rgroup-1.c | 8 ++ .../rvv/autovec/partial/single_rgroup-1.h | 106 ++++++++++++++++++ .../rvv/autovec/partial/single_rgroup_run-1.c | 19 ++++ .../gcc.target/riscv/rvv/autovec/template-1.h | 68 +++++++++++ .../gcc.target/riscv/rvv/autovec/v-1.c | 4 + .../gcc.target/riscv/rvv/autovec/v-2.c | 6 + .../gcc.target/riscv/rvv/autovec/zve32f-1.c | 4 + .../gcc.target/riscv/rvv/autovec/zve32f-2.c | 5 + .../gcc.target/riscv/rvv/autovec/zve32f-3.c | 6 + .../riscv/rvv/autovec/zve32f_zvl128b-1.c | 4 + .../riscv/rvv/autovec/zve32f_zvl128b-2.c | 6 + .../gcc.target/riscv/rvv/autovec/zve32x-1.c | 4 + .../gcc.target/riscv/rvv/autovec/zve32x-2.c | 6 + .../gcc.target/riscv/rvv/autovec/zve32x-3.c | 6 + .../riscv/rvv/autovec/zve32x_zvl128b-1.c | 5 + .../riscv/rvv/autovec/zve32x_zvl128b-2.c | 6 + .../gcc.target/riscv/rvv/autovec/zve64d-1.c | 4 + .../gcc.target/riscv/rvv/autovec/zve64d-2.c | 4 + .../gcc.target/riscv/rvv/autovec/zve64d-3.c | 6 + .../riscv/rvv/autovec/zve64d_zvl128b-1.c | 4 + .../riscv/rvv/autovec/zve64d_zvl128b-2.c | 6 + .../gcc.target/riscv/rvv/autovec/zve64f-1.c | 4 + .../gcc.target/riscv/rvv/autovec/zve64f-2.c | 4 + .../gcc.target/riscv/rvv/autovec/zve64f-3.c | 6 + .../riscv/rvv/autovec/zve64f_zvl128b-1.c | 4 + .../riscv/rvv/autovec/zve64f_zvl128b-2.c | 6 + .../gcc.target/riscv/rvv/autovec/zve64x-1.c | 4 + .../gcc.target/riscv/rvv/autovec/zve64x-2.c | 4 + .../gcc.target/riscv/rvv/autovec/zve64x-3.c | 6 + .../riscv/rvv/autovec/zve64x_zvl128b-1.c | 4 + .../riscv/rvv/autovec/zve64x_zvl128b-2.c | 6 + gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 16 +++ 32 files changed, 351 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/template-1.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c new file mode 100644 index 00000000000..6384888dd03 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fno-tree-loop-distribute-patterns" } */ + +#include "single_rgroup-1.h" + +TEST_ALL (test_1) + +/* { dg-final { scan-assembler-times {vsetvli} 10 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.h new file mode 100644 index 00000000000..be6b4c641cb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.h @@ -0,0 +1,106 @@ +#include +#include + +#define N 777 + +#define test_1(TYPE) \ + TYPE a_##TYPE[N]; \ + TYPE b_##TYPE[N]; \ + void __attribute__ ((noinline, noclone)) test_1_##TYPE (unsigned int n) \ + { \ + unsigned int i = 0; \ + for (i = 0; i < n; i++) \ + b_##TYPE[i] = a_##TYPE[i]; \ + } + +#define run_1(TYPE) \ + for (unsigned int i = 0; i < N; i++) \ + a_##TYPE[i] = i * 2 * 33 + 1 + 109; \ + test_1_##TYPE (5); \ + for (unsigned int i = 0; i < 5; i++) \ + if (b_##TYPE[i] != a_##TYPE[i]) \ + __builtin_abort (); + +#define run_2(TYPE) \ + for (unsigned int i = 0; i < N; i++) \ + a_##TYPE[i] = i * 2 * 57 + 1 + 999; \ + test_1_##TYPE (17); \ + for (unsigned int i = 0; i < 17; i++) \ + if (b_##TYPE[i] != a_##TYPE[i]) \ + __builtin_abort (); + +#define run_3(TYPE) \ + for (unsigned int i = 0; i < N; i++) \ + a_##TYPE[i] = i * 2 * 77 + 1 + 3; \ + test_1_##TYPE (32); \ + for (unsigned int i = 0; i < 32; i++) \ + if (b_##TYPE[i] != a_##TYPE[i]) \ + __builtin_abort (); + +#define run_4(TYPE) \ + for (unsigned int i = 0; i < N; i++) \ + a_##TYPE[i] = i * 2 * 45 + 1 + 11; \ + test_1_##TYPE (128); \ + for (unsigned int i = 0; i < 128; i++) \ + if (b_##TYPE[i] != a_##TYPE[i]) \ + __builtin_abort (); + +#define run_5(TYPE) \ + for (unsigned int i = 0; i < N; i++) \ + a_##TYPE[i] = i * 2 * 199 + 1 + 79; \ + test_1_##TYPE (177); \ + for (unsigned int i = 0; i < 177; i++) \ + if (b_##TYPE[i] != a_##TYPE[i]) \ + __builtin_abort (); + +#define run_6(TYPE) \ + for (unsigned int i = 0; i < N; i++) \ + a_##TYPE[i] = i * 2 * 377 + 1 + 73; \ + test_1_##TYPE (255); \ + for (unsigned int i = 0; i < 255; i++) \ + if (b_##TYPE[i] != a_##TYPE[i]) \ + __builtin_abort (); + +#define run_7(TYPE) \ + for (unsigned int i = 0; i < N; i++) \ + a_##TYPE[i] = i * 2 * 98 + 1 + 66; \ + test_1_##TYPE (333); \ + for (unsigned int i = 0; i < 333; i++) \ + if (b_##TYPE[i] != a_##TYPE[i]) \ + __builtin_abort (); + +#define run_8(TYPE) \ + for (unsigned int i = 0; i < N; i++) \ + a_##TYPE[i] = i * 2 * 7 + 1 * 7; \ + test_1_##TYPE (512); \ + for (unsigned int i = 0; i < 512; i++) \ + if (b_##TYPE[i] != a_##TYPE[i]) \ + __builtin_abort (); + +#define run_9(TYPE) \ + for (unsigned int i = 0; i < N; i++) \ + a_##TYPE[i] = i * 2 + 1 + 88; \ + test_1_##TYPE (637); \ + for (unsigned int i = 0; i < 637; i++) \ + if (b_##TYPE[i] != a_##TYPE[i]) \ + __builtin_abort (); + +#define run_10(TYPE) \ + for (unsigned int i = 0; i < N; i++) \ + a_##TYPE[i] = i * 2 * 331 + 1 + 547; \ + test_1_##TYPE (777); \ + for (unsigned int i = 0; i < 777; i++) \ + if (b_##TYPE[i] != a_##TYPE[i]) \ + __builtin_abort (); + +#define TEST_ALL(T) \ + T (int8_t) \ + T (uint8_t) \ + T (int16_t) \ + T (uint16_t) \ + T (int32_t) \ + T (uint32_t) \ + T (int64_t) \ + T (uint64_t) \ + T (float) \ + T (double) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c new file mode 100644 index 00000000000..4af2f18de8a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c @@ -0,0 +1,19 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "-fno-vect-cost-model -fno-tree-loop-distribute-patterns --param riscv-autovec-preference=scalable" } */ + +#include "single_rgroup-1.c" + +int main (void) +{ + TEST_ALL (run_1) + TEST_ALL (run_2) + TEST_ALL (run_3) + TEST_ALL (run_4) + TEST_ALL (run_5) + TEST_ALL (run_6) + TEST_ALL (run_7) + TEST_ALL (run_8) + TEST_ALL (run_9) + TEST_ALL (run_10) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/template-1.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/template-1.h new file mode 100644 index 00000000000..799e2d7d754 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/template-1.h @@ -0,0 +1,68 @@ +#include +#include + +void +foo0 (int8_t *__restrict f, int16_t *__restrict d, int n) +{ + for (int i = 0; i < n; ++i) + { + f[i * 2 + 0] = 1; + f[i * 2 + 1] = 2; + d[i] = 3; + } +} + +void +foo1 (int16_t *__restrict f, int32_t *__restrict d, int n) +{ + for (int i = 0; i < n; ++i) + { + f[i * 2 + 0] = 1; + f[i * 2 + 1] = 2; + d[i] = 3; + } +} + +void +foo2 (int32_t *__restrict f, int64_t *__restrict d, int n) +{ + for (int i = 0; i < n; ++i) + { + f[i * 2 + 0] = 1; + f[i * 2 + 1] = 2; + d[i] = 3; + } +} + +void +foo3 (int16_t *__restrict f, float *__restrict d, int n) +{ + for (int i = 0; i < n; ++i) + { + f[i * 2 + 0] = 1; + f[i * 2 + 1] = 2; + d[i] = 3; + } +} + +void +foo4 (int32_t *__restrict f, float *__restrict d, int n) +{ + for (int i = 0; i < n; ++i) + { + f[i * 2 + 0] = 1; + f[i * 2 + 1] = 2; + d[i] = 3; + } +} + +void +foo5 (float *__restrict f, double *__restrict d, int n) +{ + for (int i = 0; i < n; ++i) + { + f[i * 2 + 0] = 1; + f[i * 2 + 1] = 2; + d[i] = 3; + } +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c new file mode 100644 index 00000000000..7ff84f60749 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c new file mode 100644 index 00000000000..dc22eefbd36 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c new file mode 100644 index 00000000000..36f6d98a5cb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d --param riscv-autovec-preference=scalable -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c new file mode 100644 index 00000000000..794f28e73bd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" + diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c new file mode 100644 index 00000000000..8e68b9932b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c new file mode 100644 index 00000000000..d5e36190b31 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c new file mode 100644 index 00000000000..d154df4c4ba --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl128b -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize -fno-vect-cost-model -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c new file mode 100644 index 00000000000..68e7696ed65 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d --param riscv-autovec-preference=scalable -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c new file mode 100644 index 00000000000..f8860a36332 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" + + diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c new file mode 100644 index 00000000000..c26c2c95afb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c new file mode 100644 index 00000000000..3a6a3aa1261 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32x_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" + diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c new file mode 100644 index 00000000000..d1aaf3f4297 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32x_zvl128b -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c new file mode 100644 index 00000000000..0d03536389f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d --param riscv-autovec-preference=scalable -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c new file mode 100644 index 00000000000..ca423285011 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c new file mode 100644 index 00000000000..40fcbdf1dfb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c new file mode 100644 index 00000000000..4c6c7e2fb3b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c new file mode 100644 index 00000000000..b8253476973 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl128b -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c new file mode 100644 index 00000000000..e7900b82215 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d --param riscv-autovec-preference=scalable -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c new file mode 100644 index 00000000000..1c0e8c2785b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c new file mode 100644 index 00000000000..0f9ff7a6105 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c new file mode 100644 index 00000000000..daf4a4e8e64 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64f_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c new file mode 100644 index 00000000000..3866e45546c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64f_zvl128b -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c new file mode 100644 index 00000000000..4c190c303c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d --param riscv-autovec-preference=scalable -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c new file mode 100644 index 00000000000..66bb1f44170 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c new file mode 100644 index 00000000000..e30a6bce18b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c new file mode 100644 index 00000000000..6920a395d1c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64x_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c new file mode 100644 index 00000000000..d8b60babf9a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64x_zvl128b -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp index 4b5509db385..49bb6012af6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp @@ -46,6 +46,22 @@ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.\[cS\]]] \ "" $CFLAGS gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]] \ "" $CFLAGS +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \ + "" $CFLAGS + +set AUTOVEC_TEST_OPTS [list \ + {-ftree-vectorize -O3 --param riscv-autovec-lmul=m1} \ + {-ftree-vectorize -O3 --param riscv-autovec-lmul=m2} \ + {-ftree-vectorize -O3 --param riscv-autovec-lmul=m4} \ + {-ftree-vectorize -O3 --param riscv-autovec-lmul=m8} \ + {-ftree-vectorize -O2 --param riscv-autovec-lmul=m1} \ + {-ftree-vectorize -O2 --param riscv-autovec-lmul=m2} \ + {-ftree-vectorize -O2 --param riscv-autovec-lmul=m4} \ + {-ftree-vectorize -O2 --param riscv-autovec-lmul=m8} ] +foreach op $AUTOVEC_TEST_OPTS { + gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/partial/*.\[cS\]]] \ + "" "$op" +} # All done. dg-finish