From patchwork Wed Apr 19 16:36:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 85495 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp521827vqo; Wed, 19 Apr 2023 09:39:07 -0700 (PDT) X-Google-Smtp-Source: AKy350ZDSj62Ixmyj7dPdehrGlBDh0SeyGNoiNr4t4iPpp5A5UId3Z+7UMHXwgZ5k4p0ZUD8qPiX X-Received: by 2002:a17:906:22c9:b0:94a:67a9:6052 with SMTP id q9-20020a17090622c900b0094a67a96052mr15756368eja.67.1681922347011; Wed, 19 Apr 2023 09:39:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681922346; cv=none; d=google.com; s=arc-20160816; b=RC8cgnqIZHjGIawj/FPXx91LLiKjg/rf52w0VLotJ/lBYm6brqwkolIgtVb96qnmZa R0lGwkreo5y7Ols6UCR8KjPjDhtOoBwbX2lcJXNQBYFW3KTi6LdWHX86+zLctGvU2v/2 bYD0yn88J78lWK0l+jmXRkVsq1wYYeDujPD+R+TMU1r4CNfObEkHZ4rpXq85Wk7BA0zM hk49jLnPZoIZYKJ6vX3F797v8kbEKcwtWCBz+7OCFJ5+amP1J+IiIOq3nndzYSKz/X9C wZl+x0zzNvcM8AHZrzUi0ar4tA4PXr3D+WnC9CLkNzHydLAM6k19KjIJvgUFBtkna/re avSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:feedback-id :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dmarc-filter:delivered-to; bh=hE0hD8dc8C2ByjbTYUpuo1mCqtB4qPjyktx5kjjcBag=; b=ENST6DXJTMZTIc+gwxhnPqKUbXma4cHaHM8fTb7dOUPPubVAvPJRGUm2mP66f2izxP B5hLNpGWVGc8RWp/j8l3Qydrd0dutJEysWP5g3R7Jjg9KyMK+31oA/G6sp0GlhUC4zcu VuGgpRU6X7gAk4T9KFynkHBffjoxoY44ClMfxYhRnARQQETEUZ9cm+vI49Pt4rVA4Ibp 6/B/F1Y7CkQPpx0DNKVF2D2LHBVHLspMk9f+AN2BjmfbaP7c2ZSJUDbTB/a4aH5HXIzx RTjA3EFgmFRdrYFIDvnCk/TO3LV142+yIwxlM+UMePxIY7SV1ncs7lHt/vrdsu2w0B/V Dozw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id fr21-20020a170906891500b0094f6fdfc626si7786128ejc.677.2023.04.19.09.39.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 09:39:06 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5F182385B52E for ; Wed, 19 Apr 2023 16:37:27 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg154.qq.com (smtpbg154.qq.com [15.184.224.54]) by sourceware.org (Postfix) with ESMTPS id 4DCEB385772E for ; Wed, 19 Apr 2023 16:36:46 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4DCEB385772E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp62t1681922201tpydy01c Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 20 Apr 2023 00:36:40 +0800 (CST) X-QQ-SSF: 01400000000000F0P000000A0000000 X-QQ-FEAT: /pBoQNkXukW+ASjdmlNcLo1UacjPprbDjoJbAS/vtmoNSakbSblW1OEnT8UO9 06b58aLS/fdnEJuAaubRgr448ZvOkcc0MNajUCQBVYl3TJK0xast9VPvAsbE418Lv0V4dVS 1TEP+gMoA1AsuwFywgwykkCkK+McWIq3ez08XELOOVdTSiHYFK3LA4LGqJDTWQ2u9i52Nb3 I3aCmxIGLlrdaxo57UgjOZMCObkPjEARQNCgnPOaXdhstPBHpvAxRDwJ0IEQNAtMwlMyUAx QCQlv4SYiG6cI1nmBIo0sK0xoaeViDCVNax2zj/hdREbmP9KsOIpRtTrBN37Fze2t0hmr28 PSjvbTh3ksnUdt4pZhuFojHjPPXpFRAzgqbwx1twhVciyESJVfl7JNtdq84nA== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 7725104505256673044 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, jeffreyalaw@gmail.com, Ju-Zhe Zhong Subject: [PATCH 1/3] RISC-V: Add auto-vectorization compile option for RVV Date: Thu, 20 Apr 2023 00:36:32 +0800 Message-Id: <20230419163634.1030144-2-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 In-Reply-To: <20230419163634.1030144-1-juzhe.zhong@rivai.ai> References: <20230419163634.1030144-1-juzhe.zhong@rivai.ai> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, RCVD_IN_SBL_CSS, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763623406830181512?= X-GMAIL-MSGID: =?utf-8?q?1763623406830181512?= From: Ju-Zhe Zhong This patch is adding 2 compile option for RVV auto-vectorization. 1. -param=riscv-autovec-preference= This option is to specify the auto-vectorization approach for RVV. Currently, we only support scalable and fixed-vlmax. - scalable means VLA auto-vectorization. The vector-length to compiler is unknown and runtime invariant. Such approach can allow us compile the code run on any vector-length RVV CPU. - fixed-vlmax means the compile known the RVV CPU vector-length, compile option in fixed-length VLS auto-vectorization. Meaning if we specify vector-length=512. The execution file can only run on vector-length = 512 RVV CPU. - TODO: we may need to support min-length VLS auto-vectorization, means the execution file can run on larger length RVV CPU. gcc/ChangeLog: * config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Add enum for auto-vectorization preference. (enum riscv_autovec_lmul_enum): Add enum for choosing LMUL of RVV auto-vectorization. * config/riscv/riscv.opt: Add compile option for RVV auto-vectorization. --- gcc/config/riscv/riscv-opts.h | 15 ++++++++++++++ gcc/config/riscv/riscv.opt | 37 +++++++++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index cf0cd669be4..4207db240ea 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -67,6 +67,21 @@ enum stack_protector_guard { SSP_GLOBAL /* global canary */ }; +/* RISC-V auto-vectorization preference. */ +enum riscv_autovec_preference_enum { + NO_AUTOVEC, + RVV_SCALABLE, + RVV_FIXED_VLMAX +}; + +/* RISC-V auto-vectorization RVV LMUL. */ +enum riscv_autovec_lmul_enum { + RVV_M1 = 1, + RVV_M2 = 2, + RVV_M4 = 4, + RVV_M8 = 8 +}; + #define MASK_ZICSR (1 << 0) #define MASK_ZIFENCEI (1 << 1) diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index ff1dd4ddd4f..ef1bdfcfe28 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -254,3 +254,40 @@ Enum(isa_spec_class) String(20191213) Value(ISA_SPEC_CLASS_20191213) misa-spec= Target RejectNegative Joined Enum(isa_spec_class) Var(riscv_isa_spec) Init(TARGET_DEFAULT_ISA_SPEC) Set the version of RISC-V ISA spec. + +Enum +Name(riscv_autovec_preference) Type(enum riscv_autovec_preference_enum) +The RISC-V auto-vectorization preference: + +EnumValue +Enum(riscv_autovec_preference) String(none) Value(NO_AUTOVEC) + +EnumValue +Enum(riscv_autovec_preference) String(scalable) Value(RVV_SCALABLE) + +EnumValue +Enum(riscv_autovec_preference) String(fixed-vlmax) Value(RVV_FIXED_VLMAX) + +-param=riscv-autovec-preference= +Target RejectNegative Joined Enum(riscv_autovec_preference) Var(riscv_autovec_preference) Init(NO_AUTOVEC) +-param=riscv-autovec-preference= Set the preference of auto-vectorization in the RISC-V port. + +Enum +Name(riscv_autovec_lmul) Type(enum riscv_autovec_lmul_enum) +The RVV possible LMUL: + +EnumValue +Enum(riscv_autovec_lmul) String(m1) Value(RVV_M1) + +EnumValue +Enum(riscv_autovec_lmul) String(m2) Value(RVV_M2) + +EnumValue +Enum(riscv_autovec_lmul) String(m4) Value(RVV_M4) + +EnumValue +Enum(riscv_autovec_lmul) String(m8) Value(RVV_M8) + +-param=riscv-autovec-lmul= +Target RejectNegative Joined Enum(riscv_autovec_lmul) Var(riscv_autovec_lmul) Init(RVV_M1) +-param=riscv-autovec-lmul= Set the RVV LMUL of auto-vectorization in the RISC-V port. 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[8.43.85.97]) by mx.google.com with ESMTPS id x23-20020aa7dad7000000b004acd22dcc07si16712497eds.212.2023.04.19.09.39.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 09:39:04 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id EDAF3383468D for ; Wed, 19 Apr 2023 16:37:26 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgjp3.qq.com (smtpbgjp3.qq.com [54.92.39.34]) by sourceware.org (Postfix) with ESMTPS id 3F502385701C for ; Wed, 19 Apr 2023 16:36:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3F502385701C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp88t1681922185thiiwzg4 Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 20 Apr 2023 00:36:25 +0800 (CST) X-QQ-SSF: 01400000000000F0P000000A0000000 X-QQ-FEAT: jXjag1m6xl79OaDyaZ2f2twW8rG3+UtnIs0crLfqNHv8lz08E7Jyj79TvTjbT hWdrJ6RCfAQDg4MSdcnz77D88eyE6Cl/pCSv8EnlsrLG8syfjy91ZUHLkD1cRmWswHvHoKF u7W5HiVZLVphvOct8AnRCZBA9LJkn81o3dXtBd5orK6vhJo/BDHysUrhu7myPz2C9FfgGi1 NUYVnWSW8MvOy9ZDB8m5p4C3wz+tpCQaTLb0WGWfwHTdRAKJsuT20gByKO92t4L0+sR2ujg BnlObp+63VI0GKBdw089CcaQWmiPt+w3lGUxGIPVJ+SOihE9L3HuTf9p8waAfARthqt4hy8 kgoYuTWYHyj/g5HbuNoLfHxo8tyAep1hKpEuFeit1VS1kS1k7A= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 11620680523976071824 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, jeffreyalaw@gmail.com, Ju-Zhe Zhong Subject: [PATCH 2/3] RISC-V: Enable basic auto-vectorization for RVV Date: Thu, 20 Apr 2023 00:36:15 +0800 Message-Id: <20230419163616.1030090-3-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 In-Reply-To: <20230419163616.1030090-1-juzhe.zhong@rivai.ai> References: <20230419163616.1030090-1-juzhe.zhong@rivai.ai> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763623405093368012?= X-GMAIL-MSGID: =?utf-8?q?1763623405093368012?= From: Ju-Zhe Zhong This patch enables auto-vectorization accurately according to '-march' And add len_load/len_store pattern. For example, for -march=rv32gc_zve32x, we should allow SEW = 64 RVV auto-vectorization. gcc/ChangeLog: * config/riscv/riscv-protos.h (preferred_simd_mode): Enable basic auto-vectorization support. * config/riscv/riscv-v.cc (autovec_use_vlmax_p): New function. (preferred_simd_mode): Ditto. * config/riscv/riscv.cc (riscv_convert_vector_bits): Enable basic auto-vectorization support. (riscv_preferred_simd_mode): New function. (TARGET_VECTORIZE_PREFERRED_SIMD_MODE): New target hook. * config/riscv/vector.md: include autovec.md * config/riscv/autovec.md: New file. --- gcc/config/riscv/autovec.md | 49 ++++++++++++++++++++++++++++++ gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv-v.cc | 53 +++++++++++++++++++++++++++++++++ gcc/config/riscv/riscv.cc | 24 ++++++++++++++- gcc/config/riscv/vector.md | 4 ++- 5 files changed, 129 insertions(+), 2 deletions(-) create mode 100644 gcc/config/riscv/autovec.md diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md new file mode 100644 index 00000000000..b5d46ff57ab --- /dev/null +++ b/gcc/config/riscv/autovec.md @@ -0,0 +1,49 @@ +;; Machine description for auto-vectorization using RVV for GNU compiler. +;; Copyright (C) 2023 Free Software Foundation, Inc. +;; Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +;; ========================================================================= +;; == Loads/Stores +;; ========================================================================= + +;; len_load/len_store is a sub-optimal pattern for RVV auto-vectorization support. +;; We will replace them when len_maskload/len_maskstore is supported in loop vectorizer. +(define_expand "len_load_" + [(match_operand:V 0 "register_operand") + (match_operand:V 1 "memory_operand") + (match_operand 2 "vector_length_operand") + (match_operand 3 "const_0_operand")] + "TARGET_VECTOR" +{ + riscv_vector::emit_nonvlmax_op (code_for_pred_mov (mode), operands[0], + operands[1], operands[2], mode); + DONE; +}) + +(define_expand "len_store_" + [(match_operand:V 0 "memory_operand") + (match_operand:V 1 "register_operand") + (match_operand 2 "vector_length_operand") + (match_operand 3 "const_0_operand")] + "TARGET_VECTOR" +{ + riscv_vector::emit_nonvlmax_op (code_for_pred_mov (mode), operands[0], + operands[1], operands[2], mode); + DONE; +}) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 5244e8dcbf0..2de9d40be46 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -207,6 +207,7 @@ enum vlen_enum bool slide1_sew64_helper (int, machine_mode, machine_mode, machine_mode, rtx *); rtx gen_avl_for_scalar_move (rtx); +machine_mode preferred_simd_mode (scalar_mode); } /* We classify builtin types into two classes: diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 99c414cc910..5e69427ac54 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -43,6 +43,7 @@ #include "optabs.h" #include "tm-constrs.h" #include "rtx-vector-builder.h" +#include "targhooks.h" using namespace riscv_vector; @@ -742,4 +743,56 @@ gen_avl_for_scalar_move (rtx avl) } } +/* SCALABLE means that the vector-length is agnostic (run-time invariant and + compile-time unknown). FIXED meands that the vector-length is specific + (compile-time known). Both RVV_SCALABLE and RVV_FIXED_VLMAX are doing + auto-vectorization using VLMAX vsetvl configuration. */ +static bool +autovec_use_vlmax_p (void) +{ + return riscv_autovec_preference == RVV_SCALABLE + || riscv_autovec_preference == RVV_FIXED_VLMAX; +} + +/* Return the vectorization machine mode for RVV according to LMUL. */ +machine_mode +preferred_simd_mode (scalar_mode mode) +{ + /* We only enable auto-vectorization when TARGET_MIN_VLEN >= 128 + which is -march=rv64gcv. Since GCC loop vectorizer report ICE + when we enable -march=rv64gc_zve32* and -march=rv32gc_zve64*. + in the 'can_duplicate_and_interleave_p' of tree-vect-slp.cc. Since we have + VNx1SImode in -march=*zve32* and VNx1DImode in -march=*zve64*, they are + enabled in targetm. vector_mode_supported_p and SLP vectorizer will try to + use them. Currently, we can support auto-vectorization in + -march=rv32_zve32x_zvl128b. Wheras, -march=rv32_zve32x_zvl32b or + -march=rv32_zve32x_zvl64b are disabled. + */ + if (autovec_use_vlmax_p ()) + { + /* If TARGET_MIN_VLEN < 128, we don't allow LMUL < 2 + auto-vectorization since Loop Vectorizer may use VNx1SImode or + VNx1DImode to vectorize which will create ICE in the + 'can_duplicate_and_interleave_p' of tree-vect-slp.cc. */ + if (TARGET_MIN_VLEN < 128 && riscv_autovec_lmul < RVV_M2) + return word_mode; + /* We use LMUL = 1 as base bytesize which is BYTES_PER_RISCV_VECTOR and + riscv_autovec_lmul as multiply factor to calculate the the NUNITS to + get the auto-vectorization mode. */ + poly_uint64 nunits; + poly_uint64 vector_size + = BYTES_PER_RISCV_VECTOR * ((int) riscv_autovec_lmul); + poly_uint64 scalar_size = GET_MODE_SIZE (mode); + if (!multiple_p (vector_size, scalar_size, &nunits)) + return word_mode; + machine_mode rvv_mode; + if (get_vector_mode (mode, nunits).exists (&rvv_mode)) + return rvv_mode; + } + /* TODO: We will support minimum length VLS auto-vectorization in the future. + */ + return word_mode; +} + + } // namespace riscv_vector diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 5d2550871c7..c601389b540 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -6228,7 +6228,15 @@ riscv_convert_vector_bits (void) to set RVV mode size. The RVV machine modes size are run-time constant if TARGET_VECTOR is enabled. The RVV machine modes size remains default compile-time constant if TARGET_VECTOR is disabled. */ - return TARGET_VECTOR ? poly_uint16 (1, 1) : 1; + if (TARGET_VECTOR) + { + if (riscv_autovec_preference == RVV_FIXED_VLMAX) + return (int) TARGET_MIN_VLEN / (riscv_bytes_per_vector_chunk * 8); + else + return poly_uint16 (1, 1); + } + else + return 1; } /* Implement TARGET_OPTION_OVERRIDE. */ @@ -7158,6 +7166,17 @@ riscv_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) & ~zeroed_hardregs); } +/* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */ + +static machine_mode +riscv_preferred_simd_mode (scalar_mode mode) +{ + if (TARGET_VECTOR) + return riscv_vector::preferred_simd_mode (mode); + + return word_mode; +} + /* Initialize the GCC target structure. */ #undef TARGET_ASM_ALIGNED_HI_OP #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" @@ -7412,6 +7431,9 @@ riscv_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) #undef TARGET_ZERO_CALL_USED_REGS #define TARGET_ZERO_CALL_USED_REGS riscv_zero_call_used_regs +#undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE +#define TARGET_VECTORIZE_PREFERRED_SIMD_MODE riscv_preferred_simd_mode + struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-riscv.h" diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 0fda11ed67d..3f06ab574c1 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -23,7 +23,7 @@ ;; This file include : ;; ;; - Intrinsics (https://github.com/riscv/rvv-intrinsic-doc) -;; - Auto-vectorization (TBD) +;; - Auto-vectorization (autovec.md) ;; - Combine optimization (TBD) (include "vector-iterators.md") @@ -7419,3 +7419,5 @@ "vleff.v\t%0,%3%p1" [(set_attr "type" "vldff") (set_attr "mode" "")]) + +(include "autovec.md") From patchwork Wed Apr 19 16:36:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 85498 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp523485vqo; Wed, 19 Apr 2023 09:41:56 -0700 (PDT) X-Google-Smtp-Source: AKy350YjIQZ7Ec+lKcC5L53Od713EGpag+n17hS5vfrP1AqIPmrq+7G3yGKwKtmd1m6QnhflPB// X-Received: by 2002:a17:907:8dcd:b0:94f:ba0d:be71 with SMTP id tg13-20020a1709078dcd00b0094fba0dbe71mr8237203ejc.31.1681922516077; Wed, 19 Apr 2023 09:41:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681922516; cv=none; d=google.com; s=arc-20160816; b=qZQ3Q1YWKNFJIKKcvVwaSZIhlKOYvCRmnUU7lMU6h0+NaRXBk3CTdT0h2k4jk/fhUM L2dbmAYHalqxiy6XOXaIXRy3n7jiANpM3oFGMEjmxRoOi+A/EVbrPDj6vMwVrFQszQ/w /huNUTg1BGrHqfEuhCJakEGr5ImUuuHT4fVdZ73RHEtN4xmRhn73a+t3XczAO1Uj6Eal t56D4qFD28TvBq1U3RiX4W2rrfdgovLzWwQfIdcFZyht2jZ8p2f4q+aRpD8DwPG8ST3p Wt6fiInWsOm5Q558c+xT81AgqimK9RlJP/5ADSFOrYgYti2+z3zTRJrQGBoLj8qrrTKQ eCJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:feedback-id :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dmarc-filter:delivered-to; bh=hhttlB67u6yf2ChX0uj/Ngnw7IzBhIu0b1UqKBD17Tw=; b=Lgn32kdCEb1yq4gfFxHwsiifWoiGQJy6XZOY3iNGkUUCDgFjDoDMg9umyxB8xH1Cvr UvHnER+vcZyMj4NSVEZsDhOAUfHFNOmExcuMVT/CmtDBw7yoxZtrkusDQ0nymlStfHeb 3lBIiGvCxOExvfGfrErWoFHiautZfxw6z9yxtkahAsZQki/duid3sRI+tbekutxK6uAm 0STNCnnkBTgNARC294n4Lzl4Cftj/ed7BN4h2+8X827PkS7cTguH8twnaiQSRCRu7wYd 2kwvMmQ+w8XHUcYzEP9h3y3MhpGxr2SL95RbEilSInu31dXwdTftY83O43/SukGCG4/A WoHA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id ff23-20020a1709069c1700b0094facaa94a0si5559645ejc.417.2023.04.19.09.41.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 09:41:56 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 46ED53898380 for ; Wed, 19 Apr 2023 16:38:14 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgjp3.qq.com (smtpbgjp3.qq.com [54.92.39.34]) by sourceware.org (Postfix) with ESMTPS id DC4373857356 for ; Wed, 19 Apr 2023 16:36:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DC4373857356 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp88t1681922188tfrifkpd Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 20 Apr 2023 00:36:28 +0800 (CST) X-QQ-SSF: 01400000000000F0P000000A0000000 X-QQ-FEAT: RmDZc/K2LPF2oXhOUU58hfYE5XxmRlxuhy3U1agxNPYbc2jrdsEikSDQ2z8ZD KDoznu5kTnNQhxX7T5CTsKpE5DvNWjWOGpwsDw1PMLF1XXYG32Q6wWaPYs7DdvSb2IyR2ux xEBMlLseCZvLL3DISaBo9+Gd0zEaih69b/ZQPYgJ/9eloiOVeLMj6kBT/vg0Rjbfiuev4e0 ABaeui6G4Lgs3+qC1h5uESx9ar6z3cvWx1ml5qXix71VaE4BmB8ONQEXDsDKMfBaeFjzB4H p5vtS+Lr7nEavvQoZZOtnkmWJzmubi3ApvhIVJETgp3mGrl3Wgc9uYQItty0LRYtjZdj90X VeSVUzU+dr7RZ7xf9PRLs3HZhZyXDwRARuacbzRKkHPhF5lows= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 18141604926296610890 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, jeffreyalaw@gmail.com, Ju-Zhe Zhong Subject: [PATCH 3/3] RISC-V: Add sanity testcases for RVV auto-vectorization Date: Thu, 20 Apr 2023 00:36:16 +0800 Message-Id: <20230419163616.1030090-4-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 In-Reply-To: <20230419163616.1030090-1-juzhe.zhong@rivai.ai> References: <20230419163616.1030090-1-juzhe.zhong@rivai.ai> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763623584465829309?= X-GMAIL-MSGID: =?utf-8?q?1763623584465829309?= From: Ju-Zhe Zhong This patch adds sanity tests for basic enabling auto-vectorization. We should make sure compiler enable auto-vectorization strictly according to '-march' For example, '-march=rv32gc_zve32x' can not allow INT64 auto-vectorization. Since SEW = 64 RVV instructions are illegal instructions in this situation. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/rvv.exp: Add auto-vectorization tests. * gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c: New test. * gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.h: New test. * gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c: New test. * gcc.target/riscv/rvv/autovec/template-1.h: New test. * gcc.target/riscv/rvv/autovec/v-1.c: New test. * gcc.target/riscv/rvv/autovec/v-2.c: New test. * gcc.target/riscv/rvv/autovec/zve32f-1.c: New test. * gcc.target/riscv/rvv/autovec/zve32f-2.c: New test. * gcc.target/riscv/rvv/autovec/zve32f-3.c: New test. * gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c: New test. * gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c: New test. * gcc.target/riscv/rvv/autovec/zve32x-1.c: New test. * gcc.target/riscv/rvv/autovec/zve32x-2.c: New test. * gcc.target/riscv/rvv/autovec/zve32x-3.c: New test. * gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c: New test. * gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c: New test. * gcc.target/riscv/rvv/autovec/zve64d-1.c: New test. * gcc.target/riscv/rvv/autovec/zve64d-2.c: New test. * gcc.target/riscv/rvv/autovec/zve64d-3.c: New test. * gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c: New test. * gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c: New test. * gcc.target/riscv/rvv/autovec/zve64f-1.c: New test. * gcc.target/riscv/rvv/autovec/zve64f-2.c: New test. * gcc.target/riscv/rvv/autovec/zve64f-3.c: New test. * gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c: New test. * gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c: New test. * gcc.target/riscv/rvv/autovec/zve64x-1.c: New test. * gcc.target/riscv/rvv/autovec/zve64x-2.c: New test. * gcc.target/riscv/rvv/autovec/zve64x-3.c: New test. * gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c: New test. * gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c: New test. --- .../rvv/autovec/partial/single_rgroup-1.c | 8 ++ .../rvv/autovec/partial/single_rgroup-1.h | 106 ++++++++++++++++++ .../rvv/autovec/partial/single_rgroup_run-1.c | 19 ++++ .../gcc.target/riscv/rvv/autovec/template-1.h | 68 +++++++++++ .../gcc.target/riscv/rvv/autovec/v-1.c | 4 + .../gcc.target/riscv/rvv/autovec/v-2.c | 6 + .../gcc.target/riscv/rvv/autovec/zve32f-1.c | 4 + .../gcc.target/riscv/rvv/autovec/zve32f-2.c | 5 + .../gcc.target/riscv/rvv/autovec/zve32f-3.c | 6 + .../riscv/rvv/autovec/zve32f_zvl128b-1.c | 4 + .../riscv/rvv/autovec/zve32f_zvl128b-2.c | 6 + .../gcc.target/riscv/rvv/autovec/zve32x-1.c | 4 + .../gcc.target/riscv/rvv/autovec/zve32x-2.c | 6 + .../gcc.target/riscv/rvv/autovec/zve32x-3.c | 6 + .../riscv/rvv/autovec/zve32x_zvl128b-1.c | 5 + .../riscv/rvv/autovec/zve32x_zvl128b-2.c | 6 + .../gcc.target/riscv/rvv/autovec/zve64d-1.c | 4 + .../gcc.target/riscv/rvv/autovec/zve64d-2.c | 4 + .../gcc.target/riscv/rvv/autovec/zve64d-3.c | 6 + .../riscv/rvv/autovec/zve64d_zvl128b-1.c | 4 + .../riscv/rvv/autovec/zve64d_zvl128b-2.c | 6 + .../gcc.target/riscv/rvv/autovec/zve64f-1.c | 4 + .../gcc.target/riscv/rvv/autovec/zve64f-2.c | 4 + .../gcc.target/riscv/rvv/autovec/zve64f-3.c | 6 + .../riscv/rvv/autovec/zve64f_zvl128b-1.c | 4 + .../riscv/rvv/autovec/zve64f_zvl128b-2.c | 6 + .../gcc.target/riscv/rvv/autovec/zve64x-1.c | 4 + .../gcc.target/riscv/rvv/autovec/zve64x-2.c | 4 + .../gcc.target/riscv/rvv/autovec/zve64x-3.c | 6 + .../riscv/rvv/autovec/zve64x_zvl128b-1.c | 4 + .../riscv/rvv/autovec/zve64x_zvl128b-2.c | 6 + gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 16 +++ 32 files changed, 351 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/template-1.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c new file mode 100644 index 00000000000..6384888dd03 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fno-tree-loop-distribute-patterns" } */ + +#include "single_rgroup-1.h" + +TEST_ALL (test_1) + +/* { dg-final { scan-assembler-times {vsetvli} 10 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.h new file mode 100644 index 00000000000..be6b4c641cb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.h @@ -0,0 +1,106 @@ +#include +#include + +#define N 777 + +#define test_1(TYPE) \ + TYPE a_##TYPE[N]; \ + TYPE b_##TYPE[N]; \ + void __attribute__ ((noinline, noclone)) test_1_##TYPE (unsigned int n) \ + { \ + unsigned int i = 0; \ + for (i = 0; i < n; i++) \ + b_##TYPE[i] = a_##TYPE[i]; \ + } + +#define run_1(TYPE) \ + for (unsigned int i = 0; i < N; i++) \ + a_##TYPE[i] = i * 2 * 33 + 1 + 109; \ + test_1_##TYPE (5); \ + for (unsigned int i = 0; i < 5; i++) \ + if (b_##TYPE[i] != a_##TYPE[i]) \ + __builtin_abort (); + +#define run_2(TYPE) \ + for (unsigned int i = 0; i < N; i++) \ + a_##TYPE[i] = i * 2 * 57 + 1 + 999; \ + test_1_##TYPE (17); \ + for (unsigned int i = 0; i < 17; i++) \ + if (b_##TYPE[i] != a_##TYPE[i]) \ + __builtin_abort (); + +#define run_3(TYPE) \ + for (unsigned int i = 0; i < N; i++) \ + a_##TYPE[i] = i * 2 * 77 + 1 + 3; \ + test_1_##TYPE (32); \ + for (unsigned int i = 0; i < 32; i++) \ + if (b_##TYPE[i] != a_##TYPE[i]) \ + __builtin_abort (); + +#define run_4(TYPE) \ + for (unsigned int i = 0; i < N; i++) \ + a_##TYPE[i] = i * 2 * 45 + 1 + 11; \ + test_1_##TYPE (128); \ + for (unsigned int i = 0; i < 128; i++) \ + if (b_##TYPE[i] != a_##TYPE[i]) \ + __builtin_abort (); + +#define run_5(TYPE) \ + for (unsigned int i = 0; i < N; i++) \ + a_##TYPE[i] = i * 2 * 199 + 1 + 79; \ + test_1_##TYPE (177); \ + for (unsigned int i = 0; i < 177; i++) \ + if (b_##TYPE[i] != a_##TYPE[i]) \ + __builtin_abort (); + +#define run_6(TYPE) \ + for (unsigned int i = 0; i < N; i++) \ + a_##TYPE[i] = i * 2 * 377 + 1 + 73; \ + test_1_##TYPE (255); \ + for (unsigned int i = 0; i < 255; i++) \ + if (b_##TYPE[i] != a_##TYPE[i]) \ + __builtin_abort (); + +#define run_7(TYPE) \ + for (unsigned int i = 0; i < N; i++) \ + a_##TYPE[i] = i * 2 * 98 + 1 + 66; \ + test_1_##TYPE (333); \ + for (unsigned int i = 0; i < 333; i++) \ + if (b_##TYPE[i] != a_##TYPE[i]) \ + __builtin_abort (); + +#define run_8(TYPE) \ + for (unsigned int i = 0; i < N; i++) \ + a_##TYPE[i] = i * 2 * 7 + 1 * 7; \ + test_1_##TYPE (512); \ + for (unsigned int i = 0; i < 512; i++) \ + if (b_##TYPE[i] != a_##TYPE[i]) \ + __builtin_abort (); + +#define run_9(TYPE) \ + for (unsigned int i = 0; i < N; i++) \ + a_##TYPE[i] = i * 2 + 1 + 88; \ + test_1_##TYPE (637); \ + for (unsigned int i = 0; i < 637; i++) \ + if (b_##TYPE[i] != a_##TYPE[i]) \ + __builtin_abort (); + +#define run_10(TYPE) \ + for (unsigned int i = 0; i < N; i++) \ + a_##TYPE[i] = i * 2 * 331 + 1 + 547; \ + test_1_##TYPE (777); \ + for (unsigned int i = 0; i < 777; i++) \ + if (b_##TYPE[i] != a_##TYPE[i]) \ + __builtin_abort (); + +#define TEST_ALL(T) \ + T (int8_t) \ + T (uint8_t) \ + T (int16_t) \ + T (uint16_t) \ + T (int32_t) \ + T (uint32_t) \ + T (int64_t) \ + T (uint64_t) \ + T (float) \ + T (double) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c new file mode 100644 index 00000000000..4af2f18de8a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c @@ -0,0 +1,19 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "-fno-vect-cost-model -fno-tree-loop-distribute-patterns --param riscv-autovec-preference=scalable" } */ + +#include "single_rgroup-1.c" + +int main (void) +{ + TEST_ALL (run_1) + TEST_ALL (run_2) + TEST_ALL (run_3) + TEST_ALL (run_4) + TEST_ALL (run_5) + TEST_ALL (run_6) + TEST_ALL (run_7) + TEST_ALL (run_8) + TEST_ALL (run_9) + TEST_ALL (run_10) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/template-1.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/template-1.h new file mode 100644 index 00000000000..799e2d7d754 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/template-1.h @@ -0,0 +1,68 @@ +#include +#include + +void +foo0 (int8_t *__restrict f, int16_t *__restrict d, int n) +{ + for (int i = 0; i < n; ++i) + { + f[i * 2 + 0] = 1; + f[i * 2 + 1] = 2; + d[i] = 3; + } +} + +void +foo1 (int16_t *__restrict f, int32_t *__restrict d, int n) +{ + for (int i = 0; i < n; ++i) + { + f[i * 2 + 0] = 1; + f[i * 2 + 1] = 2; + d[i] = 3; + } +} + +void +foo2 (int32_t *__restrict f, int64_t *__restrict d, int n) +{ + for (int i = 0; i < n; ++i) + { + f[i * 2 + 0] = 1; + f[i * 2 + 1] = 2; + d[i] = 3; + } +} + +void +foo3 (int16_t *__restrict f, float *__restrict d, int n) +{ + for (int i = 0; i < n; ++i) + { + f[i * 2 + 0] = 1; + f[i * 2 + 1] = 2; + d[i] = 3; + } +} + +void +foo4 (int32_t *__restrict f, float *__restrict d, int n) +{ + for (int i = 0; i < n; ++i) + { + f[i * 2 + 0] = 1; + f[i * 2 + 1] = 2; + d[i] = 3; + } +} + +void +foo5 (float *__restrict f, double *__restrict d, int n) +{ + for (int i = 0; i < n; ++i) + { + f[i * 2 + 0] = 1; + f[i * 2 + 1] = 2; + d[i] = 3; + } +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c new file mode 100644 index 00000000000..7ff84f60749 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c new file mode 100644 index 00000000000..dc22eefbd36 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c new file mode 100644 index 00000000000..36f6d98a5cb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d --param riscv-autovec-preference=scalable -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c new file mode 100644 index 00000000000..794f28e73bd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" + diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c new file mode 100644 index 00000000000..8e68b9932b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c new file mode 100644 index 00000000000..d5e36190b31 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c new file mode 100644 index 00000000000..d154df4c4ba --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl128b -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize -fno-vect-cost-model -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c new file mode 100644 index 00000000000..68e7696ed65 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d --param riscv-autovec-preference=scalable -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c new file mode 100644 index 00000000000..f8860a36332 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" + + diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c new file mode 100644 index 00000000000..c26c2c95afb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c new file mode 100644 index 00000000000..3a6a3aa1261 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32x_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" + diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c new file mode 100644 index 00000000000..d1aaf3f4297 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32x_zvl128b -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c new file mode 100644 index 00000000000..0d03536389f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d --param riscv-autovec-preference=scalable -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c new file mode 100644 index 00000000000..ca423285011 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c new file mode 100644 index 00000000000..40fcbdf1dfb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c new file mode 100644 index 00000000000..4c6c7e2fb3b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c new file mode 100644 index 00000000000..b8253476973 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl128b -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c new file mode 100644 index 00000000000..e7900b82215 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d --param riscv-autovec-preference=scalable -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c new file mode 100644 index 00000000000..1c0e8c2785b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c new file mode 100644 index 00000000000..0f9ff7a6105 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c new file mode 100644 index 00000000000..daf4a4e8e64 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64f_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c new file mode 100644 index 00000000000..3866e45546c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64f_zvl128b -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c new file mode 100644 index 00000000000..4c190c303c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d --param riscv-autovec-preference=scalable -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c new file mode 100644 index 00000000000..66bb1f44170 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c new file mode 100644 index 00000000000..e30a6bce18b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c new file mode 100644 index 00000000000..6920a395d1c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64x_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c new file mode 100644 index 00000000000..d8b60babf9a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64x_zvl128b -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ + +#include "template-1.h" + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp index 4b5509db385..49bb6012af6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp @@ -46,6 +46,22 @@ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.\[cS\]]] \ "" $CFLAGS gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]] \ "" $CFLAGS +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \ + "" $CFLAGS + +set AUTOVEC_TEST_OPTS [list \ + {-ftree-vectorize -O3 --param riscv-autovec-lmul=m1} \ + {-ftree-vectorize -O3 --param riscv-autovec-lmul=m2} \ + {-ftree-vectorize -O3 --param riscv-autovec-lmul=m4} \ + {-ftree-vectorize -O3 --param riscv-autovec-lmul=m8} \ + {-ftree-vectorize -O2 --param riscv-autovec-lmul=m1} \ + {-ftree-vectorize -O2 --param riscv-autovec-lmul=m2} \ + {-ftree-vectorize -O2 --param riscv-autovec-lmul=m4} \ + {-ftree-vectorize -O2 --param riscv-autovec-lmul=m8} ] +foreach op $AUTOVEC_TEST_OPTS { + gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/partial/*.\[cS\]]] \ + "" "$op" +} # All done. dg-finish