From patchwork Wed Apr 19 07:38:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xianwei Zhao X-Patchwork-Id: 85235 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp193177vqo; Wed, 19 Apr 2023 00:51:23 -0700 (PDT) X-Google-Smtp-Source: AKy350ZEFyNXr+hHwO71g2gIFZihiM3cd+lM59QtJ5CzMub6ehhGf6RHQ4AQVedEgEY6w8nPV7zZ X-Received: by 2002:aca:bc55:0:b0:38d:ef18:53b5 with SMTP id m82-20020acabc55000000b0038def1853b5mr1972352oif.51.1681890683685; Wed, 19 Apr 2023 00:51:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681890683; cv=none; d=google.com; s=arc-20160816; b=d7kF+W6oflbqg8etxXneZfgJ+NWX4ubj8SOU9g/fDSGObCLETDWd+n1Ud0pR/XOaAx cTqaCm640qWXMoWc9VGVnITCJ6wKT0zGNW/F5kASAShWWdrYDUpnxl/ztwTG3rOva5WS O3AYJURbVxuOLzntbOVe3qRCPJ6tZQ6FfjYyvLqjiQ3DOYOAAkWRobfe2wpxLIpf7zN0 QjAWuatMZEKNBx5yPV0saRhLgQMa+DxBsZ3pYUGmw3blZkOeBjmZSmP8fCUrk3+QRTbg DXDE5g5oV5R8Ho01J4xSydrtCy10vWq2L0y2sHzYRXjHjOissTPlaNKnf1gFDuz4kSSu aDZg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=px87CcZjB0CefLcU8f9osP8m5uOk0v23cZvz8wO9CXo=; b=gYVCt+DYHrCJcNZQU4GitGiqOmNgs6vWqI2+nYx52mGhZmQPyyZNiXgMkGkxvFABTo 3v7qGpKTMAB6v02RBsqIfCdNg2ftUZ2Y+TwnabLpTaGIa5M1460ZAVEOFQz6Z6RZ2sen +QAdVbkzItQEOZXFJN1Ex5coJy0k0ZT9oAy4jsvN4HUV4oRh2JWYy92iJYGUEx5TtdfV BMyt5WgVPQDfhpO7FI6KDry3FlyEL5o5vQ/u0hFrYayYLTnFYI5FZ5JDW5dQywg9jVc5 gTsfIEbVRwFLF0+9PWdA2L5s67mV22s2wW7X4xOvWGkDxnR3BzyTYF9dQBM8BOoyhpg0 dSDw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id v6-20020aca6106000000b0038de8a632adsi8280820oib.16.2023.04.19.00.51.10; Wed, 19 Apr 2023 00:51:23 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232408AbjDSHjD (ORCPT + 99 others); Wed, 19 Apr 2023 03:39:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58316 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232418AbjDSHit (ORCPT ); Wed, 19 Apr 2023 03:38:49 -0400 Received: from mail-sh.amlogic.com (mail-sh.amlogic.com [58.32.228.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 21AAC3AB8; Wed, 19 Apr 2023 00:38:45 -0700 (PDT) Received: from droid01-cd.amlogic.com (10.98.11.200) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.13; Wed, 19 Apr 2023 15:39:58 +0800 From: =Xianwei Zhao To: , , , CC: Catalin Marinas , Will Deacon , Neil Armstrong , Kevin Hilman , Rob Herring , Krzysztof Kozlowski , Xianwei Zhao Subject: [RFC PATCH 1/2] arm64: amlogic: add new ARCH_AMLIPC for IPC SoC Date: Wed, 19 Apr 2023 15:38:33 +0800 Message-ID: <20230419073834.972273-2-xianwei.zhao@amlogic.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20230419073834.972273-1-xianwei.zhao@amlogic.com> References: <20230419073834.972273-1-xianwei.zhao@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.98.11.200] X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763590146278563554?= X-GMAIL-MSGID: =?utf-8?q?1763590205634449458?= From: Xianwei Zhao The C series SoCs are designed for smart IP camera applications, which does not belong to Meson series. So, Add ARCH_AMLIPC for the new series. There are now multiple amlogic SoC seies supported, so group them under their own menu. we can easily add new platforms there in the future. Introduce ARCH_AMLOGIC to cover all Amlogic SoC series. No functional changes introduced. Signed-off-by: Xianwei Zhao --- arch/arm64/Kconfig.platforms | 12 ++++++++++++ arch/arm64/configs/defconfig | 2 ++ 2 files changed, 14 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 89a0b13b058d..bfbc817eef8f 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -162,12 +162,24 @@ config ARCH_MEDIATEK This enables support for MediaTek MT27xx, MT65xx, MT76xx & MT81xx ARMv8 SoCs +menuconfig ARCH_AMLOGIC + bool "NXP SoC support" + +if ARCH_AMLOGIC + config ARCH_MESON bool "Amlogic Platforms" help This enables support for the arm64 based Amlogic SoCs such as the s905, S905X/D, S912, A113X/D or S905X/D2 +config ARCH_AMLIPC + bool "Amlogic IPC Platforms" + help + This enables support for the arm64 based Amlogic IPC SoCs + such as the C302X, C308L +endif + config ARCH_MVEBU bool "Marvell EBU SoC Family" select ARMADA_AP806_SYSCON diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 7790ee42c68a..f231bd1723fd 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -46,7 +46,9 @@ CONFIG_ARCH_LG1K=y CONFIG_ARCH_HISI=y CONFIG_ARCH_KEEMBAY=y CONFIG_ARCH_MEDIATEK=y +CONFIG_ARCH_AMLOGIC=y CONFIG_ARCH_MESON=y +CONFIG_ARCH_AMLIPC=y CONFIG_ARCH_MVEBU=y CONFIG_ARCH_NXP=y CONFIG_ARCH_LAYERSCAPE=y From patchwork Wed Apr 19 07:38:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xianwei Zhao X-Patchwork-Id: 85236 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp193262vqo; Wed, 19 Apr 2023 00:51:32 -0700 (PDT) X-Google-Smtp-Source: AKy350aS7T3tG6qYKDkMsqLivoTFBLSaUWvesDga8UbFG1jweEhpJAYB4zaraZR3kgQrn6xLUdFD X-Received: by 2002:a05:6871:5c9:b0:187:dbb8:f5fc with SMTP id v9-20020a05687105c900b00187dbb8f5fcmr3704483oan.35.1681890692542; Wed, 19 Apr 2023 00:51:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681890692; cv=none; d=google.com; s=arc-20160816; b=nrj35UvCXdql7SAVl1zohhl/8S3zqQgjyq4/FD1rXvVdMUyAnPGLEGeyn3NSaQzAYt p2OPh1ANohTFhaQD77bbH3RD9KVhmJ14lRryP302laAZMWnqaqBpoXDE2rhwK3I8I3oB j7TGRqxILS93dcNe+rbXO+rJ5M7k47B7f1grg5Cn1kQfuDs0TNmv1gN6zQuqcGpW+Nq/ QwIaaqQ0U0zErtxmbgu/LleQw90AfyxD1wOfjJBERHChSJQJcwqFKNIKYNBmMWQSuWbU 3PccwPt5oPZG+njJN43mzYB7NtWw3uqi6ESoogyTuKYNHTRDkWWIjwKOhTklGD4s791M l75A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=5t1YZhEm+at5QqkTXyucuJMVkzHpCFHi2VPgGL7Ys/g=; b=W/3wlHOsMBVQ2jOxK4JBYlKYeCKBkDCPgLQTcEVq7HjJ9dAD0AUdzwRtLFOievuhIX EvKQja5WDOgv4P+PFgBSYqsiodGUbFz5xeQSG5C3Y13AUmSkxIebu/2tmNkxjZcB1rtY PojcOOqCAgMSytk6ISgE47WVXQynclmAMzG+2DfyGGsFeJVFCyQvdns8mvYZNk5bf5cf bBrXqDSNVEYiFyCL/A5+paTEwZ6TgRcJZY7hnBEWxD47c8rggciXpov/gTpgc3B+ri+I kNDO9h6thyIyDvtS7XtLgR51xWsy6ENzvDCBkEXGHgoZZyKtjJw4f4ljG53cJ+MxbK++ 50Yw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id l5-20020a0568301d6500b006a07046628csi14763835oti.168.2023.04.19.00.51.19; Wed, 19 Apr 2023 00:51:32 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232454AbjDSHkL (ORCPT + 99 others); Wed, 19 Apr 2023 03:40:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58204 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232455AbjDSHjh (ORCPT ); Wed, 19 Apr 2023 03:39:37 -0400 Received: from mail-sh.amlogic.com (mail-sh.amlogic.com [58.32.228.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 26A719010; Wed, 19 Apr 2023 00:38:49 -0700 (PDT) Received: from droid01-cd.amlogic.com (10.98.11.200) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.13; Wed, 19 Apr 2023 15:40:00 +0800 From: =Xianwei Zhao To: , , , CC: Catalin Marinas , Will Deacon , Neil Armstrong , Kevin Hilman , Rob Herring , Krzysztof Kozlowski , Xianwei Zhao Subject: [RFC PATCH 2/2] arm64: dts: add support for C3 based Amlogic AW409 Date: Wed, 19 Apr 2023 15:38:34 +0800 Message-ID: <20230419073834.972273-3-xianwei.zhao@amlogic.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20230419073834.972273-1-xianwei.zhao@amlogic.com> References: <20230419073834.972273-1-xianwei.zhao@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.98.11.200] X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763590214544996649?= X-GMAIL-MSGID: =?utf-8?q?1763590214544996649?= From: Xianwei Zhao Amlogic C3 is an advanced edge AI processor designed for smart IP camera applications. Add basic support for the C3 based Amlogic AW409 board, which describes the following components: CPU, GIC, IRQ, Timer, UART. It's capable of booting up into the serial console. Signed-off-by: Xianwei Zhao --- arch/arm64/boot/dts/amlogic/Makefile | 1 + .../amlogic/amlogic-c3-c302x-aw409-256m.dts | 30 +++++++ arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi | 87 +++++++++++++++++++ 3 files changed, 118 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409-256m.dts create mode 100644 arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index cd1c5b04890a..d2b5d0d750bc 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -74,3 +74,4 @@ dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-hc4.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-air-gbit.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-air.dtb +dtb-$(CONFIG_ARCH_AMLIPC) += amlogic-c3-c302x-aw409-256m.dtb diff --git a/arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409-256m.dts b/arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409-256m.dts new file mode 100644 index 000000000000..38ca98a32181 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409-256m.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "amlogic-c3.dtsi" + +/ { + model = "Amlogic C302 aw409 Development Board"; + compatible = "amlogic,aw409", "amlogic,c3"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart_B; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x10000000>; + }; + +}; + +&uart_B { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi new file mode 100644 index 000000000000..c69072ac57f5 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. + */ + +#include +#include +#include + +/ { + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@fff01000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xfff01000 0 0x1000>, + <0x0 0xfff02000 0 0x2000>, + <0x0 0xfff04000 0 0x2000>, + <0x0 0xfff06000 0 0x2000>; + interrupts = ; + }; + + apb4: apb4@fe000000 { + compatible = "simple-bus"; + reg = <0x0 0xfe000000 0x0 0x480000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; + + uart_B: serial@7a000 { + compatible = "amlogic,meson-g12a-uart"; + reg = <0x0 0x7a000 0x0 0x18>; + interrupts = ; + status = "disabled"; + clocks = <&xtal>, <&xtal>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + }; + + }; + }; +};