From patchwork Wed Apr 19 06:17:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jayesh Choudhary X-Patchwork-Id: 85199 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp146110vqo; Tue, 18 Apr 2023 23:20:37 -0700 (PDT) X-Google-Smtp-Source: AKy350YWGYV8FvrEDmyixQjXhPRt8h77DOutZmggdD0+YfZc7Y31iBUtL1GGAK42Zo619uKokW0r X-Received: by 2002:a05:6a00:2387:b0:63d:45f3:9fc with SMTP id f7-20020a056a00238700b0063d45f309fcmr1662004pfc.5.1681885237664; Tue, 18 Apr 2023 23:20:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681885237; cv=none; d=google.com; s=arc-20160816; b=KQJjdwnTnq7Y4G8DABWpIqkjxbfmXIuRlqlUWQZuqhHJ2ISwqY+IECNLs6jJDn1QkQ 4BakO3xUNom1Sm7Zh6eRXmFBaM7ztYI9dz51xaak6g5TGfvVbKYm/O1AgZ063bN+wNRn RgMKZOA+6RbWeSgbTHIbSHQEtEWbULLwC4WsXE/9a1ccYRiJTuRNfOTmk9j6fd4ZwFWX MQ0/mkR9ME2clkQgoZ3Na7ZfCio/YXNoc52mWd+8XnfAwbaR9yyBQe032VkU9x34mX5h 6tQrsCwU95Z2qmeKazVOm85EyT86o7FV/XxicsV4sfechu66uS26GY597giItD67xh+P enwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Fm0aTVswfF119yj8u2DtQRLssdzWg+pA7dI7E0KBRYA=; b=obIGfpt7Sa/zHNF3ZB1j7uJneD/e7/W4GeqFLXwOE7IDJKOSrRkVJ0dbQ4h7jUMamA 9ctqvLjaHYrKzqhJNBMPkxqaFtTvpec3uJASpnbPBv+H4Vi87QfAjcHq2jzMof9FhPUv A4BPvp3Dmuh2slAtbZgJugz/b1sVgKnRDgBKdmX4A19pAf4+LwvZ+6+mvrCcbtZyIKZ9 akPbYDLU1TcRjC36VCILE8TcsZTM1iVKkMF/cVvYIaYK+DFE41HlUWprjHyr40RO8lKO mMT9gEoEQsahLOxoAoQtb58ccG0pnwkrburNSR06v8/nn2N4adS1bYnwIN0YyMUxzyBO 3/1g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=LOPajOsj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id v7-20020a655687000000b005139874b88bsi15704646pgs.87.2023.04.18.23.20.25; Tue, 18 Apr 2023 23:20:37 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=LOPajOsj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231226AbjDSGRe (ORCPT + 99 others); Wed, 19 Apr 2023 02:17:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231642AbjDSGR2 (ORCPT ); Wed, 19 Apr 2023 02:17:28 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 215BF5257; Tue, 18 Apr 2023 23:17:27 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 33J6HDMw124874; Wed, 19 Apr 2023 01:17:13 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1681885033; bh=Fm0aTVswfF119yj8u2DtQRLssdzWg+pA7dI7E0KBRYA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=LOPajOsjiDebkDoW8RBBKJKi89/KEypHSE+CY7q5mABQfPO6bW4acfN0ejz6gmv+i XhqBrB4lZAZbaIGVFmZZPXoCUmHUXv4GBp1Sqy6k1WuCmFmvujZdiUlQVaeqFSzi5B LebDNhrheO1zeGl9Jyg72by8GbMqwXi0YmRQbgkg= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 33J6HDAo125729 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 19 Apr 2023 01:17:13 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 19 Apr 2023 01:17:12 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 19 Apr 2023 01:17:12 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 33J6HCoW040858; Wed, 19 Apr 2023 01:17:12 -0500 From: Jayesh Choudhary To: , , CC: , , , , , , , , Subject: [PATCH v3 1/5] arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane mux Date: Wed, 19 Apr 2023 11:47:06 +0530 Message-ID: <20230419061710.290068-2-j-choudhary@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230419061710.290068-1-j-choudhary@ti.com> References: <20230419061710.290068-1-j-choudhary@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763584494704729193?= X-GMAIL-MSGID: =?utf-8?q?1763584494704729193?= From: Siddharth Vadapalli The system controller node manages the CTRL_MMR0 region. Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux. Signed-off-by: Siddharth Vadapalli [j-choudhary@ti.com: Minor cleanup to fix dtc warnings] Signed-off-by: Jayesh Choudhary --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index e9169eb358c1..5fb7edf4f5a0 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -5,6 +5,9 @@ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ */ +#include +#include + &cbass_main { msmc_ram: sram@70000000 { compatible = "mmio-sram"; @@ -26,6 +29,25 @@ l3cache-sram@200000 { }; }; + scm_conf: syscon@100000 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00 0x00100000 0x00 0x1c000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x00100000 0x1c000>; + + serdes_ln_ctrl: mux-controller-4080 { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ + <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */ + <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ + <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */ + <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ + <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */ + }; + }; + gic500: interrupt-controller@1800000 { compatible = "arm,gic-v3"; #address-cells = <2>; From patchwork Wed Apr 19 06:17:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jayesh Choudhary X-Patchwork-Id: 85198 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp145954vqo; Tue, 18 Apr 2023 23:20:19 -0700 (PDT) X-Google-Smtp-Source: AKy350azM8b01cr3N2qwbndYODmjc/yzMz6nla8HurMoGPb1edEYz+mMqFYB8dCGtFERBUO41hWk X-Received: by 2002:a05:6a21:78e:b0:f0:942e:873b with SMTP id mg14-20020a056a21078e00b000f0942e873bmr2201272pzb.7.1681885219455; Tue, 18 Apr 2023 23:20:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681885219; cv=none; d=google.com; s=arc-20160816; b=iwPssfvguy7Uf72+ls+VHD50txkjYUpXDsURkfPR8v/RCCbf3tJIvNZhB7w2DGIPMh sbthUrS+4UE64bclmct8/6+NAN0tKymDic1UUHQOiQn1S3J25z7i0I8ArDNlPU7xyTAq u7RV5uG+JsDpllfC5dJn+MgEiJ0c5Ab9jts48OgJjtSOKR+nEcR/WzT1N3Gj0I9nUx1N xWS+pZ9slJyi+W/Ut1Vjja/cvOTZQOzmTKeaoGMl2XhIvQwcaXZZTRGi1vK7iF0v1fTJ ahwXIpEQ3VdtFZEmXgFmZPyKpOhSuZdNSkeN7drX5rMRSWlvgmL2X2DDRXYQVizqfyMQ M7iw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=dO74LX6UCcLkkqB0AJwaOAyJvEScpBBA7QMwhX+XshI=; b=OxihD7OvQPA4DMSbtI9ytDCOyLuI165hXMVZz/DTI6y0VOUvn10D05n8QMVvOENFZ8 HHGtkZjaDpbVVExWy1CxO+Ie0kT3NeNc/GXxw8++gURfFVdr9NjFKep3BQWUHwnfgNV7 rwyELyDs3Iat5jeASKFP/HccOwQnQ5k3FaMFN+qUH6gusALMjDQ1p/2ZckrmrDmg2kce /Wlngtk/AsCEr3UNkxviUfYsparbXoJyMhz3E5gA1MDk5tPYPte8L0hiSmyetX/MJvyP /uc73ios65qXM3on85MIpS0J/XkFmhBSKdXcaNLPUxn9hHpiClIBtEVpzg/Vzj+vz9DE oMdQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=eQiQfI48; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id y17-20020a1709029b9100b001a6e9d170c1si5217463plp.511.2023.04.18.23.20.07; Tue, 18 Apr 2023 23:20:19 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=eQiQfI48; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231719AbjDSGRb (ORCPT + 99 others); Wed, 19 Apr 2023 02:17:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60338 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231464AbjDSGR2 (ORCPT ); Wed, 19 Apr 2023 02:17:28 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D82EF1BE3; Tue, 18 Apr 2023 23:17:25 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 33J6HEaJ022670; Wed, 19 Apr 2023 01:17:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1681885034; bh=dO74LX6UCcLkkqB0AJwaOAyJvEScpBBA7QMwhX+XshI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=eQiQfI48oe71FsO8agYDGAjENqKFTiCZcUFwMl77RyXhGe8rs1mypUWQj5IX54Ln2 7zfBRCAtyFKfssUBPZFrESe21auQHVwmqBZBQyfCPmerdZSrturFsBR5Z9WOQwPNsP 1p3e2nMM+AQw07v5B6uraMfJEhScgP7T6dke0WZ8= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 33J6HEvB001886 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 19 Apr 2023 01:17:14 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 19 Apr 2023 01:17:14 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 19 Apr 2023 01:17:14 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 33J6HDIn009540; Wed, 19 Apr 2023 01:17:13 -0500 From: Jayesh Choudhary To: , , CC: , , , , , , , , Subject: [PATCH v3 2/5] arm64: dts: ti: k3-j784s4: Add Main CPSW2G node Date: Wed, 19 Apr 2023 11:47:07 +0530 Message-ID: <20230419061710.290068-3-j-choudhary@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230419061710.290068-1-j-choudhary@ti.com> References: <20230419061710.290068-1-j-choudhary@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763584476198631446?= X-GMAIL-MSGID: =?utf-8?q?1763584476198631446?= From: Siddharth Vadapalli J784S4 SoC has a Main CPSW2G instance of the CPSW Ethernet Switch. Add the device-tree nodes for the Main CPSW2G instance and enable it. Signed-off-by: Siddharth Vadapalli Signed-off-by: Jayesh Choudhary --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 48 +++++++++++++++ arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 68 ++++++++++++++++++++++ 2 files changed, 116 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index f33815953e77..aef6f53ae8ac 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -105,6 +105,30 @@ vdd_sd_dv: regulator-TLV71033 { }; &main_pmx0 { + main_cpsw2g_pins_default: main-cpsw2g-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x0b8, PIN_INPUT, 6) /* (AC34) MCASP1_ACLKX.RGMII1_RD0 */ + J784S4_IOPAD(0x0a0, PIN_INPUT, 6) /* (AD34) MCASP0_AXR12.RGMII1_RD1 */ + J784S4_IOPAD(0x0a4, PIN_INPUT, 6) /* (AJ36) MCASP0_AXR13.RGMII1_RD2 */ + J784S4_IOPAD(0x0a8, PIN_INPUT, 6) /* (AF34) MCASP0_AXR14.RGMII1_RD3 */ + J784S4_IOPAD(0x0b0, PIN_INPUT, 6) /* (AL33) MCASP1_AXR3.RGMII1_RXC */ + J784S4_IOPAD(0x0ac, PIN_INPUT, 6) /* (AE34) MCASP0_AXR15.RGMII1_RX_CTL */ + J784S4_IOPAD(0x08c, PIN_INPUT, 6) /* (AE35) MCASP0_AXR7.RGMII1_TD0 */ + J784S4_IOPAD(0x090, PIN_INPUT, 6) /* (AC35) MCASP0_AXR8.RGMII1_TD1 */ + J784S4_IOPAD(0x094, PIN_INPUT, 6) /* (AG35) MCASP0_AXR9.RGMII1_TD2 */ + J784S4_IOPAD(0x098, PIN_INPUT, 6) /* (AH36) MCASP0_AXR10.RGMII1_TD3 */ + J784S4_IOPAD(0x0b4, PIN_INPUT, 6) /* (AL34) MCASP1_AXR4.RGMII1_TXC */ + J784S4_IOPAD(0x09c, PIN_INPUT, 6) /* (AF35) MCASP0_AXR11.RGMII1_TX_CTL */ + >; + }; + + main_cpsw2g_mdio_pins_default: main-cpsw2g-mdio-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x0c0, PIN_INPUT, 6) /* (AD38) MCASP1_AXR0.MDIO0_MDC */ + J784S4_IOPAD(0x0bc, PIN_INPUT, 6) /* (AD33) MCASP1_AFSX.MDIO0_MDIO */ + >; + }; + main_uart8_pins_default: main-uart8-pins-default { pinctrl-single,pins = < J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */ @@ -253,3 +277,27 @@ &mcu_cpsw_port1 { phy-mode = "rgmii-rxid"; phy-handle = <&mcu_phy0>; }; + +&main_cpsw1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_cpsw2g_pins_default>; +}; + +&main_cpsw1_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&main_cpsw2g_mdio_pins_default>; + + main_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&main_cpsw1_port1 { + status = "okay"; + phy-mode = "rgmii-rxid"; + phy-handle = <&main_phy0>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 5fb7edf4f5a0..8bd8aebebe1c 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -36,6 +36,12 @@ scm_conf: syscon@100000 { #size-cells = <1>; ranges = <0x00 0x00 0x00100000 0x1c000>; + cpsw1_phy_gmii_sel: phy@4034 { + compatible = "ti,am654-phy-gmii-sel"; + reg = <0x4034 0x4>; + #phy-cells = <1>; + }; + serdes_ln_ctrl: mux-controller-4080 { compatible = "mmio-mux"; #mux-control-cells = <1>; @@ -777,6 +783,68 @@ cpts@310d0000 { }; }; + main_cpsw1: ethernet@c200000 { + compatible = "ti,j721e-cpsw-nuss"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x00 0xc200000 0x00 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x00 0x00 0x00 0xc200000 0x00 0x200000>; + dma-coherent; + clocks = <&k3_clks 62 0>; + clock-names = "fck"; + power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&main_udmap 0xc640>, + <&main_udmap 0xc641>, + <&main_udmap 0xc642>, + <&main_udmap 0xc643>, + <&main_udmap 0xc644>, + <&main_udmap 0xc645>, + <&main_udmap 0xc646>, + <&main_udmap 0xc647>, + <&main_udmap 0x4640>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + status = "disabled"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + main_cpsw1_port1: port@1 { + reg = <1>; + label = "port1"; + phys = <&cpsw1_phy_gmii_sel 1>; + ti,mac-only; + status = "disabled"; + }; + }; + + main_cpsw1_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio", "ti,davinci_mdio"; + reg = <0x00 0xf00 0x00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 62 0>; + clock-names = "fck"; + bus_freq = <1000000>; + }; + + cpts@3d000 { + compatible = "ti,am65-cpts"; + reg = <0x00 0x3d000 0x00 0x400>; + clocks = <&k3_clks 62 3>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; + main_mcan0: can@2701000 { compatible = "bosch,m_can"; reg = <0x00 0x02701000 0x00 0x200>, From patchwork Wed Apr 19 06:17:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jayesh Choudhary X-Patchwork-Id: 85202 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp147089vqo; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id l16-20020a056830055000b006a44614e43csi9582230otb.43.2023.04.18.23.22.31; Tue, 18 Apr 2023 23:22:43 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=gUPHjFpC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231953AbjDSGRo (ORCPT + 99 others); Wed, 19 Apr 2023 02:17:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60352 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231779AbjDSGR3 (ORCPT ); Wed, 19 Apr 2023 02:17:29 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5D2B75276; Tue, 18 Apr 2023 23:17:27 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 33J6HFj2022684; Wed, 19 Apr 2023 01:17:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1681885035; bh=OXCA3LIay5KHENJF7Dc2nVxwrTCC4FSZPftHlfXQhNA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=gUPHjFpCzrxKbwf5KWG0shB5O9SF8pgie2YQEJs9/0MeuAP1fw7KexW3/KQntJNU2 VBIs5ikgf95RwlulLlR/64RN4n22nn+tmD932F4gvq9kmzD6Gb6fcyhKmh+qe8ov3/ n4nr3m5khxpCOsFpsuaiyjAB44PfVuBmwiK8aZRo= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 33J6HF17125772 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 19 Apr 2023 01:17:15 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 19 Apr 2023 01:17:15 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 19 Apr 2023 01:17:15 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 33J6HE9Q045442; Wed, 19 Apr 2023 01:17:15 -0500 From: Jayesh Choudhary To: , , CC: , , , , , , , , Subject: [PATCH v3 3/5] arm64: dts: ti: k3-j784s4: Add WIZ and SERDES PHY nodes Date: Wed, 19 Apr 2023 11:47:08 +0530 Message-ID: <20230419061710.290068-4-j-choudhary@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230419061710.290068-1-j-choudhary@ti.com> References: <20230419061710.290068-1-j-choudhary@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763584627080959302?= X-GMAIL-MSGID: =?utf-8?q?1763584627080959302?= From: Siddharth Vadapalli J784S4 SoC has 4 Serdes instances along with their respective WIZ instances. Add device-tree nodes for them and disable them by default. Signed-off-by: Siddharth Vadapalli Signed-off-by: Jayesh Choudhary --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 171 +++++++++++++++++++++ 1 file changed, 171 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 8bd8aebebe1c..51aa476dedba 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -7,6 +7,15 @@ #include #include +#include +#include + +/ { + serdes_refclk: serdes-refclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; +}; &cbass_main { msmc_ram: sram@70000000 { @@ -440,6 +449,168 @@ main_sdhci1: mmc@4fb0000 { status = "disabled"; }; + serdes_wiz0: wiz@5060000 { + compatible = "ti,j784s4-wiz-10g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 404 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 404 2>, <&k3_clks 404 6>, <&k3_clks 404 5>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "core_ref1_clk", "ext_ref_clk"; + assigned-clocks = <&k3_clks 404 6>; + assigned-clock-parents = <&k3_clks 404 10>; + num-lanes = <4>; + #reset-cells = <1>; + #clock-cells = <1>; + ranges = <0x5060000 0x00 0x5060000 0x10000>; + + status = "disabled"; + + serdes0: serdes@5060000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x05060000 0x010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz0 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; + clock-names = "refclk", "phy_en_refclk"; + assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 404 6>, + <&k3_clks 404 6>, + <&k3_clks 404 6>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + status = "disabled"; + }; + }; + + serdes_wiz1: wiz@5070000 { + compatible = "ti,j784s4-wiz-10g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 405 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 405 2>, <&k3_clks 405 6>, <&k3_clks 405 5>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "core_ref1_clk", "ext_ref_clk"; + assigned-clocks = <&k3_clks 405 6>; + assigned-clock-parents = <&k3_clks 405 10>; + num-lanes = <4>; + #reset-cells = <1>; + #clock-cells = <1>; + ranges = <0x05070000 0x00 0x05070000 0x10000>; + + status = "disabled"; + + serdes1: serdes@5070000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x05070000 0x010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz1 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>; + clock-names = "refclk", "phy_en_refclk"; + assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz1 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 405 6>, + <&k3_clks 405 6>, + <&k3_clks 405 6>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + status = "disabled"; + }; + }; + + serdes_wiz2: wiz@5020000 { + compatible = "ti,j784s4-wiz-10g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 406 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 406 2>, <&k3_clks 406 6>, <&k3_clks 406 5>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "core_ref1_clk", "ext_ref_clk"; + assigned-clocks = <&k3_clks 406 6>; + assigned-clock-parents = <&k3_clks 406 10>; + num-lanes = <4>; + #reset-cells = <1>; + #clock-cells = <1>; + ranges = <0x05020000 0x00 0x05020000 0x10000>; + + status = "disabled"; + + serdes2: serdes@5020000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x05020000 0x010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz2 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz2 TI_WIZ_PHY_EN_REFCLK>; + clock-names = "refclk", "phy_en_refclk"; + assigned-clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz2 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 406 6>, + <&k3_clks 406 6>, + <&k3_clks 406 6>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + status = "disabled"; + }; + }; + + serdes_wiz4: wiz@5050000 { + compatible = "ti,j784s4-wiz-10g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 407 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 407 2>, <&k3_clks 407 6>, <&k3_clks 407 5>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "core_ref1_clk", "ext_ref_clk"; + assigned-clocks = <&k3_clks 407 6>; + assigned-clock-parents = <&k3_clks 407 10>; + num-lanes = <4>; + #reset-cells = <1>; + #clock-cells = <1>; + ranges = <0x05050000 0x00 0x05050000 0x10000>, + <0xa030a00 0x00 0xa030a00 0x40>; /* DPTX PHY */ + + status = "disabled"; + + serdes4: serdes@5050000 { + /* + * Note: we also map DPTX PHY registers as the Torrent + * needs to manage those. + */ + compatible = "ti,j721e-serdes-10g"; + reg = <0x05050000 0x010000>, + <0x0a030a00 0x40>; /* DPTX PHY */ + reg-names = "torrent_phy"; + resets = <&serdes_wiz4 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz4 TI_WIZ_PHY_EN_REFCLK>; + clock-names = "refclk", "phy_en_refclk"; + assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz4 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 407 6>, + <&k3_clks 407 6>, + <&k3_clks 407 6>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + status = "disabled"; + }; + }; + main_navss: bus@30000000 { compatible = "simple-bus"; #address-cells = <2>; From patchwork Wed Apr 19 06:17:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jayesh Choudhary X-Patchwork-Id: 85197 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp145159vqo; Tue, 18 Apr 2023 23:18:52 -0700 (PDT) X-Google-Smtp-Source: AKy350Y9DlOQxbgSul1Lq1YG3OEK9X4LEaw/OLnEjyLu2ytkIFapTNH3lXsfVC8nVNgvpxM/bDEt X-Received: by 2002:a17:902:ecc1:b0:19c:be57:9c82 with SMTP id a1-20020a170902ecc100b0019cbe579c82mr4929365plh.65.1681885132001; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id c8-20020a170902d48800b001a526bc2b84si16538142plg.620.2023.04.18.23.18.40; Tue, 18 Apr 2023 23:18:51 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=LHKv2s6Q; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231753AbjDSGR3 (ORCPT + 99 others); Wed, 19 Apr 2023 02:17:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60326 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231265AbjDSGR1 (ORCPT ); Wed, 19 Apr 2023 02:17:27 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7B5C8E5; Tue, 18 Apr 2023 23:17:25 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 33J6HHXS124891; Wed, 19 Apr 2023 01:17:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1681885037; bh=piX+ON1Oiun6W8lCeERO4CEWEgtwAYMuZNvQcGbvzxk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=LHKv2s6QcDR3PIcsXgoUNWrVD/h48vzlvLYILL79cGQ0TlyUQypQauyEDiz/6H+/y u2FzcxO/SBASTCoEM6Qg+U0SJCBNKztPTPKTuVys/0I2pHh85giSckAEn9GMnSHj3h t5Ef5GpbXm9F+QDuq9Jz8yCmzynbGtYvZrT4fNuM= Received: from DFLE110.ent.ti.com (dfle110.ent.ti.com [10.64.6.31]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 33J6HHc9001920 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 19 Apr 2023 01:17:17 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 19 Apr 2023 01:17:17 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 19 Apr 2023 01:17:16 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 33J6HGO4040914; Wed, 19 Apr 2023 01:17:16 -0500 From: Jayesh Choudhary To: , , CC: , , , , , , , , Subject: [PATCH v3 4/5] arm64: dts: ti: k3-j784s4-main: Add DSS and DP-bridge node Date: Wed, 19 Apr 2023 11:47:09 +0530 Message-ID: <20230419061710.290068-5-j-choudhary@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230419061710.290068-1-j-choudhary@ti.com> References: <20230419061710.290068-1-j-choudhary@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763584384352494632?= X-GMAIL-MSGID: =?utf-8?q?1763584384352494632?= From: Rahul T R Add DSS and DP-bridge node for J784S4 SoC. DSS IP in J784S4 is same as DSS IP in J721E, so same compatible is being used. The DP is Cadence MHDP8546. Signed-off-by: Rahul T R [j-choudhary@ti.com: move all k3-j784s4-main.dtsi changes together] Signed-off-by: Jayesh Choudhary --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 77 ++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 51aa476dedba..739741e93bc1 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -1373,4 +1373,81 @@ main_spi7: spi@2170000 { clocks = <&k3_clks 383 1>; status = "disabled"; }; + + mhdp: dp-bridge@a000000 { + compatible = "ti,j721e-mhdp8546"; + + reg = <0x0 0xa000000 0x0 0x30a00>, + <0x0 0x4f40000 0x0 0x20>; + reg-names = "mhdptx", "j721e-intg"; + + clocks = <&k3_clks 217 11>; + + interrupt-parent = <&gic500>; + interrupts = ; + + power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>; + + status = "disabled"; + + dp0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + dss: dss@4a00000 { + compatible = "ti,j721e-dss"; + reg = + <0x00 0x04a00000 0x00 0x10000>, + <0x00 0x04a10000 0x00 0x10000>, + <0x00 0x04b00000 0x00 0x10000>, + <0x00 0x04b10000 0x00 0x10000>, + + <0x00 0x04a20000 0x00 0x10000>, + <0x00 0x04a30000 0x00 0x10000>, + <0x00 0x04a50000 0x00 0x10000>, + <0x00 0x04a60000 0x00 0x10000>, + + <0x00 0x04a70000 0x00 0x10000>, + <0x00 0x04a90000 0x00 0x10000>, + <0x00 0x04ab0000 0x00 0x10000>, + <0x00 0x04ad0000 0x00 0x10000>, + + <0x00 0x04a80000 0x00 0x10000>, + <0x00 0x04aa0000 0x00 0x10000>, + <0x00 0x04ac0000 0x00 0x10000>, + <0x00 0x04ae0000 0x00 0x10000>, + <0x00 0x04af0000 0x00 0x10000>; + + reg-names = "common_m", "common_s0", + "common_s1", "common_s2", + "vidl1", "vidl2","vid1","vid2", + "ovr1", "ovr2", "ovr3", "ovr4", + "vp1", "vp2", "vp3", "vp4", + "wb"; + + clocks = <&k3_clks 218 0>, + <&k3_clks 218 2>, + <&k3_clks 218 5>, + <&k3_clks 218 14>, + <&k3_clks 218 18>; + clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; + + power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>; + + interrupts = , + , + , + ; + interrupt-names = "common_m", + "common_s0", + "common_s1", + "common_s2"; + + status = "disabled"; + + dss_ports: ports { + }; + }; }; From patchwork Wed Apr 19 06:17:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jayesh Choudhary X-Patchwork-Id: 85203 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp147174vqo; Tue, 18 Apr 2023 23:22:53 -0700 (PDT) X-Google-Smtp-Source: AKy350YFhY4sx7ZMZud8lL4Ic8/otS0FNXldmZuI1EYu9uM++gp9qeJbH9IxKxN1KjXeAy4aimVD X-Received: by 2002:a4a:4951:0:b0:546:4bca:b572 with SMTP id z78-20020a4a4951000000b005464bcab572mr5108194ooa.0.1681885373661; Tue, 18 Apr 2023 23:22:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681885373; cv=none; d=google.com; s=arc-20160816; b=aSToLPmUJPCKe3bpc9CurOa5siK6MaJCa9aoH4nuFwrQFD6tJWt80rhciodABBMkTQ wGJddF29YCRwJJtHono8pSzaszYObboLq+1ClhbwzYc0RXPtO7oZ9j4dXL3Ug3gKGvVs zSR1aQCzX8zZs9ARWNof7vPwes03/TwrzSjHOIVP5h3cm1BHT2M4a/pbbrenxCk1U39y 8LYhghZjEZx2tgWwNTi+0mYQU6z7z3renIwcBc+EIntSQ9tzoxz76Ljv81GQSa9S8bUa r1hnSPTntYlAfoBb1MKVNeZI4pYvIG8WiBuqF66K9Ih58u0aNtgnMlIbZV5sQsmPbb8z ziVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=xNUIKXBBWa/IdIZgk/VsRjGwKSnuZMpj29WMOW5S6cI=; b=KOLobFCenHFRoOg2LjOXvvu2BGkP15zFIU6pviCEMmTCR4TcynocF1PbiVw4w94p10 wyCwMSOGvG1LiljbIKyDpcY/JhTskijQsQT9ePkjfZlhuitEQ21ftKTREYWE5plzV4qc TTBil9DxJp9IzmKITKVzzPwBiKNI2A7O8SRJWdfuPTAuujhciDWRiMoFbukGa1vnpf60 GrTPTugl6IggQI5dsohHc/n5PDaYE2Pw6chCl9Ym/DCmHa+Cey4gKHp/1jdE2AaJyUWU vICDXRCDzPqCLAPCFaDp1uMa7Dyt8pSWlJheDnl6Vcw9VpNxtRW7h4myxHNnNS8ExeN+ HZeg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=B+FrE5Lk; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id p5-20020a4ae145000000b00541d2049972si13874731oot.48.2023.04.18.23.22.40; Tue, 18 Apr 2023 23:22:53 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=B+FrE5Lk; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231862AbjDSGRl (ORCPT + 99 others); Wed, 19 Apr 2023 02:17:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231741AbjDSGR3 (ORCPT ); Wed, 19 Apr 2023 02:17:29 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5D038525F; Tue, 18 Apr 2023 23:17:27 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 33J6HJh7022698; Wed, 19 Apr 2023 01:17:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1681885039; bh=xNUIKXBBWa/IdIZgk/VsRjGwKSnuZMpj29WMOW5S6cI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=B+FrE5Lk6vMo3Ez9eo8UNxW9Dtmxm5LBHOgW9dv9rXuBLnZ4CDxCpe42U9wV+nbFB TfE1lYKMOatQh4Ptyyoadp5uO1tOsJMTv1iqMESBoxfmot04tbArz+RwKx91sz2mW9 VMdLBigzny2NlJcEYXTqKJlRCoGuvG3w7qW0d0Jw= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 33J6HJe0125790 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 19 Apr 2023 01:17:19 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 19 Apr 2023 01:17:18 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 19 Apr 2023 01:17:18 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 33J6HIhS018725; Wed, 19 Apr 2023 01:17:18 -0500 From: Jayesh Choudhary To: , , CC: , , , , , , , , Subject: [PATCH v3 5/5] arm64: dts: ti: k3-j784s4-evm: Enable DisplayPort-0 Date: Wed, 19 Apr 2023 11:47:10 +0530 Message-ID: <20230419061710.290068-6-j-choudhary@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230419061710.290068-1-j-choudhary@ti.com> References: <20230419061710.290068-1-j-choudhary@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763584637423050512?= X-GMAIL-MSGID: =?utf-8?q?1763584637423050512?= From: Rahul T R Enable display for J784S4 EVM. Add assigned clocks for DSS, DT node for DisplayPort PHY and pinmux for DP HPD. Add the clock frequency for serdes_refclk. Add the endpoint nodes to describe connection from: DSS => MHDP => DisplayPort connector. Also add the GPIO expander-4 node and pinmux for main_i2c4 which is required for controlling DP power. Set status for all required nodes for DP-0 as "okay". Signed-off-by: Rahul T R [j-choudhary@ti.com: move all the changes together to enable DP-0 in EVM] Signed-off-by: Jayesh Choudhary --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 116 +++++++++++++++++++++++ 1 file changed, 116 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index aef6f53ae8ac..03c9bf34cb1b 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -102,6 +102,28 @@ vdd_sd_dv: regulator-TLV71033 { states = <1800000 0x0>, <3300000 0x1>; }; + + dp0_pwr_3v3: regulator-dp0-prw { + compatible = "regulator-fixed"; + regulator-name = "dp0-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + dp0: dp0-connector { + compatible = "dp-connector"; + label = "DP0"; + type = "full-size"; + dp-pwr-supply = <&dp0_pwr_3v3>; + + port { + dp0_connector_in: endpoint { + remote-endpoint = <&dp0_out>; + }; + }; + }; }; &main_pmx0 { @@ -163,6 +185,19 @@ vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ >; }; + + dp0_pins_default: dp0-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x0cc, PIN_INPUT, 12) /* (AM37) SPI0_CS0.DP0_HPD */ + >; + }; + + main_i2c4_pins_default: main-i2c4-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AG33) MCAN14_TX.I2C4_SCL */ + J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */ + >; + }; }; &wkup_pmx0 { @@ -301,3 +336,84 @@ &main_cpsw1_port1 { phy-mode = "rgmii-rxid"; phy-handle = <&main_phy0>; }; + +&serdes_refclk { + clock-frequency = <100000000>; +}; + +&dss { + status = "okay"; + assigned-clocks = <&k3_clks 218 2>, + <&k3_clks 218 5>, + <&k3_clks 218 14>, + <&k3_clks 218 18>; + assigned-clock-parents = <&k3_clks 218 3>, + <&k3_clks 218 7>, + <&k3_clks 218 16>, + <&k3_clks 218 22>; +}; + +&serdes_wiz4 { + status = "okay"; +}; + +&serdes4 { + status = "okay"; + serdes4_dp_link: phy@0 { + reg = <0>; + cdns,num-lanes = <4>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>, + <&serdes_wiz4 3>, <&serdes_wiz4 4>; + }; +}; + +&mhdp { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dp0_pins_default>; + phys = <&serdes4_dp_link>; + phy-names = "dpphy"; +}; + +&dss_ports { + port { + dpi0_out: endpoint { + remote-endpoint = <&dp0_in>; + }; + }; +}; + +&main_i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c4_pins_default>; + clock-frequency = <400000>; + + exp4: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&dp0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; + + port@4 { + reg = <4>; + dp0_out: endpoint { + remote-endpoint = <&dp0_connector_in>; + }; + }; +};