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[8.43.85.97]) by mx.google.com with ESMTPS id d19-20020a056402001300b00506734fe162si12491839edu.450.2023.04.18.19.05.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 19:05:51 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=cE177uDk; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 02E94385841E for ; Wed, 19 Apr 2023 02:05:50 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 02E94385841E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1681869950; bh=1OeE7QCvdtHDyRPrvHysNKiM8wHnOMhxpwd0WCDyQD4=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=cE177uDkLuutxsXHZZJZQL/C+NZZA5+gf0Nlo7zW01w1CVCoRqTIVZb7KnZ6aLgAc H8FHmmN5mAd1X3HZsXG5gNqk2BcYjVGqLgPzoQfLDtXe+P2iODUNIJTTcExcykjy4i W/gHZXgUelfpnlXA2D+eyTTKZWOH37u5ij1fdfTM= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by sourceware.org (Postfix) with ESMTPS id 1D6403857722 for ; Wed, 19 Apr 2023 02:05:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1D6403857722 X-IronPort-AV: E=McAfee;i="6600,9927,10684"; a="408238032" X-IronPort-AV: E=Sophos;i="5.99,208,1677571200"; d="scan'208";a="408238032" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Apr 2023 19:05:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10684"; a="691314551" X-IronPort-AV: E=Sophos;i="5.99,208,1677571200"; d="scan'208";a="691314551" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga002.jf.intel.com with ESMTP; 18 Apr 2023 19:05:02 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id B3CB710081E8; Wed, 19 Apr 2023 10:05:01 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com Subject: [PATCH] Re-arrange sections of i386 cpuid Date: Wed, 19 Apr 2023 10:03:01 +0800 Message-Id: <20230419020301.1864306-1-zewei.mo@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "Mo, Zewei via Gcc-patches" From: "Li, Pan2 via Gcc-patches" Reply-To: "Mo, Zewei" Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763568465744671828?= X-GMAIL-MSGID: =?utf-8?q?1763568465744671828?= Re-order i386 cpuid based on the order of CPUID. gcc/ChangeLog: * config/i386/cpuid.h: Open a new section for Extended Features Leaf (%eax == 7, %ecx == 0) and Extended Features Sub-leaf (%eax == 7, %ecx == 1). --- gcc/config/i386/cpuid.h | 35 +++++++++++++++++++---------------- 1 file changed, 19 insertions(+), 16 deletions(-) diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h index be162dd8c78..971781c2b91 100644 --- a/gcc/config/i386/cpuid.h +++ b/gcc/config/i386/cpuid.h @@ -24,15 +24,6 @@ #ifndef _CPUID_H_INCLUDED #define _CPUID_H_INCLUDED -/* %eax */ -#define bit_RAOINT (1 << 3) -#define bit_AVXVNNI (1 << 4) -#define bit_AVX512BF16 (1 << 5) -#define bit_CMPCCXADD (1 << 7) -#define bit_AMX_FP16 (1 << 21) -#define bit_HRESET (1 << 22) -#define bit_AVXIFMA (1 << 23) - /* %ecx */ #define bit_SSE3 (1 << 0) #define bit_PCLMUL (1 << 1) @@ -52,10 +43,7 @@ #define bit_RDRND (1 << 30) /* %edx */ -#define bit_AVXVNNIINT8 (1 << 4) -#define bit_AVXNECONVERT (1 << 5) #define bit_CMPXCHG8B (1 << 8) -#define bit_PREFETCHI (1 << 14) #define bit_CMOV (1 << 15) #define bit_MMX (1 << 23) #define bit_FXSAVE (1 << 24) @@ -84,7 +72,7 @@ #define bit_CLZERO (1 << 0) #define bit_WBNOINVD (1 << 9) -/* Extended Features (%eax == 7) */ +/* Extended Features Leaf (%eax == 7, %ecx == 0) */ /* %ebx */ #define bit_FSGSBASE (1 << 0) #define bit_SGX (1 << 2) @@ -132,9 +120,9 @@ #define bit_AVX5124VNNIW (1 << 2) #define bit_AVX5124FMAPS (1 << 3) #define bit_AVX512VP2INTERSECT (1 << 8) -#define bit_AVX512FP16 (1 << 23) -#define bit_IBT (1 << 20) -#define bit_UINTR (1 << 5) +#define bit_AVX512FP16 (1 << 23) +#define bit_IBT (1 << 20) +#define bit_UINTR (1 << 5) #define bit_PCONFIG (1 << 18) #define bit_SERIALIZE (1 << 14) #define bit_TSXLDTRK (1 << 16) @@ -142,6 +130,21 @@ #define bit_AMX_TILE (1 << 24) #define bit_AMX_INT8 (1 << 25) +/* Extended Features Sub-leaf (%eax == 7, %ecx == 1) */ +/* %eax */ +#define bit_RAOINT (1 << 3) +#define bit_AVXVNNI (1 << 4) +#define bit_AVX512BF16 (1 << 5) +#define bit_CMPCCXADD (1 << 7) +#define bit_AMX_FP16 (1 << 21) +#define bit_HRESET (1 << 22) +#define bit_AVXIFMA (1 << 23) + +/* %edx */ +#define bit_AVXVNNIINT8 (1 << 4) +#define bit_AVXNECONVERT (1 << 5) +#define bit_PREFETCHI (1 << 14) + /* Extended State Enumeration Sub-leaf (%eax == 0xd, %ecx == 1) */ #define bit_XSAVEOPT (1 << 0) #define bit_XSAVEC (1 << 1)