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[83.9.29.144]) by smtp.gmail.com with ESMTPSA id q17-20020a19a411000000b004d86808fd33sm2365895lfc.15.2023.04.18.05.10.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 05:10:59 -0700 (PDT) From: Konrad Dybcio Date: Tue, 18 Apr 2023 14:10:56 +0200 Subject: [PATCH v2 1/5] dt-bindings: display/msm: Add reg bus interconnect MIME-Version: 1.0 Message-Id: <20230417-topic-dpu_regbus-v2-1-91a66d04898e@linaro.org> References: <20230417-topic-dpu_regbus-v2-0-91a66d04898e@linaro.org> In-Reply-To: <20230417-topic-dpu_regbus-v2-0-91a66d04898e@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681819856; l=1310; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=9eGzIhdzE/kh12Ssb8zLi8BB+5t4kj0lnuayorvjl54=; b=6fysWEnV+Y3QmSTMiVPNmoQ9u0QIAaEjvJEkX1mj0vdB2azvjMKBFTXFeb43KILmDBjB8FFs4iVp BB/S89PrA4Ytu9jBc2Dfi9OeeG/7wbARaGTUTtuRCJrQlU8X+ytt X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763516362990721489?= X-GMAIL-MSGID: =?utf-8?q?1763516362990721489?= Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's another path that needs to be handled to ensure MDSS functions properly, namely the "reg bus", a.k.a the CPU-MDSS interconnect. Gating that path may have a variety of effects.. from none to otherwise inexplicable DSI timeouts.. Describe it in bindings to allow for use in device trees. Signed-off-by: Konrad Dybcio Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/display/msm/mdss-common.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml index ccd7d6417523..30a8aed4289a 100644 --- a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml +++ b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml @@ -66,12 +66,14 @@ properties: items: - description: Interconnect path from mdp0 (or a single mdp) port to the data bus - description: Interconnect path from mdp1 port to the data bus + - description: Interconnect path from CPU to the reg bus interconnect-names: minItems: 1 items: - const: mdp0-mem - const: mdp1-mem + - const: cpu-cfg resets: items: From patchwork Tue Apr 18 12:10:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 84820 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2796928vqo; Tue, 18 Apr 2023 05:13:42 -0700 (PDT) X-Google-Smtp-Source: AKy350aWRt25q8nw6hU4+ub4Bm7VSu5GqKKrEPI8qGwepwY18+8h2fFWYXxXilpn8dClPRhanUrS X-Received: by 2002:a05:6a20:8422:b0:ee:93d3:2224 with SMTP id c34-20020a056a20842200b000ee93d32224mr15388336pzd.10.1681820022089; Tue, 18 Apr 2023 05:13:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681820022; cv=none; d=google.com; s=arc-20160816; b=wvoBgKMyqbG/LuSHxR+zTyv7h/MtsO51oWuMLg041/L2Q9RWIEB2rdInzAAT1h3978 +F8Kl+ASwvn5Mp0J7kgknKiTJT1BF9kAxH+JhUOTwLWWgx0MzJ4IluDPlYgeLYH7ORP0 yqyLkosoRW3VpWCQANGCWg6CyeHNkZwMv5knft4HYHUrruJn8b/161dw03GCqTueWU1T fOk2HHAMHt4A+ZWMh9L9tlao+9MjP/lF8BBR7+1B33VVIjKmdh9F8y7TdEMmkirJqPP6 9utkbnRP96SYOzVUin1c+UIVxu+TlccnlV6sCAEYV/7jMDKW09DYYBSgWMxejrjtbqUX xQDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=TusSYFhXpBTw3hD+Ig+2V6T5nJHWfXxfYQbiZRqJGNM=; b=Tnr+0edTKP+AbJFacSpFFoIIIRTFzlKfu4IVp/+ZDZfNP6GjLUCiJKt0UtUstLsIRW x8dCetgPrkyR0cNGtCxeWbX+roti7++Fmc53H2R5qXbxULFUIxyoRqAvwhS8MfqXaxUT rLYKa7cU5ITbFL07FLqLK6dzuEP+jztQ+yPq7rdrW+hqyj5vtpd54WzQstsxbFna5ZjS i0/Tfo9djc9LWRGwcU+rcTFt5WovuMSh8Hga8xMSLZy8KHIm7c4J/lekh4HYCNx8dSyq vIvsB54KAxZHEiKTKmZGbc9P0Ru1QZezqdiXXAxT1FdcFy1+IRDKEHrbBE1qC0YAupWu FdKA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qMjBZA6z; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.29.144]) by smtp.gmail.com with ESMTPSA id q17-20020a19a411000000b004d86808fd33sm2365895lfc.15.2023.04.18.05.10.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 05:11:00 -0700 (PDT) From: Konrad Dybcio Date: Tue, 18 Apr 2023 14:10:57 +0200 Subject: [PATCH v2 2/5] drm/msm/dpu1: Rename path references to mdp_path MIME-Version: 1.0 Message-Id: <20230417-topic-dpu_regbus-v2-2-91a66d04898e@linaro.org> References: <20230417-topic-dpu_regbus-v2-0-91a66d04898e@linaro.org> In-Reply-To: <20230417-topic-dpu_regbus-v2-0-91a66d04898e@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681819856; l=3187; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=RHVX4b0dy7ygKXk/64XZDOzn26jUEVt2/m6N5KVO6Vs=; b=r2TFBVO5Hj5SdRdHTZ0YLUP9sN8AtEd+o8gl6ja50IX5vktPr9lMiBBhBuvVF1QlIRM+I182r2iE 3e7I94N5DkppyOmS4WSIUeWXQZcRNBW8stdmAZtfC7dB3OlvbPvx X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763516111315098202?= X-GMAIL-MSGID: =?utf-8?q?1763516111315098202?= The DPU1 driver needs to handle all MDPn<->DDR paths, as well as CPU<->SLAVE_DISPLAY_CFG. The former ones share how their values are calculated, but the latter one has static predefines spanning all SoCs. In preparation for supporting the CPU<->SLAVE_DISPLAY_CFG path, rename the path-related struct members to include "mdp_". Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 10 +++++----- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 12 ++++++------ drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 4 ++-- 3 files changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c index 1d9d83d7b99e..349c6cb3301d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c @@ -230,18 +230,18 @@ static int _dpu_core_perf_crtc_update_bus(struct dpu_kms *kms, DRM_DEBUG_ATOMIC("crtc=%d bw=%llu paths:%d\n", tmp_crtc->base.id, - dpu_cstate->new_perf.bw_ctl, kms->num_paths); + dpu_cstate->new_perf.bw_ctl, kms->num_mdp_paths); } } - if (!kms->num_paths) + if (!kms->num_mdp_paths) return 0; avg_bw = perf.bw_ctl; - do_div(avg_bw, (kms->num_paths * 1000)); /*Bps_to_icc*/ + do_div(avg_bw, (kms->num_mdp_paths * 1000)); /*Bps_to_icc*/ - for (i = 0; i < kms->num_paths; i++) - icc_set_bw(kms->path[i], avg_bw, perf.max_per_pipe_ib); + for (i = 0; i < kms->num_mdp_paths; i++) + icc_set_bw(kms->mdp_path[i], avg_bw, perf.max_per_pipe_ib); return ret; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 0e7a68714e9e..dd6c1c40ab9e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -397,12 +397,12 @@ static int dpu_kms_parse_data_bus_icc_path(struct dpu_kms *dpu_kms) if (IS_ERR_OR_NULL(path0)) return PTR_ERR_OR_ZERO(path0); - dpu_kms->path[0] = path0; - dpu_kms->num_paths = 1; + dpu_kms->mdp_path[0] = path0; + dpu_kms->num_mdp_paths = 1; if (!IS_ERR_OR_NULL(path1)) { - dpu_kms->path[1] = path1; - dpu_kms->num_paths++; + dpu_kms->mdp_path[1] = path1; + dpu_kms->num_mdp_paths++; } return 0; } @@ -1238,8 +1238,8 @@ static int __maybe_unused dpu_runtime_suspend(struct device *dev) dev_pm_opp_set_rate(dev, 0); clk_bulk_disable_unprepare(dpu_kms->num_clocks, dpu_kms->clocks); - for (i = 0; i < dpu_kms->num_paths; i++) - icc_set_bw(dpu_kms->path[i], 0, 0); + for (i = 0; i < dpu_kms->num_mdp_paths; i++) + icc_set_bw(dpu_kms->mdp_path[i], 0, 0); return 0; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index aca39a4689f4..d5d9bec90705 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -109,8 +109,8 @@ struct dpu_kms { * when disabled. */ atomic_t bandwidth_ref; - struct icc_path *path[2]; - u32 num_paths; + struct icc_path *mdp_path[2]; + u32 num_mdp_paths; }; struct vsync_info { From patchwork Tue Apr 18 12:10:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 84822 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2799393vqo; Tue, 18 Apr 2023 05:17:10 -0700 (PDT) X-Google-Smtp-Source: AKy350bgwcz6GP518etFo/Ch3nbYK3KYeyR/MkQJP4TCFJYxCdP3UhcJ1MyKAO9R1qR2ur5Bp1+K X-Received: by 2002:a17:90a:f0c6:b0:247:6ec8:7e93 with SMTP id fa6-20020a17090af0c600b002476ec87e93mr1747136pjb.33.1681820229896; Tue, 18 Apr 2023 05:17:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681820229; cv=none; d=google.com; s=arc-20160816; b=p3zAA1O7PHLUwPRPMtCn2+Rb1L+gALQdDPg5oa6w/7xhx4Vy7UcuurVkSVgaMYJJku I2crUlRaw2GQAL9H1eCk5QM16w0IEYsRww0Brwd3yL8YiLm9es+0Pu7tUyJyMkgJSSGb 4vtpo4Mb8y+Bbs5xpgpfnuDer3pUA2YDFF+o2kweZIhyXWz4iwfaHuNwijwf8sVHCbQ2 9oBTiK+z02iCr5S24l/Kbm690bBvhQeg5BuazrwMCngJdVcL5dXyF0pK0u96wRVofL6Y /nrX0yHzKpPlgI60EM26Z4Pz3H6jA/AC4gqFWiK6O5XgszBki04AviJEEnZgoGVtf0fh pauA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=hUGnN7QmHFXWvkEalaWeWFmgMZnzSnPU7k2aFfVSknQ=; b=YCKu6Lm5iz3nCb64By7wpAA5H/11aKhQtwrjMeWoZBBVEuiQIC2w8wsopijkxrAHPv DXL5XphEqcOOU4lZstHUB4lZyNJgcHy6Y3rmT7x+fMfbkRLX53GEGlI0RsxpkcPcnlkk cHAmK2aK2NL+1pnWLVWGLfLC9rsBERER/x8bzClbejWL827n6m0ZSr5blGoSyETyVvfH CFk5BHXFsV4aP2NdR9i+g0JJ2UhvTF+R5O0MolbxInvg/oLmpDhij9YJfqtkjTTFp25o MjHQyI/pgc/4ASrYsbXpQB3f0tKRDmMwtI67wKiKbV3bwLJwYBnbmiWwOl1tqaybO0Js g8TA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=plwhb253; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.29.144]) by smtp.gmail.com with ESMTPSA id q17-20020a19a411000000b004d86808fd33sm2365895lfc.15.2023.04.18.05.11.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 05:11:02 -0700 (PDT) From: Konrad Dybcio Date: Tue, 18 Apr 2023 14:10:58 +0200 Subject: [PATCH v2 3/5] drm/msm/mdss: Rename path references to mdp_path MIME-Version: 1.0 Message-Id: <20230417-topic-dpu_regbus-v2-3-91a66d04898e@linaro.org> References: <20230417-topic-dpu_regbus-v2-0-91a66d04898e@linaro.org> In-Reply-To: <20230417-topic-dpu_regbus-v2-0-91a66d04898e@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681819856; l=2175; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=mFT0UyX9LhxCNCpprLZW/XLO+LLNqKMZSGZE8MZeFUU=; b=GK2A60TzVMQEAOzKUYKUR6rw8jItcwySKTJju9xkPZNGM9M1lTpTARcjPYfRz6gWTY1sXayeI4j8 7oyqnIXZBh56Seh+aoobZZkMDYr+Pqf4TEujHIxmbrCBrmvszl0p X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763516329255725003?= X-GMAIL-MSGID: =?utf-8?q?1763516329255725003?= The DPU1 driver needs to handle all MDPn<->DDR paths, as well as CPU<->SLAVE_DISPLAY_CFG. The former ones share how their values are calculated, but the latter one has static predefines spanning all SoCs. In preparation for supporting the CPU<->SLAVE_DISPLAY_CFG path, rename the path-related struct members to include "mdp_". Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_mdss.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index e8c93731aaa1..9e2ce7f22677 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -48,8 +48,8 @@ struct msm_mdss { struct irq_domain *domain; } irq_controller; const struct msm_mdss_data *mdss_data; - struct icc_path *path[2]; - u32 num_paths; + struct icc_path *mdp_path[2]; + u32 num_mdp_paths; }; static int msm_mdss_parse_data_bus_icc_path(struct device *dev, @@ -62,13 +62,13 @@ static int msm_mdss_parse_data_bus_icc_path(struct device *dev, if (IS_ERR_OR_NULL(path0)) return PTR_ERR_OR_ZERO(path0); - msm_mdss->path[0] = path0; - msm_mdss->num_paths = 1; + msm_mdss->mdp_path[0] = path0; + msm_mdss->num_mdp_paths = 1; path1 = of_icc_get(dev, "mdp1-mem"); if (!IS_ERR_OR_NULL(path1)) { - msm_mdss->path[1] = path1; - msm_mdss->num_paths++; + msm_mdss->mdp_path[1] = path1; + msm_mdss->num_mdp_paths++; } return 0; @@ -79,16 +79,16 @@ static void msm_mdss_put_icc_path(void *data) struct msm_mdss *msm_mdss = data; int i; - for (i = 0; i < msm_mdss->num_paths; i++) - icc_put(msm_mdss->path[i]); + for (i = 0; i < msm_mdss->num_mdp_paths; i++) + icc_put(msm_mdss->mdp_path[i]); } static void msm_mdss_icc_request_bw(struct msm_mdss *msm_mdss, unsigned long bw) { int i; - for (i = 0; i < msm_mdss->num_paths; i++) - icc_set_bw(msm_mdss->path[i], 0, Bps_to_icc(bw)); + for (i = 0; i < msm_mdss->num_mdp_paths; i++) + icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(bw)); } static void msm_mdss_irq(struct irq_desc *desc) From patchwork Tue Apr 18 12:10:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 84821 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2797659vqo; Tue, 18 Apr 2023 05:14:44 -0700 (PDT) X-Google-Smtp-Source: AKy350b+O5M3Pn6HAz5IQu9z+D9cA34F3eQI7T3DctwptqNYJQnz51FfER5LrRdfF0H5jrn5BQVc X-Received: by 2002:a17:90b:4a0d:b0:237:97a3:1479 with SMTP id kk13-20020a17090b4a0d00b0023797a31479mr1739660pjb.28.1681820083809; Tue, 18 Apr 2023 05:14:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681820083; cv=none; d=google.com; s=arc-20160816; b=eJoOQwICLXWkIaE5rxgRr3VAW67/y8cm9GU0wIk1YKcOaT7DWVhLzW9aqJCgSo2CGy YsBLEz2vzER8oDcYpbLuildmqHVLLv9Gqao/aiPWCYXubAa+WuIDcyQggABYOvTtdz9t EJKYazkNhk40rPA3GMovOM7vtv/v1FPuSzDQeY/QTelYHsS10Yjfj+AlGRRQiTlOsgT+ Wa5ECxsWYGX9AlTnDBH1DDopoKuYkATplNVg3vQ8hywjx6hg2RqTnUMdnkgQx8rB0neN vuqvQVZLp26YQimMesUmWcaaPPoQEe5egogJS0RPUlZhYOZ6fapfJJIoBTb3GdeWa3up Bccw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=PbVhusCEghNKEPZ8TLDEdqw82MnqWQVPyy1y462DY9k=; b=MHIAJaYql2meA/XLQQxoykWsXTlw33KGDMY43RGnwoyMR2SCNzvwt4ntu1jatencCi jPG47c8QWXg25ePSYOQuCA7EqpHC3dM8qE6xvnuJF8/KR2btmqmXIMzk9PWJMPY8gNR5 CptVTdN+dKc1mLLi0qlO28G5YjkPISJlDj/XFRpwoTqQFs/QC8xvE3/91+V8BnZCq/VI 1zU8Bx2eok/0TEyWoaoQxwhPXllExUfgemqjr1tl21T8mv50unkLp+2PSG8fqYBE+RLr xXxo8UP1gwCmm3WgPgDxGCH855un8kYZcPQdkOIzhfCUh7xU9xVUsGnvsMj2yIAeWh6M svHA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="swJ6/Exu"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.29.144]) by smtp.gmail.com with ESMTPSA id q17-20020a19a411000000b004d86808fd33sm2365895lfc.15.2023.04.18.05.11.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 05:11:03 -0700 (PDT) From: Konrad Dybcio Date: Tue, 18 Apr 2023 14:10:59 +0200 Subject: [PATCH v2 4/5] drm/msm/mdss: Handle the reg bus ICC path MIME-Version: 1.0 Message-Id: <20230417-topic-dpu_regbus-v2-4-91a66d04898e@linaro.org> References: <20230417-topic-dpu_regbus-v2-0-91a66d04898e@linaro.org> In-Reply-To: <20230417-topic-dpu_regbus-v2-0-91a66d04898e@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681819856; l=3137; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=wX+gJPCe8UmLoFyI2GJLXSE1t0Mv12xmqDSsK2E8jZI=; b=Fl2losD0yxtKUBCjTBabIjaes/wJD0CNKIE43B+HBU9fLD5PGoyshXp3GJ8ZfODxRfctdbQnAGhz EDCNeSo8CFhnc35D2jEK9RnI6hh2Gf2ys+xxVtGeDWOXIMH07UQL X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763516176106162568?= X-GMAIL-MSGID: =?utf-8?q?1763516176106162568?= Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's another path that needs to be handled to ensure MDSS functions properly, namely the "reg bus", a.k.a the CPU-MDSS interconnect. Gating that path may have a variety of effects.. from none to otherwise inexplicable DSI timeouts.. On the MDSS side, we only have to ensure that it's on at what Qualcomm downstream calls "77 MHz", a.k.a 76.8 Mbps and turn it off at suspend. To achieve that, make msm_mdss_icc_request_bw() accept a boolean to indicate whether we want the busses to be on or off, as this function's only use is to vote for minimum or no bandwidth at all. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/msm_mdss.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 9e2ce7f22677..4d126d20d661 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -50,6 +50,7 @@ struct msm_mdss { const struct msm_mdss_data *mdss_data; struct icc_path *mdp_path[2]; u32 num_mdp_paths; + struct icc_path *reg_bus_path; }; static int msm_mdss_parse_data_bus_icc_path(struct device *dev, @@ -57,6 +58,7 @@ static int msm_mdss_parse_data_bus_icc_path(struct device *dev, { struct icc_path *path0; struct icc_path *path1; + struct icc_path *reg_bus_path; path0 = of_icc_get(dev, "mdp0-mem"); if (IS_ERR_OR_NULL(path0)) @@ -71,6 +73,10 @@ static int msm_mdss_parse_data_bus_icc_path(struct device *dev, msm_mdss->num_mdp_paths++; } + reg_bus_path = of_icc_get(dev, "cpu-cfg"); + if (!IS_ERR_OR_NULL(reg_bus_path)) + msm_mdss->reg_bus_path = reg_bus_path; + return 0; } @@ -83,12 +89,15 @@ static void msm_mdss_put_icc_path(void *data) icc_put(msm_mdss->mdp_path[i]); } -static void msm_mdss_icc_request_bw(struct msm_mdss *msm_mdss, unsigned long bw) +static void msm_mdss_icc_request_bw(struct msm_mdss *msm_mdss, bool enable) { int i; for (i = 0; i < msm_mdss->num_mdp_paths; i++) - icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(bw)); + icc_set_bw(msm_mdss->mdp_path[i], 0, enable ? Bps_to_icc(MIN_IB_BW) : 0); + + if (msm_mdss->reg_bus_path) + icc_set_bw(msm_mdss->reg_bus_path, 0, enable ? 76800 : 0); } static void msm_mdss_irq(struct irq_desc *desc) @@ -241,7 +250,7 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) * the interconnect is enabled (non-zero bandwidth). Let's make sure * that the interconnects are at least at a minimum amount. */ - msm_mdss_icc_request_bw(msm_mdss, MIN_IB_BW); + msm_mdss_icc_request_bw(msm_mdss, true); ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks); if (ret) { @@ -289,7 +298,7 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) static int msm_mdss_disable(struct msm_mdss *msm_mdss) { clk_bulk_disable_unprepare(msm_mdss->num_clocks, msm_mdss->clocks); - msm_mdss_icc_request_bw(msm_mdss, 0); + msm_mdss_icc_request_bw(msm_mdss, false); return 0; } From patchwork Tue Apr 18 12:11:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 84823 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2799552vqo; Tue, 18 Apr 2023 05:17:23 -0700 (PDT) X-Google-Smtp-Source: AKy350Z7gzQCFEWHyuR+Ecitr+JK5YoTtRGdxIfvPRvWARtvTzC82ea9NtxeyF+5yzFu6Zn9Fpwj X-Received: by 2002:a05:6a00:1954:b0:63d:38aa:5617 with SMTP id s20-20020a056a00195400b0063d38aa5617mr2716229pfk.6.1681820243111; Tue, 18 Apr 2023 05:17:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681820243; cv=none; d=google.com; s=arc-20160816; b=N3i8Ney/w91AL79XB+CMjPCo7IFvV+mLtrhuttyCze9PJYTxr40JTZ5MuDyBwbp97o XgOtieDWhrJLENegRPkNxoGwJpGxgAQYka7B9C/hbq81q4Vfpy9VQqERDZs7JTf/HFbD sJXT0ECmd+AHAU257vE01q8UZBemkN3FA9NyBIkH9myXrRUZjKB6uoXTwiO0BhbSx5t6 V3nxWPgN1ogtm3/89aYj+AcLyBqRWbuojTBzsCWh5nJNFjSWPAE+08Wj5E/W/CGURfB+ wyuOmInWRE5BjwT0kQGU3laTWwChaerWH9otyq9MZnBebAfz9zl8IFVT9/5HkyArBk9r itYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=jK7H3+ErS03Ewzys5ptfYi+3TCq3sJWDKGWiaxXPxVc=; b=edp75F4X2+pcjeZHGesMq2VV8u2oPu6zi1N1Rshgroml0IE0TeZoE1M/mQqoZOboO1 +S+zCYgUHNyqhv3fQX66OQZPZ0vtGJIIbZAaJuwgNEzgkTUPghl+jcrW2jbuNoEayX7f 0kw3Z8nBiWketNxhwNaod9Lx436o3MmnxTrMLmCigReFmIngkyzkfkjF8Ywp4JgrOd/h BpPeRptOfOXG5QXBjzuPdhoQmLncTW+5XTPdW8Npj76x72WZiM3RvN0PFhZ3Eo319z4C v2/6/fcG7H0W99fQj/zh1Mbqtrrl03IK/flW1K7dj7YtlYpaP6kBxlnuu467VmFr6T0P soww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fuHWc+pU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.29.144]) by smtp.gmail.com with ESMTPSA id q17-20020a19a411000000b004d86808fd33sm2365895lfc.15.2023.04.18.05.11.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 05:11:05 -0700 (PDT) From: Konrad Dybcio Date: Tue, 18 Apr 2023 14:11:00 +0200 Subject: [PATCH v2 5/5] drm/msm/dpu1: Handle the reg bus ICC path MIME-Version: 1.0 Message-Id: <20230417-topic-dpu_regbus-v2-5-91a66d04898e@linaro.org> References: <20230417-topic-dpu_regbus-v2-0-91a66d04898e@linaro.org> In-Reply-To: <20230417-topic-dpu_regbus-v2-0-91a66d04898e@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681819856; l=3473; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=xOdy2dn+gE2SKrybPYSqoFq4IriT0JQjTQ+e3Ay5cn0=; b=h9ntcpkRQz9/aOBujWPi2GBuMqSjHjzJl4e3f8Ec2wwZlXLEV4LprmN69VRjW49s9bxj9Fi/LWe0 LEWJnLoPDtmj5vBJezWgfnSaCTM6RowO4Lqti71GkxnGl0OFOQI+ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763516343414784618?= X-GMAIL-MSGID: =?utf-8?q?1763516343414784618?= Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's another path that needs to be handled to ensure MDSS functions properly, namely the "reg bus", a.k.a the CPU-MDSS interconnect. Gating that path may have a variety of effects.. from none to otherwise inexplicable DSI timeouts.. On the DPU side, we need to keep the bus alive. The vendor driver kickstarts it to max (300Mbps) throughput on first commit, but in exchange for some battery life in rare DPU-enabled-panel-disabled usecases, we can request it at DPU init and gate it at suspend. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 22 ++++++++++++++++++++-- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 + 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index dd6c1c40ab9e..5e1ed338114d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -384,15 +384,17 @@ static int dpu_kms_global_obj_init(struct dpu_kms *dpu_kms) return 0; } -static int dpu_kms_parse_data_bus_icc_path(struct dpu_kms *dpu_kms) +static int dpu_kms_parse_icc_paths(struct dpu_kms *dpu_kms) { struct icc_path *path0; struct icc_path *path1; + struct icc_path *reg_bus_path; struct drm_device *dev = dpu_kms->dev; struct device *dpu_dev = dev->dev; path0 = msm_icc_get(dpu_dev, "mdp0-mem"); path1 = msm_icc_get(dpu_dev, "mdp1-mem"); + reg_bus_path = msm_icc_get(dpu_dev, "cpu-cfg"); if (IS_ERR_OR_NULL(path0)) return PTR_ERR_OR_ZERO(path0); @@ -404,6 +406,10 @@ static int dpu_kms_parse_data_bus_icc_path(struct dpu_kms *dpu_kms) dpu_kms->mdp_path[1] = path1; dpu_kms->num_mdp_paths++; } + + if (!IS_ERR_OR_NULL(reg_bus_path)) + dpu_kms->reg_bus_path = reg_bus_path; + return 0; } @@ -1039,7 +1045,7 @@ static int dpu_kms_hw_init(struct msm_kms *kms) DPU_DEBUG("REG_DMA is not defined"); } - dpu_kms_parse_data_bus_icc_path(dpu_kms); + dpu_kms_parse_icc_paths(dpu_kms); rc = pm_runtime_resume_and_get(&dpu_kms->pdev->dev); if (rc < 0) @@ -1241,6 +1247,9 @@ static int __maybe_unused dpu_runtime_suspend(struct device *dev) for (i = 0; i < dpu_kms->num_mdp_paths; i++) icc_set_bw(dpu_kms->mdp_path[i], 0, 0); + if (dpu_kms->reg_bus_path) + icc_set_bw(dpu_kms->reg_bus_path, 0, 0); + return 0; } @@ -1261,6 +1270,15 @@ static int __maybe_unused dpu_runtime_resume(struct device *dev) return rc; } + /* + * The vendor driver supports setting 76.8 / 150 / 300 MBps on this + * path, but it seems to go for the highest level when display output + * is enabled and zero otherwise. For simplicity, we can assume that + * DPU being enabled and running implies that. + */ + if (dpu_kms->reg_bus_path) + icc_set_bw(dpu_kms->reg_bus_path, 0, MBps_to_icc(300)); + dpu_vbif_init_memtypes(dpu_kms); drm_for_each_encoder(encoder, ddev) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index d5d9bec90705..c332381d58c4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -111,6 +111,7 @@ struct dpu_kms { atomic_t bandwidth_ref; struct icc_path *mdp_path[2]; u32 num_mdp_paths; + struct icc_path *reg_bus_path; }; struct vsync_info {