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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Apr 2023 11:35:36.9684 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8705403d-37c3-4767-d523-08db400107b5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT007.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8323 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763514364172097494?= X-GMAIL-MSGID: =?utf-8?q?1763514364172097494?= From: Sanjay Chandrashekara cpufreq_verify_current_freq checks if the frequency returned by the hardware has a slight delta with the valid frequency value last set and returns "policy->cur" if the delta is within "1 MHz". In the comparison, "policy->cur" is in "kHz" but it's compared against HZ_PER_MHZ. So, the comparison range becomes "1 GHz". Fix this by comparing against KHZ_PER_MHZ instead of HZ_PER_MHZ. Fixes: f55ae08c8987 ("cpufreq: Avoid unnecessary frequency updates due to mismatch") Signed-off-by: Sanjay Chandrashekara [ sumit gupta: Commit message update ] Signed-off-by: Sumit Gupta --- drivers/cpufreq/cpufreq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c index 8b0509f89f1b..6b52ebe5a890 100644 --- a/drivers/cpufreq/cpufreq.c +++ b/drivers/cpufreq/cpufreq.c @@ -1732,7 +1732,7 @@ static unsigned int cpufreq_verify_current_freq(struct cpufreq_policy *policy, b * MHz. In such cases it is better to avoid getting into * unnecessary frequency updates. */ - if (abs(policy->cur - new_freq) < HZ_PER_MHZ) + if (abs(policy->cur - new_freq) < KHZ_PER_MHZ) return policy->cur; cpufreq_out_of_sync(policy, new_freq); From patchwork Tue Apr 18 11:34:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Gupta X-Patchwork-Id: 84775 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2777113vqo; Tue, 18 Apr 2023 04:42:16 -0700 (PDT) X-Google-Smtp-Source: AKy350bLWbJLXJXKdg7plcylI/exdmqZ8mUYiwtxYx26r3gAO5o+mmw+UxbPUx9WUezYt6GDQPS6 X-Received: by 2002:a17:902:d4c6:b0:1a1:e33f:d567 with SMTP id o6-20020a170902d4c600b001a1e33fd567mr2159056plg.52.1681818135951; Tue, 18 Apr 2023 04:42:15 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1681818135; cv=pass; d=google.com; s=arc-20160816; b=eCUdTrK9MGTGQcN8FagM39oo/qcPYt3IK0BTiTarTj9rgwYor6PXpiG76XtuCmxWhZ sAEKPdur5buoEP6PIx08oGWAnCjNkjC7toqW4OYVSe8q/ABRhw65HXqoWsTYkZdLlq7Z 6JE8y3FXtMWHgO4KmSLlzNc2HRGm0eJV1W6ij09JGuAomelViIWwCKz0ph7BPS4o3Xa6 FF6lpiS4BJoOMhrR5XrIjhnx+HSdT5FTSM/G4+RyTT7od1SOb7/Ss5aPtFFnemZ62opZ 8gyfxHzbfIL3oVd4XJrV1iqRwrPuu0Y9LF/jtX1QvAt6LlUsyRPj9KELOgDskjPNy9oo Gcxg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=+Y653bwi3M5aOq9x8QWV3YqXHIBfbVcGhKhc8M8w/8g=; b=GG09fEP2gibHgXOW00y+TMMQDu6E5dIaocXN3Xte84R+utDeSfjrEtnD+LKVWIWoMX Dw+E5hA8MLHZ6I3WO7IuA7Vztan1Gm9AP12/dDq9DORNq/oBsiuPH+5mkQ+GL5CrrCMJ zsixi6nUFy3p9EqTpD3Pgnec65eOw5YqKpNIBShxIY1oy4aUGlYCaLncs8kaRd6kBfNc qCsZpBniY0l4+9Tb85G2+gmkiWgoOz6sqO8HQOCPAuOgY/TMBWrnqUbRkHPGOuzQG4tK 4kpMgXt7x6LPl+EU+gW4jpDlyHe5m7TMZlWsnaK0XdshlZZwA129MNM0Vu2pPe4qr7Yv EX9g== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b="H/UU0Cta"; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Sumit Gupta --- drivers/cpufreq/cppc_cpufreq.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index 022e3555407c..15c2cbb7a50e 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -43,10 +43,13 @@ static LIST_HEAD(cpu_data_list); static bool boost_supported; +static void cppc_check_hisi_workaround(void); + struct cppc_workaround_oem_info { char oem_id[ACPI_OEM_ID_SIZE + 1]; char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1]; u32 oem_revision; + void (*apply_wa_func)(void); }; static struct cppc_workaround_oem_info wa_info[] = { @@ -54,10 +57,12 @@ static struct cppc_workaround_oem_info wa_info[] = { .oem_id = "HISI ", .oem_table_id = "HIP07 ", .oem_revision = 0, + .apply_wa_func = cppc_check_hisi_workaround, }, { .oem_id = "HISI ", .oem_table_id = "HIP08 ", .oem_revision = 0, + .apply_wa_func = cppc_check_hisi_workaround, } }; @@ -938,6 +943,13 @@ static unsigned int hisi_cppc_cpufreq_get_rate(unsigned int cpu) } static void cppc_check_hisi_workaround(void) +{ + /* Overwrite the get() callback */ + cppc_cpufreq_driver.get = hisi_cppc_cpufreq_get_rate; + fie_disabled = FIE_DISABLED; +} + +static void cppc_apply_workarounds(void) { struct acpi_table_header *tbl; acpi_status status = AE_OK; @@ -951,9 +963,8 @@ static void cppc_check_hisi_workaround(void) if (!memcmp(wa_info[i].oem_id, tbl->oem_id, ACPI_OEM_ID_SIZE) && !memcmp(wa_info[i].oem_table_id, tbl->oem_table_id, ACPI_OEM_TABLE_ID_SIZE) && wa_info[i].oem_revision == tbl->oem_revision) { - /* Overwrite the get() callback */ - cppc_cpufreq_driver.get = hisi_cppc_cpufreq_get_rate; - fie_disabled = FIE_DISABLED; + /* call work around function which matched from the table */ + wa_info[i].apply_wa_func(); break; } } @@ -968,7 +979,7 @@ static int __init cppc_cpufreq_init(void) if (!acpi_cpc_valid()) return -ENODEV; - cppc_check_hisi_workaround(); + cppc_apply_workarounds(); cppc_freq_invariance_init(); populate_efficiency_class(); From patchwork Tue Apr 18 11:34:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Gupta X-Patchwork-Id: 84783 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2779806vqo; Tue, 18 Apr 2023 04:47:28 -0700 (PDT) X-Google-Smtp-Source: AKy350Z6x06LxeJGAaoW8kqXuQ07eMdTFkbScRq4v614xhlwflRqTgVzg+FrFI8tBzNAN586wThl X-Received: by 2002:a17:902:e5c1:b0:1a5:27d2:b6de with SMTP id u1-20020a170902e5c100b001a527d2b6demr2384587plf.3.1681818448294; Tue, 18 Apr 2023 04:47:28 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1681818448; cv=pass; d=google.com; s=arc-20160816; b=wDiAbnEJUJVQSygx9af/GSw1qT6a7ffdRuNGyCHoANJN8ql8oAWy9UclejIVmO/+93 kLpxd7EZ03UHep705Z1jQmWcK2iKmAR0rpzK8Qx2TUDE/R/Tg7BXu+Zwvthw86Ubvcwv k7kv9kW7aV+30l7hFaskVoPk7vdvezwCbGHPcKeUFC9r9GzbGNerPuUSIvM2czaJHOSD 1+LLcWieZBF87eROqNEYBS8qGjLou9/O8Yt1c0DbzkBCQiRlZuk002kO3AoDqf4jel6k qxmdYX4OanBv67sNwzRWJFnesfrFPeN0uf+9ALesUOC1G8IH5uxCopO1sb+GmgaCNTjq JUNg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=9k+bEkt5RDqztAdxzqxHIwHzJm6hMa7GABcVPzZ3aBI=; b=wLMcH/hnyBi6V3/5gJXvv4iMwTqYlYszj8oQQ3O0Hd+0aRCTBOMfCwL1XTbXxZYXlr BZbg9Ubx9y96ztJxEuKxLyDTqEKpaWR3ao3i/W+ZI3vdx0wolOpuDlSdhtwYW/AQ1Oy1 nAyZqa5oh4yHaWKWWApcJkaJwW2O1t11bpc0OwLSzgA1cjaxBmBqyZSDJctN0ZpGfTYe zz9khBTbWknfXuz+s5oGeyIukuiq99o8smDa10Idzu80GFweHMn28E3lASE/fm05Vyqn 8I82MOR9AQtdT/ckWj3F0VVIYql1ktVAD6RVU8wZc/QdumEDzq4ayF/I7ahjJHVT5l7h 8mBw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=Uaq9CLrR; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Apr 2023 11:36:05.9007 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9f8ab61c-bcb5-4082-8f5c-08db400118f4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT050.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7677 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763514461215470837?= X-GMAIL-MSGID: =?utf-8?q?1763514461215470837?= Export arm_smccc_get_soc_id_version() function which is needed in CPPC_CPUFREQ to check and apply workaround for Tegra241 SoC. Also, exporting arm_smccc_get_soc_id_revision() function as it might be needed in future. Signed-off-by: Sumit Gupta --- drivers/firmware/smccc/smccc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/firmware/smccc/smccc.c b/drivers/firmware/smccc/smccc.c index db818f9dcb8e..b4224da46988 100644 --- a/drivers/firmware/smccc/smccc.c +++ b/drivers/firmware/smccc/smccc.c @@ -64,11 +64,13 @@ s32 arm_smccc_get_soc_id_version(void) { return smccc_soc_id_version; } +EXPORT_SYMBOL_GPL(arm_smccc_get_soc_id_version); s32 arm_smccc_get_soc_id_revision(void) { return smccc_soc_id_revision; } +EXPORT_SYMBOL_GPL(arm_smccc_get_soc_id_revision); static int __init smccc_devices_init(void) { From patchwork Tue Apr 18 11:34:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Gupta X-Patchwork-Id: 84782 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2779625vqo; Tue, 18 Apr 2023 04:47:07 -0700 (PDT) X-Google-Smtp-Source: AKy350bVbu1jlBtSHvqWX8OO2xRO0t3LIecO06hYL5e7qKbrshXle0ouuFMHs+NKXz+QwIXLD6vx X-Received: by 2002:a05:6a20:2591:b0:ef:1807:2df1 with SMTP id k17-20020a056a20259100b000ef18072df1mr11124819pzd.10.1681818427042; Tue, 18 Apr 2023 04:47:07 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1681818427; cv=pass; d=google.com; s=arc-20160816; b=IHfEZbb75gEIoguQsc9wbU/xLvf3G7g4rdAnhjT5C5ahXFhuQfmPCMkMTzMF081+hS VzwkT2SmViVm47yRh5dvbkfCzxfBzciKeKHMjqkSMg/Bk2G4P6zGLIKEZTn9aRyg/K+B O+AmrkdOlb1yxK8SmrlalPbnXRtFT5Ry/sdUHiwXeNDsgYdQPslF9499cfFdFdRTC1Oq E4T/JYLI0fOo5Sbv/uUDRdmEcFDGVe2mRYXYbm15eg9dMsrdc5qD6cosJhbYw5wpZwwd JQI90NZTB4n7qwh+UmfySN3IY5qSGy2sw5uPjCGOMzCmn1KsRLMvWU5C6QESXrxoDehM bCXA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=5ykCwYzo+l/9NAsygK+a1+QKJV6mGzFqPf5shfdBEvo=; b=oqxIHkglh8eO0BdMKyatblXWo0XTzVdpuntVASHsoZim7ikaPOi3ecvbzn2Fdiswaw 0m9w1fh31b/UbEWaY+qSRQOcPeBih0jmrxqQWdJcUueF2MyxS+BriaJQvM5DwKoSfzJ8 yEaqxZS5paVEQMYY797xy+9Tj+6gJL7pq2bJ+AyQx4jE7X3Lq30kEyp7pIepRD3pvXWL 923rCWfvNnMSkdYfB2DRteKXBxwSMx512fi2x5MFm9DYQkVmIl1eRSRJU19TCQQU7xRO EVczVTtXch0pOpubjmLWd9AX37gA0zaxiR03rRSD3w6tUTW2V+rDzTFH+uHOVvYOSQ8F hngw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=m7uMPR8d; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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For example reference counter may increment by '0x20' every '32' periods of ARM periphclk. This quantization of the reference counter is a source of error when reconstructing the frequency from the AMU counter data. To fix, increase the observation time interval so the error percentage becomes less. Signed-off-by: Sumit Gupta --- drivers/cpufreq/cppc_cpufreq.c | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index 15c2cbb7a50e..5e6a132a525e 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -43,12 +43,17 @@ static LIST_HEAD(cpu_data_list); static bool boost_supported; +/* default 2usec delay between sampling */ +static unsigned int sampling_delay_us = 2; + static void cppc_check_hisi_workaround(void); +static void cppc_nvidia_workaround(void); struct cppc_workaround_oem_info { char oem_id[ACPI_OEM_ID_SIZE + 1]; char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1]; u32 oem_revision; + u32 smcc_soc_id; void (*apply_wa_func)(void); }; @@ -63,6 +68,10 @@ static struct cppc_workaround_oem_info wa_info[] = { .oem_table_id = "HIP08 ", .oem_revision = 0, .apply_wa_func = cppc_check_hisi_workaround, + }, { + .oem_id = "NVIDIA", + .smcc_soc_id = 0x036b0241, /* JEP106 code for NVIDIA T241 chip (036b:0241) */ + .apply_wa_func = cppc_nvidia_workaround, } }; @@ -856,7 +865,7 @@ static unsigned int cppc_cpufreq_get_rate(unsigned int cpu) if (ret) return ret; - udelay(2); /* 2usec delay between sampling */ + udelay(sampling_delay_us); ret = cppc_get_perf_ctrs(cpu, &fb_ctrs_t1); if (ret) @@ -942,6 +951,11 @@ static unsigned int hisi_cppc_cpufreq_get_rate(unsigned int cpu) return cppc_cpufreq_perf_to_khz(cpu_data, desired_perf); } +static void cppc_nvidia_workaround(void) +{ + sampling_delay_us = 25; +} + static void cppc_check_hisi_workaround(void) { /* Overwrite the get() callback */ @@ -953,8 +967,21 @@ static void cppc_apply_workarounds(void) { struct acpi_table_header *tbl; acpi_status status = AE_OK; + s32 soc_id; int i; +#ifdef CONFIG_HAVE_ARM_SMCCC_DISCOVERY + for (i = 0; i < ARRAY_SIZE(wa_info); i++) { + if (wa_info[i].smcc_soc_id) { + soc_id = arm_smccc_get_soc_id_version(); + if (wa_info[i].smcc_soc_id == soc_id) { + wa_info[i].apply_wa_func(); + return; + } + } + } +#endif + status = acpi_get_table(ACPI_SIG_PCCT, 0, &tbl); if (ACPI_FAILURE(status) || !tbl) return; From patchwork Tue Apr 18 11:34:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Gupta X-Patchwork-Id: 84778 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2777952vqo; Tue, 18 Apr 2023 04:43:58 -0700 (PDT) X-Google-Smtp-Source: AKy350bA6nsl548OnTIvjIwOd+hR7gpcbS7YK679l2MMt5FWmdVrmk7T+JCouoLWp5BUH9ok7vOa X-Received: by 2002:a05:6a00:1744:b0:63a:d2e4:cc35 with SMTP id j4-20020a056a00174400b0063ad2e4cc35mr26362818pfc.31.1681818238496; Tue, 18 Apr 2023 04:43:58 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1681818238; cv=pass; d=google.com; s=arc-20160816; b=cRsnlvE29aT0JMC14vc2QMVg1y1b7fC7+auajTfmLyvWhpMPaSEmUDpkXnKDi4/CBM 5rJplG2mJ/9ZTbUq1aK7hfpWh9vZXhWe/obxaZrp03A60Slaqs9H12MuZg4Ngk6YLbwe WqgSOE6v0MPjcXjhm0F9cdwY/heIKG6GVPfHGILkK6mSR+gLKTrzJrkUXHjBwMsoQC3f As4OFIicdcuh1s/sBoqO/YceWD1OBqOOE4+chbRT+keDoee46FTZUx/1FinMr26BxdHb BvBMAq9ylAF7IiJ9dbYiBaNcBPX7HDsD6AVaiZk+6y2uKChZ8uF0qTayyd+1EoF0wlFS CemA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=/rahqSi0lxKjo4ecE7XdMLzWetALNSJxu0JOZbNFBoU=; b=rRe3e9TyTOUjjvw5yTElrQMY5AGGUj0D4fNSXOCvCjCnGatU7ftTY0AbukDUvG3Ugx Lm/5ZGUtd7rOnEFp4ZKHUMHiCrx/kYgQs0nu6CBpxzeqr5I1tU5YN3xqRFQFkDdsxkv8 V2w6Llkpfir1Cdr1t3BGCmVUMKNpDRtqT+o3VHZaYPMa6BHiomsrlDtcCNjzazNKEZcP OPgAcEllExishUnp++IJYYqxc5n+FA56slE56hOTMokRq1QEuhA+ohXQOXaGi8wXzK/Q Ce24Vs7ruTCMZIjQ6lkBE54oqKcatdhf/cXxlluYqcLJOa8dTZk+3YB5GADjsNsC7RQq 2oJA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=DNNYZXYb; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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If AMU is available, then for re-constructing the current CPU freq from its counters, queue work on target CPU to read the counters in a single call instead of reading them in separate smp calls. Signed-off-by: Sumit Gupta --- arch/arm64/kernel/cpufeature.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index d9345e9c0226..ec31da7043eb 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1917,6 +1917,7 @@ int get_cpu_with_amu_feat(void) { return cpumask_any(&amu_cpus); } +EXPORT_SYMBOL_GPL(get_cpu_with_amu_feat); static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) { From patchwork Tue Apr 18 11:34:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Gupta X-Patchwork-Id: 84780 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2778919vqo; Tue, 18 Apr 2023 04:45:52 -0700 (PDT) X-Google-Smtp-Source: AKy350aDtyzbAmaES0ROaG1hJZvUAvu3E42kPQ4EuDSYEqT30OgKe2Y698umhH70GdRTf2eJwDqn X-Received: by 2002:a05:6a20:734f:b0:ef:c4f6:9122 with SMTP id v15-20020a056a20734f00b000efc4f69122mr8227713pzc.24.1681818352225; Tue, 18 Apr 2023 04:45:52 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1681818352; cv=pass; d=google.com; s=arc-20160816; b=BAFRt0KQEn0TANL9Khz6IoOwXUtcNWvjbPgXPeb4Fum1hQp/+dmoaGtqJujAn98gRs 34s2r9T8eBxfyQ5VffKUx6l/uRzyJbEQXFxf2Se18HzSlQxbqLGYK/3/1Ud9TGagcEUP UyPy5XbZwoyFQnKt1Spm4T0WSy6q1Ve60ivcAxLWeXQ8V9Mw3CbjWcrdTThvLz+3qi7s i9PaiuIgbRWEKJLz0szB66qoD5JOVW/24yHzHlnQhlEvNU72ZjG+aRNixdA27H9AjV/i 57HTv0DzuOb5KnLSXr+hcbtjE4P7sPA28WJJXjFsD/wkErYW3e3y3x9FkUFTJI4b1jzd BMnw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=bUt+6/5XC1OaGh7iuH+Z/LJrw1UWkzVE+H6FlLwW0qM=; b=Lsuef730K0ofN931k/Rs5l2la+E8Ja2olXqu98GdtKPolXIIC7WaSGzQkH6xu+mQmF A+1KHkg83ovQG2Q2WJdpO5KrKDslLWgxojHMh3e48qf7JOtoaRukkJ79Z4kkNJGW1odr TzaoMm5rRZDzbL+DStS5Fi2Efb3LHlH3pGCnKwVZnlJQOWE5FMtF+UeSPzLR9ohfzx9d d4b4bQ6oyOefgW/0jY2zkX+QNwHYcdv696CjiOiAwGsL7DhqD/6beHdUlwHV0dAmF9AS 8+6zn4qmOUGlLvNXe12EPB4wP1FIdBl0/Bt8Wu39k2UUjdxGSGglTjmyLLNwdhgmSoOo 2a/g== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b="fMSo8o/B"; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Apr 2023 11:36:23.2191 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9409800e-d1b8-4413-9990-08db4001233d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT098.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5767 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763514360857538411?= X-GMAIL-MSGID: =?utf-8?q?1763514360857538411?= ARM cores which implement the Activity Monitor Unit (AMU) use Functional Fixed Hardware (FFH) to map AMU counters to Delivered_Counter and Reference_Counter registers. Each sysreg is read separately with a smp_call_function_single call. So, total four IPI's are used, one per register. Due to this, the AMU's core counter and constant counter sampling can happen at a non-consistent time interval if an IPI is handled late. This results in unstable frequency value from "cpuinfo_cur_req" node sometimes. To fix, queue work on target CPU to read all counters synchronously in sequence. This helps to remove the inter-IPI latency and make sure that both the counters are sampled at a close time interval. Without this change we observed that the re-generated value of CPU Frequency from AMU counters sometimes deviates by ~25% as the counters are read at non-determenistic time. Currently, kept the change specific to Tegra241. It can be applied to other SoC's having AMU if same issue is observed. Signed-off-by: Sumit Gupta --- drivers/cpufreq/cppc_cpufreq.c | 53 +++++++++++++++++++++++++++------- 1 file changed, 43 insertions(+), 10 deletions(-) diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index 5e6a132a525e..52b93ac6225e 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -46,6 +46,8 @@ static bool boost_supported; /* default 2usec delay between sampling */ static unsigned int sampling_delay_us = 2; +static bool get_rate_use_wq; + static void cppc_check_hisi_workaround(void); static void cppc_nvidia_workaround(void); @@ -99,6 +101,12 @@ struct cppc_freq_invariance { static DEFINE_PER_CPU(struct cppc_freq_invariance, cppc_freq_inv); static struct kthread_worker *kworker_fie; +struct feedback_ctrs { + u32 cpu; + struct cppc_perf_fb_ctrs fb_ctrs_t0; + struct cppc_perf_fb_ctrs fb_ctrs_t1; +}; + static unsigned int hisi_cppc_cpufreq_get_rate(unsigned int cpu); static int cppc_perf_from_fbctrs(struct cppc_cpudata *cpu_data, struct cppc_perf_fb_ctrs *fb_ctrs_t0, @@ -851,28 +859,44 @@ static int cppc_perf_from_fbctrs(struct cppc_cpudata *cpu_data, return (reference_perf * delta_delivered) / delta_reference; } +static int cppc_get_perf_ctrs_sync(void *fb_ctrs) +{ + struct feedback_ctrs *ctrs = fb_ctrs; + int ret; + + ret = cppc_get_perf_ctrs(ctrs->cpu, &(ctrs->fb_ctrs_t0)); + if (ret) + return ret; + + udelay(sampling_delay_us); + + ret = cppc_get_perf_ctrs(ctrs->cpu, &(ctrs->fb_ctrs_t1)); + if (ret) + return ret; + + return ret; +} + static unsigned int cppc_cpufreq_get_rate(unsigned int cpu) { - struct cppc_perf_fb_ctrs fb_ctrs_t0 = {0}, fb_ctrs_t1 = {0}; struct cpufreq_policy *policy = cpufreq_cpu_get(cpu); struct cppc_cpudata *cpu_data = policy->driver_data; + struct feedback_ctrs fb_ctrs = {0}; u64 delivered_perf; int ret; cpufreq_cpu_put(policy); + fb_ctrs.cpu = cpu; - ret = cppc_get_perf_ctrs(cpu, &fb_ctrs_t0); - if (ret) - return ret; - - udelay(sampling_delay_us); - - ret = cppc_get_perf_ctrs(cpu, &fb_ctrs_t1); + if (get_rate_use_wq) + ret = smp_call_on_cpu(cpu, cppc_get_perf_ctrs_sync, &fb_ctrs, false); + else + ret = cppc_get_perf_ctrs_sync(&fb_ctrs); if (ret) return ret; - delivered_perf = cppc_perf_from_fbctrs(cpu_data, &fb_ctrs_t0, - &fb_ctrs_t1); + delivered_perf = cppc_perf_from_fbctrs(cpu_data, &(fb_ctrs.fb_ctrs_t0), + &(fb_ctrs.fb_ctrs_t1)); return cppc_cpufreq_perf_to_khz(cpu_data, delivered_perf); } @@ -953,7 +977,16 @@ static unsigned int hisi_cppc_cpufreq_get_rate(unsigned int cpu) static void cppc_nvidia_workaround(void) { + int cpu; + sampling_delay_us = 25; + +#ifdef CONFIG_ARM64_AMU_EXTN + cpu = get_cpu_with_amu_feat(); + + if (cpu < nr_cpu_ids) + get_rate_use_wq = true; +#endif } static void cppc_check_hisi_workaround(void)