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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id m13-20020a50ef0d000000b0050493f364b9si11746807eds.440.2023.04.17.23.58.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Apr 2023 23:58:04 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=lDxwg2Jl; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C5D8A3858C27 for ; Tue, 18 Apr 2023 06:58:02 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C5D8A3858C27 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1681801082; bh=WVJox04qSLpTX8dq+7IFmSC2olTSE8/V+5Eq6pvVMTM=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=lDxwg2Jl9QbT6/s8rdGlXD4A/LzcLxGy4JzXsiHILeOtbfvR8deF+7pFzFOHPJ4KT x1yz0Xp+OgQpgQPeOEQ5gmkHyCE09NjqgVOQPCAZ5am09mBMZ7Dv1uvXCxLoKQOXVP n77UqvdzweLBOZc6yVG/6IrNuTvGRrQYdu2DkmTo= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by sourceware.org (Postfix) with ESMTPS id 2CF3E3858D1E for ; Tue, 18 Apr 2023 06:57:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2CF3E3858D1E X-IronPort-AV: E=McAfee;i="6600,9927,10683"; a="329265986" X-IronPort-AV: E=Sophos;i="5.99,206,1677571200"; d="scan'208";a="329265986" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Apr 2023 23:57:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10683"; a="865267838" X-IronPort-AV: E=Sophos;i="5.99,206,1677571200"; d="scan'208";a="865267838" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga005.jf.intel.com with ESMTP; 17 Apr 2023 23:57:15 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 50CF410081C8; Tue, 18 Apr 2023 14:57:14 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com Subject: [PATCH] i386: Use macro to wrap up share builtin exceptions in builtin isa check Date: Tue, 18 Apr 2023 14:55:14 +0800 Message-Id: <20230418065514.4003416-1-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UPPERCASE_50_75 autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Haochen Jiang via Gcc-patches From: "Jiang, Haochen" Reply-To: Haochen Jiang Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763496253760043552?= X-GMAIL-MSGID: =?utf-8?q?1763496253760043552?= Hi all, Currently in i386, we have several ISAs share builtin between each other which is handled in ix86_check_builtin_isa_match with if condition clauses. The patterns for these clauses are quite similar so it will be more friendly for developers if we rewrite them as a macro. This patch adds that macro. Tested on x86_64-pc-linux-gnu. Ok for trunk? BRs, Haochen gcc/ChangeLog: * config/i386/i386-expand.cc (ix86_check_builtin_isa_match): Correct wrong comments. Add a new macro SHARE_BUILTIN and refactor the current if clauses to macro. --- gcc/config/i386/i386-expand.cc | 72 ++++++++++++---------------------- 1 file changed, 24 insertions(+), 48 deletions(-) diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index 0d817fc3f3b..54d5dfae677 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -12588,6 +12588,7 @@ ix86_check_builtin_isa_match (unsigned int fcode, HOST_WIDE_INT isa2 = ix86_isa_flags2; HOST_WIDE_INT bisa = ix86_builtins_isa[fcode].isa; HOST_WIDE_INT bisa2 = ix86_builtins_isa[fcode].isa2; + HOST_WIDE_INT tmp_isa = isa, tmp_isa2 = isa2; /* The general case is we require all the ISAs specified in bisa{,2} to be enabled. The exceptions are: @@ -12596,60 +12597,35 @@ ix86_check_builtin_isa_match (unsigned int fcode, OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4 (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL) or OPTION_MASK_ISA2_AVXVNNI - (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512IFMA) or + (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL) or OPTION_MASK_ISA2_AVXIFMA - (OPTION_MASK_ISA_AVXNECONVERT | OPTION_MASK_ISA2_AVX512BF16) or + (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA2_AVX512BF16) or OPTION_MASK_ISA2_AVXNECONVERT where for each such pair it is sufficient if either of the ISAs is enabled, plus if it is ored with other options also those others. OPTION_MASK_ISA_MMX in bisa is satisfied also if TARGET_MMX_WITH_SSE. */ - if (((bisa & (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A)) - == (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A)) - && (isa & (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A)) != 0) - isa |= (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A); - if (((bisa & (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32)) - == (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32)) - && (isa & (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32)) != 0) - isa |= (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32); - - if (((bisa & (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4)) - == (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4)) - && (isa & (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4)) != 0) - isa |= (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4); - - if ((((bisa & (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL)) - == (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL)) - || (bisa2 & OPTION_MASK_ISA2_AVXVNNI) != 0) - && (((isa & (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL)) - == (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL)) - || (isa2 & OPTION_MASK_ISA2_AVXVNNI) != 0)) - { - isa |= OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL; - isa2 |= OPTION_MASK_ISA2_AVXVNNI; - } - - if ((((bisa & (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL)) - == (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL)) - || (bisa2 & OPTION_MASK_ISA2_AVXIFMA) != 0) - && (((isa & (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL)) - == (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL)) - || (isa2 & OPTION_MASK_ISA2_AVXIFMA) != 0)) - { - isa |= OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL; - isa2 |= OPTION_MASK_ISA2_AVXIFMA; - } - - if ((((bisa & OPTION_MASK_ISA_AVX512VL) != 0 - && (bisa2 & OPTION_MASK_ISA2_AVX512BF16) != 0) - && (bisa2 & OPTION_MASK_ISA2_AVXNECONVERT) != 0) - && (((isa & OPTION_MASK_ISA_AVX512VL) != 0 - && (isa2 & OPTION_MASK_ISA2_AVX512BF16) != 0) - || (isa2 & OPTION_MASK_ISA2_AVXNECONVERT) != 0)) - { - isa |= OPTION_MASK_ISA_AVX512VL; - isa2 |= OPTION_MASK_ISA2_AVXNECONVERT | OPTION_MASK_ISA2_AVX512BF16; - } +#define SHARE_BUILTIN(A1, A2, B1, B2) \ + if ((((bisa & (A1)) == (A1) && (bisa2 & (A2)) == (A2)) \ + && ((bisa & (B1)) == (B1) && (bisa2 & (B2)) == (B2))) \ + && (((isa & (A1)) == (A1) && (isa2 & (A2)) == (A2)) \ + || ((isa & (B1)) == (B1) && (isa2 & (B2)) == (B2)))) \ + { \ + tmp_isa |= (A1) | (B1); \ + tmp_isa2 |= (A2) | (B2); \ + } + + SHARE_BUILTIN (OPTION_MASK_ISA_SSE, 0, OPTION_MASK_ISA_3DNOW_A, 0); + SHARE_BUILTIN (OPTION_MASK_ISA_SSE4_2, 0, OPTION_MASK_ISA_CRC32, 0); + SHARE_BUILTIN (OPTION_MASK_ISA_FMA, 0, OPTION_MASK_ISA_FMA4, 0); + SHARE_BUILTIN (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL, 0, 0, + OPTION_MASK_ISA2_AVXVNNI); + SHARE_BUILTIN (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, 0, 0, + OPTION_MASK_ISA2_AVXIFMA); + SHARE_BUILTIN (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512BF16, 0, + OPTION_MASK_ISA2_AVXNECONVERT); + isa = tmp_isa; + isa2 = tmp_isa2; if ((bisa & OPTION_MASK_ISA_MMX) && !TARGET_MMX && TARGET_MMX_WITH_SSE /* __builtin_ia32_maskmovq requires MMX registers. */