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[8.43.85.97]) by mx.google.com with ESMTPS id fi16-20020a1709073ad000b0094f697070f6si3194887ejc.56.2023.04.17.11.38.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Apr 2023 11:38:42 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=nEoUq14K; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 760FD38708DF for ; Mon, 17 Apr 2023 18:37:33 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-yw1-x112b.google.com (mail-yw1-x112b.google.com [IPv6:2607:f8b0:4864:20::112b]) by sourceware.org (Postfix) with ESMTPS id D40A63858C2D for ; Mon, 17 Apr 2023 18:37:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D40A63858C2D Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-yw1-x112b.google.com with SMTP id 00721157ae682-54fc337a650so176550527b3.4 for ; Mon, 17 Apr 2023 11:37:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1681756623; x=1684348623; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=TnFyMkovn1MwpJF5gBhM1rzNKKR2Jo31TJ2blUebek8=; b=nEoUq14KAS9pYU9ItdjkqB262o4JaoK2LQSbiskOT9JqInioRO0fS/6e4mNPBP9d1i vBjhr2uR0Vc28vccqW9giOwX8rObok6G7uSeX1kTH/ZBHUgleWlyQ631XB7eDou/sQEi ot0GlJxDNFOKU/b3Isq3FUWhDxAls2Ls2Azy93oxSLdhLbs7Wy7GF2PWXxVyMZgv+bRH PTeNlyQO3p/TgByK4Rx2aygsxrVhGe+I0rfDckOjT9EFQ9TdNIFTJ8Yvz6RlUAQWZ0ZI Tu6JldCBHFv1eD1yamH3gpJEJOYmvD+/GYx2VlnuSM2ghyPHzdNbKogUuH8flz5PDrRq 0ZVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681756623; x=1684348623; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TnFyMkovn1MwpJF5gBhM1rzNKKR2Jo31TJ2blUebek8=; b=OyeuLh00ktC/BtLZb8eXza2yTwshpHiglDKJUHCr931XGQ2DAP3yoxUsAkR1c4hHFi 0lXcdykPhys0ShWbtK/ztx3GAGUO2jIRRseHI22rhIgU/NEXW8I/1YM1uPIx1qsCD5Bw 2PVy2iCvgUhM9fUr3jBoBMw0Zk1MR7Mw/KbGhQKA1lMbUi5PtMYCmmKTG5FbvWOYDQep WtU/pbf6d9Kl2e8XfRvrqlrsyNWaxkCj2OFICbmr1SDLfxtLVVqaCvlcL6WrR0vFaoWd s7RtSrwpcwnEsLzFLXaZtHeZmXvLbroVOZlyN1UGG29NfWswMIC9lrd5KU/J4Z2Fc2ZS 1iGA== X-Gm-Message-State: AAQBX9c/+2lhDkwK1u4w4mugdbczn7vqOe8268a9Vr+Q7+alFfodRnR9 tbJkJ60I1L48HrMivn8Wka1aUWKZhk+sgsOZThQi2Q== X-Received: by 2002:a0d:eb04:0:b0:54f:6a20:5a19 with SMTP id u4-20020a0deb04000000b0054f6a205a19mr15452380ywe.34.1681756623069; Mon, 17 Apr 2023 11:37:03 -0700 (PDT) Received: from system76-pc.ba.rivosinc.com ([136.57.172.92]) by smtp.gmail.com with ESMTPSA id 66-20020a810645000000b0054f6f65f258sm3278559ywg.16.2023.04.17.11.37.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Apr 2023 11:37:02 -0700 (PDT) From: Michael Collison To: gcc-patches@gcc.gnu.org Subject: [PATCH v4 01/10] RISC-V: Add new predicates and function prototypes Date: Mon, 17 Apr 2023 14:36:52 -0400 Message-Id: <20230417183701.2249183-2-collison@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230417183701.2249183-1-collison@rivosinc.com> References: <20230417183701.2249183-1-collison@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763449737180091185?= X-GMAIL-MSGID: =?utf-8?q?1763449737180091185?= 2023-03-02 Michael Collison Juzhe Zhong * config/riscv/riscv-protos.h (riscv_classify_vlmul_field): New external declaration. (riscv_vector_preferred_simd_mode): Ditto. (riscv_tuple_mode_p): Ditto. (riscv_vector_mask_mode_p): Ditto. (riscv_classify_nf): Ditto. (riscv_vlmul_regsize): Ditto. (riscv_vector_preferred_simd_mode): Ditto. (riscv_vector_get_mask_mode): Ditto. (emit_vlmax_vsetvl): Ditto. (get_mask_policy_no_pred): Ditto. (get_tail_policy_no_pred): Ditto. * config/riscv/riscv-opts.h (riscv_vector_bits_enum): New enum. (riscv_vector_lmul_enum): Ditto. (vlmul_field_enum): Ditto. * config/riscv/riscv-v.cc (emit_vlmax_vsetvl): Remove static scope. * config/riscv/riscv.opt (riscv_vector_lmul): New option -mriscv_vector_lmul. * config/riscv/predicates.md (p_reg_or_const_csr_operand): New predicate. (vector_reg_or_const_dup_operand): Ditto. --- gcc/config/riscv/predicates.md | 13 +++++++++++ gcc/config/riscv/riscv-opts.h | 40 +++++++++++++++++++++++++++++++++ gcc/config/riscv/riscv-protos.h | 14 ++++++++++++ gcc/config/riscv/riscv.opt | 20 +++++++++++++++++ 4 files changed, 87 insertions(+) diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 8654dbc5943..b3f2d622c7b 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -264,6 +264,14 @@ }) ;; Predicates for the V extension. +(define_special_predicate "p_reg_or_const_csr_operand" + (match_code "reg, subreg, const_int") +{ + if (CONST_INT_P (op)) + return satisfies_constraint_K (op); + return GET_MODE (op) == Pmode; +}) + (define_special_predicate "vector_length_operand" (ior (match_operand 0 "pmode_register_operand") (match_operand 0 "const_csr_operand"))) @@ -291,6 +299,11 @@ (and (match_code "const_vector") (match_test "rtx_equal_p (op, riscv_vector::gen_scalar_move_mask (GET_MODE (op)))"))) +(define_predicate "vector_reg_or_const_dup_operand" + (ior (match_operand 0 "register_operand") + (match_test "const_vec_duplicate_p (op) + && !CONST_POLY_INT_P (CONST_VECTOR_ELT (op, 0))"))) + (define_predicate "vector_mask_operand" (ior (match_operand 0 "register_operand") (match_operand 0 "vector_all_trues_mask_operand"))) diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index cf0cd669be4..70711310749 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -67,6 +67,46 @@ enum stack_protector_guard { SSP_GLOBAL /* global canary */ }; +/* RVV vector register sizes. */ +enum riscv_vector_bits_enum +{ + RVV_SCALABLE, + RVV_NOT_IMPLEMENTED = RVV_SCALABLE, + RVV_64 = 64, + RVV_128 = 128, + RVV_256 = 256, + RVV_512 = 512, + RVV_1024 = 1024, + RVV_2048 = 2048, + RVV_4096 = 4096, + RVV_8192 = 8192, + RVV_16384 = 16384, + RVV_32768 = 32768, + RVV_65536 = 65536 +}; + +/* vectorization factor. */ +enum riscv_vector_lmul_enum +{ + RVV_LMUL1 = 1, + RVV_LMUL2 = 2, + RVV_LMUL4 = 4, + RVV_LMUL8 = 8 +}; + +enum vlmul_field_enum +{ + VLMUL_FIELD_000, /* LMUL = 1. */ + VLMUL_FIELD_001, /* LMUL = 2. */ + VLMUL_FIELD_010, /* LMUL = 4. */ + VLMUL_FIELD_011, /* LMUL = 8. */ + VLMUL_FIELD_100, /* RESERVED. */ + VLMUL_FIELD_101, /* LMUL = 1/8. */ + VLMUL_FIELD_110, /* LMUL = 1/4. */ + VLMUL_FIELD_111, /* LMUL = 1/2. */ + MAX_VLMUL_FIELD +}; + #define MASK_ZICSR (1 << 0) #define MASK_ZIFENCEI (1 << 1) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 5244e8dcbf0..41f60f82a55 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -237,4 +237,18 @@ extern const char* th_mempair_output_move (rtx[4], bool, machine_mode, RTX_CODE); #endif +/* Routines implemented in riscv-v.cc. */ + +namespace riscv_vector { +extern unsigned int riscv_classify_vlmul_field (enum machine_mode m); +extern machine_mode riscv_vector_preferred_simd_mode (scalar_mode mode, + unsigned vf); +extern bool riscv_tuple_mode_p (machine_mode); +extern bool riscv_vector_mask_mode_p (machine_mode); +extern int riscv_classify_nf (machine_mode); +extern int riscv_vlmul_regsize (machine_mode); +extern opt_machine_mode riscv_vector_get_mask_mode (machine_mode mode); +extern rtx get_mask_policy_no_pred (); +extern rtx get_tail_policy_no_pred (); +} #endif /* ! GCC_RISCV_PROTOS_H */ diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index ff1dd4ddd4f..4db3b2cac55 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -70,6 +70,26 @@ Enum(abi_type) String(lp64f) Value(ABI_LP64F) EnumValue Enum(abi_type) String(lp64d) Value(ABI_LP64D) +Enum +Name(riscv_vector_lmul) Type(enum riscv_vector_lmul_enum) +The possible vectorization factor: + +EnumValue +Enum(riscv_vector_lmul) String(1) Value(RVV_LMUL1) + +EnumValue +Enum(riscv_vector_lmul) String(2) Value(RVV_LMUL2) + +EnumValue +Enum(riscv_vector_lmul) String(4) Value(RVV_LMUL4) + +EnumValue +Enum(riscv_vector_lmul) String(8) Value(RVV_LMUL8) + +mriscv-vector-lmul= +Target RejectNegative Joined Enum(riscv_vector_lmul) Var(riscv_vector_lmul) Init(RVV_LMUL1) +-mriscv-vector-lmul= Set the vf using lmul in auto-vectorization. + mfdiv Target Mask(FDIV) Use hardware floating-point divide and square root instructions. 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(get_mask_policy_for_pred): Ditto. * config/riscv/riscv-vector-builtins.h (get_tail_policy_for_pred): New external declaration. (get_mask_policy_for_pred): Ditto. --- gcc/config/riscv/riscv-vector-builtins.cc | 4 ++-- gcc/config/riscv/riscv-vector-builtins.h | 3 +++ 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index 01cea23d3e6..1ed9e4acc40 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -2493,7 +2493,7 @@ use_real_merge_p (enum predication_type_index pred) /* Get TAIL policy for predication. If predication indicates TU, return the TU. Otherwise, return the prefer default configuration. */ -static rtx +rtx get_tail_policy_for_pred (enum predication_type_index pred) { if (pred == PRED_TYPE_tu || pred == PRED_TYPE_tum || pred == PRED_TYPE_tumu) @@ -2503,7 +2503,7 @@ get_tail_policy_for_pred (enum predication_type_index pred) /* Get MASK policy for predication. If predication indicates MU, return the MU. Otherwise, return the prefer default configuration. */ -static rtx +rtx get_mask_policy_for_pred (enum predication_type_index pred) { if (pred == PRED_TYPE_tumu || pred == PRED_TYPE_mu) diff --git a/gcc/config/riscv/riscv-vector-builtins.h b/gcc/config/riscv/riscv-vector-builtins.h index 8ffb9d33e33..de3fd6ca290 100644 --- a/gcc/config/riscv/riscv-vector-builtins.h +++ b/gcc/config/riscv/riscv-vector-builtins.h @@ -483,6 +483,9 @@ extern rvv_builtin_types_t builtin_types[NUM_VECTOR_TYPES + 1]; extern function_instance get_read_vl_instance (void); extern tree get_read_vl_decl (void); +extern rtx get_tail_policy_for_pred (enum predication_type_index pred); +extern rtx get_mask_policy_for_pred (enum predication_type_index pred); + inline tree rvv_arg_type_info::get_scalar_type (vector_type_index type_idx) const { From patchwork Mon Apr 17 18:36:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Collison X-Patchwork-Id: 84400 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2328727vqo; Mon, 17 Apr 2023 11:40:50 -0700 (PDT) X-Google-Smtp-Source: AKy350ZO6NQgcz5nkVQy4OU+DMdhV97bGX48xRhGs4Cm5zaecQsVT8/DsppS6nHHbsnUw9aFJV4Q X-Received: by 2002:a17:906:2dda:b0:92b:f118:ef32 with SMTP id h26-20020a1709062dda00b0092bf118ef32mr9192742eji.48.1681756849937; Mon, 17 Apr 2023 11:40:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681756849; cv=none; d=google.com; s=arc-20160816; b=jRnXV0kaj4SXGxSy0t70aSGGw7/nBcoFinFcRDGosRMETEN5lgrBjsx6o/M5EAX0L6 lmlHBjFTXSuf33xsWq/9JeCuwVzzU3nAIauQs75z+kdOibQ2wnVpP81ET4HdPsrhrn/X +de+bPd+peWnuTmHdtHFwoCaFZd7j3dr3OpsPc4t04gQGnciBNy0X1XFnx3YnXMzsXwr YW3uwjks4ZXK0jK1I9rnUnryq3sJu2HGw06uTiBMHfvQmaRrrHLm8Y7iHgMtbse0w1Gs KoR/bXsZMOoeZ8n+8BzyhTJn5w0p8Gjlu1pjrtsNtOgz0BgvJ0M80pCO/18zXyWx9fUu Wm+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature:dmarc-filter:delivered-to; bh=EP+KbKdXGecqWIGIE2TLDrxuAoh/r9kHm5XI3rL4bU0=; b=A7GQv+v2TmbZxWUdzXFyXg07AG75hzwBALwguXvcfmAfCejOhK4iGNcib8rNT/RR8I 4d0HmWcCnQrMWl5xqH5EoPk3EsVIlr6iYRrTW2vA8Dqc4lJptfC1Lmf6Z85hoPdR9KtI L/3PvlWEF5rEsrfFedsQ4T+VANZmwcnR7YnQeYSl85kmxuidCQWnmWoBjAOyy5hgGtGP I65AIN/YB5m2TznO0jrFlHgFPBpbOumJ3RU2C864m7qfEK0ZrdXvgfl3n30Gn6Ksxd2d L1hmi3gnXM3arZfE/CzYP/6vM7rF/Nd9mfg9112jJe+BefQ4+uhfDHJc9LhiGzMEGZyH 9Rxw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=Py3XPdxT; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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(riscv_vector_preferred_simd_mode): Ditto. (get_mask_policy_no_pred): Ditto. (get_tail_policy_no_pred): Ditto. (riscv_tuple_mode_p): Ditto. (riscv_classify_nf): Ditto. (riscv_vlmul_regsize): Ditto. (riscv_vector_mask_mode_p): Ditto. (riscv_vector_get_mask_mode): Ditto. --- gcc/config/riscv/riscv-v.cc | 176 ++++++++++++++++++++++++++++++++++++ 1 file changed, 176 insertions(+) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 392f5d02e17..9df86419caa 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -39,9 +39,11 @@ #include "emit-rtl.h" #include "tm_p.h" #include "target.h" +#include "targhooks.h" #include "expr.h" #include "optabs.h" #include "tm-constrs.h" +#include "riscv-vector-builtins.h" #include "rtx-vector-builder.h" using namespace riscv_vector; @@ -118,6 +120,41 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT minval, && IN_RANGE (INTVAL (elt), minval, maxval)); } +/* Return the vlmul field for a specific machine mode. */ +unsigned int +riscv_classify_vlmul_field (enum machine_mode mode) +{ + /* Make the decision based on the mode's enum value rather than its + properties, so that we keep the correct classification regardless + of -mriscv-vector-bits. */ + switch (mode) + { + case E_VNx8BImode: + return VLMUL_FIELD_111; + + case E_VNx4BImode: + return VLMUL_FIELD_110; + + case E_VNx2BImode: + return VLMUL_FIELD_101; + + case E_VNx16BImode: + return VLMUL_FIELD_000; + + case E_VNx32BImode: + return VLMUL_FIELD_001; + + case E_VNx64BImode: + return VLMUL_FIELD_010; + + default: + break; + } + + /* we don't care about VLMUL for Mask. */ + return VLMUL_FIELD_000; +} + /* Emit a vlmax vsetvl instruction. This should only be used when optimization is disabled or after vsetvl insertion pass. */ void @@ -176,6 +213,64 @@ calculate_ratio (unsigned int sew, enum vlmul_type vlmul) return ratio; } +/* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE for RVV. */ + +machine_mode +riscv_vector_preferred_simd_mode (scalar_mode mode, unsigned vf) +{ + if (!TARGET_VECTOR) + return word_mode; + + switch (mode) + { + case E_QImode: + return vf == 1 ? VNx8QImode + : vf == 2 ? VNx16QImode + : vf == 4 ? VNx32QImode + : VNx64QImode; + break; + case E_HImode: + return vf == 1 ? VNx4HImode + : vf == 2 ? VNx8HImode + : vf == 4 ? VNx16HImode + : VNx32HImode; + break; + case E_SImode: + return vf == 1 ? VNx2SImode + : vf == 2 ? VNx4SImode + : vf == 4 ? VNx8SImode + : VNx16SImode; + break; + case E_DImode: + if (riscv_vector_elen_flags != MASK_VECTOR_ELEN_32 + && riscv_vector_elen_flags != MASK_VECTOR_ELEN_FP_32) + return vf == 1 ? VNx1DImode + : vf == 2 ? VNx2DImode + : vf == 4 ? VNx4DImode + : VNx8DImode; + break; + case E_SFmode: + if (TARGET_HARD_FLOAT && riscv_vector_elen_flags != MASK_VECTOR_ELEN_32 + && riscv_vector_elen_flags != MASK_VECTOR_ELEN_64) + return vf == 1 ? VNx2SFmode + : vf == 2 ? VNx4SFmode + : vf == 4 ? VNx8SFmode + : VNx16SFmode; + break; + case E_DFmode: + if (TARGET_DOUBLE_FLOAT && TARGET_VECTOR_ELEN_FP_64) + return vf == 1 ? VNx1DFmode + : vf == 2 ? VNx2DFmode + : vf == 4 ? VNx4DFmode + : VNx8DFmode; + break; + default: + break; + } + + return word_mode; +} + /* Emit an RVV unmask && vl mov from SRC to DEST. */ static void emit_pred_op (unsigned icode, rtx mask, rtx dest, rtx src, rtx len, @@ -421,6 +516,87 @@ get_avl_type_rtx (enum avl_type type) return gen_int_mode (type, Pmode); } +rtx +get_mask_policy_no_pred () +{ + return get_mask_policy_for_pred (PRED_TYPE_none); +} + +rtx +get_tail_policy_no_pred () +{ + return get_mask_policy_for_pred (PRED_TYPE_none); +} + +/* Return true if it is a RVV tuple mode. */ +bool +riscv_tuple_mode_p (machine_mode mode ATTRIBUTE_UNUSED) +{ + return false; +} + +/* Return nf for a machine mode. */ +int +riscv_classify_nf (machine_mode mode) +{ + switch (mode) + { + + default: + break; + } + + return 1; +} + +/* Return vlmul register size for a machine mode. */ +int +riscv_vlmul_regsize (machine_mode mode) +{ + if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL) + return 1; + switch (riscv_classify_vlmul_field (mode)) + { + case VLMUL_FIELD_001: + return 2; + case VLMUL_FIELD_010: + return 4; + case VLMUL_FIELD_011: + return 8; + case VLMUL_FIELD_100: + gcc_unreachable (); + default: + return 1; + } +} + +/* Return true if it is a RVV mask mode. */ +bool +riscv_vector_mask_mode_p (machine_mode mode) +{ + return (mode == VNx1BImode || mode == VNx2BImode || mode == VNx4BImode + || mode == VNx8BImode || mode == VNx16BImode || mode == VNx32BImode + || mode == VNx64BImode); +} + +/* Implement TARGET_VECTORIZE_GET_MASK_MODE for RVV. */ + +opt_machine_mode +riscv_vector_get_mask_mode (machine_mode mode) +{ + machine_mode mask_mode; + int nf = 1; + if (riscv_tuple_mode_p (mode)) + nf = riscv_classify_nf (mode); + + FOR_EACH_MODE_IN_CLASS (mask_mode, MODE_VECTOR_BOOL) + if (GET_MODE_INNER (mask_mode) == BImode + && known_eq (GET_MODE_NUNITS (mask_mode) * nf, GET_MODE_NUNITS (mode)) + && riscv_vector_mask_mode_p (mask_mode)) + return mask_mode; + return default_get_mask_mode (mode); +} + /* Return the RVV vector mode that has NUNITS elements of mode INNER_MODE. This function is not only used by builtins, but also will be used by auto-vectorization in the future. */ From patchwork Mon Apr 17 18:36:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Collison X-Patchwork-Id: 84399 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2327898vqo; Mon, 17 Apr 2023 11:39:14 -0700 (PDT) X-Google-Smtp-Source: AKy350Zhv5YjgVwxuf5wdoWQpnJrmvAStMv4dsN0hEygtndVT8TYtCirIr2sG5Hs8HgUKRBKWDR3 X-Received: by 2002:a17:906:c098:b0:94e:e0d9:f6ff with SMTP id f24-20020a170906c09800b0094ee0d9f6ffmr6913952ejz.31.1681756754753; Mon, 17 Apr 2023 11:39:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681756754; cv=none; d=google.com; s=arc-20160816; b=VUZk8EIGK0Eh2Xm4hkz0LuxrRy5mLA+nu9CJppEoCxJc4CE3yvYW+ecF7fJWQgOL6+ aGIfGXiC3b/rZ9+bNDT3XniNv7FxKwuvPfhdtWxd+jnBZo0KDfiXaE2/YWeAjDPticuS NxWyHu7DwWSwnYG4qYQMmqgncCAvPfUYJsvuVbu3qV1jDNurg9lL1joxATyARyakyKP5 7UJhchVW0wnGJsofx+vi2gTcgc2y+VwSRZh9RSwVwxokcoX+ZDfeFyuVfz85yCRCziWc +Bjbpny/282Nw5fLV6D5UjdP7OmPDHx9DDDtQ6NO8A0tgci0C5U2+lYL6CUQoGZD+Jvl CA4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature:dmarc-filter:delivered-to; bh=V/VXsleDiAHLosN3szsaf7V8WtfFsIyW00/0RzZxydc=; b=nUnfDp8vP8kjUDFuV4wEFHVXmIpxoNPt4yYx5ecRpR/2sJYWqLJHpZ6tdJBG7Eur4Q PTxu409r5ppHZjnEvB5efmG4Zw2+n/fJpQVh+0Ll0Wdb9lJL93V/3GmkyNzKR4CvePpA jzXfcSFCF/vQxtDoO1WefqJCCIXzsIwOJB9//OdyZUqMcr6JBq5UP+0PZr/INfo25opv /L5MTEo8wPAnhrp9v3YZlPVQVxQVx7AzaUKUYfsPKQyAAIlXAMT36sSEuWMuxG5ZYvCn dELKgk9MG98vSExGkikCG4mcdLEoavo3zXcBVYX4rEvSOPn/CvxjYCLTkFoyvCtXCaJi Lhew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=CGpCJd3x; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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(riscv_estimated_poly_value): Implement TARGET_ESTIMATED_POLY_VALUE. (riscv_preferred_simd_mode): Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. (riscv_autovectorize_vector_modes): Implement TARGET_AUTOVECTORIZE_VECTOR_MODES. (riscv_get_mask_mode): Implement TARGET_VECTORIZE_GET_MASK_MODE. (riscv_empty_mask_is_expensive): Implement TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE. (riscv_vectorize_create_costs): Implement TARGET_VECTORIZE_CREATE_COSTS. (TARGET_ESTIMATED_POLY_VALUE): Register target macro. (TARGET_VECTORIZE_PREFERRED_SIMD_MODE): Ditto. (TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES): Ditto. (TARGET_VECTORIZE_GET_MASK_MODE): Ditto. (TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE): Ditto. (TARGET_VECTORIZE_LOOP_LEN_OVERRIDE_MASK): Ditto. --- gcc/config/riscv/riscv.cc | 156 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 156 insertions(+) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index dc47434fac4..9af06d926cf 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -60,6 +60,15 @@ along with GCC; see the file COPYING3. If not see #include "opts.h" #include "tm-constrs.h" #include "rtl-iter.h" +#include "gimple.h" +#include "cfghooks.h" +#include "cfgloop.h" +#include "cfgrtl.h" +#include "sel-sched.h" +#include "fold-const.h" +#include "gimple-iterator.h" +#include "gimple-expr.h" +#include "tree-vectorizer.h" /* This file should be included last. */ #include "target-def.h" @@ -275,6 +284,9 @@ poly_uint16 riscv_vector_chunks; /* The number of bytes in a vector chunk. */ unsigned riscv_bytes_per_vector_chunk; +/* Prefer vf for auto-vectorizer. */ +unsigned riscv_vectorization_factor; + /* Index R is the smallest register class that contains register R. */ const enum reg_class riscv_regno_to_class[FIRST_PSEUDO_REGISTER] = { GR_REGS, GR_REGS, GR_REGS, GR_REGS, @@ -6363,6 +6375,10 @@ riscv_option_override (void) /* Convert -march to a chunks count. */ riscv_vector_chunks = riscv_convert_vector_bits (); + + if (TARGET_VECTOR) + riscv_vectorization_factor = riscv_vector_lmul; + } /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */ @@ -7057,6 +7073,128 @@ riscv_dwarf_poly_indeterminate_value (unsigned int i, unsigned int *factor, return RISCV_DWARF_VLENB; } +/* Implement TARGET_ESTIMATED_POLY_VALUE. + Look into the tuning structure for an estimate. + KIND specifies the type of requested estimate: min, max or likely. + For cores with a known RVV width all three estimates are the same. + For generic RVV tuning we want to distinguish the maximum estimate from + the minimum and likely ones. + The likely estimate is the same as the minimum in that case to give a + conservative behavior of auto-vectorizing with RVV when it is a win + even for 128-bit RVV. + When RVV width information is available VAL.coeffs[1] is multiplied by + the number of VQ chunks over the initial Advanced SIMD 128 bits. */ + +static HOST_WIDE_INT +riscv_estimated_poly_value (poly_int64 val, + poly_value_estimate_kind kind = POLY_VALUE_LIKELY) +{ + unsigned int width_source = BITS_PER_RISCV_VECTOR.is_constant () + ? (unsigned int) BITS_PER_RISCV_VECTOR.to_constant () + : (unsigned int) RVV_SCALABLE; + + /* If there is no core-specific information then the minimum and likely + values are based on 128-bit vectors and the maximum is based on + the architectural maximum of 2048 bits. */ + if (width_source == RVV_SCALABLE) + switch (kind) + { + case POLY_VALUE_MIN: + case POLY_VALUE_LIKELY: + return val.coeffs[0]; + + case POLY_VALUE_MAX: + return val.coeffs[0] + val.coeffs[1] * 15; + } + + /* Allow BITS_PER_RISCV_VECTOR to be a bitmask of different VL, treating the + lowest as likely. This could be made more general if future -mtune + options need it to be. */ + if (kind == POLY_VALUE_MAX) + width_source = 1 << floor_log2 (width_source); + else + width_source = least_bit_hwi (width_source); + + /* If the core provides width information, use that. */ + HOST_WIDE_INT over_128 = width_source - 128; + return val.coeffs[0] + val.coeffs[1] * over_128 / 128; +} + +/* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */ + +static machine_mode +riscv_preferred_simd_mode (scalar_mode mode) +{ + machine_mode vmode = + riscv_vector::riscv_vector_preferred_simd_mode (mode, + riscv_vectorization_factor); + if (VECTOR_MODE_P (vmode)) + return vmode; + + return word_mode; +} + +/* Implement TARGET_AUTOVECTORIZE_VECTOR_MODES for RVV. */ +static unsigned int +riscv_autovectorize_vector_modes (vector_modes *modes, bool) +{ + if (!TARGET_VECTOR) + return 0; + + if (riscv_vectorization_factor == RVV_LMUL1) + { + modes->safe_push (VNx16QImode); + modes->safe_push (VNx8QImode); + modes->safe_push (VNx4QImode); + modes->safe_push (VNx2QImode); + } + else if (riscv_vectorization_factor == RVV_LMUL2) + { + modes->safe_push (VNx32QImode); + modes->safe_push (VNx16QImode); + modes->safe_push (VNx8QImode); + modes->safe_push (VNx4QImode); + } + else if (riscv_vectorization_factor == RVV_LMUL4) + { + modes->safe_push (VNx64QImode); + modes->safe_push (VNx32QImode); + modes->safe_push (VNx16QImode); + modes->safe_push (VNx8QImode); + } + else + { + modes->safe_push (VNx64QImode); + modes->safe_push (VNx32QImode); + modes->safe_push (VNx16QImode); + } + + return 0; +} + +/* Implement TARGET_VECTORIZE_GET_MASK_MODE. */ + +static opt_machine_mode +riscv_get_mask_mode (machine_mode mode) +{ + machine_mode mask_mode = VOIDmode; + if (TARGET_VECTOR + && riscv_vector::riscv_vector_get_mask_mode (mode).exists (&mask_mode)) + return mask_mode; + + return default_get_mask_mode (mode); +} + +/* Implement TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE. Assume for now that + it isn't worth branching around empty masked ops (including masked + stores). */ + +static bool +riscv_empty_mask_is_expensive (unsigned) +{ + return false; +} + /* Return true if a shift-amount matches the trailing cleared bits on a bitmask. */ @@ -7382,6 +7520,24 @@ riscv_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) #undef TARGET_VERIFY_TYPE_CONTEXT #define TARGET_VERIFY_TYPE_CONTEXT riscv_verify_type_context +#undef TARGET_ESTIMATED_POLY_VALUE +#define TARGET_ESTIMATED_POLY_VALUE riscv_estimated_poly_value + +#undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE +#define TARGET_VECTORIZE_PREFERRED_SIMD_MODE riscv_preferred_simd_mode + +#undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES +#define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES riscv_autovectorize_vector_modes + +#undef TARGET_VECTORIZE_GET_MASK_MODE +#define TARGET_VECTORIZE_GET_MASK_MODE riscv_get_mask_mode + +#undef TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE +#define TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE riscv_empty_mask_is_expensive + +#undef TARGET_VECTORIZE_LOOP_LEN_OVERRIDE_MASK +#define TARGET_VECTORIZE_LOOP_LEN_OVERRIDE_MASK riscv_loop_len_override_mask + #undef TARGET_VECTOR_ALIGNMENT #define TARGET_VECTOR_ALIGNMENT riscv_vector_alignment From patchwork Mon Apr 17 18:36:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Collison X-Patchwork-Id: 84401 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2328743vqo; Mon, 17 Apr 2023 11:40:51 -0700 (PDT) X-Google-Smtp-Source: AKy350aObW0OOue32t9u5ZI8XBBJSeWK6pk+CTeBgx8CPJjijq5n5OkKzmFV91RCQX2Pd7w2j6W9 X-Received: by 2002:aa7:c512:0:b0:502:25ac:c72a with SMTP id o18-20020aa7c512000000b0050225acc72amr13374793edq.1.1681756851626; Mon, 17 Apr 2023 11:40:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681756851; cv=none; d=google.com; s=arc-20160816; b=t4JUY7GRvyLBrSr+6Zlrfysl546MGDIoyrYheMMQv5SK5vALpLpICIHYzayPhapMuG VpQvrnJvEAn+msiKbN8scxDtW7Jy863fQPQJ6oJ4oOoUIc1aZ4u9umseFS+nXIUGq0W2 fd7N9NBzeyoVXkwFxnCeDY2orKVyK7KdfleTEIQxh5ZbsYfeZmtiHUbMbcJSvT+7pedB mKhlVDt6AWgNHswEGbOO/p7QxzNVIOLe5SFn4L8ANvzwDDjgOSqvxsILQcNmCXYsgwjG 0LrxvAmIItdPlw9s6eHmWa2/9vNEo1wbU587Sp3VerRJTaceuwwSQiQyL4j4NgmQgeQD EKxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature:dmarc-filter:delivered-to; bh=kNdM6598qP5dqXNBBPOrBmXj1znhIcSzh93RznI2g+8=; b=nCuZB2+7ARRx6zMe2uufe+K4ESJnQDyX3B4ez4FVvpE1k2rW6sThIXAyHCPgmixv2t yVF5gv8pyvxqHZzzKrACHR77qqLFEQylXOU62Ir3ZmAUgpL26aa+k/Y3OZlPP4OVnHCV piXeMpDJuZLhN68WanO0qy267JSwjogKJGoYoNrk52Jmh0QFZWcOA7jioCj1iSQShfr5 GSh9vT6wXonFgML+MW7ol5HEm4h5Td5jO4U4oibEQxq4AP0ndo1XQo0FP/0BhDSAmL3V 3Zt2H4bOj+HXqwQ/I9fsxOBBgBa9rW+RYdo0mX2fJGS5Xwyh1JYlU36K+lEPpuvNRG3N 4Scw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=PogzW9lc; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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Mon, 17 Apr 2023 11:37:05 -0700 (PDT) From: Michael Collison To: gcc-patches@gcc.gnu.org Subject: [PATCH v4 05/10] RISC-V:autovec: Add autovectorization patterns for binary integer operations Date: Mon, 17 Apr 2023 14:36:56 -0400 Message-Id: <20230417183701.2249183-6-collison@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230417183701.2249183-1-collison@rivosinc.com> References: <20230417183701.2249183-1-collison@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763449872525044782?= X-GMAIL-MSGID: =?utf-8?q?1763449872525044782?= 2023-03-02 Michael Collison Juzhe Zhong * config/riscv/riscv.md (riscv_vector_preferred_simd_mode): Include vector-iterators.md. * config/riscv/vector-auto.md: New file containing autovectorization patterns. * config/riscv/vector-iterators.md (UNSPEC_VADD/UNSPEC_VSUB): New unspecs for autovectorization patterns. * config/riscv/vector.md: Remove include of vector-iterators.md and include vector-auto.md. --- gcc/config/riscv/riscv.md | 1 + gcc/config/riscv/vector-auto.md | 79 ++++++++++++++++++++++++++++ gcc/config/riscv/vector-iterators.md | 2 + gcc/config/riscv/vector.md | 4 +- 4 files changed, 84 insertions(+), 2 deletions(-) create mode 100644 gcc/config/riscv/vector-auto.md diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index bc384d9aedf..7f8f3a6cb18 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -135,6 +135,7 @@ (include "predicates.md") (include "constraints.md") (include "iterators.md") +(include "vector-iterators.md") ;; .................... ;; diff --git a/gcc/config/riscv/vector-auto.md b/gcc/config/riscv/vector-auto.md new file mode 100644 index 00000000000..dc62f9af705 --- /dev/null +++ b/gcc/config/riscv/vector-auto.md @@ -0,0 +1,79 @@ +;; Machine description for RISC-V 'V' Extension for GNU compiler. +;; Copyright (C) 2022-2023 Free Software Foundation, Inc. +;; Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd. +;; Contributed by Michael Collison (collison@rivosinc.com, Rivos Inc. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + + +;; ------------------------------------------------------------------------- +;; ---- [INT] Addition +;; ------------------------------------------------------------------------- +;; Includes: +;; - vadd.vv +;; - vadd.vx +;; - vadd.vi +;; ------------------------------------------------------------------------- + +(define_expand "3" + [(set (match_operand:VI 0 "register_operand") + (any_int_binop:VI (match_operand:VI 1 "register_operand") + (match_operand:VI 2 "register_operand")))] + "TARGET_VECTOR" +{ + using namespace riscv_vector; + + rtx merge = RVV_VUNDEF (mode); + rtx vl = gen_reg_rtx (Pmode); + emit_vlmax_vsetvl (mode, vl); + rtx mask_policy = get_mask_policy_no_pred(); + rtx tail_policy = get_tail_policy_no_pred(); + rtx mask = CONSTM1_RTX(mode); + rtx vlmax_avl_p = get_avl_type_rtx(NONVLMAX); + + emit_insn(gen_pred_(operands[0], mask, merge, operands[1], operands[2], + vl, tail_policy, mask_policy, vlmax_avl_p)); + + DONE; +}) + +(define_expand "cond_3" + [(set (match_operand:VI 0 "register_operand") + (if_then_else:VI + (unspec: + [(match_operand: 1 "register_operand")] UNSPEC_VPREDICATE) + (any_int_binop:VI + (match_operand:VI 2 "register_operand") + (match_operand:VI 3 "register_operand")) + (match_operand:VI 4 "register_operand")))] + "TARGET_VECTOR" +{ + using namespace riscv_vector; + + rtx merge = operands[4]; + rtx vl = gen_reg_rtx (Pmode); + emit_vlmax_vsetvl (mode, vl); + rtx mask_policy = get_mask_policy_no_pred(); + rtx tail_policy = get_tail_policy_no_pred(); + rtx mask = operands[1]; + rtx vlmax_avl_p = get_avl_type_rtx(NONVLMAX); + + emit_insn(gen_pred_(operands[0], mask, merge, operands[2], operands[3], + vl, tail_policy, mask_policy, vlmax_avl_p)); + DONE; +}) + diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 70ad85b661b..7fae87968d7 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -34,6 +34,8 @@ UNSPEC_VMULHU UNSPEC_VMULHSU + UNSPEC_VADD + UNSPEC_VSUB UNSPEC_VADC UNSPEC_VSBC UNSPEC_VMADC diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 0ecca98f20c..2ac5b744503 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -26,8 +26,6 @@ ;; - Auto-vectorization (TBD) ;; - Combine optimization (TBD) -(include "vector-iterators.md") - (define_constants [ (INVALID_ATTRIBUTE 255) (X0_REGNUM 0) @@ -351,6 +349,8 @@ (symbol_ref "INTVAL (operands[4])")] (const_int INVALID_ATTRIBUTE))) +(include "vector-auto.md") + ;; ----------------------------------------------------------------- ;; ---- Miscellaneous Operations ;; ----------------------------------------------------------------- From patchwork Mon Apr 17 18:36:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Collison X-Patchwork-Id: 84402 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2329003vqo; Mon, 17 Apr 2023 11:41:21 -0700 (PDT) X-Google-Smtp-Source: AKy350bTOXuVPoVb+PIwsV4eBZ+yFdumoVpUGumsVepJMEaBhWFLv2A3vdcX7IKcerAEAsaXw0kx X-Received: by 2002:a17:906:8805:b0:933:130e:e81a with SMTP id zh5-20020a170906880500b00933130ee81amr7363841ejb.32.1681756881024; Mon, 17 Apr 2023 11:41:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681756881; cv=none; d=google.com; s=arc-20160816; b=W2+3bPZryxW/ow3XFM4YVZFqIU48dglgXTPIHdIajXfvxnVyQsFPnTbNQc1rmZ/afo 62ACiy6WgXH/vhWG06Wvqn59ir/d8cUxM5Zqdb0Uv/bRYZkgv9EMr6wLOOm+zdcLJ9aY AfppXLYOBjfD5idlqnIY1j+p1/44HPIp5hXZsVmxU8EiBr+zwAajU0qe28fepsmyeZRf R36p9zr5kwJCTxHgEJnx5Vu2A9D5QD/2s7TqQ14cYAgaED9RvkaC1NIMj9x4I7eZ/Fjf UicOKBs+J3/NCP/ATi/Ko/bqyIr3HfDfTwIKXiWU3L1x/aODE99AsAf2zwcvNh+vpqYd lUVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature:dmarc-filter:delivered-to; bh=nfeKVTPOx4lLGqWjSYL0cYLaY1Ole3hW51CK3s0URU8=; b=EUpMoT23NuQvMQYTsjylI7TME7NXPgcP+rJ8hAnwQpo/wFcYB5urhahVjP/OHjzdQR nBuhji3r+A3qdg1s0qXLWvs+omYhQ/hKhRQ3dEg5EomShsn22wWVN7VGmOVbEf6lCyVf NQuqLeR2hlbsiXofwcHSdH1pQ0j4+5JuHkoxw3HMUn4/+lx9UP8xLE1CI9FTiEdmqzMd 2GarvPEK3caN7VUwr7KIvNJHUvZ70kGV6uNDvT5JtjImOpVJU0q/prCLvDj4xc24bEfz NOTe8d/4/3EMVZj3le0QYSOyVW8vdqvInGVr3vMQrhZpTU6u26YIFfZBjINyUjbhw61w bSnA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=qaKJMU6d; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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Mon, 17 Apr 2023 11:37:05 -0700 (PDT) From: Michael Collison To: gcc-patches@gcc.gnu.org Subject: [PATCH v4 06/10] RISC-V:autovec: Add autovectorization tests for add & sub Date: Mon, 17 Apr 2023 14:36:57 -0400 Message-Id: <20230417183701.2249183-7-collison@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230417183701.2249183-1-collison@rivosinc.com> References: <20230417183701.2249183-1-collison@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763449903653992115?= X-GMAIL-MSGID: =?utf-8?q?1763449903653992115?= 2023-03-02 Michael Collison Vineet Gupta * gcc.target/riscv/rvv/autovec: New directory for autovectorization tests. * gcc.target/riscv/rvv/autovec/loop-add-rv32.c: New test to verify code generation of vector add on rv32. * gcc.target/riscv/rvv/autovec/loop-add.c: New test to verify code generation of vector add on rv64. * gcc.target/riscv/rvv/autovec/loop-sub-rv32.c: New test to verify code generation of vector subtract on rv32. * gcc.target/riscv/rvv/autovec/loop-sub.c: New test to verify code generation of vector subtract on rv64. --- .../riscv/rvv/autovec/loop-add-rv32.c | 24 +++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/loop-add.c | 24 +++++++++++++++++++ .../riscv/rvv/autovec/loop-sub-rv32.c | 24 +++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/loop-sub.c | 24 +++++++++++++++++++ 4 files changed, 96 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c new file mode 100644 index 00000000000..bdc3b6892e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] + b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvadd\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c new file mode 100644 index 00000000000..d7f992c7d27 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] + b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvadd\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c new file mode 100644 index 00000000000..7d0a40ec539 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] - b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvsub\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c new file mode 100644 index 00000000000..c8900884f83 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] - b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvsub\.vv} 6 } } */ From patchwork Mon Apr 17 18:36:58 2023 Content-Type: text/plain; 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Date: Mon, 17 Apr 2023 14:36:58 -0400 Message-Id: <20230417183701.2249183-8-collison@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230417183701.2249183-1-collison@rivosinc.com> References: <20230417183701.2249183-1-collison@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763449984494843423?= X-GMAIL-MSGID: =?utf-8?q?1763449984494843423?= While working on autovectorizing for the RISCV port I encountered an issue where can_duplicate_and_interleave_p assumes that GET_MODE_NUNITS is a evenly divisible by two. The RISC-V target has vector modes (e.g. VNx1DImode), where GET_MODE_NUNITS is equal to one. Tested on RISCV and x86_64-linux-gnu. Okay? 2023-03-09 Michael Collison * tree-vect-slp.cc (can_duplicate_and_interleave_p): Check that GET_MODE_NUNITS is a multiple of 2. --- gcc/tree-vect-slp.cc | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect-slp.cc index d73deaecce0..a64fe454e19 100644 --- a/gcc/tree-vect-slp.cc +++ b/gcc/tree-vect-slp.cc @@ -423,10 +423,13 @@ can_duplicate_and_interleave_p (vec_info *vinfo, unsigned int count, (GET_MODE_BITSIZE (int_mode), 1); tree vector_type = get_vectype_for_scalar_type (vinfo, int_type, count); + poly_int64 half_nelts; if (vector_type && VECTOR_MODE_P (TYPE_MODE (vector_type)) && known_eq (GET_MODE_SIZE (TYPE_MODE (vector_type)), - GET_MODE_SIZE (base_vector_mode))) + GET_MODE_SIZE (base_vector_mode)) + && multiple_p (GET_MODE_NUNITS (TYPE_MODE (vector_type)), + 2, &half_nelts)) { /* Try fusing consecutive sequences of COUNT / NVECTORS elements together into elements of type INT_TYPE and using the result @@ -434,7 +437,7 @@ can_duplicate_and_interleave_p (vec_info *vinfo, unsigned int count, poly_uint64 nelts = GET_MODE_NUNITS (TYPE_MODE (vector_type)); vec_perm_builder sel1 (nelts, 2, 3); vec_perm_builder sel2 (nelts, 2, 3); - poly_int64 half_nelts = exact_div (nelts, 2); + for (unsigned int i = 0; i < 3; ++i) { sel1.quick_push (i); From patchwork Mon Apr 17 18:36:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Collison X-Patchwork-Id: 84405 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2329927vqo; Mon, 17 Apr 2023 11:43:06 -0700 (PDT) X-Google-Smtp-Source: AKy350bqH4ZFNO35TKoEpzbI1L4J2wzhbKHaCvZktkTajhMLqW/jqnsVOX5jIQDiV2BpkMoJejP4 X-Received: by 2002:a17:906:c355:b0:94f:b5c:a254 with SMTP id ci21-20020a170906c35500b0094f0b5ca254mr7339399ejb.49.1681756986793; Mon, 17 Apr 2023 11:43:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681756986; cv=none; d=google.com; s=arc-20160816; b=w7mYvriqcWG2ZJsVbUPn10aYjRmi9gDmT94J4qQy7DZV+deHPGYIl3Y5IQQVwIl3qx IysFjrWDuIM27qg52S0Sb7W2kIe3TiUnR0mtbyFh8zV3XIn1IV/n85dhvLUEJkF7/kfr cQCcf0425cyT9tJMkU+w04YyS7u+YE7J7usMO1i+0EWcjj95Lp/zRrzXU3hgSkVtyUJS 89itg/VgdX9GVlHQvODH+kFDUaTa/2BFYGC1BBuXtHcSIGA+PHE4FmZCmnu4KXNf9nEl i/bcfX/9Crir+UbwxXd7nXCxm84N2ZvZe22+5FWNg1kYaMHMM6LF0L9xIy3Teh15jFyW rwAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature:dmarc-filter:delivered-to; bh=mx4LKw5aHkZd8r9iRza5i+JDG7Q3SjJ2p74l2D5IdGk=; b=ZPmMlzoATQSUj2KvHbx7NgxJolbQewM+uvok0l86uQb8nTSaOmMlpCSa2MG56rzW+R 1mzuZEQIlcrzdj72OLMzOaiPOp+rzMmusHd6QftXxsbXcJvG/oopQEES9hVSVtjUBBMR 3hDi4aFYg6FHncW98l9Ujk9a6IGZnVrZsOaZjrF59/oBKx5w8h7aZvuZdnUqVqAGuiju eLThhkN72Ti8hO7igQtb8ww0dgtUpxJuz/d0xtmjcNwxY0HOSqyJIKb9phRCNLyC2/+b mTNCSYq8QZ2GwTtVg/qeWIrk8BUM4gwbpeN3qGhAUlGeCIMUkPFu7eVZJmsKf5SK2dMp Q/Zw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=3D8NCo1G; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763450013825860932?= X-GMAIL-MSGID: =?utf-8?q?1763450013825860932?= 2023-04-05 Michael Collison * gcc.target/riscv/rvv/autovec/loop-and-rv32.c: New test to verify code generation of vector "and" on rv32. * gcc.target/riscv/rvv/autovec/loop-and.c: New test to verify code generation of vector "and" on rv64. * gcc.target/riscv/rvv/autovec/loop-div-rv32.c: New test to verify code generation of vector divide on rv32. * gcc.target/riscv/rvv/autovec/loop-div.c: New test to verify code generation of vector divide on rv64. * gcc.target/riscv/rvv/autovec/loop-max-rv32.c: New test to verify code generation of vector maximum on rv32. * gcc.target/riscv/rvv/autovec/loop-max.c: New test to verify code generation of vector maximum on rv64. * gcc.target/riscv/rvv/autovec/loop-min-rv32.c: New test to verify code generation of vector minimum on rv32. * gcc.target/riscv/rvv/autovec/loop-min.c: New test to verify code generation of vector minimum on rv64. * gcc.target/riscv/rvv/autovec/loop-mod-rv32.c: New test to verify code generation of vector modulus on rv32. * gcc.target/riscv/rvv/autovec/loop-mod.c: New test to verify code generation of vector modulus on rv64. * gcc.target/riscv/rvv/autovec/loop-mul-rv32.c: New test to verify code generation of vector multiply on rv32. * gcc.target/riscv/rvv/autovec/loop-mul.c: New test to verify code generation of vector multiply on rv64. * gcc.target/riscv/rvv/autovec/loop-or-rv32.c: New test to verify code generation of vector "or" on rv32. * gcc.target/riscv/rvv/autovec/loop-or.c: New test to verify code generation of vector "or" on rv64. * gcc.target/riscv/rvv/autovec/loop-xor-rv32.c: New test to verify code generation of vector xor on rv32. * gcc.target/riscv/rvv/autovec/loop-xor.c: New test to verify code generation of vector xor on rv64. --- .../riscv/rvv/autovec/loop-and-rv32.c | 24 ++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/loop-and.c | 24 ++++++++++++++++++ .../riscv/rvv/autovec/loop-div-rv32.c | 25 +++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/loop-div.c | 25 +++++++++++++++++++ .../riscv/rvv/autovec/loop-max-rv32.c | 25 +++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/loop-max.c | 25 +++++++++++++++++++ .../riscv/rvv/autovec/loop-min-rv32.c | 25 +++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/loop-min.c | 25 +++++++++++++++++++ .../riscv/rvv/autovec/loop-mod-rv32.c | 25 +++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/loop-mod.c | 25 +++++++++++++++++++ .../riscv/rvv/autovec/loop-mul-rv32.c | 24 ++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/loop-mul.c | 24 ++++++++++++++++++ .../riscv/rvv/autovec/loop-or-rv32.c | 24 ++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/loop-or.c | 24 ++++++++++++++++++ .../riscv/rvv/autovec/loop-xor-rv32.c | 24 ++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/loop-xor.c | 24 ++++++++++++++++++ gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 3 +++ 17 files changed, 395 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c new file mode 100644 index 00000000000..eb1ac5b44fd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vand_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] & b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvand\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c new file mode 100644 index 00000000000..ff0cc2a5df7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vand_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] & b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvand\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c new file mode 100644 index 00000000000..21960f265b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vdiv_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] / b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvdiv\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvdivu\.vv} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c new file mode 100644 index 00000000000..bd675b4f6f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vdiv_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] / b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvdiv\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvdivu\.vv} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c new file mode 100644 index 00000000000..751ee9ecaa3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vmax_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] >= b[i] ? a[i] : b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvmax\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c new file mode 100644 index 00000000000..f4dbf3f04fc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vmax_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] >= b[i] ? a[i] : b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvmax\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c new file mode 100644 index 00000000000..e51cf590577 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vmin_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] <= b[i] ? a[i] : b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvmin\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvminu\.vv} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c new file mode 100644 index 00000000000..304f939f6f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vmin_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] <= b[i] ? a[i] : b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvmin\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvminu\.vv} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c new file mode 100644 index 00000000000..7c497f6e4cc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vmod_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] % b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvrem\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvremu\.vv} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c new file mode 100644 index 00000000000..7508f4a50d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vmod_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] % b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvrem\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvremu\.vv} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c new file mode 100644 index 00000000000..fd6dcbf9c53 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] * b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvmul\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c new file mode 100644 index 00000000000..9fce40890ef --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] * b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvmul\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c new file mode 100644 index 00000000000..305d106abd9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vor_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] | b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvor\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c new file mode 100644 index 00000000000..501017bc790 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vor_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] | b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvor\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c new file mode 100644 index 00000000000..6a9ffdb11d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vxor_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] ^ b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvxor\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c new file mode 100644 index 00000000000..c9d7d7f8a75 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vxor_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] ^ b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvxor\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp index 7a9a2b6ac48..081fa9363de 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp @@ -40,10 +40,13 @@ dg-init # Main loop. set CFLAGS "$DEFAULT_CFLAGS -march=$gcc_march -O3" +set AUTOVECFLAGS "$DEFAULT_CFLAGS -march=$gcc_march -O2 -fno-vect-cost-model -std=c99" dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.\[cS\]]] \ "" $CFLAGS gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]] \ "" $CFLAGS +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \ + "" $AUTOVECFLAGS # All done. dg-finish From patchwork Mon Apr 17 18:37:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Collison X-Patchwork-Id: 84403 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2329091vqo; Mon, 17 Apr 2023 11:41:29 -0700 (PDT) X-Google-Smtp-Source: AKy350Z04M9oyv70z5Rt1ayYsf+c4mt566dHFHNlenLmkAg2FZDIjGBZ2uHvtbn7W3NBFv4Rw77p X-Received: by 2002:aa7:d7d5:0:b0:506:ad45:49b1 with SMTP id e21-20020aa7d7d5000000b00506ad4549b1mr2840372eds.42.1681756889183; Mon, 17 Apr 2023 11:41:29 -0700 (PDT) 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[8.43.85.97]) by mx.google.com with ESMTPS id f15-20020a05640214cf00b005049b5c6f4fsi10609050edx.425.2023.04.17.11.41.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Apr 2023 11:41:29 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=N0WRyniW; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 84B0B3852751 for ; Mon, 17 Apr 2023 18:38:14 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-yw1-x1129.google.com (mail-yw1-x1129.google.com [IPv6:2607:f8b0:4864:20::1129]) by sourceware.org (Postfix) with ESMTPS id 11C90385841C for ; Mon, 17 Apr 2023 18:37:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 11C90385841C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-yw1-x1129.google.com with SMTP id 00721157ae682-54c12009c30so535088787b3.9 for ; Mon, 17 Apr 2023 11:37:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1681756627; x=1684348627; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=3UyxEYbY1lHxXBiydL8RZMJ4aK38w5sY/3i6sxcAAwg=; b=N0WRyniWOETfaBznfsJuYYDcJJqpn8bqm4qwOZGbvbGa1SrHoNlxUXELa47mAuWs61 XKEymRCbCKkR2CTsLhKA0bR6OtQyQ1VNMXb16+L4ep+acd5N/1jaTSsnVl5kR4NqPo64 tmps9RJgj7qf3bz1tEOAiOSfOSgMX4e/OBEUSWicMAa/hKA6Q9W/LUEEt6H0tuXNLGCX 6TYDsDjV6yd0sVqf6kuyO8n4sxxzT0mgkBI0WYj2D8W7uT/1xKNYuobQggxj7uEhKC4j 0NJ0BGEnU5hGac38wwJsI1+wrgky1ntAKnVPQiarybyAckiQlNdEQPiTBbrnW38FnXZa kSoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681756627; x=1684348627; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3UyxEYbY1lHxXBiydL8RZMJ4aK38w5sY/3i6sxcAAwg=; b=AcSynMyQ6BF3PcaY1B4B0sYTXVCfsnVTLpsKIH6QnLUR2i+wakMrDCexKH8G/kOCT2 V/uPbk2i/NNqL70WcQSPH/Qaa73wb5OO2ibhkfKtbdKEZojqntnkCsrVkus2hePKgZli RnvCLfs6f/eaiYlbdTGtV40dFSa9XJf1B3h+u3hjBOWjjCAJtXXmnEl9gGfTY/+1n2tB vfMgXWvOsgxFDzfGVeIsgvFfWdE1NXmfw14FCARi3mhq8oyAY8k1sDbf9NtEZYxKXWI0 gPtc9PzjB/T1hC/iOKmd9hqsQltmzzaWhPkH5mB+MGN5ohgwdVWMcR1b29n37gsghFKc HThg== X-Gm-Message-State: AAQBX9ebHct3CEcia2XpPMEOJ9jQL7ERId67cHnRC94Rk4XfSHqqF2Rw fZS7x/0RBgrluk+m4KjWLjrGrm2rgEDKxjy5YHMPaw== X-Received: by 2002:a81:6d84:0:b0:54f:b5bc:42d1 with SMTP id i126-20020a816d84000000b0054fb5bc42d1mr15686397ywc.47.1681756627418; Mon, 17 Apr 2023 11:37:07 -0700 (PDT) Received: from system76-pc.ba.rivosinc.com ([136.57.172.92]) by smtp.gmail.com with ESMTPSA id 66-20020a810645000000b0054f6f65f258sm3278559ywg.16.2023.04.17.11.37.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Apr 2023 11:37:07 -0700 (PDT) From: Michael Collison To: gcc-patches@gcc.gnu.org Subject: [PATCH v4 09/10] This patch adds a guard for VNx1 vectors that are present in ports like riscv. Date: Mon, 17 Apr 2023 14:37:00 -0400 Message-Id: <20230417183701.2249183-10-collison@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230417183701.2249183-1-collison@rivosinc.com> References: <20230417183701.2249183-1-collison@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763449912061089725?= X-GMAIL-MSGID: =?utf-8?q?1763449912061089725?= From: Kevin Lee Kevin Lee gcc/ChangeLog: * tree-vect-data-refs.cc (vect_grouped_store_supported): Add new condition --- gcc/tree-vect-data-refs.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/gcc/tree-vect-data-refs.cc b/gcc/tree-vect-data-refs.cc index 8daf7bd7dd3..df393ba723d 100644 --- a/gcc/tree-vect-data-refs.cc +++ b/gcc/tree-vect-data-refs.cc @@ -5399,6 +5399,8 @@ vect_grouped_store_supported (tree vectype, unsigned HOST_WIDE_INT count) poly_uint64 nelt = GET_MODE_NUNITS (mode); /* The encoding has 2 interleaved stepped patterns. */ + if(!multiple_p (nelt, 2)) + return false; vec_perm_builder sel (nelt, 2, 3); sel.quick_grow (6); for (i = 0; i < 3; i++) From patchwork Mon Apr 17 18:37:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Collison X-Patchwork-Id: 84406 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2330134vqo; Mon, 17 Apr 2023 11:43:30 -0700 (PDT) X-Google-Smtp-Source: AKy350a8yk2G9bnY3bcYJpewZlFXSArcxtw9UgEgZFsHXqKQ/T0FL3sEFtprRF9UBJIkgO/6oU1o X-Received: by 2002:a17:906:2dd4:b0:94f:a03:3d3b with SMTP id h20-20020a1709062dd400b0094f0a033d3bmr7179300eji.20.1681757009863; Mon, 17 Apr 2023 11:43:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681757009; cv=none; d=google.com; s=arc-20160816; b=kKM8dsq1Ji1zFFqh7jrqItUEnvCD3YFOkauCWzzfVNzmR4YE5wXo8+6U1OEAZzApAz 8AeCcKm0/+C2s0PMDqTFhN38JfR+LExHWJ83GGHY6k63jK5eGlVBcFmmX8hq0tlgH+Rr beEDMZ+Iv6a+as6VQ4xO/1DAj/TrqoFtGz31ysRIBeNNBjnQZYIFiMFWmNtoMeoJ8dsd AgNunmm7cB6AYFwk328SAVFC1RIbTNyk7A6EaEQA8SRzso79K3vRba366Mx6GDCHHHpj iSKXFbMikBIfCOyRFjBe7X8kghAXI0KudnnOL/Uhb7vPbhr5hi9/3hWoZGL2DiBicEzl y6qg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature:dmarc-filter:delivered-to; bh=ijfpcilzfPJZNTHFPuu8uJvJ+S5DLQyVa0vjdAbP5ME=; b=Mw+u3NHzDu2nN32W3LZWOuGApLFXia6C4HwDpEbCkrHdvCx4PynsH7Z6XvCTSNKBSx LThhy8q6rdMzaRuvQOuqubYuBjlBHmN00xxyBql6A1FTYqWnZBlfSeT7AY/oBe/2bgSa FXL0RaFuvt16LlpGQEDNRDFRIKJQN3rDXhNPM8s7ceEgNdv7E9thVD4dan4CYEfw40qa 3JDhw8ygzoxX867iX7xZ+3yS0KJMIlNqszUeM7LJ0ErymiaNiuBWcw/PNhsWF91A8r2b ZUKBi10iUEXcR8q+Zc3WNkhyQyILWUaByb/Usfes7O0UMkI88STPUs5WF9liUcpsHr0t CQ9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=DEw4qMOo; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (ip-8-43-85-97.sourceware.org. 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Date: Mon, 17 Apr 2023 14:37:01 -0400 Message-Id: <20230417183701.2249183-11-collison@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230417183701.2249183-1-collison@rivosinc.com> References: <20230417183701.2249183-1-collison@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763450038016588242?= X-GMAIL-MSGID: =?utf-8?q?1763450038016588242?= From: Kevin Lee 2023-04-14 Kevin Lee gcc/testsuite/ChangeLog: * config/riscv/riscv.cc (riscv_autovectorize_vector_modes): Add new vector mode * gcc.target/riscv/rvv/autovec/loop-add-rv32.c: Support 8bit type * gcc.target/riscv/rvv/autovec/loop-add.c: Ditto * gcc.target/riscv/rvv/autovec/loop-and-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-and.c: Ditto * gcc.target/riscv/rvv/autovec/loop-div-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-div.c: Ditto * gcc.target/riscv/rvv/autovec/loop-max-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-max.c: Ditto * gcc.target/riscv/rvv/autovec/loop-min-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-min.c: Ditto * gcc.target/riscv/rvv/autovec/loop-mod-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-mod.c: Ditto * gcc.target/riscv/rvv/autovec/loop-mul-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-mul.c: Ditto * gcc.target/riscv/rvv/autovec/loop-or-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-or.c: Ditto * gcc.target/riscv/rvv/autovec/loop-sub-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-sub.c: Ditto * gcc.target/riscv/rvv/autovec/loop-xor-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-xor.c: Ditto --- gcc/config/riscv/riscv.cc | 1 + .../gcc.target/riscv/rvv/autovec/loop-add-rv32.c | 5 +++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c | 5 +++-- .../gcc.target/riscv/rvv/autovec/loop-and-rv32.c | 5 +++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c | 5 +++-- .../gcc.target/riscv/rvv/autovec/loop-div-rv32.c | 8 +++++--- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c | 8 +++++--- .../gcc.target/riscv/rvv/autovec/loop-max-rv32.c | 7 ++++--- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c | 7 ++++--- .../gcc.target/riscv/rvv/autovec/loop-min-rv32.c | 7 ++++--- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c | 7 ++++--- .../gcc.target/riscv/rvv/autovec/loop-mod-rv32.c | 8 +++++--- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c | 8 +++++--- .../gcc.target/riscv/rvv/autovec/loop-mul-rv32.c | 5 +++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c | 5 +++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c | 5 +++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c | 5 +++-- .../gcc.target/riscv/rvv/autovec/loop-sub-rv32.c | 5 +++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c | 5 +++-- .../gcc.target/riscv/rvv/autovec/loop-xor-rv32.c | 5 +++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c | 5 +++-- 21 files changed, 73 insertions(+), 48 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 9af06d926cf..a2cb83e1916 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7147,6 +7147,7 @@ riscv_autovectorize_vector_modes (vector_modes *modes, bool) modes->safe_push (VNx8QImode); modes->safe_push (VNx4QImode); modes->safe_push (VNx2QImode); + modes->safe_push (VNx1QImode); } else if (riscv_vectorization_factor == RVV_LMUL2) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c index bdc3b6892e9..76f5a3a3ff5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c @@ -10,8 +10,9 @@ dst[i] = a[i] + b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvadd\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvadd\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c index d7f992c7d27..3d1e10bf4e1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c @@ -10,8 +10,9 @@ dst[i] = a[i] + b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvadd\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvadd\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c index eb1ac5b44fd..a4c7abfb0ad 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c @@ -10,8 +10,9 @@ dst[i] = a[i] & b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvand\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvand\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c index ff0cc2a5df7..a795e0968a9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c @@ -10,8 +10,9 @@ dst[i] = a[i] & b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvand\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvand\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c index 21960f265b7..c734bb9c5f0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c @@ -10,8 +10,9 @@ dst[i] = a[i] / b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,6 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvdiv\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vv} 3 } } */ +/* int8_t and int16_t not autovec currently */ +/* { dg-final { scan-assembler-times {\tvdiv\.vv} 2 } } */ +/* { dg-final { scan-assembler-times {\tvdivu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c index bd675b4f6f0..9f57cd91054 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c @@ -10,8 +10,9 @@ dst[i] = a[i] / b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,6 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvdiv\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vv} 3 } } */ +/* int8_t and int16_t not autovec currently */ +/* { dg-final { scan-assembler-times {\tvdiv\.vv} 2 } } */ +/* { dg-final { scan-assembler-times {\tvdivu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c index 751ee9ecaa3..bd825c3dfaa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c @@ -10,8 +10,9 @@ dst[i] = a[i] >= b[i] ? a[i] : b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,5 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvmax\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvmax\.vv} 4 } } */ +/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c index f4dbf3f04fc..729fbe0bc76 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c @@ -10,8 +10,9 @@ dst[i] = a[i] >= b[i] ? a[i] : b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,5 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvmax\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvmax\.vv} 4 } } */ +/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c index e51cf590577..808c2879d86 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c @@ -10,8 +10,9 @@ dst[i] = a[i] <= b[i] ? a[i] : b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,5 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvmin\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvminu\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvmin\.vv} 4 } } */ +/* { dg-final { scan-assembler-times {\tvminu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c index 304f939f6f9..c81ba64223f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c @@ -10,8 +10,9 @@ dst[i] = a[i] <= b[i] ? a[i] : b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,5 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvmin\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvminu\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvmin\.vv} 4 } } */ +/* { dg-final { scan-assembler-times {\tvminu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c index 7c497f6e4cc..9ce4f82b3a8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c @@ -10,8 +10,9 @@ dst[i] = a[i] % b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,6 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvrem\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvremu\.vv} 3 } } */ +/* int8_t and int16_t not autovec currently */ +/* { dg-final { scan-assembler-times {\tvrem\.vv} 2 } } */ +/* { dg-final { scan-assembler-times {\tvremu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c index 7508f4a50d1..46fbff22266 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c @@ -10,8 +10,9 @@ dst[i] = a[i] % b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,6 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvrem\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvremu\.vv} 3 } } */ +/* int8_t and int16_t not autovec currently */ +/* { dg-final { scan-assembler-times {\tvrem\.vv} 2 } } */ +/* { dg-final { scan-assembler-times {\tvremu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c index fd6dcbf9c53..336af62359e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c @@ -10,8 +10,9 @@ dst[i] = a[i] * b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvmul\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvmul\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c index 9fce40890ef..12a17d0da00 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c @@ -10,8 +10,9 @@ dst[i] = a[i] * b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvmul\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvmul\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c index 305d106abd9..b272d893114 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c @@ -10,8 +10,9 @@ dst[i] = a[i] | b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvor\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvor\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c index 501017bc790..52243be3712 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c @@ -10,8 +10,9 @@ dst[i] = a[i] | b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvor\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvor\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c index 7d0a40ec539..6fdce0f7881 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c @@ -10,8 +10,9 @@ dst[i] = a[i] - b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvsub\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvsub\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c index c8900884f83..73369745afc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c @@ -10,8 +10,9 @@ dst[i] = a[i] - b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvsub\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvsub\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c index 6a9ffdb11d5..bd43e60cceb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c @@ -10,8 +10,9 @@ dst[i] = a[i] ^ b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvxor\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvxor\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c index c9d7d7f8a75..cb3adde80c9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c @@ -10,8 +10,9 @@ dst[i] = a[i] ^ b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvxor\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvxor\.vv} 8 } } */