From patchwork Mon Apr 17 18:03:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Machon X-Patchwork-Id: 84385 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2311340vqo; Mon, 17 Apr 2023 11:09:53 -0700 (PDT) X-Google-Smtp-Source: AKy350aYwbSdMWXdoHvkU6qLZ0130rIkj8XJ5AwNrDLBhcUqRuODcoZNhWdFlHTlxdGsmWeUqKXi X-Received: by 2002:aa7:88c4:0:b0:63d:254a:3901 with SMTP id k4-20020aa788c4000000b0063d254a3901mr4204284pff.25.1681754992862; Mon, 17 Apr 2023 11:09:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681754992; cv=none; d=google.com; s=arc-20160816; b=hZwYFQiiXFzhMfzZTP92ymPRD8w2hGsKt+WIHhtpdOyNRHPkkbSBB/KXthTW26DXkE 52xC08SuKPiDlESd088ZOHE8/yYlRDps/u3edFdtnK4dlBuxF2G6vomNstLM7UYREH17 It/XIvnvRP+NYRDcfcMfO+hI0hizzOQYPNEfBxS66QyXSEhHp0f3zeTpGL6yKm/ZzgW+ ujJiOfxPMxR1fT5HjgPuHyVDferq6Euml3rZigwspnfWszciGRRE6y3nKWK+/8wgzbaj 6AyJsBJljUJmjm37Iw9ZsTuLqx7VQCkbg6bZbhcIzBneIJahSitY83AnyNG6Up+KnXxG yl6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=OZAbXFv2wmMj0lFwKQTsi+ObNpCKRa+5WbIB4qzxmNw=; b=dB0j8OwMUl0vmmGIg+RAAxMwVaVsPkAgSs2Cmdo5WMG/rDwol80ghoX5l/vQJAj0Ve SaHQP8Bvj7TpJLnkoLzGSjWu+Of6wg4x0iTeS6Fzgbe6y6l0M6TSS+pUc7GcO3Eqzulp /MVeXkRdVBFaNJvXRL3aGHBi1OOFIb6cBWrkz29HAq9hvxtrIJ7wytWsHR3FwqSj8pI4 mPLpx9TuWyLImdWE8phLpg0nJAIKYZ38J6V3W01czlaWLmSuiskk0zaSAjmKgixmLbwC Xf50ejs1g+XjtCdr1fmxgwjkJ48djT5J1yBhgr22P4OCewlw8py8pFbCJnrx1DbguEtv PthA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=bluhDxYL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id y18-20020aa78f32000000b0063b239ab96asi2130165pfr.360.2023.04.17.11.09.40; Mon, 17 Apr 2023 11:09:52 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=bluhDxYL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230515AbjDQSEB (ORCPT + 99 others); Mon, 17 Apr 2023 14:04:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52732 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230443AbjDQSD7 (ORCPT ); Mon, 17 Apr 2023 14:03:59 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 11056728D for ; Mon, 17 Apr 2023 11:03:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1681754637; x=1713290637; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OzrZ7Z7YiYIaFp4WsXi8lfyg6YwsVetQDS6QQOYXX/4=; b=bluhDxYLMi64BA280NWmJv5FwbBRZB0YBwLx5WiGoLJnlrhwRk655Uix 19g6wI0wTEq1q59Y+f/nBZIjVieE1KkKm33vX9DELFko8AAdIuzqpfPkj 1k86lVA1HQBXEhRvnDollDNKJ7FLz43L4JGOaokhzI6MeLFAODhzKmqOE dZ6h0Y+pn9lpsjHY57E7My522wbAcRfyWrWZL7o8gEIKaP5GpyFY67/kz 86eDaDSm+R47LtGpxhsJnGocei7yaWTY+2iyPSxYlpCiWZk++52FvLEE5 GBVCRW9vPWCrxkrUXZCgi+bByajtbNm+irm9cBOuPnmKqSmpBqST2XpiT A==; X-IronPort-AV: E=Sophos;i="5.99,204,1677567600"; d="scan'208";a="206900840" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Apr 2023 11:03:46 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 17 Apr 2023 11:03:44 -0700 Received: from DEN-LT-70577.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 17 Apr 2023 11:03:42 -0700 From: Daniel Machon To: CC: , , , , , , , Subject: [PATCH 1/7] phy: sparx5-serdes: add registers required for SD/CMU power down Date: Mon, 17 Apr 2023 20:03:29 +0200 Message-ID: <20230417180335.2787494-2-daniel.machon@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230417180335.2787494-1-daniel.machon@microchip.com> References: <20230417180335.2787494-1-daniel.machon@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE, UPPERCASE_50_75 autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763447923677896661?= X-GMAIL-MSGID: =?utf-8?q?1763447923677896661?= Add registers required to configure serdeses and CMUs for initial power down. Signed-off-by: Daniel Machon --- drivers/phy/microchip/sparx5_serdes_regs.h | 106 +++++++++++++++++++++ 1 file changed, 106 insertions(+) diff --git a/drivers/phy/microchip/sparx5_serdes_regs.h b/drivers/phy/microchip/sparx5_serdes_regs.h index b96386a4df5a..d0543fd3dc94 100644 --- a/drivers/phy/microchip/sparx5_serdes_regs.h +++ b/drivers/phy/microchip/sparx5_serdes_regs.h @@ -2149,6 +2149,92 @@ enum sparx5_serdes_target { #define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_GET(x)\ FIELD_GET(SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0, x) +/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_06 */ +#define SD_CMU_CMU_06(t) \ + __REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 4, 0, 1, 4) + +#define SD_CMU_CMU_06_CFG_DISLOS BIT(0) +#define SD_CMU_CMU_06_CFG_DISLOS_SET(x)\ + FIELD_PREP(SD_CMU_CMU_06_CFG_DISLOS, x) +#define SD_CMU_CMU_06_CFG_DISLOS_GET(x)\ + FIELD_GET(SD_CMU_CMU_06_CFG_DISLOS, x) + +#define SD_CMU_CMU_06_CFG_DISLOL BIT(1) +#define SD_CMU_CMU_06_CFG_DISLOL_SET(x)\ + FIELD_PREP(SD_CMU_CMU_06_CFG_DISLOL, x) +#define SD_CMU_CMU_06_CFG_DISLOL_GET(x)\ + FIELD_GET(SD_CMU_CMU_06_CFG_DISLOL, x) + +#define SD_CMU_CMU_06_CFG_DCLOL BIT(2) +#define SD_CMU_CMU_06_CFG_DCLOL_SET(x)\ + FIELD_PREP(SD_CMU_CMU_06_CFG_DCLOL, x) +#define SD_CMU_CMU_06_CFG_DCLOL_GET(x)\ + FIELD_GET(SD_CMU_CMU_06_CFG_DCLOL, x) + +#define SD_CMU_CMU_06_CFG_FORCE_RX_FILT BIT(3) +#define SD_CMU_CMU_06_CFG_FORCE_RX_FILT_SET(x)\ + FIELD_PREP(SD_CMU_CMU_06_CFG_FORCE_RX_FILT, x) +#define SD_CMU_CMU_06_CFG_FORCE_RX_FILT_GET(x)\ + FIELD_GET(SD_CMU_CMU_06_CFG_FORCE_RX_FILT, x) + +#define SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD BIT(4) +#define SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD_SET(x)\ + FIELD_PREP(SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD, x) +#define SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD_GET(x)\ + FIELD_GET(SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD, x) + +#define SD_CMU_CMU_06_CFG_VCO_PD BIT(5) +#define SD_CMU_CMU_06_CFG_VCO_PD_SET(x)\ + FIELD_PREP(SD_CMU_CMU_06_CFG_VCO_PD, x) +#define SD_CMU_CMU_06_CFG_VCO_PD_GET(x)\ + FIELD_GET(SD_CMU_CMU_06_CFG_VCO_PD, x) + +#define SD_CMU_CMU_06_CFG_VCO_CAL_RESETN BIT(6) +#define SD_CMU_CMU_06_CFG_VCO_CAL_RESETN_SET(x)\ + FIELD_PREP(SD_CMU_CMU_06_CFG_VCO_CAL_RESETN, x) +#define SD_CMU_CMU_06_CFG_VCO_CAL_RESETN_GET(x)\ + FIELD_GET(SD_CMU_CMU_06_CFG_VCO_CAL_RESETN, x) + +#define SD_CMU_CMU_06_CFG_VCO_CAL_BYP BIT(7) +#define SD_CMU_CMU_06_CFG_VCO_CAL_BYP_SET(x)\ + FIELD_PREP(SD_CMU_CMU_06_CFG_VCO_CAL_BYP, x) +#define SD_CMU_CMU_06_CFG_VCO_CAL_BYP_GET(x)\ + FIELD_GET(SD_CMU_CMU_06_CFG_VCO_CAL_BYP, x) + +/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_08 */ +#define SD_CMU_CMU_08(t) \ + __REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 12, 0, 1, 4) + +#define SD_CMU_CMU_08_CFG_VFILT2PAD BIT(0) +#define SD_CMU_CMU_08_CFG_VFILT2PAD_SET(x)\ + FIELD_PREP(SD_CMU_CMU_08_CFG_VFILT2PAD, x) +#define SD_CMU_CMU_08_CFG_VFILT2PAD_GET(x)\ + FIELD_GET(SD_CMU_CMU_08_CFG_VFILT2PAD, x) + +#define SD_CMU_CMU_08_CFG_EN_DUMMY BIT(1) +#define SD_CMU_CMU_08_CFG_EN_DUMMY_SET(x)\ + FIELD_PREP(SD_CMU_CMU_08_CFG_EN_DUMMY, x) +#define SD_CMU_CMU_08_CFG_EN_DUMMY_GET(x)\ + FIELD_GET(SD_CMU_CMU_08_CFG_EN_DUMMY, x) + +#define SD_CMU_CMU_08_CFG_CK_TREE_PD BIT(2) +#define SD_CMU_CMU_08_CFG_CK_TREE_PD_SET(x)\ + FIELD_PREP(SD_CMU_CMU_08_CFG_CK_TREE_PD, x) +#define SD_CMU_CMU_08_CFG_CK_TREE_PD_GET(x)\ + FIELD_GET(SD_CMU_CMU_08_CFG_CK_TREE_PD, x) + +#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN BIT(3) +#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_SET(x)\ + FIELD_PREP(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN, x) +#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_GET(x)\ + FIELD_GET(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN, x) + +#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN BIT(4) +#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN_SET(x)\ + FIELD_PREP(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN, x) +#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN_GET(x)\ + FIELD_GET(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN, x) + /* SD10G_CMU_TARGET:CMU_GRP_1:CMU_09 */ #define SD_CMU_CMU_09(t) __REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 16, 0, 1, 4) @@ -2443,6 +2529,16 @@ enum sparx5_serdes_target { #define SD_LANE_SD_LANE_STAT_DBG_OBS_GET(x)\ FIELD_GET(SD_LANE_SD_LANE_STAT_DBG_OBS, x) +/* SD_LANE_TARGET:SD_PWR_CFG:QUIET_MODE_6G */ +#define SD_LANE_QUIET_MODE_6G(t) \ + __REG(TARGET_SD_LANE, t, 25, 24, 0, 1, 8, 4, 0, 1, 4) + +#define SD_LANE_QUIET_MODE_6G_QUIET_MODE GENMASK(24, 0) +#define SD_LANE_QUIET_MODE_6G_QUIET_MODE_SET(x)\ + FIELD_PREP(SD_LANE_QUIET_MODE_6G_QUIET_MODE, x) +#define SD_LANE_QUIET_MODE_6G_QUIET_MODE_GET(x)\ + FIELD_GET(SD_LANE_QUIET_MODE_6G_QUIET_MODE, x) + /* SD_LANE_TARGET:CFG_STAT_FX100:MISC */ #define SD_LANE_MISC(t) __REG(TARGET_SD_LANE, t, 25, 56, 0, 1, 56, 0, 0, 1, 4) @@ -2692,4 +2788,14 @@ enum sparx5_serdes_target { #define SD_LANE_25G_SD_LANE_STAT_DBG_OBS_GET(x)\ FIELD_GET(SD_LANE_25G_SD_LANE_STAT_DBG_OBS, x) +/* SD25G_CFG_TARGET:SD_PWR_CFG:QUIET_MODE_6G */ +#define SD_LANE_25G_QUIET_MODE_6G(t) \ + __REG(TARGET_SD_LANE_25G, t, 8, 28, 0, 1, 8, 4, 0, 1, 4) + +#define SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE GENMASK(24, 0) +#define SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE_SET(x)\ + FIELD_PREP(SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE, x) +#define SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE_GET(x)\ + FIELD_GET(SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE, x) + #endif /* _SPARX5_SERDES_REGS_H_ */ From patchwork Mon Apr 17 18:03:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Machon X-Patchwork-Id: 84383 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2310582vqo; Mon, 17 Apr 2023 11:08:42 -0700 (PDT) X-Google-Smtp-Source: AKy350aPnaEsI22AugHXDNPajW6OpSjP8QXiyTCwp2JkN6GBB5UpEse7dazztXuTtiV0GtPlWKgO X-Received: by 2002:a17:902:6bc9:b0:1a5:2540:729 with SMTP id m9-20020a1709026bc900b001a525400729mr12534371plt.56.1681754922034; Mon, 17 Apr 2023 11:08:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681754922; cv=none; d=google.com; s=arc-20160816; b=d55fDARRQb5hsGkwA4sDQJVpg50m2rOM0ZWGANKM5b6/pG5+e9tT5P38UvSVMEQzXe 8Dp4kTAZyQGnUFA549yZ1C+N8/EpuxT6Hhb2IRfQOVtBPkZLLlz3dWsAtH825wPyxFUN VXWzywz8WM1gjh7gagQnVuVlvRP7dCpSYnuFeu7TKgeRJ4LhLfGZct89LGxt7WLwF4hM zUIAsdBKVjEnl1Y+3/yWa/oqk9Rp6wnxIJ3w9oq3zt4WuHlFc5YmsvkXd3eCHgJOaOTc YEpAk5H+RtQy4AWr+vnj+1zh2yB6N1PBG225ekqPJj8t14cNdJE6QuSHL+EAWfxCikE1 57EA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=gFiohJLtG0OaS+u5q2JhQq09FXUgFehuLa7yI3AinAs=; b=wlTl8XEh41e7Cxa3rbqT4JYc0Cd9P7whUiecCrh3AgPhgIgeZcRxn37otTX3J7h/5D 5aONCk1IKBCkAVeVsgQwJ31caLUu0NviCV/LvcqEzY6VhY0QW7CQkp1afj+AF1NYY7ue HzME5Xer7sTJlOxpjJxt4LdVWMvxOAtbarG/gfNXnjUZZQxNJdZgLk+HOuADhr5iz0SR TFrg7HJob36pQxWsl0o+8JCqIYz+n1A2+g9i4Sbq43edW14eWX5wKvZMyLwoZ2kWmmtb +07l56e0UwN0Cq+znkeVFEIwbtSbowr3M/zQ8GdUSf+ulYe+62yzXSp/ESs8Z2vFRpnt Z6+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=Q5gTHLuw; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id be7-20020a170902aa0700b001a6fce1d951si212773plb.377.2023.04.17.11.08.29; Mon, 17 Apr 2023 11:08:42 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=Q5gTHLuw; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230466AbjDQSDw (ORCPT + 99 others); Mon, 17 Apr 2023 14:03:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52502 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230443AbjDQSDs (ORCPT ); Mon, 17 Apr 2023 14:03:48 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 363B355BE for ; Mon, 17 Apr 2023 11:03:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1681754626; x=1713290626; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZWQh9zj/V577BO9z6BgacIjliHqRr9/mCbIBPB/bemc=; b=Q5gTHLuw6MuF/WZGkGOAZ+RocCVc0N9r5thkidfKV08dJnBrMp2Y468x WTtM9SwjBbL2933oyVpc6pKiTDNZwT3dDlJ+VK0sbc1X6kBPIjdJU81v1 +jv4jitgzMLGtnDWgYmUzQ+Pf9LS86xwQTaPdUHXsKa/zW8cCafx6NIth jvgpJA+T1RC9BiDunKqZFFgBgm90F98cnBBe2VcCbaBtKbcDEwu85UGGr l2VzVggrU+Re5993eAEe6x3sDeaICRtcR+YLbRJC3c0S/V73inXm0f6Zr hM2n+fL3tOg6reKvhXIgslHORX7YpwdQRog0JlIoIOd0d54Ead3a+A7WK g==; X-IronPort-AV: E=Sophos;i="5.99,204,1677567600"; d="scan'208";a="221268900" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Apr 2023 11:03:46 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 17 Apr 2023 11:03:46 -0700 Received: from DEN-LT-70577.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 17 Apr 2023 11:03:44 -0700 From: Daniel Machon To: CC: , , , , , , , Subject: [PATCH 2/7] phy: sparx5-serdes: configure optimal quiet mode for serdes lanes Date: Mon, 17 Apr 2023 20:03:30 +0200 Message-ID: <20230417180335.2787494-3-daniel.machon@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230417180335.2787494-1-daniel.machon@microchip.com> References: <20230417180335.2787494-1-daniel.machon@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763447849154433881?= X-GMAIL-MSGID: =?utf-8?q?1763447849154433881?= All the serdes lanes of the sparx5 will transition between normal mode and quiet mode, depending on activity. Make sure that the quiet mode is configured optimally for all lanes initially. Although not much, this will save a small amount of power. Signed-off-by: Daniel Machon --- drivers/phy/microchip/sparx5_serdes.c | 32 ++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/drivers/phy/microchip/sparx5_serdes.c b/drivers/phy/microchip/sparx5_serdes.c index ab1b0986aa67..6ba058b2482f 100644 --- a/drivers/phy/microchip/sparx5_serdes.c +++ b/drivers/phy/microchip/sparx5_serdes.c @@ -26,6 +26,9 @@ #define SPX5_SERDES_10G_START 13 #define SPX5_SERDES_25G_START 25 +/* Optimal power settings from GUC */ +#define SPX5_SERDES_QUIET_MODE_VAL 0x01ef4e0c + enum sparx5_10g28cmu_mode { SPX5_SD10G28_CMU_MAIN = 0, SPX5_SD10G28_CMU_AUX1 = 1, @@ -1899,7 +1902,7 @@ static int sparx5_sd10g28_config(struct sparx5_serdes_macro *macro, bool reset) static int sparx5_serdes_power_save(struct sparx5_serdes_macro *macro, u32 pwdn) { struct sparx5_serdes_private *priv = macro->priv; - void __iomem *sd_inst; + void __iomem *sd_inst, *sd_lane_inst; if (macro->serdestype == SPX5_SDT_6G) sd_inst = sdx5_inst_get(priv, TARGET_SD6G_LANE, macro->stpidx); @@ -1909,12 +1912,36 @@ static int sparx5_serdes_power_save(struct sparx5_serdes_macro *macro, u32 pwdn) sd_inst = sdx5_inst_get(priv, TARGET_SD25G_LANE, macro->stpidx); if (macro->serdestype == SPX5_SDT_25G) { + sd_lane_inst = sdx5_inst_get(priv, TARGET_SD_LANE_25G, + macro->stpidx); + /* Take serdes out of reset */ + sdx5_inst_rmw(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(0), + SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST, sd_lane_inst, + SD_LANE_25G_SD_LANE_CFG(0)); + + /* Configure optimal settings for quiet mode */ + sdx5_inst_rmw(SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE_SET(SPX5_SERDES_QUIET_MODE_VAL), + SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE, + sd_lane_inst, SD_LANE_25G_QUIET_MODE_6G(0)); + sdx5_inst_rmw(SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER_SET(pwdn), SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER, sd_inst, SD25G_LANE_LANE_04(0)); } else { /* 6G and 10G */ + sd_lane_inst = sdx5_inst_get(priv, TARGET_SD_LANE, macro->sidx); + + /* Take serdes out of reset */ + sdx5_inst_rmw(SD_LANE_SD_LANE_CFG_EXT_CFG_RST_SET(0), + SD_LANE_SD_LANE_CFG_EXT_CFG_RST, sd_lane_inst, + SD_LANE_SD_LANE_CFG(0)); + + /* Configure optimal settings for quiet mode */ + sdx5_inst_rmw(SD_LANE_QUIET_MODE_6G_QUIET_MODE_SET(SPX5_SERDES_QUIET_MODE_VAL), + SD_LANE_QUIET_MODE_6G_QUIET_MODE, sd_lane_inst, + SD_LANE_QUIET_MODE_6G(0)); + sdx5_inst_rmw(SD10G_LANE_LANE_06_CFG_PD_DRIVER_SET(pwdn), SD10G_LANE_LANE_06_CFG_PD_DRIVER, sd_inst, @@ -2308,6 +2335,9 @@ static int sparx5_phy_create(struct sparx5_serdes_private *priv, phy_set_drvdata(*phy, macro); + /* Power off serdes by default */ + sparx5_serdes_power_off(*phy); + return 0; } From patchwork Mon Apr 17 18:03:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Machon X-Patchwork-Id: 84386 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2311369vqo; Mon, 17 Apr 2023 11:09:55 -0700 (PDT) X-Google-Smtp-Source: AKy350ZJYq70GYZuUc+NqH6Rlm/yhWvHYboYqWuFothxfLZuFuIyqEkbb2CS8pF8FECUaVOdlQoQ X-Received: by 2002:a17:902:efd4:b0:1a2:9e64:bc5e with SMTP id ja20-20020a170902efd400b001a29e64bc5emr12187251plb.39.1681754995345; Mon, 17 Apr 2023 11:09:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681754995; cv=none; d=google.com; s=arc-20160816; b=lG5hXqaoK1gkNUI+5+eHmoO/risVaMFPCMHE1FMdR9vd1Yy/iKcPqf+pg1mXMm2hK0 1w/yKwOdBXVlKzJ+EZjWC6VIquMAmKO7T+IDDl2Pob4z//maSe75isxsIjJuttBYX77/ 6dwxrg7n6mqeh3gOO7TzqKkhdcPBgnv+vZCuVfX+IceHKCojycvZbJtImUF427SN7jaz htx4DqYOrnh+u+0ewiUuKYmu8Q7cgzIYBDgbHI91nUJM9Huj+fqyh/qTLrghUx25fwiy h6jUGrivQSYJpNVmX4jXsjK2mZ15eqg4eTJSV6tpurKpIVJIVxhkvZ8YR9uzTqgFNlMI Mfsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=M5U5kvhGhmTDPPsD0dEyoRZyzOrPRU90yGMs0tWPcyA=; b=Ovpj+GcqY1Dgx0QW33R+E0EqctuOc/AuizzeyXpw3Ydklh7HzTLfRHOSkauD1xyLy1 sOnTJBOVTQH/9ktVSo42I2MIHXSl0QjdSUh+dOacRtlQZ7ETE0u5M9fhpoAHrMmPPrCh rZmrsiT1Dws7YWiGE2UlotkyYKn1vicdiGgOsBXALjMzId1A8DUncbiCAjMEYWTgVF/K fs+qwtYb3GC8qwCpOJINO+V7BZXH5jE+OqcOzNBdXgVtmpuHkfHw5olTPtY+/49FxXHx exuDnmZ5KDcigPAciXV3yHTdxuVRTN6jv6zipDvVKImUjz7KDrPQOWtY1DGuCcxWx77W +86Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=yAXVk3YW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id f8-20020a17090274c800b001a1abc91980si11760224plt.211.2023.04.17.11.09.42; Mon, 17 Apr 2023 11:09:55 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=yAXVk3YW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231171AbjDQSEF (ORCPT + 99 others); Mon, 17 Apr 2023 14:04:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52674 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230492AbjDQSEA (ORCPT ); Mon, 17 Apr 2023 14:04:00 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6DDD28692 for ; Mon, 17 Apr 2023 11:03:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1681754638; x=1713290638; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3uLKkGcs/8EltrBSlra1gjG4qIRlejr3L2TWbWqYgXw=; b=yAXVk3YW0lXImILOqG3yT8JxwQ/0VrHSP2nC63cIYkOMHRTcHdYWQ/U1 5TlNkAlq2yv30Yuqz+xTKnPwC4BDxyu2E3nA2hIL6xWvYA6XCZyA/y9lu 0+S1Z0kl7dFBr8WJ3zb3QAn1fZxX6J5zDmQFglarW0xetfYUeHB41UpqQ Hcog6/adrpJ5Xg32MNQcKmNgjLkh1GOFyV5XEb6mVofo1GHl6xXkx2Iaf f8JBRQmXBIO3EIQM5wne8ynsHtr3F+bn3NlCjF3wRiLIvu1LKQZziFFDn dg0xo9jZZAOGC0PAuR+X/b9XQtcrF45dudmI1ouvQMcnUnE0vWCJJvw59 Q==; X-IronPort-AV: E=Sophos;i="5.99,204,1677567600"; d="scan'208";a="147469770" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Apr 2023 11:03:57 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 17 Apr 2023 11:03:48 -0700 Received: from DEN-LT-70577.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 17 Apr 2023 11:03:46 -0700 From: Daniel Machon To: CC: , , , , , , , Subject: [PATCH 3/7] phy: sparx5-serdes: reorder CMU functions Date: Mon, 17 Apr 2023 20:03:31 +0200 Message-ID: <20230417180335.2787494-4-daniel.machon@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230417180335.2787494-1-daniel.machon@microchip.com> References: <20230417180335.2787494-1-daniel.machon@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763447925991479173?= X-GMAIL-MSGID: =?utf-8?q?1763447925991479173?= Reorder CMU functions, as some of them are now required by the serdes functions. No functional changes. Signed-off-by: Daniel Machon --- drivers/phy/microchip/sparx5_serdes.c | 306 +++++++++++++------------- 1 file changed, 153 insertions(+), 153 deletions(-) diff --git a/drivers/phy/microchip/sparx5_serdes.c b/drivers/phy/microchip/sparx5_serdes.c index 6ba058b2482f..d8620e0fae7b 100644 --- a/drivers/phy/microchip/sparx5_serdes.c +++ b/drivers/phy/microchip/sparx5_serdes.c @@ -925,6 +925,159 @@ static void sparx5_sd10g28_get_params(struct sparx5_serdes_macro *macro, *params = init; } +static int sparx5_cmu_apply_cfg(struct sparx5_serdes_private *priv, + u32 cmu_idx, + void __iomem *cmu_tgt, + void __iomem *cmu_cfg_tgt, + u32 spd10g) +{ + void __iomem **regs = priv->regs; + struct device *dev = priv->dev; + int value; + + cmu_tgt = sdx5_inst_get(priv, TARGET_SD_CMU, cmu_idx); + cmu_cfg_tgt = sdx5_inst_get(priv, TARGET_SD_CMU_CFG, cmu_idx); + + if (cmu_idx == 1 || cmu_idx == 4 || cmu_idx == 7 || + cmu_idx == 10 || cmu_idx == 13) { + spd10g = 0; + } + + sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(1), + SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, + cmu_cfg_tgt, + SD_CMU_CFG_SD_CMU_CFG(cmu_idx)); + + sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(0), + SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, + cmu_cfg_tgt, + SD_CMU_CFG_SD_CMU_CFG(cmu_idx)); + + sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(1), + SD_CMU_CFG_SD_CMU_CFG_CMU_RST, + cmu_cfg_tgt, + SD_CMU_CFG_SD_CMU_CFG(cmu_idx)); + + sdx5_inst_rmw(SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_SET(0x1) | + SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_SET(0x1) | + SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_SET(0x1) | + SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_SET(0x1) | + SD_CMU_CMU_45_R_EN_RATECHG_CTRL_SET(0x0), + SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT | + SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT | + SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT | + SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT | + SD_CMU_CMU_45_R_EN_RATECHG_CTRL, + cmu_tgt, + SD_CMU_CMU_45(cmu_idx)); + + sdx5_inst_rmw(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_SET(0), + SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0, + cmu_tgt, + SD_CMU_CMU_47(cmu_idx)); + + sdx5_inst_rmw(SD_CMU_CMU_1B_CFG_RESERVE_7_0_SET(0), + SD_CMU_CMU_1B_CFG_RESERVE_7_0, + cmu_tgt, + SD_CMU_CMU_1B(cmu_idx)); + + sdx5_inst_rmw(SD_CMU_CMU_0D_CFG_JC_BYP_SET(0x1), + SD_CMU_CMU_0D_CFG_JC_BYP, + cmu_tgt, + SD_CMU_CMU_0D(cmu_idx)); + + sdx5_inst_rmw(SD_CMU_CMU_1F_CFG_VTUNE_SEL_SET(1), + SD_CMU_CMU_1F_CFG_VTUNE_SEL, + cmu_tgt, + SD_CMU_CMU_1F(cmu_idx)); + + sdx5_inst_rmw(SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_SET(3), + SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0, + cmu_tgt, + SD_CMU_CMU_00(cmu_idx)); + + sdx5_inst_rmw(SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_SET(3), + SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0, + cmu_tgt, + SD_CMU_CMU_05(cmu_idx)); + + sdx5_inst_rmw(SD_CMU_CMU_30_R_PLL_DLOL_EN_SET(1), + SD_CMU_CMU_30_R_PLL_DLOL_EN, + cmu_tgt, + SD_CMU_CMU_30(cmu_idx)); + + sdx5_inst_rmw(SD_CMU_CMU_09_CFG_SW_10G_SET(spd10g), + SD_CMU_CMU_09_CFG_SW_10G, + cmu_tgt, + SD_CMU_CMU_09(cmu_idx)); + + sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(0), + SD_CMU_CFG_SD_CMU_CFG_CMU_RST, + cmu_cfg_tgt, + SD_CMU_CFG_SD_CMU_CFG(cmu_idx)); + + msleep(20); + + sdx5_inst_rmw(SD_CMU_CMU_44_R_PLL_RSTN_SET(0), + SD_CMU_CMU_44_R_PLL_RSTN, + cmu_tgt, + SD_CMU_CMU_44(cmu_idx)); + + sdx5_inst_rmw(SD_CMU_CMU_44_R_PLL_RSTN_SET(1), + SD_CMU_CMU_44_R_PLL_RSTN, + cmu_tgt, + SD_CMU_CMU_44(cmu_idx)); + + msleep(20); + + value = readl(sdx5_addr(regs, SD_CMU_CMU_E0(cmu_idx))); + value = SD_CMU_CMU_E0_PLL_LOL_UDL_GET(value); + + if (value) { + dev_err(dev, "CMU PLL Loss of Lock: 0x%x\n", value); + return -EINVAL; + } + sdx5_inst_rmw(SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_SET(0), + SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD, + cmu_tgt, + SD_CMU_CMU_0D(cmu_idx)); + return 0; +} + +static int sparx5_cmu_cfg(struct sparx5_serdes_private *priv, u32 cmu_idx) +{ + void __iomem *cmu_tgt, *cmu_cfg_tgt; + u32 spd10g = 1; + + if (cmu_idx == 1 || cmu_idx == 4 || cmu_idx == 7 || + cmu_idx == 10 || cmu_idx == 13) { + spd10g = 0; + } + + cmu_tgt = sdx5_inst_get(priv, TARGET_SD_CMU, cmu_idx); + cmu_cfg_tgt = sdx5_inst_get(priv, TARGET_SD_CMU_CFG, cmu_idx); + + return sparx5_cmu_apply_cfg(priv, cmu_idx, cmu_tgt, cmu_cfg_tgt, spd10g); +} + +static int sparx5_serdes_cmu_enable(struct sparx5_serdes_private *priv) +{ + int idx, err = 0; + + if (!priv->cmu_enabled) { + for (idx = 0; idx < SPX5_CMU_MAX; idx++) { + err = sparx5_cmu_cfg(priv, idx); + if (err) { + dev_err(priv->dev, "CMU %u, error: %d\n", idx, err); + goto leave; + } + } + priv->cmu_enabled = true; + } +leave: + return err; +} + static void sparx5_sd25g28_reset(void __iomem *regs[], struct sparx5_sd25g28_params *params, u32 sd_index) @@ -1966,159 +2119,6 @@ static int sparx5_serdes_clock_config(struct sparx5_serdes_macro *macro) return 0; } -static int sparx5_cmu_apply_cfg(struct sparx5_serdes_private *priv, - u32 cmu_idx, - void __iomem *cmu_tgt, - void __iomem *cmu_cfg_tgt, - u32 spd10g) -{ - void __iomem **regs = priv->regs; - struct device *dev = priv->dev; - int value; - - cmu_tgt = sdx5_inst_get(priv, TARGET_SD_CMU, cmu_idx); - cmu_cfg_tgt = sdx5_inst_get(priv, TARGET_SD_CMU_CFG, cmu_idx); - - if (cmu_idx == 1 || cmu_idx == 4 || cmu_idx == 7 || - cmu_idx == 10 || cmu_idx == 13) { - spd10g = 0; - } - - sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(1), - SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, - cmu_cfg_tgt, - SD_CMU_CFG_SD_CMU_CFG(cmu_idx)); - - sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(0), - SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, - cmu_cfg_tgt, - SD_CMU_CFG_SD_CMU_CFG(cmu_idx)); - - sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(1), - SD_CMU_CFG_SD_CMU_CFG_CMU_RST, - cmu_cfg_tgt, - SD_CMU_CFG_SD_CMU_CFG(cmu_idx)); - - sdx5_inst_rmw(SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_SET(0x1) | - SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_SET(0x1) | - SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_SET(0x1) | - SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_SET(0x1) | - SD_CMU_CMU_45_R_EN_RATECHG_CTRL_SET(0x0), - SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT | - SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT | - SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT | - SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT | - SD_CMU_CMU_45_R_EN_RATECHG_CTRL, - cmu_tgt, - SD_CMU_CMU_45(cmu_idx)); - - sdx5_inst_rmw(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_SET(0), - SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0, - cmu_tgt, - SD_CMU_CMU_47(cmu_idx)); - - sdx5_inst_rmw(SD_CMU_CMU_1B_CFG_RESERVE_7_0_SET(0), - SD_CMU_CMU_1B_CFG_RESERVE_7_0, - cmu_tgt, - SD_CMU_CMU_1B(cmu_idx)); - - sdx5_inst_rmw(SD_CMU_CMU_0D_CFG_JC_BYP_SET(0x1), - SD_CMU_CMU_0D_CFG_JC_BYP, - cmu_tgt, - SD_CMU_CMU_0D(cmu_idx)); - - sdx5_inst_rmw(SD_CMU_CMU_1F_CFG_VTUNE_SEL_SET(1), - SD_CMU_CMU_1F_CFG_VTUNE_SEL, - cmu_tgt, - SD_CMU_CMU_1F(cmu_idx)); - - sdx5_inst_rmw(SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_SET(3), - SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0, - cmu_tgt, - SD_CMU_CMU_00(cmu_idx)); - - sdx5_inst_rmw(SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_SET(3), - SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0, - cmu_tgt, - SD_CMU_CMU_05(cmu_idx)); - - sdx5_inst_rmw(SD_CMU_CMU_30_R_PLL_DLOL_EN_SET(1), - SD_CMU_CMU_30_R_PLL_DLOL_EN, - cmu_tgt, - SD_CMU_CMU_30(cmu_idx)); - - sdx5_inst_rmw(SD_CMU_CMU_09_CFG_SW_10G_SET(spd10g), - SD_CMU_CMU_09_CFG_SW_10G, - cmu_tgt, - SD_CMU_CMU_09(cmu_idx)); - - sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(0), - SD_CMU_CFG_SD_CMU_CFG_CMU_RST, - cmu_cfg_tgt, - SD_CMU_CFG_SD_CMU_CFG(cmu_idx)); - - msleep(20); - - sdx5_inst_rmw(SD_CMU_CMU_44_R_PLL_RSTN_SET(0), - SD_CMU_CMU_44_R_PLL_RSTN, - cmu_tgt, - SD_CMU_CMU_44(cmu_idx)); - - sdx5_inst_rmw(SD_CMU_CMU_44_R_PLL_RSTN_SET(1), - SD_CMU_CMU_44_R_PLL_RSTN, - cmu_tgt, - SD_CMU_CMU_44(cmu_idx)); - - msleep(20); - - value = readl(sdx5_addr(regs, SD_CMU_CMU_E0(cmu_idx))); - value = SD_CMU_CMU_E0_PLL_LOL_UDL_GET(value); - - if (value) { - dev_err(dev, "CMU PLL Loss of Lock: 0x%x\n", value); - return -EINVAL; - } - sdx5_inst_rmw(SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_SET(0), - SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD, - cmu_tgt, - SD_CMU_CMU_0D(cmu_idx)); - return 0; -} - -static int sparx5_cmu_cfg(struct sparx5_serdes_private *priv, u32 cmu_idx) -{ - void __iomem *cmu_tgt, *cmu_cfg_tgt; - u32 spd10g = 1; - - if (cmu_idx == 1 || cmu_idx == 4 || cmu_idx == 7 || - cmu_idx == 10 || cmu_idx == 13) { - spd10g = 0; - } - - cmu_tgt = sdx5_inst_get(priv, TARGET_SD_CMU, cmu_idx); - cmu_cfg_tgt = sdx5_inst_get(priv, TARGET_SD_CMU_CFG, cmu_idx); - - return sparx5_cmu_apply_cfg(priv, cmu_idx, cmu_tgt, cmu_cfg_tgt, spd10g); -} - -static int sparx5_serdes_cmu_enable(struct sparx5_serdes_private *priv) -{ - int idx, err = 0; - - if (!priv->cmu_enabled) { - for (idx = 0; idx < SPX5_CMU_MAX; idx++) { - err = sparx5_cmu_cfg(priv, idx); - if (err) { - dev_err(priv->dev, "CMU %u, error: %d\n", idx, err); - goto leave; - } - } - priv->cmu_enabled = true; - } -leave: - return err; -} - static int sparx5_serdes_get_serdesmode(phy_interface_t portmode, int speed) { switch (portmode) { From patchwork Mon Apr 17 18:03:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Machon X-Patchwork-Id: 84393 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2321088vqo; Mon, 17 Apr 2023 11:27:01 -0700 (PDT) X-Google-Smtp-Source: AKy350bq4TLGvFGIEa8s5yIQq1Nlllmy3p4iPHnAekP8428sDsH/kJ3oXPBRaN6CdIuif4r7LGiF X-Received: by 2002:a05:6a00:23d3:b0:63b:608a:eeaf with SMTP id g19-20020a056a0023d300b0063b608aeeafmr19078410pfc.14.1681756021007; Mon, 17 Apr 2023 11:27:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681756020; cv=none; d=google.com; s=arc-20160816; b=xoiRbcz0jtf9A+kcE+ZXfL1W6VTUO1ABmyRVCHMPcc58jlEPUo43Hcu7g0nXkOZS6x 7cKejn9Fgy9+5PdLbakiosPrCLsm4sfojuHLoVcVobnL4STgn6KYNqA9STQgQTMPg0BY M0i7XsiAbpMf2xoE4S18WpvUugFQHwqgowbxU8RYZ3lsMd0Eu0gh02/j8ZWOBRfFs7LL c6bpVKA3dpFZjPCZ/1z2Z8CNli++eGX3I9Txlnr8os8P6FJ9eBboTvUojRxMFmQf0wQU sfFQwMXAHkz8V1k9uDh4qgQOM7LFy2TbJhs2JDOfmz/aXwM2tW9FqYlGPZVy8fDIQV/f fdXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=S8RklCwxO547zxMy+O2kwFqWB1go3TaBp771ZLIXR/M=; b=K286HTaQQStRtC6FFLcExRqIF3AJlPUrxZwYddGMLANDV+vmJwRlWRzfCMEmz3dNL0 yCKTMrRqE2/DUAnJXwpGkznj3acLNVJbvwBDVjbtsVEPNxYwP4RGn71A2C4/YRurOMzT IPT+BZ6/vN7Stdi5lVtrs4ddi9QPzuNw+QT0s4DwenHH5/IIRC/yPTTC2HIx7Rrem0Wy +L20HtnpvHjb7CYPoifqHZNgeRRegnOe6lhhIP28EpsQpvVii2LgjX43KPwHiVMEJqdM j+21Pzz2l0j/yPfYHh3L0jeCpFsvUUc5kIu01YlU0NMab9y3ICvbVMXcXdCXLn4nA1v0 8ayA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=lWnfQRkj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id j19-20020a635953000000b0051b2ba6c511si12620842pgm.568.2023.04.17.11.26.45; Mon, 17 Apr 2023 11:27:00 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=lWnfQRkj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231216AbjDQSEL (ORCPT + 99 others); Mon, 17 Apr 2023 14:04:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53036 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231182AbjDQSEG (ORCPT ); Mon, 17 Apr 2023 14:04:06 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 143065269 for ; Mon, 17 Apr 2023 11:04:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1681754639; x=1713290639; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KoHza1vejrzAkyGsjA2yudMh/oMxUYOS4fEMrrvFgz8=; b=lWnfQRkjgkn/cxKHQStTXy5UiohWfe5I/gzcwWh9eWqiMdw3MsckHVV1 sxXg84y29Ym4be4Zj5DF8neTpGsYsDuzxii6WTjaCN5S6fdvZQXZAV1+o OEju2eLJ7GJU0vrBiflMWfIKkd4OaOCDBee2GInnec4Oq5/cgWXdElZF8 O9FGqiPGAGaS4JVljVwU/dXpm8sEeRR/uJlV1aHBJLJky8qChetJmAg15 tGheW+1KfFuU5WI348wn2B4QOHHc74g69lXVUb9Qg6Su+VbE1Wvb5U6SP C8UVuj/VR0CLXiX78AbCtdReF/L97hIHpjRM6KIrRE0Jw/k/bAVxSKRph A==; X-IronPort-AV: E=Sophos;i="5.99,204,1677567600"; d="scan'208";a="147469774" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Apr 2023 11:03:57 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 17 Apr 2023 11:03:50 -0700 Received: from DEN-LT-70577.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 17 Apr 2023 11:03:48 -0700 From: Daniel Machon To: CC: , , , , , , , Subject: [PATCH 4/7] phy: sparx5-serdes: power down all CMUs by default Date: Mon, 17 Apr 2023 20:03:32 +0200 Message-ID: <20230417180335.2787494-5-daniel.machon@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230417180335.2787494-1-daniel.machon@microchip.com> References: <20230417180335.2787494-1-daniel.machon@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763449001680556641?= X-GMAIL-MSGID: =?utf-8?q?1763449001680556641?= All CMUs are powered up initially. This uses needless power. This patch makes sure all CMUs are powered down by default. This involves configuring a number reference clock and power-down registers of the CMU. Individual CMUs are later powered up, when the serdes lanes are configured. Signed-off-by: Daniel Machon --- drivers/phy/microchip/sparx5_serdes.c | 51 +++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/drivers/phy/microchip/sparx5_serdes.c b/drivers/phy/microchip/sparx5_serdes.c index d8620e0fae7b..0e9db7b36b60 100644 --- a/drivers/phy/microchip/sparx5_serdes.c +++ b/drivers/phy/microchip/sparx5_serdes.c @@ -1078,6 +1078,54 @@ static int sparx5_serdes_cmu_enable(struct sparx5_serdes_private *priv) return err; } +static void sparx5_serdes_cmu_power_off(struct sparx5_serdes_private *priv) +{ + void __iomem *cmu_inst, *cmu_cfg_inst; + int i; + + /* Power down each CMU */ + for (i = 0; i < SPX5_CMU_MAX; i++) { + cmu_inst = sdx5_inst_get(priv, TARGET_SD_CMU, i); + cmu_cfg_inst = sdx5_inst_get(priv, TARGET_SD_CMU_CFG, i); + + sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(0), + SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, cmu_cfg_inst, + SD_CMU_CFG_SD_CMU_CFG(0)); + + sdx5_inst_rmw(SD_CMU_CMU_05_CFG_REFCK_TERM_EN_SET(0), + SD_CMU_CMU_05_CFG_REFCK_TERM_EN, cmu_inst, + SD_CMU_CMU_05(0)); + + sdx5_inst_rmw(SD_CMU_CMU_09_CFG_EN_TX_CK_DN_SET(0), + SD_CMU_CMU_09_CFG_EN_TX_CK_DN, cmu_inst, + SD_CMU_CMU_09(0)); + + sdx5_inst_rmw(SD_CMU_CMU_06_CFG_VCO_PD_SET(1), + SD_CMU_CMU_06_CFG_VCO_PD, cmu_inst, + SD_CMU_CMU_06(0)); + + sdx5_inst_rmw(SD_CMU_CMU_09_CFG_EN_TX_CK_UP_SET(0), + SD_CMU_CMU_09_CFG_EN_TX_CK_UP, cmu_inst, + SD_CMU_CMU_09(0)); + + sdx5_inst_rmw(SD_CMU_CMU_08_CFG_CK_TREE_PD_SET(1), + SD_CMU_CMU_08_CFG_CK_TREE_PD, cmu_inst, + SD_CMU_CMU_08(0)); + + sdx5_inst_rmw(SD_CMU_CMU_0D_CFG_REFCK_PD_SET(1) | + SD_CMU_CMU_0D_CFG_PD_DIV64_SET(1) | + SD_CMU_CMU_0D_CFG_PD_DIV66_SET(1), + SD_CMU_CMU_0D_CFG_REFCK_PD | + SD_CMU_CMU_0D_CFG_PD_DIV64 | + SD_CMU_CMU_0D_CFG_PD_DIV66, cmu_inst, + SD_CMU_CMU_0D(0)); + + sdx5_inst_rmw(SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD_SET(1), + SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD, cmu_inst, + SD_CMU_CMU_06(0)); + } +} + static void sparx5_sd25g28_reset(void __iomem *regs[], struct sparx5_sd25g28_params *params, u32 sd_index) @@ -2521,6 +2569,9 @@ static int sparx5_serdes_probe(struct platform_device *pdev) return err; } + /* Power down all CMUs by default */ + sparx5_serdes_cmu_power_off(priv); + provider = devm_of_phy_provider_register(priv->dev, sparx5_serdes_xlate); return PTR_ERR_OR_ZERO(provider); From patchwork Mon Apr 17 18:03:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Machon X-Patchwork-Id: 84389 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2316675vqo; Mon, 17 Apr 2023 11:18:25 -0700 (PDT) X-Google-Smtp-Source: AKy350ZZ15on2HCMAbLXbwuX74xAqKqDHdevpUi0f/lLJ4v9BIODiEKM4AhuRMq/GgASKF5BRQ4Z X-Received: by 2002:a17:903:1107:b0:1a5:206:4c88 with SMTP id n7-20020a170903110700b001a502064c88mr15485338plh.18.1681755504873; Mon, 17 Apr 2023 11:18:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681755504; cv=none; d=google.com; s=arc-20160816; b=0R/HrDyrYNA45U7czJ51jRtSytMhIqDYuneGOfYAAm4uMBhKuw6DkJmXWA/o8U8z0c rANRIowVLvxDt7uzsnCXiflqQQ8+9z+w0hCmc0iI6t97XLi7s228sjJivDsdcH04qZQd v7RuZ6RNvqRKdgTpE7Duz+2Hzd+3C536Lh0rqyLq/sVc+ysUATekZ0jvLU8TN8bJLzh3 CwvnIKjl618jxYES0bliRzHt0Rx3AowcVVUOZgGJu3oq5PXevPFOHw10hMqhwnm7uJfh lBhm1yiR362WQJGVOYjqnRi7BmRHZPhsp/RX22nFO7EhQ9rX87OxkAs4/3D7nF8dT2I5 4v+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ZT7tSCURBbiDnEpGAQ22j1OkWpMwwPt2j4H8fXoatlo=; b=pBZBpez0rjCRwYS6SkXBTHc0nwgZbL+fn1jXIfY+HbLQWgKd0BGpjZpg99jqP1Afic Eh/rqYfS4R4xEvCtrIlqWYFdCjqG/9v6p14jsrCqnRtimIYfWGX4MMFMYd+7SHa7F8/Z B1YDp836n0W3weVfc1zzy9NZrzoaMScGB6AxDxhDYxpmzYZ2WdaPc8kkMcOfYKkq9kBo ncVP5cg/sz02tj4moaymwMlZ3SAtMoIMRR3au6gWnlCseGHZFamql1cH/5t3JWOv0JM3 eUAtt7ZPE1Mt2TFIomaeBxZKZYWnmOuI3zVbVDZYsIQEu5YFqfV3hhRwUxEP2LqUCOrz ZIYQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=SPMiTOv8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id qe15-20020a17090b4f8f00b002475bc0a189si7433131pjb.113.2023.04.17.11.18.10; Mon, 17 Apr 2023 11:18:24 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=SPMiTOv8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230463AbjDQSEO (ORCPT + 99 others); Mon, 17 Apr 2023 14:04:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53074 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231207AbjDQSEH (ORCPT ); Mon, 17 Apr 2023 14:04:07 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 16AA376A8 for ; Mon, 17 Apr 2023 11:04:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1681754640; x=1713290640; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qWBx4BKoFDrQnCpgyAMwdPuAQ4nlRpG6oep6/zjdvDg=; b=SPMiTOv8lG6jPe0YVtkkhAuZBOSOjP+Ge2hwlgXaR5njPCBKVxk0S7WB Agdr8CXBBV47m+nneW0SGZ5LCIxkb1ZEZFZzAeCwGmyP8yatfwbKtOijp WJpXBwKxy6tb/z91HJk2MQBMIb9+msCUmB61CKwF8pA6EAr80PRqhHLH/ Q9BNhmzPvvFCRk48okqSDdV0eYfwjxbZ0VCQLyr2rdh91yb4S4oE1LPyy HqT8vz8NRC/0FU0hEHXFrPxNQVUPd4LXpE2iqS6BgB7ZR7gJM7Pe6Q7YX dPAqjl25+nFsFtvCZLZUVeop6iwLlQ0hMU/52G8d13ZPK/JZnXgiPzQ05 A==; X-IronPort-AV: E=Sophos;i="5.99,204,1677567600"; d="scan'208";a="147469779" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Apr 2023 11:03:58 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 17 Apr 2023 11:03:52 -0700 Received: from DEN-LT-70577.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 17 Apr 2023 11:03:50 -0700 From: Daniel Machon To: CC: , , , , , , , Subject: [PATCH 5/7] phy: sparx5-serdes: power on CMUs individually Date: Mon, 17 Apr 2023 20:03:33 +0200 Message-ID: <20230417180335.2787494-6-daniel.machon@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230417180335.2787494-1-daniel.machon@microchip.com> References: <20230417180335.2787494-1-daniel.machon@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763448460509710096?= X-GMAIL-MSGID: =?utf-8?q?1763448460509710096?= Power on the CMU instance, that provides the clock for the serdes, given the specified serdes mode and index. The CMU instance is looked up, using a preset map of serdes mode and index to CMU index. Signed-off-by: Daniel Machon --- drivers/phy/microchip/sparx5_serdes.c | 43 ++++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/drivers/phy/microchip/sparx5_serdes.c b/drivers/phy/microchip/sparx5_serdes.c index 0e9db7b36b60..a6638d783a01 100644 --- a/drivers/phy/microchip/sparx5_serdes.c +++ b/drivers/phy/microchip/sparx5_serdes.c @@ -25,6 +25,7 @@ #define SPX5_SERDES_10G_START 13 #define SPX5_SERDES_25G_START 25 +#define SPX5_SERDES_6G10G_CNT SPX5_SERDES_25G_START /* Optimal power settings from GUC */ #define SPX5_SERDES_QUIET_MODE_VAL 0x01ef4e0c @@ -34,6 +35,7 @@ enum sparx5_10g28cmu_mode { SPX5_SD10G28_CMU_AUX1 = 1, SPX5_SD10G28_CMU_AUX2 = 3, SPX5_SD10G28_CMU_NONE = 4, + SPX5_SD10G28_CMU_MAX, }; enum sparx5_sd25g28_mode_preset_type { @@ -1078,6 +1080,39 @@ static int sparx5_serdes_cmu_enable(struct sparx5_serdes_private *priv) return err; } +/* Map of 6G/10G serdes mode and index to CMU index. */ +static const int +sparx5_serdes_cmu_map[SPX5_SD10G28_CMU_MAX][SPX5_SERDES_6G10G_CNT] = { + [SPX5_SD10G28_CMU_MAIN] = { 2, 2, 2, 2, 2, + 2, 2, 2, 5, 5, + 5, 5, 5, 5, 5, + 5, 8, 11, 11, 11, + 11, 11, 11, 11, 11 }, + [SPX5_SD10G28_CMU_AUX1] = { 0, 0, 3, 3, 3, + 3, 3, 3, 3, 3, + 6, 6, 6, 6, 6, + 6, 6, 9, 9, 12, + 12, 12, 12, 12, 12 }, + [SPX5_SD10G28_CMU_AUX2] = { 1, 1, 1, 1, 4, + 4, 4, 4, 4, 4, + 4, 4, 7, 7, 7, + 7, 7, 10, 10, 10, + 10, 13, 13, 13, 13 }, + [SPX5_SD10G28_CMU_NONE] = { 1, 1, 1, 1, 4, + 4, 4, 4, 4, 4, + 4, 4, 7, 7, 7, + 7, 7, 10, 10, 10, + 10, 13, 13, 13, 13 }, +}; + +/* Get the index of the CMU which provides the clock for the specified serdes + * mode and index. + */ +static int sparx5_serdes_cmu_get(enum sparx5_10g28cmu_mode mode, int sd_index) +{ + return sparx5_serdes_cmu_map[mode][sd_index]; +} + static void sparx5_serdes_cmu_power_off(struct sparx5_serdes_private *priv) { void __iomem *cmu_inst, *cmu_cfg_inst; @@ -1626,7 +1661,13 @@ static int sparx5_sd10g28_apply_params(struct sparx5_serdes_macro *macro, u32 lane_index = macro->sidx; u32 sd_index = macro->stpidx; void __iomem *sd_inst; - u32 value; + u32 value, cmu_idx; + int err; + + cmu_idx = sparx5_serdes_cmu_get(params->cmu_sel, lane_index); + err = sparx5_cmu_cfg(priv, cmu_idx); + if (err) + return err; if (params->is_6g) sd_inst = sdx5_inst_get(priv, TARGET_SD6G_LANE, sd_index); From patchwork Mon Apr 17 18:03:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Machon X-Patchwork-Id: 84387 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2311830vqo; Mon, 17 Apr 2023 11:10:42 -0700 (PDT) X-Google-Smtp-Source: AKy350ZlijhSq5WIPuj5aqLsKYk6OYWeSvnoCvHuNZL0UONHWo3/AwHdGbv8LMPLmHm2QDZN3UIs X-Received: by 2002:a17:90a:c484:b0:247:a3ed:63b3 with SMTP id j4-20020a17090ac48400b00247a3ed63b3mr2830023pjt.31.1681755041815; Mon, 17 Apr 2023 11:10:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681755041; cv=none; d=google.com; s=arc-20160816; b=BbqH04FCTl4wC3ENB6yFVu2TKoO7jm/FnCEf54dWBWZtz1kkZl8EFLIiuJIefwPEHh 7IdbYzeUNIFtHJPjGWu9AnkSGhSqyeR0BXCquRCq106UQ4smgsa1VPiNmAlojkPTbrzy WeOD4TOaTeK+dhy1UrbfIiflDrbwaus+D5XydYIVdmXZqrZTNeWi5BCEaZ9ruqf12Cze f900yGIEIUR+WebTd+swsN5y+9kTJMMH6EJ+5kzdIxUsQxS70kbQj/m+HO94+j2NBV92 M4hZZ2Sj7giSeZg6PYC2HVGerz3RmKCiqgg73O1grhA8ck1LPrE3fDh9+qTvkR3NW5QR 0aUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Ra6FEgSl4GmHNTWB91iEvxhTItbd0Xx3pdgY+gaP5Jw=; b=xviQJ6jWwdbKWU+xwlG8CZERtq+ENNn92ppLIKWPxL3iXCq/Bgm2Yn5TautF5EeWXS VMTz1coUNand/wnEVTuFZjNVR13MmCnicOfU/HloQ0aGRDFRFYOqZjv2u05z9ocYuTN2 4oKhi3UK9K1KruPpPumQWjl6hRmupcu25dFqqKx2F1if8wPtClH8r36Rh8y/qhNwbIyj qbQecQM3GeFk5XeVjdz9ybCgmwPJZ9IgczhV2apiBX4x+wK/BkF2xjz5ncza/7I/A/nX UnpZSlkJIJ5Cpm8CVNiJ1JagyDbObRJP5rchCBC+0Ncb9kZirhp3dJMXmbQhSKwHDQL5 ns2A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=RjDtbVGy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id my7-20020a17090b4c8700b00246d164fd7asi11221804pjb.159.2023.04.17.11.10.29; Mon, 17 Apr 2023 11:10:41 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=RjDtbVGy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231222AbjDQSEQ (ORCPT + 99 others); Mon, 17 Apr 2023 14:04:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53054 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230501AbjDQSEH (ORCPT ); Mon, 17 Apr 2023 14:04:07 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 308C16A79 for ; Mon, 17 Apr 2023 11:04:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1681754641; x=1713290641; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=k+uQ6AuSXVO9NTO3vnNTGE3OcG8q0cmFmyPP7RNm0jA=; b=RjDtbVGyJWYkzmReb8smiv3M9xyrOQfm2IY4/EyZLubPokbApsjVNi9k Q6ZUzvwUQfHrqMpqhm99NWsmGFvWZeova2OZq4GxT0VWL3SJ0AITxWspo 6iMy6zdC66Z+lnG0/XU8TZpMQz0UPzS0stTcpEHEC2MTsyG1QkpcZyUoO pVU972NQV8TIyY+Xj5d8OmXQdPAy/+Jf+JINPRFHCYyokQEgWRXvQl7oE eGLJoI7epWFkFa1cxuL3CmzXPm2idEBvylSGU10TKeJPHNWjyJYd4f2Nj Dp5dOo87VoycDRrXPSg/o4JVcKCkT+AtdAN4rOLsXR8NvvGaBlrr/J9/f Q==; X-IronPort-AV: E=Sophos;i="5.99,204,1677567600"; d="scan'208";a="147469783" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Apr 2023 11:03:59 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 17 Apr 2023 11:03:54 -0700 Received: from DEN-LT-70577.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 17 Apr 2023 11:03:52 -0700 From: Daniel Machon To: CC: , , , , , , , Subject: [PATCH 6/7] phy: sparx5-serdes: remove power up of all CMUs Date: Mon, 17 Apr 2023 20:03:34 +0200 Message-ID: <20230417180335.2787494-7-daniel.machon@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230417180335.2787494-1-daniel.machon@microchip.com> References: <20230417180335.2787494-1-daniel.machon@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-3.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,TVD_SUBJ_WIPE_DEBT, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763447974949230156?= X-GMAIL-MSGID: =?utf-8?q?1763447974949230156?= CMUs should not be powered up by default anymore, so remove responsible code. Signed-off-by: Daniel Machon --- drivers/phy/microchip/sparx5_serdes.c | 25 ------------------------- drivers/phy/microchip/sparx5_serdes.h | 1 - 2 files changed, 26 deletions(-) diff --git a/drivers/phy/microchip/sparx5_serdes.c b/drivers/phy/microchip/sparx5_serdes.c index a6638d783a01..eb9352d1de7e 100644 --- a/drivers/phy/microchip/sparx5_serdes.c +++ b/drivers/phy/microchip/sparx5_serdes.c @@ -1062,24 +1062,6 @@ static int sparx5_cmu_cfg(struct sparx5_serdes_private *priv, u32 cmu_idx) return sparx5_cmu_apply_cfg(priv, cmu_idx, cmu_tgt, cmu_cfg_tgt, spd10g); } -static int sparx5_serdes_cmu_enable(struct sparx5_serdes_private *priv) -{ - int idx, err = 0; - - if (!priv->cmu_enabled) { - for (idx = 0; idx < SPX5_CMU_MAX; idx++) { - err = sparx5_cmu_cfg(priv, idx); - if (err) { - dev_err(priv->dev, "CMU %u, error: %d\n", idx, err); - goto leave; - } - } - priv->cmu_enabled = true; - } -leave: - return err; -} - /* Map of 6G/10G serdes mode and index to CMU index. */ static const int sparx5_serdes_cmu_map[SPX5_SD10G28_CMU_MAX][SPX5_SERDES_6G10G_CNT] = { @@ -2236,10 +2218,6 @@ static int sparx5_serdes_config(struct sparx5_serdes_macro *macro) int serdesmode; int err; - err = sparx5_serdes_cmu_enable(macro->priv); - if (err) - return err; - serdesmode = sparx5_serdes_get_serdesmode(macro->portmode, macro->speed); if (serdesmode < 0) { dev_err(dev, "SerDes %u, interface not supported: %s\n", @@ -2331,9 +2309,6 @@ static int sparx5_serdes_reset(struct phy *phy) struct sparx5_serdes_macro *macro = phy_get_drvdata(phy); int err; - err = sparx5_serdes_cmu_enable(macro->priv); - if (err) - return err; if (macro->serdestype == SPX5_SDT_25G) err = sparx5_sd25g28_config(macro, true); else diff --git a/drivers/phy/microchip/sparx5_serdes.h b/drivers/phy/microchip/sparx5_serdes.h index 0a3e496e6210..13f94a29225a 100644 --- a/drivers/phy/microchip/sparx5_serdes.h +++ b/drivers/phy/microchip/sparx5_serdes.h @@ -30,7 +30,6 @@ struct sparx5_serdes_private { struct device *dev; void __iomem *regs[NUM_TARGETS]; struct phy *phys[SPX5_SERDES_MAX]; - bool cmu_enabled; unsigned long coreclock; }; From patchwork Mon Apr 17 18:03:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Machon X-Patchwork-Id: 84384 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2311221vqo; Mon, 17 Apr 2023 11:09:43 -0700 (PDT) X-Google-Smtp-Source: AKy350awfKy7vCCkZ/4NvepRvw/HJHbXmcPlcW2pdIAqeRj55DvHSIeqJ8pUN4U2LjJm4eyuFTkt X-Received: by 2002:a17:902:d4d0:b0:19f:3234:fec5 with SMTP id o16-20020a170902d4d000b0019f3234fec5mr16308624plg.51.1681754983082; Mon, 17 Apr 2023 11:09:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681754983; cv=none; d=google.com; s=arc-20160816; b=bEcO/MiAlqdc1718OXjUoxGLZZPqsy2L7yHUspg9+RXVRja6hUWhQdE0Qmt4/90bAp rjF1xn53d2Bi+hNJB9gytxw2tYmqL2/grcopcjsQtQDEHySoBMl3++IkNTBUu+BndLNU X+3RXs3bCqLTRe+BZ8iGmdZdyJko3CZI0+NQ83VZQjvGLK1x7kpk0l7+JJJRCReMOXGt +OeZ43ShFId6aGINKQvdKFB/f2VBZCfZbSWlRAH9IWCfTa+fzDl376IiTCJtb25jPinE 8uPD2ey32bL3hLBO4CXMN17iczGRaXdreFbBqCN8eoGksYLaw4p7gyIQJ0nQ5x9JZ/qx nAJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=fJ+1cucixxLbRB39Mnw7VC1OO0aBbwHqUdZpIhjaKMI=; b=edJ9G81+TTkO0RxQVzKvl3bV6uBEP8UUIDMEtok9Ura8hlKKLK5SaAwJ2B3VNnvRJq qMpA8nDtIlm6T8ZNJJfVZNCq1YLl6KsAFnKP3vg/v54dQC8Iun7ru9R8Jn/B4nhqcti7 jxgve4OATEscE73jmuvnE0eQyNCDHDEMue96zgVc6cC2LvbGC73Ps3zNn/yKi8dfyjZw nRpd0IduZH/jVmnRaBTOiprkgVNudfZ5lqOzj/VhTeJkbR98fdtHyP5q7uHxhzzQXBUQ qcz2buH53MyxFKXwrZvBIn+KULrNfDyzhG/IVwovLCejBR1x80/g6ECdQCNs5BV2s/ku bKPw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=0SMi9TqY; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 140-20020a630392000000b00513cd7f8ca7si12276664pgd.345.2023.04.17.11.09.30; Mon, 17 Apr 2023 11:09:43 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=0SMi9TqY; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230197AbjDQSEr (ORCPT + 99 others); Mon, 17 Apr 2023 14:04:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53454 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231226AbjDQSES (ORCPT ); Mon, 17 Apr 2023 14:04:18 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 39A0FBB81 for ; Mon, 17 Apr 2023 11:04:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1681754645; x=1713290645; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3HuikI716f2ys2CohTnjAOi+mGw2PSL74PJSePfvn8A=; b=0SMi9TqYOEijHumuQEKdUQNeXJIx1608hAc5+l/HhkQXwthrkWExKmkF 0A1ff4Y7+oMXpo8Wmo+FLBPNxTYBTk5h1ybMQTMJgdN/8CgtSl624mPpT FbjXkzl5/8n+vfNQAO1OOH30VUkPgHADo8BOLhFI2UZoUtu/o6W3ekrNp oYrdadTo2iYHdpRDcX2rnc/l3sUS+Yx/pW+PakOIRcc8SLus2h2I+wD4i MP1YSFzm5vGuZcm0DJC6dm3XN6/iUKKJ7Jej/2N+LVHpOnuC1JGGI1bOr 7LyLP2SEDIH5Ocs2NB8g5FjtU6+vC+WA45Rby/CT18ry6G5YE5MUJYD6o Q==; X-IronPort-AV: E=Sophos;i="5.99,204,1677567600"; d="scan'208";a="147469789" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Apr 2023 11:04:00 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 17 Apr 2023 11:03:56 -0700 Received: from DEN-LT-70577.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 17 Apr 2023 11:03:54 -0700 From: Daniel Machon To: CC: , , , , , , , Subject: [PATCH 7/7] phy: sparx5-serdes: add skip_cmu_cfg check when configuring lanes Date: Mon, 17 Apr 2023 20:03:35 +0200 Message-ID: <20230417180335.2787494-8-daniel.machon@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230417180335.2787494-1-daniel.machon@microchip.com> References: <20230417180335.2787494-1-daniel.machon@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763447912967821747?= X-GMAIL-MSGID: =?utf-8?q?1763447912967821747?= Add a check for skip_cmu_cfg when configuring the serdes lane. All individual serdeses are reset upon first configuration. Resetting the serdes involves reconfiguring it with preset values. The serdesmode is required to determine the clock-providing CMU, therefore make sure the serdes is not reconfigured if the serdesmode is not set. Signed-off-by: Daniel Machon --- drivers/phy/microchip/sparx5_serdes.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/phy/microchip/sparx5_serdes.c b/drivers/phy/microchip/sparx5_serdes.c index eb9352d1de7e..01bd5ea620c5 100644 --- a/drivers/phy/microchip/sparx5_serdes.c +++ b/drivers/phy/microchip/sparx5_serdes.c @@ -1646,6 +1646,10 @@ static int sparx5_sd10g28_apply_params(struct sparx5_serdes_macro *macro, u32 value, cmu_idx; int err; + /* Do not configure serdes if CMU is not to be configured too */ + if (params->skip_cmu_cfg) + return 0; + cmu_idx = sparx5_serdes_cmu_get(params->cmu_sel, lane_index); err = sparx5_cmu_cfg(priv, cmu_idx); if (err) @@ -2111,6 +2115,7 @@ static int sparx5_sd10g28_config(struct sparx5_serdes_macro *macro, bool reset) .rxinvert = 1, .txswing = 240, .reg_rst = reset, + .skip_cmu_cfg = reset, }; int err;