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[83.9.30.99]) by smtp.gmail.com with ESMTPSA id b16-20020ac25e90000000b004ec8a3d4200sm2053439lfq.293.2023.04.17.08.30.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Apr 2023 08:30:24 -0700 (PDT) From: Konrad Dybcio Date: Mon, 17 Apr 2023 17:30:15 +0200 Subject: [PATCH 1/5] dt-bindings: display/msm: Add reg bus interconnect MIME-Version: 1.0 Message-Id: <20230417-topic-dpu_regbus-v1-1-06fbdc1643c0@linaro.org> References: <20230417-topic-dpu_regbus-v1-0-06fbdc1643c0@linaro.org> In-Reply-To: <20230417-topic-dpu_regbus-v1-0-06fbdc1643c0@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681745422; l=1021; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=DgEhAwck/2UMFZpU98hoIh71vdQR9UmmeTw0XAyM3ys=; b=ciJNKHjiF7ITdMqgyQfJ5T8aGhSzJ7QpX1an0grzifZiCGiobk7sJ7VxHrZq7Ks1lDIevGYZ2Ppn gZhM6RO4AVtKPj9aTKdLen85YbNGGGyEr8b2giju+qcxUh69exFG X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763439040398771929?= X-GMAIL-MSGID: =?utf-8?q?1763439040398771929?= Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's another path that needs to be handled to ensure MDSS functions properly, namely the "reg bus", a.k.a the CPU-MDSS interconnect. Gating that path may have a variety of effects.. from none to otherwise inexplicable DSI timeouts.. Describe it in bindings to allow for use in device trees. Signed-off-by: Konrad Dybcio --- Documentation/devicetree/bindings/display/msm/mdss-common.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml index ccd7d6417523..9eb5b6d3e0b9 100644 --- a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml +++ b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml @@ -72,6 +72,7 @@ properties: items: - const: mdp0-mem - const: mdp1-mem + - const: cpu-cfg resets: items: From patchwork Mon Apr 17 15:30:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 84318 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2218505vqo; Mon, 17 Apr 2023 08:43:39 -0700 (PDT) X-Google-Smtp-Source: AKy350bSBMM/ntKrjAolkuazJLIRm3UKuM6rwCiMDk9CWdBOvSOm6YpWAy7uYWkdSJJYPNun5Psu X-Received: by 2002:a17:903:187:b0:1a5:3319:12f7 with SMTP id z7-20020a170903018700b001a5331912f7mr15851952plg.50.1681746219139; Mon, 17 Apr 2023 08:43:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681746219; cv=none; d=google.com; s=arc-20160816; b=hHRRe2tj4emHYeubRK3kIPs4atMlrxHdmaPJJtMUyNcbRjlDlckCwFe4T2+W+7MfYE bp4nUIKAQI6E0TD0S1rzUJ5jWiEPt3Kctr8nxW0oHoPrYtLZuZkQHBSVn0Dk8AxqJZmh Tr3J1E0bOV/61efQyi7QA/lwY0oKEBXo/pSjg4VCC55GkR50AQgQPk2BGblPi4Nseuel 8WYrGNkp12Q3PVEQju4fnju3y+zeCrRSEWrMyYtP6LaoYErLdRfx2kR+mPNVNvDD1+6e nP4T9rRk959vT6rNdHZ7jkQPrQ9HWQj2xXg4qQScquuC2XQiPLdCfdvdZ+VzNAQprwru T5Uw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=TusSYFhXpBTw3hD+Ig+2V6T5nJHWfXxfYQbiZRqJGNM=; b=0MnM6pw1xcqf9aRqUqJPBbOea3t2wFC845sUXxSvX6kWK0ugg9zapc7Pkwmmf9PKYN nAavnUtqVz7DXF4krHL+9BrfNCDVN+Zu4O6jLPg/55ZDKB74Ha9nL3ZKnzDOULGRK9ij pQTeGTx5Xqzm/L1Ebu7qcZpgyaGZXH7t+4V0j7Zc/ZcvyyZ99KxpXk+C/Nm3mNY2oJqp 5FaPwSlBDlaToNJPDwcZ9j17niT5biO6egu/7lZLeCcg9B8ZIBqLOuJxTA8BnpfVl3RG eLozJX+sz4BS23tw2ELUI0bzvJ7MdDGrFgT6gf74aR8IzlsbkVUPpw8lv9HJCQBMMuwW TxsA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dHm8aCvl; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.30.99]) by smtp.gmail.com with ESMTPSA id b16-20020ac25e90000000b004ec8a3d4200sm2053439lfq.293.2023.04.17.08.30.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Apr 2023 08:30:26 -0700 (PDT) From: Konrad Dybcio Date: Mon, 17 Apr 2023 17:30:16 +0200 Subject: [PATCH 2/5] drm/msm/dpu1: Rename path references to mdp_path MIME-Version: 1.0 Message-Id: <20230417-topic-dpu_regbus-v1-2-06fbdc1643c0@linaro.org> References: <20230417-topic-dpu_regbus-v1-0-06fbdc1643c0@linaro.org> In-Reply-To: <20230417-topic-dpu_regbus-v1-0-06fbdc1643c0@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681745422; l=3187; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=RHVX4b0dy7ygKXk/64XZDOzn26jUEVt2/m6N5KVO6Vs=; b=qhl8VwYNu7H7amoau38AAJki+EoSvXRe0p3hYZz1l9uP0M+SPAdPsESbHnLiWGF1IWWRLpLbCih8 jUqjgwyVDIwSPBiS81m0CFn3q3LaeRVXuNnjeTnu1QNfB77xNcJ5 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763438723471346292?= X-GMAIL-MSGID: =?utf-8?q?1763438723471346292?= The DPU1 driver needs to handle all MDPn<->DDR paths, as well as CPU<->SLAVE_DISPLAY_CFG. The former ones share how their values are calculated, but the latter one has static predefines spanning all SoCs. In preparation for supporting the CPU<->SLAVE_DISPLAY_CFG path, rename the path-related struct members to include "mdp_". Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 10 +++++----- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 12 ++++++------ drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 4 ++-- 3 files changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c index 1d9d83d7b99e..349c6cb3301d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c @@ -230,18 +230,18 @@ static int _dpu_core_perf_crtc_update_bus(struct dpu_kms *kms, DRM_DEBUG_ATOMIC("crtc=%d bw=%llu paths:%d\n", tmp_crtc->base.id, - dpu_cstate->new_perf.bw_ctl, kms->num_paths); + dpu_cstate->new_perf.bw_ctl, kms->num_mdp_paths); } } - if (!kms->num_paths) + if (!kms->num_mdp_paths) return 0; avg_bw = perf.bw_ctl; - do_div(avg_bw, (kms->num_paths * 1000)); /*Bps_to_icc*/ + do_div(avg_bw, (kms->num_mdp_paths * 1000)); /*Bps_to_icc*/ - for (i = 0; i < kms->num_paths; i++) - icc_set_bw(kms->path[i], avg_bw, perf.max_per_pipe_ib); + for (i = 0; i < kms->num_mdp_paths; i++) + icc_set_bw(kms->mdp_path[i], avg_bw, perf.max_per_pipe_ib); return ret; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 0e7a68714e9e..dd6c1c40ab9e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -397,12 +397,12 @@ static int dpu_kms_parse_data_bus_icc_path(struct dpu_kms *dpu_kms) if (IS_ERR_OR_NULL(path0)) return PTR_ERR_OR_ZERO(path0); - dpu_kms->path[0] = path0; - dpu_kms->num_paths = 1; + dpu_kms->mdp_path[0] = path0; + dpu_kms->num_mdp_paths = 1; if (!IS_ERR_OR_NULL(path1)) { - dpu_kms->path[1] = path1; - dpu_kms->num_paths++; + dpu_kms->mdp_path[1] = path1; + dpu_kms->num_mdp_paths++; } return 0; } @@ -1238,8 +1238,8 @@ static int __maybe_unused dpu_runtime_suspend(struct device *dev) dev_pm_opp_set_rate(dev, 0); clk_bulk_disable_unprepare(dpu_kms->num_clocks, dpu_kms->clocks); - for (i = 0; i < dpu_kms->num_paths; i++) - icc_set_bw(dpu_kms->path[i], 0, 0); + for (i = 0; i < dpu_kms->num_mdp_paths; i++) + icc_set_bw(dpu_kms->mdp_path[i], 0, 0); return 0; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index aca39a4689f4..d5d9bec90705 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -109,8 +109,8 @@ struct dpu_kms { * when disabled. */ atomic_t bandwidth_ref; - struct icc_path *path[2]; - u32 num_paths; + struct icc_path *mdp_path[2]; + u32 num_mdp_paths; }; struct vsync_info { From patchwork Mon Apr 17 15:30:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 84336 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2227833vqo; Mon, 17 Apr 2023 08:59:30 -0700 (PDT) X-Google-Smtp-Source: AKy350amIRHLbrFwhnaceOAfavg2w4c2cIj0Lxel5JMY90H5AHPY7eBLpIh0SJmJhXDRRkABEKe+ X-Received: by 2002:a05:6a20:a989:b0:d9:ecba:b9fc with SMTP id cc9-20020a056a20a98900b000d9ecbab9fcmr14456977pzb.54.1681747169824; Mon, 17 Apr 2023 08:59:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681747169; cv=none; d=google.com; s=arc-20160816; b=YTkIUU9ObNWAdl+6cs0KTdtyPnmtU7+102UYW4hLWaUhfkVN4B/qcXKAcyfqPLDVQl GEoei7pbuoAJ3tftYkfbStCdau1zWG5zYCWeZMlPkRcihsgaL8KnpNn1aGy0xctAR4s4 DKCMIwsaPCmhWo9MKntuaS/afKGfKj/+kn0ogH4dbhyigcaup1XHSc/HpgxT9xmvgsJr Jjwceiq1eEqf3ntsLeuXosNr2VGWzSCuEpsGstI4u/5a46/EU5bAbGi0uF/V7oSbHK8C BUpLvqy6DaweFiSAjvM9UUynK066sZdjI0qDs9tlAQsgI0H+jBLKs3+YRepG9KY3u/4T ySQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=hUGnN7QmHFXWvkEalaWeWFmgMZnzSnPU7k2aFfVSknQ=; b=S0/yaNohsBtoLpPMZJBnQfTc3jVdBPHY5a1Jgvr6YuWrMaVy0qlz7A6Zl6hg68nBYl oKtCYRfB5VkHteneYFP+QifTKIV2OsSu6ZOtgg6wiyH4zycmlbhX+eCkRs8dvksQrLNB Ucey/GPnWZCgfqOlRCyYps8cbloaUe4PxPN/jxnh5HU0WMHc1Ig3fRW/v4DDNbKqDM+t 9hwL0tpek1nFd86g0FQVP6BM4AO0YXICSnLz+fFF5qVWByDV8rzVYRRErQaWWbXQcJVZ gscg9q6VWrq9pNP8JczQCLEvTmAlVoph1PZRqIVl3l0HW6/nUih/rY4m7TT0X081BMyQ 8eSg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=b48X3TNr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.30.99]) by smtp.gmail.com with ESMTPSA id b16-20020ac25e90000000b004ec8a3d4200sm2053439lfq.293.2023.04.17.08.30.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Apr 2023 08:30:27 -0700 (PDT) From: Konrad Dybcio Date: Mon, 17 Apr 2023 17:30:17 +0200 Subject: [PATCH 3/5] drm/msm/mdss: Rename path references to mdp_path MIME-Version: 1.0 Message-Id: <20230417-topic-dpu_regbus-v1-3-06fbdc1643c0@linaro.org> References: <20230417-topic-dpu_regbus-v1-0-06fbdc1643c0@linaro.org> In-Reply-To: <20230417-topic-dpu_regbus-v1-0-06fbdc1643c0@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681745422; l=2175; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=mFT0UyX9LhxCNCpprLZW/XLO+LLNqKMZSGZE8MZeFUU=; b=BXHtHcUcP4g/hixvZ0bGJVRvqCP7askf6+3q9wseZvQ/7VfvWeLIM9JhT3BU/O5D9uFsmsKTreg+ diV6OtW0D5MqNkqhqHE4VLhrMAs+6iejgdtaEbsRGpVZvrINpjs1 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763439720521406195?= X-GMAIL-MSGID: =?utf-8?q?1763439720521406195?= The DPU1 driver needs to handle all MDPn<->DDR paths, as well as CPU<->SLAVE_DISPLAY_CFG. The former ones share how their values are calculated, but the latter one has static predefines spanning all SoCs. In preparation for supporting the CPU<->SLAVE_DISPLAY_CFG path, rename the path-related struct members to include "mdp_". Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_mdss.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index e8c93731aaa1..9e2ce7f22677 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -48,8 +48,8 @@ struct msm_mdss { struct irq_domain *domain; } irq_controller; const struct msm_mdss_data *mdss_data; - struct icc_path *path[2]; - u32 num_paths; + struct icc_path *mdp_path[2]; + u32 num_mdp_paths; }; static int msm_mdss_parse_data_bus_icc_path(struct device *dev, @@ -62,13 +62,13 @@ static int msm_mdss_parse_data_bus_icc_path(struct device *dev, if (IS_ERR_OR_NULL(path0)) return PTR_ERR_OR_ZERO(path0); - msm_mdss->path[0] = path0; - msm_mdss->num_paths = 1; + msm_mdss->mdp_path[0] = path0; + msm_mdss->num_mdp_paths = 1; path1 = of_icc_get(dev, "mdp1-mem"); if (!IS_ERR_OR_NULL(path1)) { - msm_mdss->path[1] = path1; - msm_mdss->num_paths++; + msm_mdss->mdp_path[1] = path1; + msm_mdss->num_mdp_paths++; } return 0; @@ -79,16 +79,16 @@ static void msm_mdss_put_icc_path(void *data) struct msm_mdss *msm_mdss = data; int i; - for (i = 0; i < msm_mdss->num_paths; i++) - icc_put(msm_mdss->path[i]); + for (i = 0; i < msm_mdss->num_mdp_paths; i++) + icc_put(msm_mdss->mdp_path[i]); } static void msm_mdss_icc_request_bw(struct msm_mdss *msm_mdss, unsigned long bw) { int i; - for (i = 0; i < msm_mdss->num_paths; i++) - icc_set_bw(msm_mdss->path[i], 0, Bps_to_icc(bw)); + for (i = 0; i < msm_mdss->num_mdp_paths; i++) + icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(bw)); } static void msm_mdss_irq(struct irq_desc *desc) From patchwork Mon Apr 17 15:30:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 84333 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2226397vqo; Mon, 17 Apr 2023 08:56:44 -0700 (PDT) X-Google-Smtp-Source: AKy350bMdbzRpTriHjJpJEzxtwxS4NFS6fhWOZQENfhGTHOp4+S8ZY2YLnjsBesBk9fbtOyhCPhm X-Received: by 2002:a17:903:200b:b0:1a6:ab6a:93c9 with SMTP id s11-20020a170903200b00b001a6ab6a93c9mr9271724pla.23.1681747004743; Mon, 17 Apr 2023 08:56:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681747004; cv=none; d=google.com; s=arc-20160816; b=kySgGcl08RTzb3fQchCO8rBXQgmPKh5AlG5lWPMq67dC8UNAm2H0+H46keNrEz7fSf tjKW0/4Wd12w3m9paOmG5M/J5hQVb4YGSJyxwfVP5gT1AJcTtgGCllclKp6J3I1EhxAd KZ85sB+7tWSmLHuEdU7FlGa9etROJ2pNwWyO7qYCZcgfOCmSR+vNYukc4TE8WUYDqti4 mQ+14TpLm0FODRM5NQGVWo+sKSQFoMOlw/ELgg0gMWzWqsboEBGBSrYHaGcGnPHZyWjd JOSOkw+Zc+J/Gmy8QupDupc2S4ZyTttJ+uSrKe1URw9P/TC87UV6OeSRKVCLbTLF4zdW Cqrw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=PbVhusCEghNKEPZ8TLDEdqw82MnqWQVPyy1y462DY9k=; b=l3l43INJ5B4DcAvcWHSA6hHLBtCNCh6bkLdEQHson2pM4HyLLuUsQ2PddpxkDcl2ML 6WXhGrG5kRHD1v8QLmILLQibRK8v0UR1Y0tbIH6PK0BXzPgK038dgXJjo3duUYYgD0ef QVF8MxRNmvhA+5Si7KsPK/bTRTaQbJEPN+lLX9dctFuCIji2osqyqYF5+c3k5U5i7lka wQOsj5PF54BHdozgmTLlW/j7k8S0gIHNkJOdEf3rnI+6Q6DztR36h1kI7VZcvXCFftNG 5RSCnAZuc2Tuq3ESXBK5gObx/j2Ehz31lIoc7OFbdz5p2ol7R2NH/1TYJse5MyALOgJw ++OQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="vG/uhlDH"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.30.99]) by smtp.gmail.com with ESMTPSA id b16-20020ac25e90000000b004ec8a3d4200sm2053439lfq.293.2023.04.17.08.30.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Apr 2023 08:30:29 -0700 (PDT) From: Konrad Dybcio Date: Mon, 17 Apr 2023 17:30:18 +0200 Subject: [PATCH 4/5] drm/msm/mdss: Handle the reg bus ICC path MIME-Version: 1.0 Message-Id: <20230417-topic-dpu_regbus-v1-4-06fbdc1643c0@linaro.org> References: <20230417-topic-dpu_regbus-v1-0-06fbdc1643c0@linaro.org> In-Reply-To: <20230417-topic-dpu_regbus-v1-0-06fbdc1643c0@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681745422; l=3137; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=wX+gJPCe8UmLoFyI2GJLXSE1t0Mv12xmqDSsK2E8jZI=; b=5xiKkr66PFQP6ZSqLKRRPFd+S077x81GWeppbqJQlTkHd+GVqAn2hoMw2omK55rgB2aCud7qPoYm 7jn8UljSDUu65rLWRgQrdQbpTqj1ZycewVweNG7g9gkRH7l6DiQU X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763439546923816057?= X-GMAIL-MSGID: =?utf-8?q?1763439546923816057?= Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's another path that needs to be handled to ensure MDSS functions properly, namely the "reg bus", a.k.a the CPU-MDSS interconnect. Gating that path may have a variety of effects.. from none to otherwise inexplicable DSI timeouts.. On the MDSS side, we only have to ensure that it's on at what Qualcomm downstream calls "77 MHz", a.k.a 76.8 Mbps and turn it off at suspend. To achieve that, make msm_mdss_icc_request_bw() accept a boolean to indicate whether we want the busses to be on or off, as this function's only use is to vote for minimum or no bandwidth at all. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/msm_mdss.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 9e2ce7f22677..4d126d20d661 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -50,6 +50,7 @@ struct msm_mdss { const struct msm_mdss_data *mdss_data; struct icc_path *mdp_path[2]; u32 num_mdp_paths; + struct icc_path *reg_bus_path; }; static int msm_mdss_parse_data_bus_icc_path(struct device *dev, @@ -57,6 +58,7 @@ static int msm_mdss_parse_data_bus_icc_path(struct device *dev, { struct icc_path *path0; struct icc_path *path1; + struct icc_path *reg_bus_path; path0 = of_icc_get(dev, "mdp0-mem"); if (IS_ERR_OR_NULL(path0)) @@ -71,6 +73,10 @@ static int msm_mdss_parse_data_bus_icc_path(struct device *dev, msm_mdss->num_mdp_paths++; } + reg_bus_path = of_icc_get(dev, "cpu-cfg"); + if (!IS_ERR_OR_NULL(reg_bus_path)) + msm_mdss->reg_bus_path = reg_bus_path; + return 0; } @@ -83,12 +89,15 @@ static void msm_mdss_put_icc_path(void *data) icc_put(msm_mdss->mdp_path[i]); } -static void msm_mdss_icc_request_bw(struct msm_mdss *msm_mdss, unsigned long bw) +static void msm_mdss_icc_request_bw(struct msm_mdss *msm_mdss, bool enable) { int i; for (i = 0; i < msm_mdss->num_mdp_paths; i++) - icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(bw)); + icc_set_bw(msm_mdss->mdp_path[i], 0, enable ? Bps_to_icc(MIN_IB_BW) : 0); + + if (msm_mdss->reg_bus_path) + icc_set_bw(msm_mdss->reg_bus_path, 0, enable ? 76800 : 0); } static void msm_mdss_irq(struct irq_desc *desc) @@ -241,7 +250,7 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) * the interconnect is enabled (non-zero bandwidth). Let's make sure * that the interconnects are at least at a minimum amount. */ - msm_mdss_icc_request_bw(msm_mdss, MIN_IB_BW); + msm_mdss_icc_request_bw(msm_mdss, true); ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks); if (ret) { @@ -289,7 +298,7 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) static int msm_mdss_disable(struct msm_mdss *msm_mdss) { clk_bulk_disable_unprepare(msm_mdss->num_clocks, msm_mdss->clocks); - msm_mdss_icc_request_bw(msm_mdss, 0); + msm_mdss_icc_request_bw(msm_mdss, false); return 0; } From patchwork Mon Apr 17 15:30:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 84317 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2218389vqo; Mon, 17 Apr 2023 08:43:25 -0700 (PDT) X-Google-Smtp-Source: AKy350bzAJx3NQspUzYiBVTUrv86vXUSP9VxodsEwrd23/39dZVq9olQ4ZYmqqc61RmsfPUT4kZl X-Received: by 2002:a05:6a20:3d96:b0:ef:1057:d80 with SMTP id s22-20020a056a203d9600b000ef10570d80mr9109500pzi.39.1681746205210; Mon, 17 Apr 2023 08:43:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681746205; cv=none; d=google.com; s=arc-20160816; b=mzO5qEqITu2cPsdEurROVPNoUTUH7HsYtNTr2S+AMMq6G5pAEnXeCs4hGhb61FY1Ec TAfKO/ou3ZfTVNPbx41uk73M5Oyw/vEaMoUV/QVjT47MFkUnTlZRhYsdgvPTnoftc4VJ puZi/0jBarPk16mHillRckVjnoe7tDCX0P3RDVoZXZsoYdbsRWYzAzyGm0DFZ/gaVRqY N9zkEzgtpT0Pa5cuovt3TKshjGrbsiE6P0Fzo5yeqIwRb1Cga77Yec8qPVhjQT1QBLNt qtt6DxWVau5Kcd6FHJ39nfFuY0W8d/xg91vQxWHAt2JhoVaeWg7Akb53OrqbQplUvNjY HCFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=lcxH0mNsQVfDuHuH7DyMK38UqQVq7f3xMxzQMn5dBWA=; b=igM55GI9kuAnTsK9nrPaLbZZIx3QNauSNyp+9yJjtfjSYlmTfHJEq89yWWOLo/yrFz Oj2wWdprv9VNYof8grkUpQedRU048ptvXvoajsUfXGMepQlkDyM7D1wqkP6+buPV7gdH bmFSD3VY5vTTmoT+vV+JLP/Qc351cAPNYC7YdgKDannCLVlBK/QaQcJyKyOuQzuLFC40 1Vp8CkdmsVKgo22oEWgYw4v++NB2+hc480tbYqSH4rzo8/9ERhLK5vH7W+0XN0XNQ2fI j07L8/TBpcGnfnsTRv2Q62EmlCc63R90WkQiuEexSOXil+XhUbqjLqijRTYVNDbPkXpb IwTA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gnQ5ympl; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.30.99]) by smtp.gmail.com with ESMTPSA id b16-20020ac25e90000000b004ec8a3d4200sm2053439lfq.293.2023.04.17.08.30.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Apr 2023 08:30:30 -0700 (PDT) From: Konrad Dybcio Date: Mon, 17 Apr 2023 17:30:19 +0200 Subject: [PATCH 5/5] drm/msm/dpu1: Handle the reg bus ICC path MIME-Version: 1.0 Message-Id: <20230417-topic-dpu_regbus-v1-5-06fbdc1643c0@linaro.org> References: <20230417-topic-dpu_regbus-v1-0-06fbdc1643c0@linaro.org> In-Reply-To: <20230417-topic-dpu_regbus-v1-0-06fbdc1643c0@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681745422; l=3473; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=yaaDRHHygxKzQdks1Y/6TtLq+nFnkHcN9/nfzu3GSEU=; b=VTNZxxN5Kh+K53Ykp22wmxgC0rpDu78abg1GvWpdZHX0debI+H9cd8gXbR/JRvN94fKwoWyLNipa 5fEg7jJlAWe/w//ky+w/HA/5ewSdnYYRe+EWAGN92gxgmZdBrX72 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763438709028635497?= X-GMAIL-MSGID: =?utf-8?q?1763438709028635497?= Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's another path that needs to be handled to ensure MDSS functions properly, namely the "reg bus", a.k.a the CPU-MDSS interconnect. Gating that path may have a variety of effects.. from none to otherwise inexplicable DSI timeouts.. On the DPU side, we need to keep the bus alive. The vendor driver kickstarts it to max (300Mbps) throughput on first commit, but in exchange for some battery life in rare DPU-enabled-panel-disabled usecases, we can request it at DPU init and gate it at suspend. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 22 ++++++++++++++++++++-- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 + 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index dd6c1c40ab9e..d1f77faebbc0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -384,15 +384,17 @@ static int dpu_kms_global_obj_init(struct dpu_kms *dpu_kms) return 0; } -static int dpu_kms_parse_data_bus_icc_path(struct dpu_kms *dpu_kms) +static int dpu_kms_parse_icc_paths(struct dpu_kms *dpu_kms) { struct icc_path *path0; struct icc_path *path1; + struct icc_path *reg_bus_path; struct drm_device *dev = dpu_kms->dev; struct device *dpu_dev = dev->dev; path0 = msm_icc_get(dpu_dev, "mdp0-mem"); path1 = msm_icc_get(dpu_dev, "mdp1-mem"); + reg_bus_path = msm_icc_get(dpu_dev, "cpu-cfg"); if (IS_ERR_OR_NULL(path0)) return PTR_ERR_OR_ZERO(path0); @@ -404,6 +406,10 @@ static int dpu_kms_parse_data_bus_icc_path(struct dpu_kms *dpu_kms) dpu_kms->mdp_path[1] = path1; dpu_kms->num_mdp_paths++; } + + if (!IS_ERR_OR_NULL(reg_bus_path)) + dpu_kms->reg_bus_path = reg_bus_path; + return 0; } @@ -1039,7 +1045,7 @@ static int dpu_kms_hw_init(struct msm_kms *kms) DPU_DEBUG("REG_DMA is not defined"); } - dpu_kms_parse_data_bus_icc_path(dpu_kms); + dpu_kms_parse_icc_paths(dpu_kms); rc = pm_runtime_resume_and_get(&dpu_kms->pdev->dev); if (rc < 0) @@ -1241,6 +1247,9 @@ static int __maybe_unused dpu_runtime_suspend(struct device *dev) for (i = 0; i < dpu_kms->num_mdp_paths; i++) icc_set_bw(dpu_kms->mdp_path[i], 0, 0); + if (dpu_kms->reg_bus_path) + icc_set_bw(dpu_kms->reg_bus_path, 0, 0); + return 0; } @@ -1261,6 +1270,15 @@ static int __maybe_unused dpu_runtime_resume(struct device *dev) return rc; } + /* + * The vendor driver supports setting 76.8 / 150 / 300 Mbps on this + * path, but it seems to go for the highest level when display output + * is enabled and zero otherwise. For simplicity, we can assume that + * DPU being enabled and running implies that. + */ + if (dpu_kms->reg_bus_path) + icc_set_bw(dpu_kms->reg_bus_path, 0, MBps_to_icc(300)); + dpu_vbif_init_memtypes(dpu_kms); drm_for_each_encoder(encoder, ddev) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index d5d9bec90705..c332381d58c4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -111,6 +111,7 @@ struct dpu_kms { atomic_t bandwidth_ref; struct icc_path *mdp_path[2]; u32 num_mdp_paths; + struct icc_path *reg_bus_path; }; struct vsync_info {