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Signed-off-by: David Yang --- .../clock/simple-clock-controller.yaml | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/simple-clock-controller.yaml diff --git a/Documentation/devicetree/bindings/clock/simple-clock-controller.yaml b/Documentation/devicetree/bindings/clock/simple-clock-controller.yaml new file mode 100644 index 000000000000..3d9b436b0ef9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/simple-clock-controller.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/simple-clock-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Simple clock controller + +maintainers: + - David Yang + +description: | + A contiguous register region of multiple different clocks. No operations are + required to enable or disable the clock controller. + +properties: + compatible: + const: simple-clock-controller + + reg: + maxItems: 1 + +patternProperties: + '.*clock.*': + type: object + description: Clock devices. + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + clock-controller@ffff000 { + compatible = "simple-clock-controller"; + reg = <0xffff000 0x1000>; + }; From patchwork Sun Apr 16 19:46:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yangfl X-Patchwork-Id: 83927 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1719431vqo; Sun, 16 Apr 2023 12:59:51 -0700 (PDT) X-Google-Smtp-Source: AKy350bpJYY2w6MmVI7cnA8j3+cb+hw3XSknC1X9mdd1DWjWbqhzQQIqcVs2cZog4i14nzDhc/Dx X-Received: by 2002:a05:6a20:6915:b0:ee:ccf9:81bd with SMTP id q21-20020a056a20691500b000eeccf981bdmr7468079pzj.47.1681675191406; Sun, 16 Apr 2023 12:59:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681675191; cv=none; d=google.com; s=arc-20160816; b=R4t4dPwmdM1qiz0WCvSPNzaDGRnpoZKTxQoz81BuBRjeSuUJLpgJkCEJ4mQRwDf0fk rdDZ2qVo8lHxpa4gw2HCtCLWDe99Uv1Z34WjjFM+sOKWOikQr9qcJfJD2NQfo66nczLx XkmjifuFZWb27rIT7iOrzeHP4SEgcGDpXcL6OAHYebEvEpiH/06YgCs2UrWpTel98aLJ gxPHggSYteteLArztmaVhacFqzneIaLoK2YQ7DcDtrtJW803f0BBUWVH4Z3KITzIkUUt KOwsAvafH9QdV0Y6s94ZEB5lVUphrdvfDkRxR0LQ3oMTZFr514cbSA2c+eVEMXaoFwD3 Amog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=nSrRFiyosuWW/GNoXp6d9t9RRxXJdRUwrLc5G51X3r4=; b=YMcL8Wd+ZWCU59oQR8vPDtaZRuTDnh511Ge1pyCSL3zZV4vlEctUAZlarQ7oOqll1j jAUE2psTZFEiclk1qMlnX5PlOOUEf7PG7ZaqOp3bFl34u/Qjt35vaDAyM7LzM7yUvxPG E14degvhZWZR4YcTs5hg2HV4HzT2RBiqo20j0nJlF+0fR2I08EubSYQqkCNopSmYDS3D OnJxdDqUiuYHTKhfsBFa6UpN4xhLCnQ6kGKqwSlPeOK+5mU6/jdoXwjZvjJOrr5UPuod +l5bwdDaUpQTRMI/KrZHV3HGntTFG0lEfZIZ+Nn3S0dbf0wBEnFBxzJDNbP5wDbRbcig 5OBA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=gxmMxbe4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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To use them, a lock is required to avoid operation conflict on a same register. Add a clock controller to manage this lock. Signed-off-by: David Yang --- drivers/clk/Makefile | 1 + drivers/clk/clk-of.c | 292 +++++++++++++++++++++++++++++++++++++++++++ drivers/clk/clk-of.h | 26 ++++ 3 files changed, 319 insertions(+) create mode 100644 drivers/clk/clk-of.c create mode 100644 drivers/clk/clk-of.h diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index e3ca0d058a25..6cf0a888b673 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_COMMON_CLK) += clk-fractional-divider.o obj-$(CONFIG_COMMON_CLK) += clk-gpio.o ifeq ($(CONFIG_OF), y) obj-$(CONFIG_COMMON_CLK) += clk-conf.o +obj-$(CONFIG_COMMON_CLK) += clk-of.o endif # hardware specific clock types diff --git a/drivers/clk/clk-of.c b/drivers/clk/clk-of.c new file mode 100644 index 000000000000..3518ae848ed0 --- /dev/null +++ b/drivers/clk/clk-of.c @@ -0,0 +1,292 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2023 David Yang + * + * Simple straight-forward register clocks bindings + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk-of.h" + +struct of_clk_ctrl_priv { + spinlock_t lock; + + struct reset_controller_dev rcdev; + void __iomem *base; + bool rst_set_to_disable; +}; + +static const struct of_clk_flag of_clk_common_flags[] = { + { "set-rate-gate", CLK_SET_RATE_GATE }, + { "set-parent-gate", CLK_SET_PARENT_GATE }, + { "set-rate-parent", CLK_SET_RATE_PARENT }, + { "ignore-unused", CLK_IGNORE_UNUSED }, + { "get-rate-nocache", CLK_GET_RATE_NOCACHE }, + { "set-rate-no-reparent", CLK_SET_RATE_NO_REPARENT }, + { "get-accuracy-nocache", CLK_GET_ACCURACY_NOCACHE }, + { "recalc-new-rates", CLK_RECALC_NEW_RATES }, + { "set-rate-ungate", CLK_SET_RATE_UNGATE }, + { "critical", CLK_IS_CRITICAL }, + { "ops-parent-enable", CLK_OPS_PARENT_ENABLE }, + { "duty-cycle-parent", CLK_DUTY_CYCLE_PARENT }, + { } +}; + +void __iomem *of_clk_get_reg(struct device_node *np) +{ + u32 offset; + void __iomem *reg; + + if (of_property_read_u32(np, "offset", &offset)) + return NULL; + + reg = of_iomap(np->parent, 0); + if (!reg) + return NULL; + + return reg + offset; +} +EXPORT_SYMBOL_GPL(of_clk_get_reg); + +const char *of_clk_get_name(struct device_node *np) +{ + const char *name; + + if (!of_property_read_string(np, "clock-output-name", &name)) + return name; + + return of_node_full_name(np); +} +EXPORT_SYMBOL_GPL(of_clk_get_name); + +unsigned long +of_clk_get_flags(struct device_node *np, const struct of_clk_flag *defs) +{ + unsigned long flags = 0; + + if (!defs) + defs = of_clk_common_flags; + + for (int i = 0; defs[i].prop; i++) + if (of_property_read_bool(np, defs[i].prop)) + flags |= defs[i].flag; + + return flags; +} +EXPORT_SYMBOL_GPL(of_clk_get_flags); + +int of_clk_remove(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + + of_clk_del_provider(np); + clk_hw_unregister(np->data); + + return 0; +} +EXPORT_SYMBOL_GPL(of_clk_remove); + +int of_clk_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = pdev->dev.of_node; + int (*setup)(struct device_node *np) = of_device_get_match_data(dev); + + return setup(np); +} +EXPORT_SYMBOL_GPL(of_clk_probe); + +/** of_rst_ctrl **/ + +#if IS_ENABLED(CONFIG_RESET_CONTROLLER) +static int +of_rst_ctrl_assert(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct of_clk_ctrl_priv *priv = container_of(rcdev, struct of_clk_ctrl_priv, rcdev); + unsigned long flags; + u32 offset = id >> 16; + u8 index = id & 0x1f; + u32 val; + + if (WARN_ON(!priv->base)) + return 0; + + spin_lock_irqsave(&priv->lock, flags); + + val = readl(priv->base + offset); + if (priv->rst_set_to_disable) + val &= ~BIT(index); + else + val |= BIT(index); + writel(val, priv->base + offset); + + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static int +of_rst_ctrl_deassert(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct of_clk_ctrl_priv *priv = container_of(rcdev, struct of_clk_ctrl_priv, rcdev); + unsigned long flags; + u32 offset = id >> 16; + u8 index = id & 0x1f; + u32 val; + + if (WARN_ON(!priv->base)) + return 0; + + spin_lock_irqsave(&priv->lock, flags); + + val = readl(priv->base + offset); + if (priv->rst_set_to_disable) + val |= BIT(index); + else + val &= ~BIT(index); + writel(val, priv->base + offset); + + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static const struct reset_control_ops of_rst_ctrl_ops = { + .assert = of_rst_ctrl_assert, + .deassert = of_rst_ctrl_deassert, +}; + +static int of_rst_ctrl_of_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + return (reset_spec->args[0] << 16) | (reset_spec->args[1] & 0x1f); +} + +static void of_rst_ctrl_unsetup(struct device_node *np) +{ + struct of_clk_ctrl_priv *priv = np->data; + + reset_controller_unregister(&priv->rcdev); +} + +static int of_rst_ctrl_setup(struct device_node *np, struct of_clk_ctrl_priv *priv) +{ + priv->base = of_iomap(np, 0); + priv->rst_set_to_disable = of_property_read_bool(np, "set-to-disable"); + + /* register no matter whether reg exists, to detect dts bug */ + priv->rcdev.ops = &of_rst_ctrl_ops; + priv->rcdev.of_node = np; + priv->rcdev.of_reset_n_cells = 2; + priv->rcdev.of_xlate = of_rst_ctrl_of_xlate; + return reset_controller_register(&priv->rcdev); +} +#else +static void of_rst_ctrl_unsetup(struct device_node *np) +{ +} + +static int of_rst_ctrl_setup(struct device_node *np, struct of_clk_ctrl_priv *priv) +{ + return 0; +} +#endif + +/** of_crg_ctrl **/ + +static void of_crg_ctrl_unsetup(struct device_node *np, bool crg) +{ + if (crg) + of_rst_ctrl_unsetup(np); + + kfree(np->data); + np->data = NULL; +} + +static int of_crg_ctrl_setup(struct device_node *np, bool crg) +{ + struct of_clk_ctrl_priv *priv; + int ret; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + np->data = priv; + + spin_lock_init(&priv->lock); + + if (crg) { + ret = of_rst_ctrl_setup(np, priv); + if (ret) + goto err; + } + + return 0; + +err: + kfree(np->data); + np->data = NULL; + return ret; +} + +/** driver **/ + +static void __init of_clk_ctrl_init(struct device_node *np) +{ + of_crg_ctrl_setup(np, false); +} +CLK_OF_DECLARE(of_clk_ctrl, "simple-clock-controller", of_clk_ctrl_init); + +static void __init of_crg_ctrl_init(struct device_node *np) +{ + of_crg_ctrl_setup(np, true); +} +CLK_OF_DECLARE(of_crg_ctrl, "simple-clock-reset-controller", of_crg_ctrl_init); + +static int of_crg_ctrl_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = pdev->dev.of_node; + bool crg = (bool) of_device_get_match_data(dev); + + of_crg_ctrl_unsetup(np, crg); + + return 0; +} + +/* This function is not executed when of_clk_ctrl_init succeeded. */ +static int of_crg_ctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = pdev->dev.of_node; + bool crg = (bool) of_device_get_match_data(dev); + + return of_crg_ctrl_setup(np, crg); +} + +static const struct of_device_id of_crg_ctrl_ids[] = { + { .compatible = "simple-clock-controller", .data = (void *) false }, + { .compatible = "simple-clock-reset-controller", .data = (void *) true }, + { } +}; + +static struct platform_driver of_crg_ctrl_driver = { + .driver = { + .name = "clk_of", + .of_match_table = of_crg_ctrl_ids, + }, + .probe = of_crg_ctrl_probe, + .remove = of_crg_ctrl_remove, +}; +builtin_platform_driver(of_crg_ctrl_driver); diff --git a/drivers/clk/clk-of.h b/drivers/clk/clk-of.h new file mode 100644 index 000000000000..ddb1e57ec2f1 --- /dev/null +++ b/drivers/clk/clk-of.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT */ +/* + * Copyright (c) 2023 David Yang + */ + +#include + +struct device_node; +struct platform_device; + +struct of_clk_ctrl { + spinlock_t lock; +}; + +struct of_clk_flag { + const char *prop; + unsigned long flag; +}; + +void __iomem *of_clk_get_reg(struct device_node *np); +const char *of_clk_get_name(struct device_node *np); +unsigned long +of_clk_get_flags(struct device_node *np, const struct of_clk_flag *defs); + +int of_clk_remove(struct platform_device *pdev); +int of_clk_probe(struct platform_device *pdev); From patchwork Sun Apr 16 19:46:21 2023 Content-Type: text/plain; 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Signed-off-by: David Yang --- .../devicetree/bindings/clock/gate-clock.yaml | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/gate-clock.yaml diff --git a/Documentation/devicetree/bindings/clock/gate-clock.yaml b/Documentation/devicetree/bindings/clock/gate-clock.yaml new file mode 100644 index 000000000000..bcd549dd9db1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/gate-clock.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/gate-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Clock which can gate its output + +maintainers: + - David Yang + +description: | + Clock which can gate its output, by toggling one bit in a register. Such + register may also control other clocks or reset requests. + + The registers map is retrieved from the parental dt-node. So the clock node + should be represented as a sub-node of a "clock-controller" node. + + See also: Documentation/devicetree/bindings/clock/simple-clock-controller.yaml + +properties: + compatible: + const: gate-clock + + '#clock-cells': + const: 0 + + clocks: + maxItems: 1 + description: Parent clock. + + offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Offset in the register map for the control register (in bytes). + + bits: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Bit index which controls the output. + + clock-output-names: + maxItems: 1 + +required: + - compatible + - '#clock-cells' + - offset + - bits + +additionalProperties: false + +examples: + - | + clock { + compatible = "gate-clock"; + #clock-cells = <0>; + offset = <0xcc>; + bits = <3>; + clock-output-names = "my-clk"; + }; From patchwork Sun Apr 16 19:46:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yangfl X-Patchwork-Id: 83925 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1716614vqo; Sun, 16 Apr 2023 12:50:11 -0700 (PDT) X-Google-Smtp-Source: AKy350Z4wnfY/deIn+SBWqq24avPE23lXzftVFY+RU4jqL4bJ1x3zNz1ZVIdxD28OHURoOn1IDXM X-Received: by 2002:a05:6a20:1602:b0:ee:788b:45e0 with SMTP id l2-20020a056a20160200b000ee788b45e0mr10613538pzj.40.1681674610905; Sun, 16 Apr 2023 12:50:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681674610; cv=none; d=google.com; s=arc-20160816; b=x0C1v66vWvsqZ6Q/PSuTnD7/Wga8Ar43Wh5f8XXjzrlh3250gmX7mFb07XiCTrb8TB B8ypBSsfCT9+Tb1f2dWk3b/Ax2q7Kyr/A8WAcraSgaWaQWY8wNHKNVpw7fRMmgSAr5qY 8mBq3+x2vxd6xq9y+/BWGjNs8fLGba9lO6wdVRRV8ELUT56HHsvdV/GKJ5wbhfbUCXnV pemQmg2LTkA1CzYKKbKblPPnIVWfG73F+sprhwzUlzgpy62O+TPveKXV7rlG2uu4MmBF r6wK6HK67yLdk9fjksLF7HAWL4fQ/PQ1cly1REF3eEPZdQ2RG4aUNf3Blu8O7ZVgli4t RqDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=bxfOnlh1gWPz4ECc5+gyXwuy61sNCNvLdcJJf29rWhA=; b=NGCDFf80tTRzS7BtxwfUVd7Vy33I0Prlm/POeIaDKrggjVGL35Z15wX0yC+6gRoY3+ JyvaFPtn+IJMDPUzjSIjAcIsuK0TW9suHLgiqRO/aVCopT6u66/h6JcYGNHFr2Xwd9cF uCdccIEDBivdsMha4COdM9zE3wg/NKHWTfIxWwajmMXgP4W7WxNtJU+JoIIv2BBY5ImV kxd2U66QIrSh4goPfkaMGDEuHD7aUxFHvVjK2IV4NCyWC9/KQ/kGRyVSkqWKoqjjDiVk CDdj5Bt56wsbU/J8VxJ9rlZLUekZO1BWIKnk/R9jpSYfM7ZCt7ayDyPG5j23FKAdJffv 8JIQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=A5N7ttd+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: David Yang --- drivers/clk/clk-gate.c | 81 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index 64283807600b..a70df4a2a9a7 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -12,8 +12,11 @@ #include #include #include +#include #include +#include "clk-of.h" + /** * DOC: basic gatable clock which can gate and ungate it's ouput * @@ -257,3 +260,81 @@ struct clk_hw *__devm_clk_hw_register_gate(struct device *dev, return hw; } EXPORT_SYMBOL_GPL(__devm_clk_hw_register_gate); + +#if IS_ENABLED(CONFIG_OF) +static const struct of_clk_flag of_clk_gate_flags[] = { + { "set-to-disable", CLK_GATE_SET_TO_DISABLE }, + { "hiword-mask", CLK_GATE_HIWORD_MASK }, + { "big-endian", CLK_GATE_BIG_ENDIAN }, + { } +}; + +static int of_clk_gate_setup(struct device_node *np) +{ + struct of_clk_ctrl *ctrl = np->parent->data; + const char *name; + void __iomem *reg; + u32 bit_idx; + + const char *property; + struct clk_hw *hw; + int ret; + + reg = of_clk_get_reg(np); + if (!reg) + return -ENOMEM; + name = of_clk_get_name(np); + if (!name) + return -EINVAL; + + property = "bits"; + if (of_property_read_u32(np, property, &bit_idx)) + goto err_property; + + hw = __clk_hw_register_gate(NULL, np, name, + of_clk_get_parent_name(np, 0), + NULL, NULL, of_clk_get_flags(np, NULL), + reg, bit_idx, + of_clk_get_flags(np, of_clk_gate_flags), + &ctrl->lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); + if (ret) + goto err_register; + + np->data = hw; + return 0; + +err_register: + clk_hw_unregister(hw); + return ret; + +err_property: + pr_err("%s: clock %s missing required property \"%s\"\n", + __func__, name, property); + return -EINVAL; +} + +static void __init of_clk_gate_init(struct device_node *np) +{ + of_clk_gate_setup(np); +} +CLK_OF_DECLARE(of_clk_gate, "gate-clock", of_clk_gate_init); + +static const struct of_device_id of_clk_gate_ids[] = { + { .compatible = "gate-clock", .data = of_clk_gate_setup }, + { } +}; + +static struct platform_driver of_clk_gate_driver = { + .driver = { + .name = "clk_gate", + .of_match_table = of_clk_gate_ids, + }, + .probe = of_clk_probe, + .remove = of_clk_remove, +}; +builtin_platform_driver(of_clk_gate_driver); +#endif