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[2620:137:e000::1:20]) by mx.google.com with ESMTP id o5-20020a63f145000000b0050b51e62c1asi7662062pgk.63.2023.04.15.10.15.19; Sat, 15 Apr 2023 10:15:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=PydQOLA8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230016AbjDORON (ORCPT + 99 others); Sat, 15 Apr 2023 13:14:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41278 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229865AbjDOROJ (ORCPT ); Sat, 15 Apr 2023 13:14:09 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F4DF19B5; Sat, 15 Apr 2023 10:14:07 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id DAB6460DD5; Sat, 15 Apr 2023 17:14:06 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPS id 376CEC4339C; Sat, 15 Apr 2023 17:14:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1681578846; bh=G2tLPQgRxtDu3DlqJOjUZMbxuxbA9j8nbZJ62Yt8Xr4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=PydQOLA8GYq4RoykBlKmDwhVvmvYNjYP0K78lPjrqBm35+n0OIM7damXQdIg4gqIA x625zOT8aNcL4vzTnwxdxoeyU6e2HbC1A7xaUEmNPPiHxojqIT1Cb8+kpt82Svf6PW 25cGTbSuLw1JrMaPE2L/teZeLJZ4ldDoM/K8CO/2j84Wv6K6n7RRpfhtNHPakxCsyN p66oFKFV5LEr3w+vfkr6qntwVPxIwwpCzePFmYsVhyBLQNHVSiH8AT5GrYTMDYc/eP 26wN/KcASaK5HRlwLHxNBNfHzmovRcFPTZt1AfkuateuX2MsHf6CQIpoZhK+6V/PRH nLCflkRSgag4w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F770C77B73; Sat, 15 Apr 2023 17:14:06 +0000 (UTC) From: Yang Xiwen via B4 Relay Date: Sun, 16 Apr 2023 01:13:16 +0800 Subject: [PATCH RFC v2 1/3] mmc: dw_mmc-hi3798cv200: rename to dw_mmc-histb MIME-Version: 1.0 Message-Id: <20230415-mmc-hi3798mv200-v2-1-1d274f9b71da@outlook.com> References: <20230415-mmc-hi3798mv200-v2-0-1d274f9b71da@outlook.com> In-Reply-To: <20230415-mmc-hi3798mv200-v2-0-1d274f9b71da@outlook.com> To: Ulf Hansson , Jaehoon Chung , Rob Herring , Krzysztof Kozlowski , Yang Xiwen Cc: tianshuliang , Jiancheng Xue , Shawn Guo , David Yang , linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681578841; l=7027; i=forbidden405@outlook.com; s=20230415; h=from:subject:message-id; bh=eoErTepi3JKctxpmeTvJxlWPwF/xYjRv313AFyJJwn4=; b=R5BBYdyqfPcT93023bQw5XUb1MJKxMX1ynole5Q+KlpYZ+0kNi0KqLfxjgvV/XGc/eRRl9BeC xKrXuvHbOkDAORvEJty5TRrlsIAVXECj+8T4LY05lmoAsHYckWxZIEF X-Developer-Key: i=forbidden405@outlook.com; a=ed25519; pk=hfdpPU3AXR+t7fdv58tXCD4UzRNq+fop2TMJezFlAhM= X-Endpoint-Received: by B4 Relay for forbidden405@outlook.com/20230415 with auth_id=44 X-Original-From: Yang Xiwen Reply-To: X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FORGED_REPLYTO, FREEMAIL_REPLYTO_END_DIGIT,RCVD_IN_DNSWL_HI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763263311521523709?= X-GMAIL-MSGID: =?utf-8?q?1763263311521523709?= From: Yang Xiwen Rename to dw_mmc-histb and introduce a mechanism similar to dw-mmc_exynos to support more devices in a single driver. It is a preparation for introducing extension for Hi3798MV200. Signed-off-by: Yang Xiwen --- drivers/mmc/host/Kconfig | 8 +-- drivers/mmc/host/Makefile | 2 +- .../host/{dw_mmc-hi3798cv200.c => dw_mmc-histb.c} | 79 ++++++++++++++-------- 3 files changed, 57 insertions(+), 32 deletions(-) diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 4745fe217ade3..0aef4d845b743 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -779,14 +779,14 @@ config MMC_DW_EXYNOS Synopsys DesignWare Memory Card Interface driver. Select this option for platforms based on Exynos4 and Exynos5 SoC's. -config MMC_DW_HI3798CV200 - tristate "Hi3798CV200 specific extensions for Synopsys DW Memory Card Interface" +config MMC_DW_HISTB + tristate "HiSTB specific extensions for Synopsys DW Memory Card Interface" depends on MMC_DW select MMC_DW_PLTFM help - This selects support for HiSilicon Hi3798CV200 SoC specific extensions to the + This selects support for HiSilicon HiSTB SoC specific extensions to the Synopsys DesignWare Memory Card Interface driver. Select this option - for platforms based on HiSilicon Hi3798CV200 SoC. + for platforms based on HiSilicon HiSTB SoC. config MMC_DW_K3 tristate "K3 specific extensions for Synopsys DW Memory Card Interface" diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index a693fa3d3f1cc..0373741afebf1 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -50,7 +50,7 @@ obj-$(CONFIG_MMC_DW) += dw_mmc.o obj-$(CONFIG_MMC_DW_PLTFM) += dw_mmc-pltfm.o obj-$(CONFIG_MMC_DW_BLUEFIELD) += dw_mmc-bluefield.o obj-$(CONFIG_MMC_DW_EXYNOS) += dw_mmc-exynos.o -obj-$(CONFIG_MMC_DW_HI3798CV200) += dw_mmc-hi3798cv200.o +obj-$(CONFIG_MMC_DW_HISTB) += dw_mmc-histb.o obj-$(CONFIG_MMC_DW_K3) += dw_mmc-k3.o obj-$(CONFIG_MMC_DW_PCI) += dw_mmc-pci.o obj-$(CONFIG_MMC_DW_ROCKCHIP) += dw_mmc-rockchip.o diff --git a/drivers/mmc/host/dw_mmc-hi3798cv200.c b/drivers/mmc/host/dw_mmc-histb.c similarity index 69% rename from drivers/mmc/host/dw_mmc-hi3798cv200.c rename to drivers/mmc/host/dw_mmc-histb.c index 6f22fe0540879..106e586bcff4b 100644 --- a/drivers/mmc/host/dw_mmc-hi3798cv200.c +++ b/drivers/mmc/host/dw_mmc-histb.c @@ -18,14 +18,29 @@ #define ALL_INT_CLR 0x1ffff -struct hi3798cv200_priv { +enum dw_mci_histb_type { + DW_MCI_TYPE_HI3798CV200, +}; + +static struct dw_mci_histb_compat { + const char * const compatible; + enum dw_mci_histb_type ctrl_type; +} histb_compat[] = { + { + .compatible = "hisilicon,hi3798cv200-dw-mshc", + .ctrl_type = DW_MCI_TYPE_HI3798CV200, + }, +}; + +struct dw_mci_histb_priv { + enum dw_mci_histb_type ctrl_type; struct clk *sample_clk; struct clk *drive_clk; }; -static void dw_mci_hi3798cv200_set_ios(struct dw_mci *host, struct mmc_ios *ios) +static void dw_mci_histb_set_ios(struct dw_mci *host, struct mmc_ios *ios) { - struct hi3798cv200_priv *priv = host->priv; + struct dw_mci_histb_priv *priv = host->priv; u32 val; val = mci_readl(host, UHS_REG); @@ -62,7 +77,7 @@ static int dw_mci_hi3798cv200_execute_tuning(struct dw_mci_slot *slot, { static const int degrees[] = { 0, 45, 90, 135, 180, 225, 270, 315 }; struct dw_mci *host = slot->host; - struct hi3798cv200_priv *priv = host->priv; + struct dw_mci_histb_priv *priv = host->priv; int raise_point = -1, fall_point = -1; int err, prev_err = -1; int found = 0; @@ -118,15 +133,21 @@ static int dw_mci_hi3798cv200_execute_tuning(struct dw_mci_slot *slot, return err; } -static int dw_mci_hi3798cv200_init(struct dw_mci *host) +static int dw_mci_histb_init(struct dw_mci *host) { - struct hi3798cv200_priv *priv; - int ret; + struct dw_mci_histb_priv *priv; + struct device_node *np = host->dev->of_node; + int ret, idx; priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; + for (idx = 0; idx < ARRAY_SIZE(histb_compat); idx++) { + if (of_device_is_compatible(np, histb_compat[idx].compatible)) + priv->ctrl_type = histb_compat[idx].ctrl_type; + } + priv->sample_clk = devm_clk_get(host->dev, "ciu-sample"); if (IS_ERR(priv->sample_clk)) { dev_err(host->dev, "failed to get ciu-sample clock\n"); @@ -161,20 +182,29 @@ static int dw_mci_hi3798cv200_init(struct dw_mci *host) static const struct dw_mci_drv_data hi3798cv200_data = { .common_caps = MMC_CAP_CMD23, - .init = dw_mci_hi3798cv200_init, - .set_ios = dw_mci_hi3798cv200_set_ios, + .init = dw_mci_histb_init, + .set_ios = dw_mci_histb_set_ios, .execute_tuning = dw_mci_hi3798cv200_execute_tuning, }; -static int dw_mci_hi3798cv200_probe(struct platform_device *pdev) +static const struct of_device_id dw_mci_histb_match[] = { + { .compatible = "hisilicon,hi3798cv200-dw-mshc", .data = &hi3798cv200_data }, + {}, +}; + +static int dw_mci_histb_probe(struct platform_device *pdev) { - return dw_mci_pltfm_register(pdev, &hi3798cv200_data); + const struct of_device_id *match; + + match = of_match_node(dw_mci_histb_match, pdev->dev.of_node); + + return dw_mci_pltfm_register(pdev, match->data); } -static int dw_mci_hi3798cv200_remove(struct platform_device *pdev) +static int dw_mci_histb_remove(struct platform_device *pdev) { struct dw_mci *host = platform_get_drvdata(pdev); - struct hi3798cv200_priv *priv = host->priv; + struct dw_mci_histb_priv *priv = host->priv; clk_disable_unprepare(priv->drive_clk); clk_disable_unprepare(priv->sample_clk); @@ -184,23 +214,18 @@ static int dw_mci_hi3798cv200_remove(struct platform_device *pdev) return 0; } -static const struct of_device_id dw_mci_hi3798cv200_match[] = { - { .compatible = "hisilicon,hi3798cv200-dw-mshc", }, - {}, -}; - -MODULE_DEVICE_TABLE(of, dw_mci_hi3798cv200_match); -static struct platform_driver dw_mci_hi3798cv200_driver = { - .probe = dw_mci_hi3798cv200_probe, - .remove = dw_mci_hi3798cv200_remove, +MODULE_DEVICE_TABLE(of, dw_mci_histb_match); +static struct platform_driver dw_mci_histb_driver = { + .probe = dw_mci_histb_probe, + .remove = dw_mci_histb_remove, .driver = { - .name = "dwmmc_hi3798cv200", + .name = "dwmmc_histb", .probe_type = PROBE_PREFER_ASYNCHRONOUS, - .of_match_table = dw_mci_hi3798cv200_match, + .of_match_table = dw_mci_histb_match, }, }; -module_platform_driver(dw_mci_hi3798cv200_driver); +module_platform_driver(dw_mci_histb_driver); -MODULE_DESCRIPTION("HiSilicon Hi3798CV200 Specific DW-MSHC Driver Extension"); +MODULE_DESCRIPTION("HiSilicon HiSTB Specific DW-MSHC Driver Extension"); MODULE_LICENSE("GPL v2"); -MODULE_ALIAS("platform:dwmmc_hi3798cv200"); +MODULE_ALIAS("platform:dwmmc_histb"); From patchwork Sat Apr 15 17:13:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Xiwen via B4 Relay X-Patchwork-Id: 83756 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1153626vqo; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id d16-20020a170903231000b001a6a50d6526si4159085plh.579.2023.04.15.10.15.24; Sat, 15 Apr 2023 10:15:39 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=gHD79JjD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230044AbjDOROQ (ORCPT + 99 others); Sat, 15 Apr 2023 13:14:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41280 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229872AbjDOROJ (ORCPT ); Sat, 15 Apr 2023 13:14:09 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7A2ED2109; Sat, 15 Apr 2023 10:14:07 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 008B86164E; Sat, 15 Apr 2023 17:14:07 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPS id 53E0EC433EF; Sat, 15 Apr 2023 17:14:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1681578846; bh=I1zVuCbwHLpIyH1CupVPrNbprfDrqjzfxLYjmXNkoeE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=gHD79JjDvgR1muY38eVKilhiwOlUSydcD9U4dxn8fnwaTwz6476QJy+yeefYXk2nS rD6FZ7PKS28FUSbFERwWDmE2ANH4gfU3Cx+a/hGHn5iBDzMr8+3omWScMRk5X3ZSTX 8+AW0QtperHtrWrSWhUImyYgiUHDfKblBIR3QUh61kxRQHRIdjgjaVx+Bii+WIFWzw rmBA+3+4KGNlBUtYKy2Iw+9DxVRqtNODxXBl4KA1VcerWNyAQ4qFmId6qGsKFT09Rc kiOksV27H0TwPtlL8oIBgHsqTVgcj4OJe2H8aCHNVgp5SbXHct0Q+9OxZbOdoYj217 HMQGfESwtVGtQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3AF2FC77B70; Sat, 15 Apr 2023 17:14:06 +0000 (UTC) From: Yang Xiwen via B4 Relay Date: Sun, 16 Apr 2023 01:13:17 +0800 Subject: [PATCH RFC v2 2/3] mmc: dw_mmc-histb: add support for hi3798mv200 MIME-Version: 1.0 Message-Id: <20230415-mmc-hi3798mv200-v2-2-1d274f9b71da@outlook.com> References: <20230415-mmc-hi3798mv200-v2-0-1d274f9b71da@outlook.com> In-Reply-To: <20230415-mmc-hi3798mv200-v2-0-1d274f9b71da@outlook.com> To: Ulf Hansson , Jaehoon Chung , Rob Herring , Krzysztof Kozlowski , Yang Xiwen Cc: tianshuliang , Jiancheng Xue , Shawn Guo , David Yang , linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681578841; l=5756; i=forbidden405@outlook.com; s=20230415; h=from:subject:message-id; bh=BbS/l7vrq8NmARY0G9T42pzQupVXhImCLr1VN3mh6sA=; b=OfPsfIkbummvSPmaS8k6+VwGFK91apAhf9qWFdECma/0SQ5q4vw0BHQGc5tabfTK1lyXih5+m 0HhmN0DmfHLA8/4NIX9t3tmNISQoXoqiYeE6S1xmxR5QoFEsbc42qN8 X-Developer-Key: i=forbidden405@outlook.com; a=ed25519; pk=hfdpPU3AXR+t7fdv58tXCD4UzRNq+fop2TMJezFlAhM= X-Endpoint-Received: by B4 Relay for forbidden405@outlook.com/20230415 with auth_id=44 X-Original-From: Yang Xiwen Reply-To: X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FORGED_REPLYTO, FREEMAIL_REPLYTO_END_DIGIT,RCVD_IN_DNSWL_HI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763263318660465493?= X-GMAIL-MSGID: =?utf-8?q?1763263318660465493?= From: Yang Xiwen Add support for Hi3798MV200 specific extension. Signed-off-by: Yang Xiwen --- drivers/mmc/host/dw_mmc-histb.c | 110 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 109 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/dw_mmc-histb.c b/drivers/mmc/host/dw_mmc-histb.c index 106e586bcff4b..039b6df0e8c4d 100644 --- a/drivers/mmc/host/dw_mmc-histb.c +++ b/drivers/mmc/host/dw_mmc-histb.c @@ -16,10 +16,14 @@ #include "dw_mmc.h" #include "dw_mmc-pltfm.h" +#define SDMMC_TUNING_CTRL 0x118 +#define SDMMC_TUNING_FIND_EDGE BIT(5) + #define ALL_INT_CLR 0x1ffff enum dw_mci_histb_type { DW_MCI_TYPE_HI3798CV200, + DW_MCI_TYPE_HI3798MV200, }; static struct dw_mci_histb_compat { @@ -29,6 +33,9 @@ static struct dw_mci_histb_compat { { .compatible = "hisilicon,hi3798cv200-dw-mshc", .ctrl_type = DW_MCI_TYPE_HI3798CV200, + }, { + .compatible = "hisilicon,hi3798mv200-dw-mshc", + .ctrl_type = DW_MCI_TYPE_HI3798MV200, }, }; @@ -36,6 +43,7 @@ struct dw_mci_histb_priv { enum dw_mci_histb_type ctrl_type; struct clk *sample_clk; struct clk *drive_clk; + struct clk *sap_dll_mode_clk; }; static void dw_mci_histb_set_ios(struct dw_mci *host, struct mmc_ios *ios) @@ -68,7 +76,10 @@ static void dw_mci_histb_set_ios(struct dw_mci *host, struct mmc_ios *ios) if (ios->timing == MMC_TIMING_MMC_HS || ios->timing == MMC_TIMING_LEGACY) clk_set_phase(priv->drive_clk, 180); - else if (ios->timing == MMC_TIMING_MMC_HS200) + else if (ios->timing == MMC_TIMING_MMC_DDR52) { + clk_set_phase(priv->drive_clk, 90); + clk_set_phase(priv->sample_clk, 45); + } else if (ios->timing == MMC_TIMING_MMC_HS200) clk_set_phase(priv->drive_clk, 135); } @@ -133,6 +144,75 @@ static int dw_mci_hi3798cv200_execute_tuning(struct dw_mci_slot *slot, return err; } +static int dw_mci_hi3798mv200_execute_tuning_mix_mode(struct dw_mci_slot *slot, + u32 opcode) +{ + static const int degrees[] = { 0, 45, 90, 135, 180, 225, 270, 315 }; + struct dw_mci *host = slot->host; + struct dw_mci_histb_priv *priv = host->priv; + int raise_point = -1, fall_point = -1; + int err, prev_err = -1; + int found = 0; + int regval; + int i; + + clk_disable(priv->sap_dll_mode_clk); + for (i = 0; i < ARRAY_SIZE(degrees); i++) { + clk_set_phase(priv->sample_clk, degrees[i]); + mci_writel(host, RINTSTS, ALL_INT_CLR); + + err = mmc_send_tuning(slot->mmc, opcode, NULL); + if (err) + found = 1; + else { + regval = mci_readl(host, TUNING_CTRL); + if (regval & SDMMC_TUNING_FIND_EDGE) + found = 1; + }; + + if (i > 0) { + if (err && !prev_err) + fall_point = i - 1; + if (!err && prev_err) + raise_point = i; + } + + if (raise_point != -1 && fall_point != -1) + goto tuning_out; + + prev_err = err; + err = 0; + } + +tuning_out: + clk_enable(priv->sap_dll_mode_clk); + if (found) { + if (raise_point == -1) + raise_point = 0; + if (fall_point == -1) + fall_point = ARRAY_SIZE(degrees) - 1; + if (fall_point < raise_point) { + if ((raise_point + fall_point) > + (ARRAY_SIZE(degrees) - 1)) + i = fall_point / 2; + else + i = (raise_point + ARRAY_SIZE(degrees) - 1) / 2; + } else { + i = (raise_point + fall_point) / 2; + } + + clk_set_phase(priv->sample_clk, degrees[i]); + dev_dbg(host->dev, "Tuning clk_sample[%d, %d], set[%d]\n", + raise_point, fall_point, degrees[i]); + } else { + dev_err(host->dev, "No valid clk_sample shift! use default\n"); + err = -EINVAL; + } + + mci_writel(host, RINTSTS, ALL_INT_CLR); + return err; +} + static int dw_mci_histb_init(struct dw_mci *host) { struct dw_mci_histb_priv *priv; @@ -160,6 +240,14 @@ static int dw_mci_histb_init(struct dw_mci *host) return PTR_ERR(priv->drive_clk); } + if (priv->ctrl_type == DW_MCI_TYPE_HI3798MV200) { + priv->sap_dll_mode_clk = devm_clk_get(host->dev, "sap-dll-mode"); + if (IS_ERR(priv->sap_dll_mode_clk)) { + dev_err(host->dev, "failed to get sap-dll-mode clock\n"); + return PTR_ERR(priv->sap_dll_mode_clk); + } + } + ret = clk_prepare_enable(priv->sample_clk); if (ret) { dev_err(host->dev, "failed to enable ciu-sample clock\n"); @@ -172,9 +260,19 @@ static int dw_mci_histb_init(struct dw_mci *host) goto disable_sample_clk; } + if (priv->ctrl_type == DW_MCI_TYPE_HI3798MV200) { + ret = clk_prepare_enable(priv->sap_dll_mode_clk); + if (ret) { + dev_err(host->dev, "failed to disable tuning mode"); + goto disable_drive_clk; + } + } + host->priv = priv; return 0; +disable_drive_clk: + clk_disable_unprepare(priv->drive_clk); disable_sample_clk: clk_disable_unprepare(priv->sample_clk); return ret; @@ -187,8 +285,16 @@ static const struct dw_mci_drv_data hi3798cv200_data = { .execute_tuning = dw_mci_hi3798cv200_execute_tuning, }; +static const struct dw_mci_drv_data hi3798mv200_data = { + .common_caps = MMC_CAP_CMD23, + .init = dw_mci_histb_init, + .set_ios = dw_mci_histb_set_ios, + .execute_tuning = dw_mci_hi3798mv200_execute_tuning_mix_mode, +}; + static const struct of_device_id dw_mci_histb_match[] = { { .compatible = "hisilicon,hi3798cv200-dw-mshc", .data = &hi3798cv200_data }, + { .compatible = "hisilicon,hi3798mv200-dw-mshc", .data = &hi3798mv200_data }, {}, }; @@ -208,6 +314,8 @@ static int dw_mci_histb_remove(struct platform_device *pdev) clk_disable_unprepare(priv->drive_clk); clk_disable_unprepare(priv->sample_clk); + if (priv->ctrl_type == DW_MCI_TYPE_HI3798MV200) + clk_disable_unprepare(priv->sap_dll_mode_clk); dw_mci_pltfm_remove(pdev); From patchwork Sat Apr 15 17:13:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Xiwen via B4 Relay X-Patchwork-Id: 83757 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1153727vqo; Sat, 15 Apr 2023 10:15:53 -0700 (PDT) X-Google-Smtp-Source: AKy350a8CyqqspFSo+1NSVp5D9XFqO0z3+NXGlOBWDIP3xpj9dY/83yEF6T5+74WRd+1wnU06BEp X-Received: by 2002:a05:6a20:6d9c:b0:d9:e45d:95cd with SMTP id gl28-20020a056a206d9c00b000d9e45d95cdmr9165291pzb.17.1681578953513; Sat, 15 Apr 2023 10:15:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681578953; cv=none; d=google.com; s=arc-20160816; b=i7fwApP/UE4Zvw0DDFzbjZgO4DHtcs6rRcoCxTYAggVoX4UhjlPRpxzqnqZlespm63 3VKcLguQ0JWbSSU8RVJtUx9TCVKrEc86S+19PkofJp6+JSn/EOoI6PGFqHwqZNTLi4q+ 2XM6PN8I1BD61A9o48KTbV11OniJnpYhiYiRkvnk6bTobgWTSdgyMsRCJJsPja8aW5ML /C8f0/cSuYLnq5WoxJ5fHAfbjkcMfm3c+K/l2/9Itltl3SUt2/k/g+G724NN0dDErvwK 4nwEwnLtPjPEjZNjuWTupW47z3Zm5+KKTYW05yLhYqkEM9EcEvUZvXcPKph2DOkTgTzC QSKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:reply-to:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=65yD+SENaJAVLBCChRPk5HuB1AhK3Cu6zT8IZqmkmu8=; b=hDxZhJ0sPnHmMTQG50z2eIf0/dvEkSJJ/5Tv+i1Hi2kmU1HSeAF1N2P+sTE4v+hZHe 4hyk29V6sqFMcTUN657CXEE+yBYYU0zSvd+VEZnuGsS5S1+78n8FE2y6dNMa1ryDNNiD c4iENzryrTe5e0V/gT9ql0gLEpzmWEs1cR/sRWAnyHWgYFyrsDe9d0AEhCaJ+0Zoix0T XZcDh6syKAlMASdxLKom9L61yFIEwknDbGYE5ECsKbsIiBg0v3jGkh90IOrmD0Yfbd77 B/McTGW28jcA1v6KUG1Vc1QmveXTVt/oiQgVnJdCX22zhPrJ/S32X5NtRSRvTh0fJVVP mzAw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=dVB7EcOV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id d19-20020aa797b3000000b0063b74b436a9si3265548pfq.237.2023.04.15.10.15.38; Sat, 15 Apr 2023 10:15:53 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=dVB7EcOV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229865AbjDOROT (ORCPT + 99 others); Sat, 15 Apr 2023 13:14:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41282 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229908AbjDOROJ (ORCPT ); Sat, 15 Apr 2023 13:14:09 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 78EA21BC3; Sat, 15 Apr 2023 10:14:07 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 0EE606168E; Sat, 15 Apr 2023 17:14:07 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPS id 6D82DC433A1; Sat, 15 Apr 2023 17:14:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1681578846; bh=saJKbak66zJFATPAuanJ62qAZcL+5qkk0XwGqdYHsb4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=dVB7EcOVecE63YwXtEf4eKs4cjEkcn90iSk2KMpBWvqp1qRFzTVTqGH+rY71ufFyK 5OoG/dkbCJAelnl1z2uLglMf9zIXWYj8bOuPQchAZmx548V71UI0Sq+xd+EYMVvKKI 18LVqansUl165uVV4+/ZMsedVRgQtjQeq5glB4YLF6A9vXH/ea9GyTQ2HqqxsD1JHu I4s3gFkjdSCVPdMtisMsB7ZR3YUO2KU0GwGpWY+eYUEzaUqR7n70FvodAI0NWXiQQP wyNEx6pewKvwcd/0eROYAcGMS1TP4leaIya3SHWUGZfFOGpZ2KsAfOnlwLQkni0wX6 Cp48zE7BpB0Cw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54DFEC77B78; Sat, 15 Apr 2023 17:14:06 +0000 (UTC) From: Yang Xiwen via B4 Relay Date: Sun, 16 Apr 2023 01:13:18 +0800 Subject: [PATCH RFC v2 3/3] binding: mmc: hi3798cv200-dw-mshc: convert to YAML and rename to histb-dw-mshc, add compatible of hi3798mv200 MIME-Version: 1.0 Message-Id: <20230415-mmc-hi3798mv200-v2-3-1d274f9b71da@outlook.com> References: <20230415-mmc-hi3798mv200-v2-0-1d274f9b71da@outlook.com> In-Reply-To: <20230415-mmc-hi3798mv200-v2-0-1d274f9b71da@outlook.com> To: Ulf Hansson , Jaehoon Chung , Rob Herring , Krzysztof Kozlowski , Yang Xiwen Cc: tianshuliang , Jiancheng Xue , Shawn Guo , David Yang , linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681578841; l=4832; i=forbidden405@outlook.com; s=20230415; h=from:subject:message-id; bh=JIt1WKO/E/jF6bqUj7ql5V34Mtu9RTATejU7vIuUpXk=; b=u+DeFJqw2haCSzMfeqhvP2+DgCHXLB0jvJLFSB40eogHx+N9bppnzPPJx/MzKvlvlMTaaDB6y OKF8RVoe8f1AkohL1hka/dk8TBQtRha+8gG7Ln7nWYAvebbeBgIxA+B X-Developer-Key: i=forbidden405@outlook.com; a=ed25519; pk=hfdpPU3AXR+t7fdv58tXCD4UzRNq+fop2TMJezFlAhM= X-Endpoint-Received: by B4 Relay for forbidden405@outlook.com/20230415 with auth_id=44 X-Original-From: Yang Xiwen Reply-To: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FORGED_REPLYTO, FREEMAIL_REPLYTO_END_DIGIT,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763263332467640889?= X-GMAIL-MSGID: =?utf-8?q?1763263332467640889?= From: Yang Xiwen Hi3798MV200 has an extra clock, also document it here. Signed-off-by: Yang Xiwen --- .../bindings/mmc/hi3798cv200-dw-mshc.txt | 40 ---------- .../devicetree/bindings/mmc/histb-dw-mshc.yaml | 90 ++++++++++++++++++++++ 2 files changed, 90 insertions(+), 40 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/hi3798cv200-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/hi3798cv200-dw-mshc.txt deleted file mode 100644 index a0693b7145f2a..0000000000000 --- a/Documentation/devicetree/bindings/mmc/hi3798cv200-dw-mshc.txt +++ /dev/null @@ -1,40 +0,0 @@ -* Hisilicon Hi3798CV200 specific extensions to the Synopsys Designware Mobile - Storage Host Controller - -Read synopsys-dw-mshc.txt for more details - -The Synopsys designware mobile storage host controller is used to interface -a SoC with storage medium such as eMMC or SD/MMC cards. This file documents -differences between the core Synopsys dw mshc controller properties described -by synopsys-dw-mshc.txt and the properties used by the Hisilicon Hi3798CV200 -specific extensions to the Synopsys Designware Mobile Storage Host Controller. - -Required Properties: -- compatible: Should contain "hisilicon,hi3798cv200-dw-mshc". -- clocks: A list of phandle + clock-specifier pairs for the clocks listed - in clock-names. -- clock-names: Should contain the following: - "ciu" - The ciu clock described in synopsys-dw-mshc.txt. - "biu" - The biu clock described in synopsys-dw-mshc.txt. - "ciu-sample" - Hi3798CV200 extended phase clock for ciu sampling. - "ciu-drive" - Hi3798CV200 extended phase clock for ciu driving. - -Example: - - emmc: mmc@9830000 { - compatible = "hisilicon,hi3798cv200-dw-mshc"; - reg = <0x9830000 0x10000>; - interrupts = ; - clocks = <&crg HISTB_MMC_CIU_CLK>, - <&crg HISTB_MMC_BIU_CLK>, - <&crg HISTB_MMC_SAMPLE_CLK>, - <&crg HISTB_MMC_DRV_CLK>; - clock-names = "ciu", "biu", "ciu-sample", "ciu-drive"; - fifo-depth = <256>; - clock-frequency = <200000000>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - non-removable; - bus-width = <8>; - }; diff --git a/Documentation/devicetree/bindings/mmc/histb-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/histb-dw-mshc.yaml new file mode 100644 index 0000000000000..ea377bd5ea4bf --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/histb-dw-mshc.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/histb-dw-mshc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: + Hisilicon HiSTB SoC specific extensions to the Synopsys Designware Mobile + Storage Host Controller + +maintainers: + - Yang Xiwen + +description: + The Synopsys designware mobile storage host controller is used to interface a + SoC with storage medium such as eMMC or SD/MMC cards. This file documents + differences between the core Synopsys dw mshc controller properties described + by synopsys-dw-mshc.txt and the properties used by the Hisilicon HiSTB SoC + specific extensions to the Synopsys Designware Mobile Storage Host Controller. + +allOf: + - $ref: "synopsys-dw-mshc-common.yaml#" + - if: + properties: + compatible: + contains: + const: hisilicon,hi3798mv200-dw-mshc + then: + properties: + clocks: + minItems: 5 + + clock-names: + minItems: 5 + +properties: + compatible: + enum: + - hisilicon,hi3798cv200-dw-mshc + - hisilicon,hi3798mv200-dw-mshc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 4 + maxItems: 5 + description: A list of phandles for the clocks listed in clock-names + + clock-names: + minItems: 4 + items: + - const: ciu + - const: biu + - const: ciu-sample + - const: ciu-drive + - const: sap-dll-mode + +unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +examples: + - | + emmc: mmc@9830000 { + compatible = "hisilicon,hi3798cv200-dw-mshc"; + reg = <0x9830000 0x10000>; + interrupts = <35>; + clocks = <&crg 1>, + <&crg 2>, + <&crg 3>, + <&crg 4>; + clock-names = "ciu", "biu", "ciu-sample", "ciu-drive"; + fifo-depth = <256>; + clock-frequency = <200000000>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + bus-width = <8>; + }; +