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Fri, 14 Apr 2023 10:10:35 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, jeffreyalaw@gmail.com, Patrick O'Neill Subject: [PATCH v4 01/10] RISCV: Eliminate SYNC memory models Date: Fri, 14 Apr 2023 10:09:33 -0700 Message-Id: <20230414170942.1695672-2-patrick@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230414170942.1695672-1-patrick@rivosinc.com> References: <20230410182348.2168356-1-patrick@rivosinc.com> <20230414170942.1695672-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762371753488530894?= X-GMAIL-MSGID: =?utf-8?q?1763172487369607060?= Remove references to MEMMODEL_SYNC_* models by converting via memmodel_base(). 2023-04-14 Patrick O'Neill * riscv.cc: Remove MEMMODEL_SYNC_* cases and sanitize memmodel input with memmodel_base Signed-off-by: Patrick O'Neill --- gcc/config/riscv/riscv.cc | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 5f542932d13..2226241217d 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4288,14 +4288,11 @@ riscv_memmodel_needs_amo_acquire (enum memmodel model) { case MEMMODEL_ACQ_REL: case MEMMODEL_SEQ_CST: - case MEMMODEL_SYNC_SEQ_CST: case MEMMODEL_ACQUIRE: case MEMMODEL_CONSUME: - case MEMMODEL_SYNC_ACQUIRE: return true; case MEMMODEL_RELEASE: - case MEMMODEL_SYNC_RELEASE: case MEMMODEL_RELAXED: return false; @@ -4314,14 +4311,11 @@ riscv_memmodel_needs_release_fence (enum memmodel model) { case MEMMODEL_ACQ_REL: case MEMMODEL_SEQ_CST: - case MEMMODEL_SYNC_SEQ_CST: case MEMMODEL_RELEASE: - case MEMMODEL_SYNC_RELEASE: return true; case MEMMODEL_ACQUIRE: case MEMMODEL_CONSUME: - case MEMMODEL_SYNC_ACQUIRE: case MEMMODEL_RELAXED: return false; @@ -4360,6 +4354,7 @@ riscv_print_operand (FILE *file, rtx op, int letter) } machine_mode mode = GET_MODE (op); enum rtx_code code = GET_CODE (op); + const enum memmodel model = memmodel_base (INTVAL (op)); switch (letter) { @@ -4497,12 +4492,12 @@ riscv_print_operand (FILE *file, rtx op, int letter) break; case 'A': - if (riscv_memmodel_needs_amo_acquire ((enum memmodel) INTVAL (op))) + if (riscv_memmodel_needs_amo_acquire (model)) fputs (".aq", file); break; case 'F': - if (riscv_memmodel_needs_release_fence ((enum memmodel) INTVAL (op))) + if (riscv_memmodel_needs_release_fence (model)) fputs ("fence iorw,ow; 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Fri, 14 Apr 2023 10:10:39 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, jeffreyalaw@gmail.com, Patrick O'Neill Subject: [PATCH v4 02/10] RISCV: Enforce Libatomic LR/SC SEQ_CST Date: Fri, 14 Apr 2023 10:09:34 -0700 Message-Id: <20230414170942.1695672-3-patrick@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230414170942.1695672-1-patrick@rivosinc.com> References: <20230410182348.2168356-1-patrick@rivosinc.com> <20230414170942.1695672-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762371993405256455?= X-GMAIL-MSGID: =?utf-8?q?1763172531417114378?= Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs recommended by table A.6 of the ISA manual. 2023-04-14 Patrick O'Neill * atomic.c: Change LR.aq/SC.rl pairs into sequentially consistent LR.aqrl/SC.rl pair. Signed-off-by: Patrick O'Neill --- libgcc/config/riscv/atomic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libgcc/config/riscv/atomic.c b/libgcc/config/riscv/atomic.c index 69f53623509..5f895939b0b 100644 --- a/libgcc/config/riscv/atomic.c +++ b/libgcc/config/riscv/atomic.c @@ -39,7 +39,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see unsigned old, tmp1, tmp2; \ \ asm volatile ("1:\n\t" \ - "lr.w.aq %[old], %[mem]\n\t" \ + "lr.w.aqrl %[old], %[mem]\n\t" \ #insn " %[tmp1], %[old], %[value]\n\t" \ invert \ "and %[tmp1], %[tmp1], %[mask]\n\t" \ @@ -73,7 +73,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see unsigned old, tmp1; \ \ asm volatile ("1:\n\t" \ - "lr.w.aq %[old], %[mem]\n\t" \ + "lr.w.aqrl %[old], %[mem]\n\t" \ "and %[tmp1], %[old], %[mask]\n\t" \ "bne %[tmp1], %[o], 1f\n\t" \ "and %[tmp1], %[old], %[not_mask]\n\t" \ From patchwork Fri Apr 14 17:09:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 83525 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp536370vqo; Fri, 14 Apr 2023 10:13:52 -0700 (PDT) X-Google-Smtp-Source: AKy350auhx/HtgCzLnkXnWrdvfoC1dYe47JFvmOeZUjpXydmigbCHJFqBHdzMJ0f1aBFAzVJ2ESj X-Received: by 2002:a17:906:a185:b0:94d:cebe:691 with SMTP id s5-20020a170906a18500b0094dcebe0691mr6760954ejy.69.1681492432489; Fri, 14 Apr 2023 10:13:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681492432; cv=none; d=google.com; s=arc-20160816; b=kJUe6+XsFj7eCZxXUiFu3rWSgnzWWWKFyIm0DST0Ch5ODPEzJjXEKhgs0Ewatp7mwH k7BrZgJh5WE1qWUADmtW2yIcfReV7c0FI/i/RtwCl7gntsm7TLgN35Fq0jCEd14VZQ3h adgtGJ2NYqIZ+tjRbD9KP67ajWnPIsU6PQg6gfN0BBajOb6vlen2Na7tMzNE1QaZIfVZ n2Jzno6bf1zOiIuvwI37SqIrZpFb97pUImGxYlHpNgAscGwrX/DWynoTt793Q9NEGgc/ YPm+d8HMZPrNGj4Q0j8hBSR6aRE3MnbyFNyIv0bah/4KSkrxTlM6ZR8zG/eOMHAqGLEb 5HsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=3/vkZhQ8PDYCEjjETm6ZrVYW+wtecAJ3RegcZLRRolU=; b=PegIxsrk4bxvGD0H6k+BweXBDEXb1jy8JPF4ko5Wdk6LyP9u3UTM3W+DVgYKeL8K1J Vc6VuwHiaO+34EQQqH2gu821an7Qv3uMPYhlxfNXu+cqzSPW4bLIsUoOTzM0fmpw7qpi P7ABOEbmIVl2IDY+0A/o3+LiQFcukai+I5vpffDj/hBHhKDugq6Sh90q/tVOGriqU9Ux PdIlkPaeX94HebUt29FKdcM5rvb74wwTBF+kCTkMBa8tkrKBIQW+tNvHJZxFR8AkbjNe 9uOF7qyr9d83aTBkLTtQmsXVvPIONnBEpYUw1vj/4ZlZIh+cG9qG/YMwIs/gULF7uwgm q43g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=mTBxqUvf; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (ip-8-43-85-97.sourceware.org. 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Replace Fence/LR.aq/SC.aq pairs with SEQ_CST LR.aqrl/SC.rl pairs recommended by table A.6 of the ISA manual. 2023-04-14 Patrick O'Neill * sync.md: Change FENCE/LR.aq/SC.aq into sequentially consistent LR.aqrl/SC.rl pair. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/sync.md | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index c932ef87b9d..de42245981b 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -115,9 +115,16 @@ UNSPEC_COMPARE_AND_SWAP)) (clobber (match_scratch:GPR 6 "=&r"))] "TARGET_ATOMIC" - "%F5 1: lr.%A5 %0,%1; bne %0,%z2,1f; sc.%A4 %6,%z3,%1; bnez %6,1b; 1:" + { + return "1:\;" + "lr..aqrl\t%0,%1\;" + "bne\t%0,%z2,1f\;" + "sc..rl\t%6,%z3,%1\;" + "bnez\t%6,1b\;" + "1:"; + } [(set_attr "type" "atomic") - (set (attr "length") (const_int 20))]) + (set (attr "length") (const_int 16))]) (define_expand "atomic_compare_and_swap" [(match_operand:SI 0 "register_operand" "") ;; bool output From patchwork Fri Apr 14 17:09:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 83526 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp536667vqo; Fri, 14 Apr 2023 10:14:20 -0700 (PDT) X-Google-Smtp-Source: AKy350YdTR/Ty079FKYk+pqklStf2axlwsMmQOqw1ZV+WbVV9KW5vd77x/ctTTkvQYFM0RE12R+y X-Received: by 2002:a50:ff10:0:b0:502:9459:a69c with SMTP id a16-20020a50ff10000000b005029459a69cmr5842524edu.40.1681492459912; Fri, 14 Apr 2023 10:14:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681492459; cv=none; d=google.com; s=arc-20160816; b=N7OjD8uyAEHqBbKtO/8MknQYqGwHdPceG/Omrem20L0oIqWEJ+0upPWardKqlWYm++ C4PwbHX9hOY3B6a18VlT0zGFIMoZ/1chOiIfRNlp8nrjrGduW/mKT2MN6m6TF3LEV/+d ng/XNxmMi86nUT8uh8o8G2pHireDdFtrh5cniWzyWH3DjgOQLpK/uBCoCzPAtmu+QJQ8 e9xr6JwFIuYRW+isHzCOd8TPAi9/almOEd54dmg4odiYbXECy0uETm4jc764bxZJ04kI 4VDEoo58gWVCkGTVvjjhfFrosuFEF1SnUY4otEy8ylH/g3S0iHX0kTBFmfeBOWoR13qL +XSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=Hs5Gfc5dajyA6H2aUYpVLseiHqvQiCxKYrmPUR0EnXM=; b=zbM0cUKCVIxN5yEDhqjW5LBFmQEJ8bVzi/HaoScCRczx97KLpVKYhrEpdD+HjJfZ9O t31J5btIdS949vJ6Oq+QHobogjco8ql2CbctxIokWaE3Hz3A7qXfPsbTJBMVBAiVIscu 15Gr3J1tDPvOgxS9E0pTVGMjqKmjynqWHyyfWRG/1NRU6Ah+s5ZmXrj91LBcC9KxY3u5 ie1AYk7Y3vZDmKedF/St2ykeJh4mN4bRaj+IZ5h9UtusG1tPpD6IOk6J06tpf9d3W90A IwgY38tDpRPpqhpgqP5iMlATVwBXE4ox82rf4ccc0GJs4IMjbXYUc5DWYmr9aUgEup5L HIew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=BfDcGe3Y; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (ip-8-43-85-97.sourceware.org. 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Signed-off-by: Patrick O'Neill --- gcc/config/riscv/riscv.cc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 2226241217d..088b8d25773 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4492,8 +4492,13 @@ riscv_print_operand (FILE *file, rtx op, int letter) break; case 'A': - if (riscv_memmodel_needs_amo_acquire (model)) + if (riscv_memmodel_needs_amo_acquire (model) && + riscv_memmodel_needs_release_fence (model)) + fputs (".aqrl", file); + else if (riscv_memmodel_needs_amo_acquire (model)) fputs (".aq", file); + else if (riscv_memmodel_needs_release_fence (model)) + fputs (".rl", file); break; case 'F': From patchwork Fri Apr 14 17:09:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 83529 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp537506vqo; Fri, 14 Apr 2023 10:15:37 -0700 (PDT) X-Google-Smtp-Source: AKy350YujDSq6d8KkGSWoHKk3QFvYvG9Dz8WQ3NuZi/7/eg7eoEcmx2zXwiuRb/SxFKRvt66qAML X-Received: by 2002:a17:906:2316:b0:94e:de7c:8610 with SMTP id l22-20020a170906231600b0094ede7c8610mr3999096eja.36.1681492537288; Fri, 14 Apr 2023 10:15:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681492537; cv=none; d=google.com; s=arc-20160816; b=a+SWzSRcvW9/xvzEPIAphk9pVPtdgr1bzass3sKko8bI8idHMoOu5mnvvU2bGtiwtr eEvijDYMKs9Pfm+jn16fOhi1VKq3oZdefhv49oSCJq4iiUdRnOUgsgqm+dbSNWgzQbPC rKLvkbFgPbC5VyZ8p34CBWXV7sKlDF3vrbbpMobYrpN0MZIaqG4KbWmuBMMX7sEWJCCk I/eYlqSzyUCENmNwFQ/ucn3AK0fCFwI4bRIW+ZOCc1ZO7pBt+ZZZ4ryZg/unz8SeHPPA JdxM/tUa9a3khBYLDKi6CyyvaEKCRk7eVY/3WpazM7zPJ/nE0V+4LzfLn5TRQRzOPXOq gP5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=hgNbI1TBcSuRzqDRKXR/B31n00G0Q993qzxrnZ/hVuk=; b=ABenWFAxAq1KzBh9FcpJZwx6BoMI3cuyQKo2GiI1IHVDcec3azQYYgwLS1kxcGdBKj 8hl3Rwb1VFIUbV+PzSX9EGHqRoh9NnG8eXzrTB/WK6xk6weqwtiHGRhX18PfPxJaJoT/ X74NIqjF7uLBXNQ8svAmLFQ7bomy0LwkS0HFRWXYbOxH4BBZlrJI/Ru3NucE/HSgMFnH 1sXh0ozWppQ9q0fHFxHDZHa6d183YS4c5T+O7egPbv1WTCpRiw84D9jCpJ/NT+qQvgYX Qfr4NPmekuBXtGy1DIAW7ZOsbipW7lqZvTdFDkYy0mEBlcTZH6x2xdFKE8rSX5EOe720 OdMA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=fYrMurrJ; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id ge6-20020a170907908600b0094cb040cd6dsi4714697ejb.226.2023.04.14.10.15.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Apr 2023 10:15:37 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=fYrMurrJ; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9D27B385695E for ; Fri, 14 Apr 2023 17:12:22 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pl1-x641.google.com (mail-pl1-x641.google.com [IPv6:2607:f8b0:4864:20::641]) by sourceware.org (Postfix) with ESMTPS id B3F413858416 for ; Fri, 14 Apr 2023 17:10:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B3F413858416 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pl1-x641.google.com with SMTP id d9443c01a7336-1a686260adcso5940215ad.0 for ; Fri, 14 Apr 2023 10:10:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1681492249; x=1684084249; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hgNbI1TBcSuRzqDRKXR/B31n00G0Q993qzxrnZ/hVuk=; b=fYrMurrJQDC9E8jTbz36HAR+hCc26aBw/zC0IJie1B7Ncp0RnXrKC9C8USJtCiJBYb LUt/JlyatoF1pOC4i7xSaBfpALrvPoVI1cpBqsLjd3wt4sKIQA/waQJ1zndQVbjLTSnm rC/Gm+SomTCwpMTmvMzsyzq68MRxMAARsiPD3CEZNDkXUTkuBKrnowz8cMGXFgNtX6ys FLJp5X4ifeyAdHCT3TDHoOCUhdZJEiExf7vtrS9W2k+6usKRxyRO6MwSrSsRxnQ61yHP cPxRpN17bWqX7AskTLcOgConcBiEwa5QneUHbVQZuFHr3ZQkMIw9O4mmJ0LG61RIYFnd 1jjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681492249; x=1684084249; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hgNbI1TBcSuRzqDRKXR/B31n00G0Q993qzxrnZ/hVuk=; b=ledeItnpbJdRFd+Zu49qXSveiO1xEZoC9hg/zaWeLydDFrkHqbVlcfxu/xtBMCFrSV Z8GICwdqnBIfPNSi2QGDVkvauNBxwg36p1uRdJZ/X1C4jMcyt/DivRRC220umc8SJpXz OkCR0RFT3stRKW1JxnS50w0jm4Mnm7Mo5gB2VeVxKznR/cn9o1C5L01d+A4EMdjff/x4 GidyxyY4SFhX4XGUIVBw4y67nsP01joGA0FawzDl5pRW88KaUBJdcLG2b+k3jfG4k7Jo NUZKMWXaO5tNUQBiwCYOvC0TxEvsqzi6mErm+StZgwzQP1+QAkW/912Nf31JsBj+kPqC /FHA== X-Gm-Message-State: AAQBX9fybynfq+/jw4V58RST805v+4C4GAzqb7bT7/+wr3vB9Y5dU03C flVPKWWLKBh7RiSaDUix3W1+JK3pkh23OhrXJl0AVCbxFAo= X-Received: by 2002:a05:6a00:1146:b0:632:d45b:4d3e with SMTP id b6-20020a056a00114600b00632d45b4d3emr9534227pfm.2.1681492249599; Fri, 14 Apr 2023 10:10:49 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id 12-20020aa7924c000000b006258dd63a3fsm3271902pfp.56.2023.04.14.10.10.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Apr 2023 10:10:48 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, jeffreyalaw@gmail.com, Patrick O'Neill Subject: [PATCH v4 05/10] RISCV: Strengthen atomic stores Date: Fri, 14 Apr 2023 10:09:37 -0700 Message-Id: <20230414170942.1695672-6-patrick@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230414170942.1695672-1-patrick@rivosinc.com> References: <20230410182348.2168356-1-patrick@rivosinc.com> <20230414170942.1695672-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762815136210833429?= X-GMAIL-MSGID: =?utf-8?q?1763172718541990677?= This change makes atomic stores strictly stronger than table A.6 of the ISA manual. This mapping makes the overall patchset compatible with table A.7 as well. 2023-04-14 Patrick O'Neill PR target/89835 * sync.md (atomic_store): Use simple store instruction in combination with a fence. * pr89835.c: New test. Signed-off-by: Patrick O'Neill --- v3 Changelog: * Use a trailing fence for atomic stores to be compatible with Table A.7 --- gcc/config/riscv/sync.md | 20 +++++++++++++++++--- gcc/testsuite/gcc.target/riscv/pr89835.c | 9 +++++++++ 2 files changed, 26 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/pr89835.c diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index de42245981b..eef083b06e8 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -53,7 +53,8 @@ ;; Atomic memory operations. -;; Implement atomic stores with amoswap. Fall back to fences for atomic loads. +;; Implement atomic stores with conservative fences. Fall back to fences for atomic loads. +;; This allows us to be compatible with the ISA manual Table A.6 and Table A.7. (define_insn "atomic_store" [(set (match_operand:GPR 0 "memory_operand" "=A") (unspec_volatile:GPR @@ -61,9 +62,22 @@ (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_ATOMIC_STORE))] "TARGET_ATOMIC" - "%F2amoswap.%A2 zero,%z1,%0" + { + enum memmodel model = (enum memmodel) INTVAL (operands[2]); + model = memmodel_base (model); + + if (model == MEMMODEL_SEQ_CST) + return "fence\trw,w\;" + "s\t%z1,%0\;" + "fence\trw,rw"; + if (model == MEMMODEL_RELEASE) + return "fence\trw,w\;" + "s\t%z1,%0"; + else + return "s\t%z1,%0"; + } [(set_attr "type" "atomic") - (set (attr "length") (const_int 8))]) + (set (attr "length") (const_int 12))]) (define_insn "atomic_" [(set (match_operand:GPR 0 "memory_operand" "+A") diff --git a/gcc/testsuite/gcc.target/riscv/pr89835.c b/gcc/testsuite/gcc.target/riscv/pr89835.c new file mode 100644 index 00000000000..ab190e11b60 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr89835.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* Verify that relaxed atomic stores use simple store instuctions. */ +/* { dg-final { scan-assembler-not "amoswap" } } */ + +void +foo(int bar, int baz) +{ + __atomic_store_n(&bar, baz, __ATOMIC_RELAXED); +} From patchwork Fri Apr 14 17:09:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 83530 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp537882vqo; Fri, 14 Apr 2023 10:16:12 -0700 (PDT) X-Google-Smtp-Source: AKy350b8CW1yv9TYMLRa9CE1ATnD6DPKi2LJo7WVMOF/iK/Ml5lPoxD1Dz6wWCSvrEESu8Ljk1sl X-Received: by 2002:aa7:cad9:0:b0:504:894b:1bc9 with SMTP id l25-20020aa7cad9000000b00504894b1bc9mr6568619edt.26.1681492572164; Fri, 14 Apr 2023 10:16:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681492572; cv=none; d=google.com; s=arc-20160816; b=O8F4iHoe2/BrJsP6wWfQM44FA83QEReqlc58OCjDPXl2W7300wpbmYbfsGrvi6nyor bszA6qqe26Vxb0btGnjGoRmgIaZn/h2COkQpS+LVJZwlt/TxvS13Njzfit2HNd4hDOza 5Pa1BVfq0U2ZgGypb0MXaG5odQm3Hf8L8MCVU8IuV2V/Wn/iO3BWwcZqgBf+en/nZLlG F5+dBkHwm2tkUSw55vcNztyF3AqYMCHdZY/ZnxS3b55FftNIC3xyQxPVm0kuhL0YoOk7 VShdwhRuUpbH7Rt8/L3VAiYpN2GGlSEuXuBIapff13jCv9OOHekrswa9kN+OiAuXUIH+ VQWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=P9Da4sGTXFtl1RlbfN0nZAdSV4+gLUU/Cs6PMOmhG0U=; b=EAj0LO8MIbA0yjuukj1vheqYNdQPX10Y6EBJp484lBaALLbp8V/LrIPNWPh3L3+yb/ d1A+CZgPee9atmDSUhHiSH77qmuskzOZOQr4F4tM7CwiwCepI1322otPDjrjEcD4gG3q dla6GrHdN8qzyRx1fZ5yHidhMJ/jmz87dXibtIVhkS4qFS4be7BZ9GOkV8Kh9CZwO71X qH5wKBLk5rq5NkG7EDgvZElKFL062ny6Fp+gWz8UvKSc5I6uuLvb48JDQzIssGPG5XS+ kyrn9hd/d56O+haf21IvJcHHS90UiLkke1IcjYUuJPA+Hgp1ZL06VXN3IuEzOqVxygGF 0WSQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=ESyUr4qR; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (ip-8-43-85-97.sourceware.org. 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Remove unnecessary release fences from atomic ops. This change brings AMO ops in line with table A.6 of the ISA manual. 2023-04-14 Patrick O'Neill * riscv.cc (riscv_memmodel_needs_amo_acquire): Change function name. * riscv.cc (riscv_print_operand): Remove unneeded %F case. * sync.md: Remove unneeded fences. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/riscv.cc | 16 +++++----------- gcc/config/riscv/sync.md | 12 ++++++------ 2 files changed, 11 insertions(+), 17 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 088b8d25773..70031b83391 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4301,11 +4301,11 @@ riscv_memmodel_needs_amo_acquire (enum memmodel model) } } -/* Return true if a FENCE should be emitted to before a memory access to - implement the release portion of memory model MODEL. */ +/* Return true if the .RL suffix should be added to an AMO to implement the + release portion of memory model MODEL. */ static bool -riscv_memmodel_needs_release_fence (enum memmodel model) +riscv_memmodel_needs_amo_release (enum memmodel model) { switch (model) { @@ -4331,7 +4331,6 @@ riscv_memmodel_needs_release_fence (enum memmodel model) 'R' Print the low-part relocation associated with OP. 'C' Print the integer branch condition for comparison OP. 'A' Print the atomic operation suffix for memory model OP. - 'F' Print a FENCE if the memory model requires a release. 'z' Print x0 if OP is zero, otherwise print OP normally. 'i' Print i if the operand is not a register. 'S' Print shift-index of single-bit mask OP. @@ -4493,19 +4492,14 @@ riscv_print_operand (FILE *file, rtx op, int letter) case 'A': if (riscv_memmodel_needs_amo_acquire (model) && - riscv_memmodel_needs_release_fence (model)) + riscv_memmodel_needs_amo_release (model)) fputs (".aqrl", file); else if (riscv_memmodel_needs_amo_acquire (model)) fputs (".aq", file); - else if (riscv_memmodel_needs_release_fence (model)) + else if (riscv_memmodel_needs_amo_release (model)) fputs (".rl", file); break; - case 'F': - if (riscv_memmodel_needs_release_fence (model)) - fputs ("fence iorw,ow; ", file); - break; - case 'i': if (code != REG) fputs ("i", file); diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index eef083b06e8..fdfc56d64a1 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -87,9 +87,9 @@ (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] "TARGET_ATOMIC" - "%F2amo.%A2 zero,%z1,%0" + "amo.%A2\tzero,%z1,%0" [(set_attr "type" "atomic") - (set (attr "length") (const_int 8))]) + (set (attr "length") (const_int 4))]) (define_insn "atomic_fetch_" [(set (match_operand:GPR 0 "register_operand" "=&r") @@ -101,9 +101,9 @@ (match_operand:SI 3 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] "TARGET_ATOMIC" - "%F3amo.%A3 %0,%z2,%1" + "amo.%A3\t%0,%z2,%1" [(set_attr "type" "atomic") - (set (attr "length") (const_int 8))]) + (set (attr "length") (const_int 4))]) (define_insn "atomic_exchange" [(set (match_operand:GPR 0 "register_operand" "=&r") @@ -114,9 +114,9 @@ (set (match_dup 1) (match_operand:GPR 2 "register_operand" "0"))] "TARGET_ATOMIC" - "%F3amoswap.%A3 %0,%z2,%1" + "amoswap.%A3\t%0,%z2,%1" [(set_attr "type" "atomic") - (set (attr "length") (const_int 8))]) + (set (attr "length") (const_int 4))]) (define_insn "atomic_cas_value_strong" [(set (match_operand:GPR 0 "register_operand" "=&r") From patchwork Fri Apr 14 17:09:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 83531 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp538336vqo; Fri, 14 Apr 2023 10:16:50 -0700 (PDT) X-Google-Smtp-Source: AKy350Z8yu5Ul7JU1FfRvd5+9TtYYu4cWRJBfH52O51xFkOH1roxyRj2FiLV6NysT5aeqa75NKpm X-Received: by 2002:a05:6402:10d4:b0:506:70c9:b870 with SMTP id p20-20020a05640210d400b0050670c9b870mr6528330edu.3.1681492610273; Fri, 14 Apr 2023 10:16:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681492610; cv=none; d=google.com; s=arc-20160816; b=yBCPcMuYFW0pGNCqvEyxBbO8//fN4DZuD4MSKkVnMFU8d4DZ02KL5qM8kiJu36O97q GQRPPyo13CYP++1V8QdRIQYFtp2/6vKD3ds9XCHmIs4oOw524x67ZFlFphmWMy2W/heX 14JM6aobEp2rrenfXXR47GV8Q4lYYxT2Lmo2mVS86gyzHvoSIcTyUSZ4bi9j/tMFEeCP mdbubyuYry5xxDMfMLpRxUlmpB1fpsXn6dbeeCeA8qg90fMwpELHOxNvw1nRGXmVfSGt gfo9Pxqz2zI5jvZ/4tGiMJFs0ePhhSzlCzY7YdHVdoBymykBysNTDfCS/c+EimOXckWQ KQsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=qnLt+TsVHGjqe8EKHgHA1KX1+FLBSLemmcKlSKvFz2A=; b=hDcXImStzlZFRxjzhEpX2KJxuryzO7thY7zzdNJMtJLNI5SBKvjeek/bXpINBHECYA tv4sGulXb3yNWVlgaG3oJRVQb5UopJMNQfSOCMiNYZuEO4kbVPAil2aROianXdhltYa8 qdoQQVUQBx18KUXLGgCkKE6gr/g9pNhroG+s8Tgz1rgGjk9yhnRKaXzh0vutaau89eJ0 IWA8Hbgj5q925boczToZC2tZLLz/hn6xkx6T/DYNPnZPHwlFwJS8TaFzpLICRIH0qpb6 xBCS2UP0EnK2MbFO0FvCU+srVRu1i6jl0a6laa9/OYhNv1oCPI7cZ597p1XvL85Gf9lM WeUg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=ChlahbTB; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (ip-8-43-85-97.sourceware.org. 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Atomic compare and exchange ops provide success and failure memory models. C++17 and later place no restrictions on the relative strength of each model, so ensure we cover both by using a model that enforces the ordering of both given models. This change brings compare_exchange LR/SC ops in line with table A.6 of the ISA manual. 2023-04-14 Patrick O'Neill * riscv.cc: Add function to get the union of two memmodels in sync.md. * riscv-protos.h: Likewise. * sync.md (atomic_cas_value_strong): Remove static .aqrl bits on SC op/.rl bits on LR op and replace with optimized %I, %J flags. Signed-off-by: Patrick O'Neill --- v3 Changelog: * Consolidate tests in [PATCH v3 10/10] --- gcc/config/riscv/riscv-protos.h | 3 +++ gcc/config/riscv/riscv.cc | 44 +++++++++++++++++++++++++++++++++ gcc/config/riscv/sync.md | 9 +++++-- 3 files changed, 54 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 4611447ddde..b03edc3e8a5 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -22,6 +22,8 @@ along with GCC; see the file COPYING3. If not see #ifndef GCC_RISCV_PROTOS_H #define GCC_RISCV_PROTOS_H +#include "memmodel.h" + /* Symbol types we understand. The order of this list must match that of the unspec enum in riscv.md, subsequent to UNSPEC_ADDRESS_FIRST. */ enum riscv_symbol_type { @@ -79,6 +81,7 @@ extern void riscv_reinit (void); extern poly_uint64 riscv_regmode_natural_size (machine_mode); extern bool riscv_v_ext_vector_mode_p (machine_mode); extern bool riscv_shamt_matches_mask_p (int, HOST_WIDE_INT); +extern enum memmodel riscv_union_memmodels (enum memmodel, enum memmodel); /* Routines implemented in riscv-c.cc. */ void riscv_cpu_cpp_builtins (cpp_reader *); diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 70031b83391..b3b89bf444b 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4278,6 +4278,36 @@ riscv_print_operand_reloc (FILE *file, rtx op, bool hi_reloc) fputc (')', file); } +/* Return the memory model that encapuslates both given models. */ + +enum memmodel +riscv_union_memmodels (enum memmodel model1, enum memmodel model2) +{ + model1 = memmodel_base (model1); + model2 = memmodel_base (model2); + + enum memmodel weaker = model1 <= model2 ? model1: model2; + enum memmodel stronger = model1 > model2 ? model1: model2; + + switch (stronger) + { + case MEMMODEL_SEQ_CST: + case MEMMODEL_ACQ_REL: + return stronger; + case MEMMODEL_RELEASE: + if (weaker == MEMMODEL_ACQUIRE || weaker == MEMMODEL_CONSUME) + return MEMMODEL_ACQ_REL; + else + return stronger; + case MEMMODEL_ACQUIRE: + case MEMMODEL_CONSUME: + case MEMMODEL_RELAXED: + return stronger; + default: + gcc_unreachable (); + } +} + /* Return true if the .AQ suffix should be added to an AMO to implement the acquire portion of memory model MODEL. */ @@ -4331,6 +4361,8 @@ riscv_memmodel_needs_amo_release (enum memmodel model) 'R' Print the low-part relocation associated with OP. 'C' Print the integer branch condition for comparison OP. 'A' Print the atomic operation suffix for memory model OP. + 'I' Print the LR suffix for memory model OP. + 'J' Print the SC suffix for memory model OP. 'z' Print x0 if OP is zero, otherwise print OP normally. 'i' Print i if the operand is not a register. 'S' Print shift-index of single-bit mask OP. @@ -4500,6 +4532,18 @@ riscv_print_operand (FILE *file, rtx op, int letter) fputs (".rl", file); break; + case 'I': + if (model == MEMMODEL_SEQ_CST) + fputs (".aqrl", file); + else if (riscv_memmodel_needs_amo_acquire (model)) + fputs (".aq", file); + break; + + case 'J': + if (riscv_memmodel_needs_amo_release (model)) + fputs (".rl", file); + break; + case 'i': if (code != REG) fputs ("i", file); diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index fdfc56d64a1..a31b8c4f28a 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -130,10 +130,15 @@ (clobber (match_scratch:GPR 6 "=&r"))] "TARGET_ATOMIC" { + enum memmodel model_success = (enum memmodel) INTVAL(operands[4]); + enum memmodel model_failure = (enum memmodel) INTVAL(operands[5]); + /* Find the union of the two memory models so we can satisfy both success + and failure memory models. */ + operands[5] = GEN_INT(riscv_union_memmodels(model_success, model_failure)); return "1:\;" - "lr..aqrl\t%0,%1\;" + "lr.%I5\t%0,%1\;" "bne\t%0,%z2,1f\;" - "sc..rl\t%6,%z3,%1\;" + "sc.%J5\t%6,%z3,%1\;" "bnez\t%6,1b\;" "1:"; } From patchwork Fri Apr 14 17:09:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 83532 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp538744vqo; Fri, 14 Apr 2023 10:17:26 -0700 (PDT) X-Google-Smtp-Source: AKy350ZOm6oUcE79zRbfKDA2KbuGW37YRVJkI+VNU6TVyoo+Ap+dskyhILKHq9TTsI/bPnpyJ0wH X-Received: by 2002:aa7:dbd2:0:b0:504:de28:36fc with SMTP id v18-20020aa7dbd2000000b00504de2836fcmr5800521edt.38.1681492645871; Fri, 14 Apr 2023 10:17:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681492645; cv=none; d=google.com; s=arc-20160816; b=zsjZfmJkmdav8UDIhaTyKrC1xRHhyh9QoXQjTJkwCW38UI1qmQld/T6eYFGkVLzSKt 5/6Wq1BZr7HSJ2gih9BPF8nRwkcQcewQOyI+vK+3AShzcWp+lYekyUi7uFzFHLbob3Op spPulN8Iso3M9NIYApuizSPDVyasM4s98IilfCe2a1Y0wWBzTAKiP6YlSsH4YE3XRFxj 2xWaWCzl9BrR7ge7NKZYSJdIKcNRvUO5S1B6Qkeku1F54muoho05BDQJi6DErH16MRzc rgaRhE+JoPl0nku67vRu106ePUplR38xI2B6WOYGxI1892cf3mlxC9ADXHl1CrC2r+rP ap1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=VQ7bZtpi2cp1uLeZu12OoYkmqoLLJkZVj1Ye9cT2adU=; b=wdZ2E6TmVI0uJQYbThGiqGuKn4G8GjIIFOdJPX4lAjoJNn1iV1UFBLmPYiqEdcpKYv 4Fw+n2oy3vP+joYsqst8fuEmp9x9kOFL0w0QFAY3smroW9PB122xtpQqj1YaJRBeHvfl rfLI+oCGljvGq//VwcAxqTbgavyBkCFJy5q9xAfdBEcleuzQkkaAGKLpmnOkzj1IwH1x Egaus46AX37PHDAqHefdShdRbTca0B06v/uR9bbFXGbPc0eVgeUqXehTR9TW1YCJ4Xes 1Agk/7vJwI/0tfDFJHUdnLq+Vm7erVGPBXuz7tFs2tT0tccDv0D9xCVDxLgfILrYbEwK ZNRQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=L4V1ZdyD; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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Relax mem_thread_fence according to the memmodel given. 2023-04-14 Patrick O'Neill * sync.md (mem_thread_fence_1): Change fence depending on the given memory model. Signed-off-by: Patrick O'Neill --- v3 Changelog: * Consolidate tests in [PATCH v3 10/10] * Remove helper functions --- gcc/config/riscv/sync.md | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index a31b8c4f28a..e91fa29da51 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -42,14 +42,24 @@ DONE; }) -;; Until the RISC-V memory model (hence its mapping from C++) is finalized, -;; conservatively emit a full FENCE. (define_insn "mem_thread_fence_1" [(set (match_operand:BLK 0 "" "") (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER)) (match_operand:SI 1 "const_int_operand" "")] ;; model "" - "fence\tiorw,iorw") + { + enum memmodel model = (enum memmodel) INTVAL (operands[1]); + model = memmodel_base (model); + if (model == MEMMODEL_SEQ_CST) + return "fence\trw,rw"; + else if (model == MEMMODEL_ACQ_REL) + return "fence.tso"; + else if (model == MEMMODEL_ACQUIRE) + return "fence\tr,rw"; + else if (model == MEMMODEL_RELEASE) + return "fence\trw,w"; + } + [(set (attr "length") (const_int 4))]) ;; Atomic memory operations. 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Fri, 14 Apr 2023 10:10:57 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, jeffreyalaw@gmail.com, Patrick O'Neill Subject: [PATCH v4 09/10] RISCV: Weaken atomic loads Date: Fri, 14 Apr 2023 10:09:41 -0700 Message-Id: <20230414170942.1695672-10-patrick@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230414170942.1695672-1-patrick@rivosinc.com> References: <20230410182348.2168356-1-patrick@rivosinc.com> <20230414170942.1695672-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762815121064605899?= X-GMAIL-MSGID: =?utf-8?q?1763172644977892289?= This change brings atomic loads in line with table A.6 of the ISA manual. 2023-04-14 Patrick O'Neill * sync.md (atomic_load): Implement atomic load mapping. Signed-off-by: Patrick O'Neill --- v3 Changelog: * Add this patch --- gcc/config/riscv/sync.md | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index e91fa29da51..9e3685f5b1c 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -23,6 +23,7 @@ UNSPEC_COMPARE_AND_SWAP UNSPEC_SYNC_OLD_OP UNSPEC_SYNC_EXCHANGE + UNSPEC_ATOMIC_LOAD UNSPEC_ATOMIC_STORE UNSPEC_MEMORY_BARRIER ]) @@ -63,7 +64,31 @@ ;; Atomic memory operations. -;; Implement atomic stores with conservative fences. Fall back to fences for atomic loads. +(define_insn "atomic_load" + [(set (match_operand:GPR 0 "register_operand" "=r") + (unspec_volatile:GPR + [(match_operand:GPR 1 "memory_operand" "A") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_ATOMIC_LOAD))] + "TARGET_ATOMIC" + { + enum memmodel model = (enum memmodel) INTVAL (operands[2]); + model = memmodel_base (model); + + if (model == MEMMODEL_SEQ_CST) + return "fence\trw,rw\;" + "l\t%0,%1\;" + "fence\tr,rw"; + if (model == MEMMODEL_ACQUIRE) + return "l\t%0,%1\;" + "fence\tr,rw"; + else + return "l\t%0,%1"; + } + [(set_attr "type" "atomic") + (set (attr "length") (const_int 12))]) + +;; Implement atomic stores with conservative fences. ;; This allows us to be compatible with the ISA manual Table A.6 and Table A.7. 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Fri, 14 Apr 2023 10:10:59 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, jeffreyalaw@gmail.com, Patrick O'Neill Subject: [PATCH v4 10/10] RISCV: Table A.6 conformance tests Date: Fri, 14 Apr 2023 10:09:42 -0700 Message-Id: <20230414170942.1695672-11-patrick@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230414170942.1695672-1-patrick@rivosinc.com> References: <20230410182348.2168356-1-patrick@rivosinc.com> <20230414170942.1695672-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762815194126570113?= X-GMAIL-MSGID: =?utf-8?q?1763172681148521651?= These tests cover basic cases to ensure the atomic mappings follow the strengthened Table A.6 mappings that are compatible with Table A.7. 2023-04-14 Patrick O'Neill * amo-table-a-6-amo-add-1.c: New test. * amo-table-a-6-amo-add-2.c: Likewise. * amo-table-a-6-amo-add-3.c: Likewise. * amo-table-a-6-amo-add-4.c: Likewise. * amo-table-a-6-amo-add-5.c: Likewise. * amo-table-a-6-compare-exchange-1.c: Likewise. * amo-table-a-6-compare-exchange-2.c: Likewise. * amo-table-a-6-compare-exchange-3.c: Likewise. * amo-table-a-6-compare-exchange-4.c: Likewise. * amo-table-a-6-compare-exchange-5.c: Likewise. * amo-table-a-6-compare-exchange-6.c: Likewise. * amo-table-a-6-compare-exchange-7.c: Likewise. * amo-table-a-6-fence-1.c: Likewise. * amo-table-a-6-fence-2.c: Likewise. * amo-table-a-6-fence-3.c: Likewise. * amo-table-a-6-fence-4.c: Likewise. * amo-table-a-6-fence-5.c: Likewise. * amo-table-a-6-load-1.c: Likewise. * amo-table-a-6-load-2.c: Likewise. * amo-table-a-6-load-3.c: Likewise. * amo-table-a-6-store-1.c: Likewise. * amo-table-a-6-store-2.c: Likewise. * amo-table-a-6-store-compat-3.c: Likewise. Signed-off-by: Patrick O'Neill --- v3 Changelog: * Consolidate existing tests in this patch * Add new tests for store/load/amoadd --- v4 Changelog: * Add additional compare-exchange testcases * Update assertions to use scan-assembler-times for fences --- .../gcc.target/riscv/amo-table-a-6-amo-add-1.c | 8 ++++++++ .../gcc.target/riscv/amo-table-a-6-amo-add-2.c | 8 ++++++++ .../gcc.target/riscv/amo-table-a-6-amo-add-3.c | 8 ++++++++ .../gcc.target/riscv/amo-table-a-6-amo-add-4.c | 8 ++++++++ .../gcc.target/riscv/amo-table-a-6-amo-add-5.c | 8 ++++++++ .../riscv/amo-table-a-6-compare-exchange-1.c | 10 ++++++++++ .../riscv/amo-table-a-6-compare-exchange-2.c | 10 ++++++++++ .../riscv/amo-table-a-6-compare-exchange-3.c | 10 ++++++++++ .../riscv/amo-table-a-6-compare-exchange-4.c | 10 ++++++++++ .../riscv/amo-table-a-6-compare-exchange-5.c | 10 ++++++++++ .../riscv/amo-table-a-6-compare-exchange-6.c | 11 +++++++++++ .../riscv/amo-table-a-6-compare-exchange-7.c | 10 ++++++++++ .../gcc.target/riscv/amo-table-a-6-fence-1.c | 8 ++++++++ .../gcc.target/riscv/amo-table-a-6-fence-2.c | 10 ++++++++++ .../gcc.target/riscv/amo-table-a-6-fence-3.c | 10 ++++++++++ .../gcc.target/riscv/amo-table-a-6-fence-4.c | 10 ++++++++++ .../gcc.target/riscv/amo-table-a-6-fence-5.c | 10 ++++++++++ gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c | 9 +++++++++ gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c | 11 +++++++++++ gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c | 11 +++++++++++ .../gcc.target/riscv/amo-table-a-6-store-1.c | 9 +++++++++ .../gcc.target/riscv/amo-table-a-6-store-2.c | 11 +++++++++++ .../gcc.target/riscv/amo-table-a-6-store-compat-3.c | 11 +++++++++++ 23 files changed, 221 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c new file mode 100644 index 00000000000..ae7e407befc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "amoadd.w\t" } } */ + +void +foo (int* bar, int* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c new file mode 100644 index 00000000000..60d84f32481 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "amoadd.w.aq\t" } } */ + +void +foo (int* bar, int* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c new file mode 100644 index 00000000000..a97231e4e73 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "amoadd.w.rl\t" } } */ + +void +foo (int* bar, int* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c new file mode 100644 index 00000000000..3c843afdd5f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "amoadd.w.aqrl\t" } } */ + +void +foo (int* bar, int* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c new file mode 100644 index 00000000000..3434229f5e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "amoadd.w.aqrl\t" } } */ + +void +foo (int* bar, int* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c new file mode 100644 index 00000000000..a9141cde48f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_RELAXED, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c new file mode 100644 index 00000000000..b1ebb20e2f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_CONSUME, __ATOMIC_CONSUME); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c new file mode 100644 index 00000000000..47d8d02f7e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c new file mode 100644 index 00000000000..af6e1d69c75 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_RELEASE, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c new file mode 100644 index 00000000000..ceb5660b6af --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c new file mode 100644 index 00000000000..7b012fb1288 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +/* Mixed mappings need to be unioned. */ +/* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_RELEASE, __ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c new file mode 100644 index 00000000000..5adec6f7a19 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_SEQ_CST, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c new file mode 100644 index 00000000000..b8c28013ef3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-not "fence\t" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + +int main() { + __atomic_thread_fence(__ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c new file mode 100644 index 00000000000..117f9036e39 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "fence\tr,rw" 1 } } */ +/* { dg-final { scan-assembler-not "fence\trw,w" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ +/* { dg-final { scan-assembler-not "fence\trw,rw" } } */ + +int main() { + __atomic_thread_fence(__ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c new file mode 100644 index 00000000000..4b6dd7a9aa7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "fence\trw,w" 1 } } */ +/* { dg-final { scan-assembler-not "fence\tr,rw" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ +/* { dg-final { scan-assembler-not "fence\trw,rw" } } */ + +int main() { + __atomic_thread_fence(__ATOMIC_RELEASE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c new file mode 100644 index 00000000000..d40d3bc37db --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "fence.tso" 1 } } */ +/* { dg-final { scan-assembler-not "fence\trw,w" } } */ +/* { dg-final { scan-assembler-not "fence\tr,rw" } } */ +/* { dg-final { scan-assembler-not "fence\trw,rw" } } */ + +int main() { + __atomic_thread_fence(__ATOMIC_ACQ_REL); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c new file mode 100644 index 00000000000..71f76c27789 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "fence\trw,rw" 1 } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ +/* { dg-final { scan-assembler-not "fence\trw,w" } } */ +/* { dg-final { scan-assembler-not "fence\tr,rw" } } */ + +int main() { + __atomic_thread_fence(__ATOMIC_SEQ_CST); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c new file mode 100644 index 00000000000..8278198072e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* Verify that load mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-not "fence\t" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + +void +foo (int* bar, int* baz) { + __atomic_load(bar, baz, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c new file mode 100644 index 00000000000..84b6cc542ac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* Verify that load mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "fence\tr,rw" 1 } } */ +/* { dg-final { scan-assembler-not "fence\trw,w" } } */ +/* { dg-final { scan-assembler-not "fence\trw,rw" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + +void +foo (int* bar, int* baz) { + __atomic_load(bar, baz, __ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c new file mode 100644 index 00000000000..3f15041d117 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* Verify that load mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "fence\tr,rw" 1 } } */ +/* { dg-final { scan-assembler-times "fence\trw,rw" 1 } } */ +/* { dg-final { scan-assembler-not "fence\trw,w" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + +void +foo (int* bar, int* baz) { + __atomic_load(bar, baz, __ATOMIC_SEQ_CST); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c new file mode 100644 index 00000000000..c200bd1d11d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* Verify that store mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-not "fence\t" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + +void +foo (int* bar, int* baz) { + __atomic_store(bar, baz, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c new file mode 100644 index 00000000000..1cf366b5986 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* Verify that store mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "fence\trw,w" 1 } } */ +/* { dg-final { scan-assembler-not "fence\tr,rw" } } */ +/* { dg-final { scan-assembler-not "fence\trw,rw" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + +void +foo (int* bar, int* baz) { + __atomic_store(bar, baz, __ATOMIC_RELEASE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c new file mode 100644 index 00000000000..288e1493156 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* Verify that store mapping are compatible with Table A.6 & A.7. */ +/* { dg-final { scan-assembler-times "fence\trw,w" 1 } } */ +/* { dg-final { scan-assembler-times "fence\trw,rw" 1 } } */ +/* { dg-final { scan-assembler-not "fence\tr,rw" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + +void +foo (int* bar, int* baz) { + __atomic_store(bar, baz, __ATOMIC_SEQ_CST); +}