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[2a02:8440:d20f:2c76:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id h23-20020aa7c957000000b005066ca60b2csm2242687edt.63.2023.04.14.09.13.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Apr 2023 09:13:01 -0700 (PDT) From: Guillaume Ranquet Date: Fri, 14 Apr 2023 18:07:46 +0200 Subject: [PATCH v2 1/2] phy: mediatek: hdmi: mt8195: fix uninitialized variable usage in pll_calc MIME-Version: 1.0 Message-Id: <20230413-fixes-for-mt8195-hdmi-phy-v2-1-bbad62e64321@baylibre.com> References: <20230413-fixes-for-mt8195-hdmi-phy-v2-0-bbad62e64321@baylibre.com> In-Reply-To: <20230413-fixes-for-mt8195-hdmi-phy-v2-0-bbad62e64321@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Matthias Brugger , AngeloGioacchino Del Regno Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Guillaume Ranquet , kernel test robot X-Mailer: b4 0.13-dev X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763169713462095614?= X-GMAIL-MSGID: =?utf-8?q?1763169713462095614?= The ret variable in mtk_hdmi_pll_calc() was used unitialized as reported by the kernel test robot. Fix the issue by removing the variable altogether and testing out the return value of mtk_hdmi_pll_set_hw() Fixes: 45810d486bb44 ("phy: mediatek: add support for phy-mtk-hdmi-mt8195") Reported-by: kernel test robot Signed-off-by: Guillaume Ranquet Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nathan Chancellor --- drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c index abfc077fb0a8..054b73cb31ee 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c @@ -213,7 +213,7 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_phy, struct clk_hw *hw, u64 tmds_clk, pixel_clk, da_hdmitx21_ref_ck, ns_hdmipll_ck, pcw; u8 txpredivs[4] = { 2, 4, 6, 12 }; u32 fbkdiv_low; - int i, ret; + int i; pixel_clk = rate; tmds_clk = pixel_clk; @@ -292,13 +292,9 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_phy, struct clk_hw *hw, if (!(digital_div <= 32 && digital_div >= 1)) return -EINVAL; - mtk_hdmi_pll_set_hw(hw, PLL_PREDIV, fbkdiv_high, fbkdiv_low, + return mtk_hdmi_pll_set_hw(hw, PLL_PREDIV, fbkdiv_high, fbkdiv_low, PLL_FBKDIV_HS3, posdiv1, posdiv2, txprediv, txposdiv, digital_div); - if (ret) - return -EINVAL; - - return 0; } static int mtk_hdmi_pll_drv_setting(struct clk_hw *hw) From patchwork Fri Apr 14 16:07:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume Ranquet X-Patchwork-Id: 83509 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp504584vqo; Fri, 14 Apr 2023 09:26:27 -0700 (PDT) X-Google-Smtp-Source: AKy350be7p4B1ZbHpWpKoHICBPzlVks7hqDlKVOQamXp4/H/75dBCPp8UNdJKKl7F5qtHfh3h3fW X-Received: by 2002:a17:90a:3fc8:b0:234:159:4003 with SMTP id u8-20020a17090a3fc800b0023401594003mr5766112pjm.25.1681489587279; Fri, 14 Apr 2023 09:26:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681489587; cv=none; d=google.com; s=arc-20160816; b=H+wSuyOZ1TH0OGBc6vzGix05SHhaJ8Rxflz9JEad8cxROFPiF8WlrUv+b+guIcJQPX fYJ1nJWcPe4pmTC9LJwPqg2mV00Z9i4p5Fbr69rYH8AstmqXUY4kVcUEH6QVlVQB+dAs vgJAtL8YqkWkjOGdLhgsfEeIndRo4VAetuv6n1XvQhtYA1CU3cUNR6DFdcCxNZ6otbGZ b/JhqhLjeiYhaDjjUC6Kr0b54BpXs8xS0pc3L0XrvqSpa02nSOejTBEwhdz7ndi8XE83 fItBKIzGpak61yhB68pyLWdTQvP/dxAqQvhQ4wYiDBxCp4O9gF2zwcKkj4H3yZnw8P8E ATKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=flkZrEmQ4lhBir76YpEsiit3KQbCll7hap6g9ky4XjY=; b=ksjXuarVG1P6TQXv3gCBOz+InRMaM8XMcE3Jt8QUJL9Et7PipElbaTEUwgWSfhhPcv 9OM8P0npfVsoOVZHb+XfA/kOiXNlJ+f/1cRlfsj/gwQAtiHZiF1m5BoxQOhv3vLXCQ/P Dgm2f6/vDpJlZHf5MUZwPlTgQXLOCw5dSMRMqda2WdLMQDMhtovuUtdYjbb8VkWkn48a +sjO6/M2sQx8CIsUMPgSgjPPUq6k7nuY+t6pFEW5ciZr/Zsw0FxRzdfx6+RguEuQjBet 1JBplbDWBhPE2DGD78FjVQuDF0ylCr/bmDAfUbwvWUtqsEJXzOmNGOdmUMzatwzfEBB8 WFMg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20221208.gappssmtp.com header.s=20221208 header.b=zaTmkBAJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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[2a02:8440:d20f:2c76:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id h23-20020aa7c957000000b005066ca60b2csm2242687edt.63.2023.04.14.09.13.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Apr 2023 09:13:03 -0700 (PDT) From: Guillaume Ranquet Date: Fri, 14 Apr 2023 18:07:47 +0200 Subject: [PATCH v2 2/2] phy: mediatek: hdmi: mt8195: fix wrong pll calculus MIME-Version: 1.0 Message-Id: <20230413-fixes-for-mt8195-hdmi-phy-v2-2-bbad62e64321@baylibre.com> References: <20230413-fixes-for-mt8195-hdmi-phy-v2-0-bbad62e64321@baylibre.com> In-Reply-To: <20230413-fixes-for-mt8195-hdmi-phy-v2-0-bbad62e64321@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Matthias Brugger , AngeloGioacchino Del Regno Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Guillaume Ranquet X-Mailer: b4 0.13-dev X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763169625800733123?= X-GMAIL-MSGID: =?utf-8?q?1763169625800733123?= The clock rate calculus in mtk_hdmi_pll_calc() was wrong when it has been replaced by 'div_u64'. Fix the issue by multiplying the values in the denominator instead of dividing them. Fixes: 45810d486bb44 ("phy: mediatek: add support for phy-mtk-hdmi-mt8195") Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Guillaume Ranquet --- drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c index 054b73cb31ee..caa953780bee 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c @@ -271,7 +271,7 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_phy, struct clk_hw *hw, * [32,24] 9bit integer, [23,0]:24bit fraction */ pcw = div_u64(((u64)ns_hdmipll_ck) << PCW_DECIMAL_WIDTH, - da_hdmitx21_ref_ck / PLL_FBKDIV_HS3); + da_hdmitx21_ref_ck * PLL_FBKDIV_HS3); if (pcw > GENMASK_ULL(32, 0)) return -EINVAL; @@ -288,7 +288,7 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_phy, struct clk_hw *hw, posdiv2 = 1; /* Digital clk divider, max /32 */ - digital_div = div_u64((u64)ns_hdmipll_ck, posdiv1 / posdiv2 / pixel_clk); + digital_div = div_u64(ns_hdmipll_ck, posdiv1 * posdiv2 * pixel_clk); if (!(digital_div <= 32 && digital_div >= 1)) return -EINVAL;