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[2620:137:e000::1:20]) by mx.google.com with ESMTP id b11-20020a170903228b00b001a637615a89si5105702plh.561.2023.04.14.07.11.32; Fri, 14 Apr 2023 07:11:45 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SPrYVWnK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230431AbjDNOH2 (ORCPT + 99 others); Fri, 14 Apr 2023 10:07:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58038 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230327AbjDNOHJ (ORCPT ); Fri, 14 Apr 2023 10:07:09 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5DD5F59E5 for ; Fri, 14 Apr 2023 07:06:42 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id q26so11327079lfe.9 for ; Fri, 14 Apr 2023 07:06:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681481183; x=1684073183; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ypGX6B4su1o68R7FNx6eRYtltMnpOZkLcf7JaVu5ncA=; b=SPrYVWnK1EQd7VQe/CpLHqnW7L67MPK8fjhM1oXAYcwtdCSId52Zvn4tnES0lpcYO3 Z5eUVaFSDJObnVQBX29XaCX+f3dJsjTzcdOnwdjo5JWT1ISg3Xn6dMTEbgIyWUFklBYj E8XV/8PTxFirdCK+1VRKGd7aDtD72vietCjMdAc5bg/ioMxP8df6yYtAx2ehd3PrPkWr Ku9N/RFBZ2ImYmCOTZj0LjdO9/uNu618m1/dn4ifwVTQbSm1cMJTgmdP2m6Pi4LTpjEI +X3L5S4+DBiigRVZdOh76xlTRv4M1G1GiCmlLWGx7Y/vihohbWh92KSBIWAUoIAj75I6 B1EA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681481183; x=1684073183; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ypGX6B4su1o68R7FNx6eRYtltMnpOZkLcf7JaVu5ncA=; b=HL+JsSsogPWLXV1snbpIFo+kXSJKc6iDuo+agWMDKhBwoYpDR16Lrn8k3VaC3PIROY mhsOsZeOHJLjqzTVCrtIP7qp4r+bEryFtdTMYinzNpuQ8egIqW7bBq9Z5kCQhUQqhD4Z HdpGo+Pt4li1KisEc5VyVzripuiscxXaobCImTgPn/qeqNkh+PZuOWm59eyl4+UI8Pll lanOZ3IgVWScxxHDpHQ+qQke2hK/NthkOcVUByhYisDXoWBvoKIDRK0CIPjyvjywCK9P ZcJu0W7DyNTbZ/NTKqmtaeV7OkYeJpt6b3mvAmtNSJpeOKq6RiJVG4yO2FNqblkLJfW1 ke1Q== X-Gm-Message-State: AAQBX9eoYh53ce1fLtmX02PZZEqxps6UylorUBhQuXc+CXQBX9BnmnB4 5DrAibGre1nKe3AxRDHI5jjMtw== X-Received: by 2002:ac2:5a1c:0:b0:4ea:f632:4738 with SMTP id q28-20020ac25a1c000000b004eaf6324738mr1670009lfn.6.1681481183240; Fri, 14 Apr 2023 07:06:23 -0700 (PDT) Received: from [127.0.1.1] ([85.235.12.238]) by smtp.gmail.com with ESMTPSA id b10-20020ac25e8a000000b004d856fe5121sm808794lfq.194.2023.04.14.07.06.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Apr 2023 07:06:22 -0700 (PDT) From: Linus Walleij Date: Fri, 14 Apr 2023 16:06:17 +0200 Subject: [PATCH 1/6] pinctrl: pic32: Convert to immutable irq_chip MIME-Version: 1.0 Message-Id: <20230414-immutable-irqchips-2-v1-1-6b59a5186b00@linaro.org> References: <20230414-immutable-irqchips-2-v1-0-6b59a5186b00@linaro.org> In-Reply-To: <20230414-immutable-irqchips-2-v1-0-6b59a5186b00@linaro.org> To: Marc Zyngier , Viresh Kumar , Shiraz Hashim , soc@kernel.org, Bjorn Andersson , Andy Gross , Konrad Dybcio Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Linus Walleij X-Mailer: b4 0.12.1 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763161151843738393?= X-GMAIL-MSGID: =?utf-8?q?1763161151843738393?= Convert the driver to immutable irq-chip with a bit of intuition. Switch some call to use irqd_to_hwirq() in the process. Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-pic32.c | 36 +++++++++++++++++++++++++----------- 1 file changed, 25 insertions(+), 11 deletions(-) diff --git a/drivers/pinctrl/pinctrl-pic32.c b/drivers/pinctrl/pinctrl-pic32.c index 37acfdfc2cae..dad05294fa72 100644 --- a/drivers/pinctrl/pinctrl-pic32.c +++ b/drivers/pinctrl/pinctrl-pic32.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -60,8 +61,8 @@ struct pic32_desc_function { struct pic32_gpio_bank { void __iomem *reg_base; + int instance; struct gpio_chip gpio_chip; - struct irq_chip irq_chip; struct clk *clk; }; @@ -2008,12 +2009,14 @@ static void pic32_gpio_irq_mask(struct irq_data *data) struct pic32_gpio_bank *bank = irqd_to_bank(data); writel(BIT(PIC32_CNCON_ON), bank->reg_base + PIC32_CLR(CNCON_REG)); + gpiochip_disable_irq(&bank->gpio_chip, irqd_to_hwirq(data)); } static void pic32_gpio_irq_unmask(struct irq_data *data) { struct pic32_gpio_bank *bank = irqd_to_bank(data); + gpiochip_enable_irq(&bank->gpio_chip, irqd_to_hwirq(data)); writel(BIT(PIC32_CNCON_ON), bank->reg_base + PIC32_SET(CNCON_REG)); } @@ -2030,7 +2033,7 @@ static unsigned int pic32_gpio_irq_startup(struct irq_data *data) static int pic32_gpio_irq_set_type(struct irq_data *data, unsigned int type) { struct pic32_gpio_bank *bank = irqd_to_bank(data); - u32 mask = BIT(data->hwirq); + u32 mask = irqd_to_hwirq(data); switch (type & IRQ_TYPE_SENSE_MASK) { case IRQ_TYPE_EDGE_RISING: @@ -2122,14 +2125,7 @@ static void pic32_gpio_irq_handler(struct irq_desc *desc) .owner = THIS_MODULE, \ .can_sleep = 0, \ }, \ - .irq_chip = { \ - .name = "GPIO" #_bank, \ - .irq_startup = pic32_gpio_irq_startup, \ - .irq_ack = pic32_gpio_irq_ack, \ - .irq_mask = pic32_gpio_irq_mask, \ - .irq_unmask = pic32_gpio_irq_unmask, \ - .irq_set_type = pic32_gpio_irq_set_type, \ - }, \ + .instance = (_bank), \ } static struct pic32_gpio_bank pic32_gpio_banks[] = { @@ -2145,6 +2141,24 @@ static struct pic32_gpio_bank pic32_gpio_banks[] = { GPIO_BANK(9, PINS_PER_BANK), }; +static void pic32_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p) +{ + struct pic32_gpio_bank *bank = irqd_to_bank(data); + + seq_printf(p, "GPIO%d", bank->instance); +} + +static const struct irq_chip pic32_gpio_irq_chip = { + .irq_startup = pic32_gpio_irq_startup, + .irq_ack = pic32_gpio_irq_ack, + .irq_mask = pic32_gpio_irq_mask, + .irq_unmask = pic32_gpio_irq_unmask, + .irq_set_type = pic32_gpio_irq_set_type, + .irq_print_chip = pic32_gpio_irq_print_chip, + .flags = IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + static int pic32_pinctrl_probe(struct platform_device *pdev) { struct pic32_pinctrl *pctl; @@ -2243,7 +2257,7 @@ static int pic32_gpio_probe(struct platform_device *pdev) bank->gpio_chip.parent = &pdev->dev; girq = &bank->gpio_chip.irq; - girq->chip = &bank->irq_chip; + gpio_irq_chip_set_chip(girq, &pic32_gpio_irq_chip); girq->parent_handler = pic32_gpio_irq_handler; girq->num_parents = 1; girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents), From patchwork Fri Apr 14 14:06:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 83435 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp420109vqo; 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Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-pistachio.c | 35 +++++++++++++++++++++++++---------- 1 file changed, 25 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/pinctrl-pistachio.c b/drivers/pinctrl/pinctrl-pistachio.c index 7ca4ecb6eb8d..53408344927a 100644 --- a/drivers/pinctrl/pinctrl-pistachio.c +++ b/drivers/pinctrl/pinctrl-pistachio.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -93,10 +94,10 @@ struct pistachio_pin_group { struct pistachio_gpio_bank { struct pistachio_pinctrl *pctl; void __iomem *base; + int instance; unsigned int pin_base; unsigned int npins; struct gpio_chip gpio_chip; - struct irq_chip irq_chip; }; struct pistachio_pinctrl { @@ -1228,12 +1229,14 @@ static void pistachio_gpio_irq_mask(struct irq_data *data) struct pistachio_gpio_bank *bank = irqd_to_bank(data); gpio_mask_writel(bank, GPIO_INTERRUPT_EN, data->hwirq, 0); + gpiochip_disable_irq(&bank->gpio_chip, irqd_to_hwirq(data)); } static void pistachio_gpio_irq_unmask(struct irq_data *data) { struct pistachio_gpio_bank *bank = irqd_to_bank(data); + gpiochip_enable_irq(&bank->gpio_chip, irqd_to_hwirq(data)); gpio_mask_writel(bank, GPIO_INTERRUPT_EN, data->hwirq, 1); } @@ -1312,6 +1315,7 @@ static void pistachio_gpio_irq_handler(struct irq_desc *desc) #define GPIO_BANK(_bank, _pin_base, _npins) \ { \ + .instance = (_bank), \ .pin_base = _pin_base, \ .npins = _npins, \ .gpio_chip = { \ @@ -1326,14 +1330,6 @@ static void pistachio_gpio_irq_handler(struct irq_desc *desc) .base = _pin_base, \ .ngpio = _npins, \ }, \ - .irq_chip = { \ - .name = "GPIO" #_bank, \ - .irq_startup = pistachio_gpio_irq_startup, \ - .irq_ack = pistachio_gpio_irq_ack, \ - .irq_mask = pistachio_gpio_irq_mask, \ - .irq_unmask = pistachio_gpio_irq_unmask, \ - .irq_set_type = pistachio_gpio_irq_set_type, \ - }, \ } static struct pistachio_gpio_bank pistachio_gpio_banks[] = { @@ -1345,6 +1341,25 @@ static struct pistachio_gpio_bank pistachio_gpio_banks[] = { GPIO_BANK(5, PISTACHIO_PIN_MFIO(80), 10), }; +static void pistachio_gpio_irq_print_chip(struct irq_data *data, + struct seq_file *p) +{ + struct pistachio_gpio_bank *bank = irqd_to_bank(data); + + seq_printf(p, "GPIO%d", bank->instance); +} + +static const struct irq_chip pistachio_gpio_irq_chip = { + .irq_startup = pistachio_gpio_irq_startup, + .irq_ack = pistachio_gpio_irq_ack, + .irq_mask = pistachio_gpio_irq_mask, + .irq_unmask = pistachio_gpio_irq_unmask, + .irq_set_type = pistachio_gpio_irq_set_type, + .irq_print_chip = pistachio_gpio_irq_print_chip, + .flags = IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + static int pistachio_gpio_register(struct pistachio_pinctrl *pctl) { struct pistachio_gpio_bank *bank; @@ -1394,7 +1409,7 @@ static int pistachio_gpio_register(struct pistachio_pinctrl *pctl) bank->gpio_chip.fwnode = child; girq = &bank->gpio_chip.irq; - girq->chip = &bank->irq_chip; + gpio_irq_chip_set_chip(girq, &pistachio_gpio_irq_chip); girq->parent_handler = pistachio_gpio_irq_handler; girq->num_parents = 1; girq->parents = devm_kcalloc(pctl->dev, 1, From patchwork Fri Apr 14 14:06:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 83431 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp415890vqo; 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Signed-off-by: Linus Walleij --- drivers/pinctrl/spear/pinctrl-plgpio.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/spear/pinctrl-plgpio.c b/drivers/pinctrl/spear/pinctrl-plgpio.c index ada401ef4342..722681e0b89b 100644 --- a/drivers/pinctrl/spear/pinctrl-plgpio.c +++ b/drivers/pinctrl/spear/pinctrl-plgpio.c @@ -301,6 +301,7 @@ static void plgpio_irq_disable(struct irq_data *d) spin_lock_irqsave(&plgpio->lock, flags); plgpio_reg_set(plgpio->regmap, offset, plgpio->regs.ie); spin_unlock_irqrestore(&plgpio->lock, flags); + gpiochip_disable_irq(gc, irqd_to_hwirq(d)); } static void plgpio_irq_enable(struct irq_data *d) @@ -317,6 +318,7 @@ static void plgpio_irq_enable(struct irq_data *d) return; } + gpiochip_enable_irq(gc, irqd_to_hwirq(d)); spin_lock_irqsave(&plgpio->lock, flags); plgpio_reg_reset(plgpio->regmap, offset, plgpio->regs.ie); spin_unlock_irqrestore(&plgpio->lock, flags); @@ -356,11 +358,13 @@ static int plgpio_irq_set_type(struct irq_data *d, unsigned trigger) return 0; } -static struct irq_chip plgpio_irqchip = { +static const struct irq_chip plgpio_irqchip = { .name = "PLGPIO", .irq_enable = plgpio_irq_enable, .irq_disable = plgpio_irq_disable, .irq_set_type = plgpio_irq_set_type, + .flags = IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, }; static void plgpio_irq_handler(struct irq_desc *desc) @@ -595,7 +599,7 @@ static int plgpio_probe(struct platform_device *pdev) struct gpio_irq_chip *girq; girq = &plgpio->chip.irq; - girq->chip = &plgpio_irqchip; + gpio_irq_chip_set_chip(girq, &plgpio_irqchip); girq->parent_handler = plgpio_irq_handler; girq->num_parents = 1; girq->parents = devm_kcalloc(&pdev->dev, 1, From patchwork Fri Apr 14 14:06:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 83427 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp411967vqo; Fri, 14 Apr 2023 07:10:37 -0700 (PDT) X-Google-Smtp-Source: AKy350bxY8NK7dbsBVA7W/n+i1ncLdlhq5IzYKk6nLzjSJZbFtANqNxYzR3N2+Z8CXOKCyP46+1J X-Received: by 2002:a05:6a20:3b92:b0:da:3903:f5e7 with SMTP id b18-20020a056a203b9200b000da3903f5e7mr5725117pzh.0.1681481437672; Fri, 14 Apr 2023 07:10:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681481437; cv=none; d=google.com; s=arc-20160816; b=vQ4SmHLs+prmR3Nh3RCSUFz81JgHYNyud54SfE8NlsvgP3pe5BIzw5Bl7KP6JBSNkg oAW9j1xc32vU7fNUVBvRsJHPXz1Z2kYrh23Cog5Nu9/cAfcwMP5mqBcsiKpTrs7HP4Eb gFFVyPG2p482U8qNnMe8gHsp9JFW5V+j24hZ68St9GSK1s/x2qlllU8v939oelVPmkuI AkEeNHWPsoQrcUIKnw8zpoi7UHv9GE0d0lnkYCCTj3QiQ94DSWTq2aPNFF631Zf0/FK5 g1NXlte053QuA6M9uhDCOwswSuGZXXrTKsPuDXKabtJETQOZZ1VGMVfMHORNBOaDu3vG 8+uA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=4BHCI/166BKjZ+FXcUih3BMF+v7LRQkg3jx37UcTFdA=; b=nhf83JAQjEz7r0cq/wWNVXHg0/oyGlrAzDP26qAo7ltonxYGSryPoERLJ7eDONZrL8 2T7LYjg9i5AMYnMvsSbfXsXBNezZCccY3JC7EFAPdRCz9X9IaKrykkz5TJ/7jiIQ34TK osQWdE2GAfMz4N9oPSuQRIVEDpmG3/DscuabOiVFkIvyslP/OsJG/rN26rS61JeNmWGE Q0W/q5c74+pHW90M/XX9ndCw72R+lHcSzxbta60EP1NmwuKQZbCd0wtZri9WrQjdwvZI PhMDHEdXqvz41MdobdNIz6l0jM14ICAMHBbDEX2s2dJonihkIXTzbbU9zSqBXjDedNqK lGFg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Rtev4/ou"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-spmi-mpp.c | 38 ++++++++++++++++++++++++--------- 1 file changed, 28 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c index 644fb4a0e72a..fe0393829c20 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c @@ -143,7 +143,6 @@ struct pmic_mpp_state { struct regmap *map; struct pinctrl_dev *ctrl; struct gpio_chip chip; - struct irq_chip irq; }; static const struct pinconf_generic_params pmic_mpp_bindings[] = { @@ -823,6 +822,33 @@ static int pmic_mpp_child_to_parent_hwirq(struct gpio_chip *chip, return 0; } +static void pmic_mpp_irq_mask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + + irq_chip_mask_parent(d); + gpiochip_disable_irq(gc, irqd_to_hwirq(d)); +} + +static void pmic_mpp_irq_unmask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + + gpiochip_enable_irq(gc, irqd_to_hwirq(d)); + irq_chip_unmask_parent(d); +} + +static const struct irq_chip pmic_mpp_irq_chip = { + .name = "spmi-mpp", + .irq_ack = irq_chip_ack_parent, + .irq_mask = pmic_mpp_irq_mask, + .irq_unmask = pmic_mpp_irq_unmask, + .irq_set_type = irq_chip_set_type_parent, + .irq_set_wake = irq_chip_set_wake_parent, + .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + static int pmic_mpp_probe(struct platform_device *pdev) { struct irq_domain *parent_domain; @@ -915,16 +941,8 @@ static int pmic_mpp_probe(struct platform_device *pdev) if (!parent_domain) return -ENXIO; - state->irq.name = "spmi-mpp", - state->irq.irq_ack = irq_chip_ack_parent, - state->irq.irq_mask = irq_chip_mask_parent, - state->irq.irq_unmask = irq_chip_unmask_parent, - state->irq.irq_set_type = irq_chip_set_type_parent, - state->irq.irq_set_wake = irq_chip_set_wake_parent, - state->irq.flags = IRQCHIP_MASK_ON_SUSPEND, - girq = &state->chip.irq; - girq->chip = &state->irq; + gpio_irq_chip_set_chip(girq, &pmic_mpp_irq_chip); girq->default_type = IRQ_TYPE_NONE; girq->handler = handle_level_irq; girq->fwnode = dev_fwnode(state->dev); From patchwork Fri Apr 14 14:06:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 83437 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp421513vqo; Fri, 14 Apr 2023 07:23:50 -0700 (PDT) X-Google-Smtp-Source: AKy350a4SBi7K/6xrIFbWB6wQNEaKC7epaVSGXQqSs6CS4dyu+B4YPMUdKCp5xw1LH01mVK4qwBd X-Received: by 2002:a05:6a20:8427:b0:ed:1355:f88a with SMTP id c39-20020a056a20842700b000ed1355f88amr4061494pzd.46.1681482229943; Fri, 14 Apr 2023 07:23:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681482229; cv=none; d=google.com; s=arc-20160816; b=YnEA8cenwS/lo8UC8PgTu76vVJ+OWedHbeloNBO6qNYniEMQtqLYXHZ1svEnOTKaTZ D49AqSzGBPuTMf0Ph9TzPtgxH7xt+RUtSELl9OWPesrA5aY8I6t/+BjZ6YR4z4h/q8KV c36LbxqS9MSgSHwfJNrkvAoCeD0kLs/sALrDRs621mx0zp1GRVj3b0nM2VChwskySNsZ vxXPGEA8/oCLFDMhTTQUW+Mk7LkW+R3vNior4z33BomKWS2sNzXQLH+l76HSTGNe5nHL 1lYTK4W4A4poHO/SyHGdTx8g0hfdPAVq6ZfOjpuvlQ5GvPqmstE9a1T6QCc4wbsD9A5S ye/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=QwKMQO59szubKjzAdKHEDn1K/Q985iFYjG/Q5Lazatw=; b=Py1F9CKBxkgHYNxTReMB1f5ULWh4QANkv00ZX4LdU2qsXQITNsdCMVK8N6XZoxkJWP R0K76yWQqH5Nbn/qdiZWOKgD5xRU4dFI/xHqNxAYizhHqx6WS0fAFeBarh0CH37WH3t8 E+Pj7wTM7n2IgU8mwCK154kX/cz/pUijLDTnNRy1PnzXnRRPTF4sUliqnXTcLLmurJtV 2jGfvhXBcp5smmu7ghFmk3FEPxngTF65xpHnGdaBBT3tSIPsBcXShb2bn97nc5Ro3aRl ojRifINePM6DddU1M14rltvxkHM+GG4f0Imh/q9ZjXcIwOCKnyiwYHkQNWEiNDl/fxgr 8yzQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mm0rr2Ai; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c | 35 +++++++++++++++++++++++++-------- 1 file changed, 27 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c index 86f66cb8bf30..b5aed540f07e 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c @@ -126,7 +126,6 @@ struct pm8xxx_mpp { struct regmap *regmap; struct pinctrl_dev *pctrl; struct gpio_chip chip; - struct irq_chip irq; struct pinctrl_desc desc; unsigned npins; @@ -778,6 +777,32 @@ static int pm8xxx_mpp_child_to_parent_hwirq(struct gpio_chip *chip, return 0; } +static void pm8xxx_mpp_irq_disable(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + + gpiochip_disable_irq(gc, irqd_to_hwirq(d)); +} + +static void pm8xxx_mpp_irq_enable(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + + gpiochip_enable_irq(gc, irqd_to_hwirq(d)); +} + +static const struct irq_chip pm8xxx_mpp_irq_chip = { + .name = "ssbi-mpp", + .irq_mask_ack = irq_chip_mask_ack_parent, + .irq_unmask = irq_chip_unmask_parent, + .irq_disable = pm8xxx_mpp_irq_disable, + .irq_enable = pm8xxx_mpp_irq_enable, + .irq_set_type = irq_chip_set_type_parent, + .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + static const struct of_device_id pm8xxx_mpp_of_match[] = { { .compatible = "qcom,pm8018-mpp", .data = (void *) 6 }, { .compatible = "qcom,pm8038-mpp", .data = (void *) 6 }, @@ -871,14 +896,8 @@ static int pm8xxx_mpp_probe(struct platform_device *pdev) if (!parent_domain) return -ENXIO; - pctrl->irq.name = "ssbi-mpp"; - pctrl->irq.irq_mask_ack = irq_chip_mask_ack_parent; - pctrl->irq.irq_unmask = irq_chip_unmask_parent; - pctrl->irq.irq_set_type = irq_chip_set_type_parent; - pctrl->irq.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE; - girq = &pctrl->chip.irq; - girq->chip = &pctrl->irq; + gpio_irq_chip_set_chip(girq, &pm8xxx_mpp_irq_chip); girq->default_type = IRQ_TYPE_NONE; girq->handler = handle_level_irq; girq->fwnode = dev_fwnode(pctrl->dev); From patchwork Fri Apr 14 14:06:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 83438 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp421555vqo; Fri, 14 Apr 2023 07:23:54 -0700 (PDT) X-Google-Smtp-Source: AKy350auyCoZhFLlSSih+QEyrXgzSq/W8/nKDRDhAsKXpZTSUIPvKZIJmvlgL8Lh85miXYqUqjiX X-Received: by 2002:a05:6a00:2285:b0:639:435:1375 with SMTP id f5-20020a056a00228500b0063904351375mr9780605pfe.31.1681482234306; Fri, 14 Apr 2023 07:23:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681482234; cv=none; d=google.com; s=arc-20160816; b=t8heLIYCyQ9OdozMw7NKOScz4cLIc8WIipufmLQpsImsAlIZOyqk7VQ2qmorkVfePU vkKod0uzcVRhCbqfP6ErIoLB/y9RMRInvcX5HmYK3gbGkA9RXiqkp9CnoCElNYGrtNNE HUl3GO60KcWMSA02WOAWOl3Tugq5jbv2+HASGJHygwi1TVC64x7/+4WY55WfCk+f6wIf T/n5z8A0uzakZ+fOFVT8IkIiKjVT6C9k1GNPHZuH7ZGDaVfxNRmJtvLiD1/3dfyvhn5S k0OgwOkThbywiOQx1B8mb+LawV1vv8+5swOcCagvg1aJ/TZ57OI9dycJD9qyKPCSocPY zpVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=YTAL+X79fFSg7Vdy2Php9Hw3wS0uqtZxqCJF6Zi/jeI=; b=RMplHyxU3W2U8jQVH7+bJDPZE1LQIo9/vxtpmO91HTaTcrkpqh0uAfbkyGMjGokNEw KrqShe0aTazae06KS0KsJbwDB/IsLSXg7oE0J4fbfZ6wY4oqviz6WdDe1bf1JV1r4lxG i3LPKo6vH7QVCnzRXbrJLevTtdQSQbn9eujestg0HuZMknCnNV6jPfboirHAea5fb7Bm 6xcTYsNJD/sp9ZJRIyt2NuQQfaqduj5Qew2qij+luqhE2PZCOTGX6/kJJvHF16KWxgOp O/wnEsS1Z9rPkfiMoGA2935cB7kfplIgrzPfO76zGtIS3EigKfw3IO+YxBuFFZKYWmWO kyrQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YGQPsnba; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c index e973001e5c88..dec1ffc49ffd 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c @@ -652,12 +652,30 @@ static int pm8xxx_pin_populate(struct pm8xxx_gpio *pctrl, return 0; } -static struct irq_chip pm8xxx_irq_chip = { +static void pm8xxx_irq_disable(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + + gpiochip_disable_irq(gc, irqd_to_hwirq(d)); +} + +static void pm8xxx_irq_enable(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + + gpiochip_enable_irq(gc, irqd_to_hwirq(d)); +} + +static const struct irq_chip pm8xxx_irq_chip = { .name = "ssbi-gpio", .irq_mask_ack = irq_chip_mask_ack_parent, .irq_unmask = irq_chip_unmask_parent, + .irq_disable = pm8xxx_irq_disable, + .irq_enable = pm8xxx_irq_enable, .irq_set_type = irq_chip_set_type_parent, - .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE, + .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, }; static int pm8xxx_domain_translate(struct irq_domain *domain, @@ -788,7 +806,7 @@ static int pm8xxx_gpio_probe(struct platform_device *pdev) return -ENXIO; girq = &pctrl->chip.irq; - girq->chip = &pm8xxx_irq_chip; + gpio_irq_chip_set_chip(girq, &pm8xxx_irq_chip); girq->default_type = IRQ_TYPE_NONE; girq->handler = handle_level_irq; girq->fwnode = dev_fwnode(pctrl->dev);