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Fri, 21 Oct 2022 12:18:27 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 29LHIQFX129441; Fri, 21 Oct 2022 12:18:27 -0500 From: Rahul T R To: , , , CC: , , , , , , , , , , , , , , , , , Rahul T R , Rob Herring Subject: [PATCH v8 1/5] dt-bindings: display: bridge: Convert cdns,dsi.txt to yaml Date: Fri, 21 Oct 2022 22:48:16 +0530 Message-ID: <20221021171820.15984-2-r-ravikumar@ti.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221021171820.15984-1-r-ravikumar@ti.com> References: <20221021171820.15984-1-r-ravikumar@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747319017383046143?= X-GMAIL-MSGID: =?utf-8?q?1747319017383046143?= Convert cdns,dsi.txt binding to yaml format Signed-off-by: Rahul T R Reviewed-by: Rob Herring --- .../bindings/display/bridge/cdns,dsi.txt | 112 ------------- .../bindings/display/bridge/cdns,dsi.yaml | 157 ++++++++++++++++++ 2 files changed, 157 insertions(+), 112 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt deleted file mode 100644 index 525a4bfd8634..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt +++ /dev/null @@ -1,112 +0,0 @@ -Cadence DSI bridge -================== - -The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes. - -Required properties: -- compatible: should be set to "cdns,dsi". -- reg: physical base address and length of the controller's registers. -- interrupts: interrupt line connected to the DSI bridge. -- clocks: DSI bridge clocks. -- clock-names: must contain "dsi_p_clk" and "dsi_sys_clk". -- phys: phandle link to the MIPI D-PHY controller. -- phy-names: must contain "dphy". -- #address-cells: must be set to 1. -- #size-cells: must be set to 0. - -Optional properties: -- resets: DSI reset lines. -- reset-names: can contain "dsi_p_rst". - -Required subnodes: -- ports: Ports as described in Documentation/devicetree/bindings/graph.txt. - 2 ports are available: - * port 0: this port is only needed if some of your DSI devices are - controlled through an external bus like I2C or SPI. Can have at - most 4 endpoints. The endpoint number is directly encoding the - DSI virtual channel used by this device. - * port 1: represents the DPI input. - Other ports will be added later to support the new kind of inputs. - -- one subnode per DSI device connected on the DSI bus. Each DSI device should - contain a reg property encoding its virtual channel. - -Example: - dsi0: dsi@fd0c0000 { - compatible = "cdns,dsi"; - reg = <0x0 0xfd0c0000 0x0 0x1000>; - clocks = <&pclk>, <&sysclk>; - clock-names = "dsi_p_clk", "dsi_sys_clk"; - interrupts = <1>; - phys = <&dphy0>; - phy-names = "dphy"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - dsi0_dpi_input: endpoint { - remote-endpoint = <&xxx_dpi_output>; - }; - }; - }; - - panel: dsi-dev@0 { - compatible = ""; - reg = <0>; - }; - }; - -or - - dsi0: dsi@fd0c0000 { - compatible = "cdns,dsi"; - reg = <0x0 0xfd0c0000 0x0 0x1000>; - clocks = <&pclk>, <&sysclk>; - clock-names = "dsi_p_clk", "dsi_sys_clk"; - interrupts = <1>; - phys = <&dphy1>; - phy-names = "dphy"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - dsi0_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&dsi_panel_input>; - }; - }; - - port@1 { - reg = <1>; - dsi0_dpi_input: endpoint { - remote-endpoint = <&xxx_dpi_output>; - }; - }; - }; - }; - - i2c@xxx { - panel: panel@59 { - compatible = ""; - reg = <0x59>; - - port { - dsi_panel_input: endpoint { - remote-endpoint = <&dsi0_output>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml new file mode 100644 index 000000000000..3161c33093c1 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml @@ -0,0 +1,157 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/cdns,dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence DSI bridge + +maintainers: + - Boris Brezillon + +description: | + CDNS DSI is a bridge device which converts DPI to DSI + +properties: + compatible: + enum: + - cdns,dsi + + reg: + maxItems: 1 + + clocks: + items: + - description: PSM clock, used by the IP + - description: sys clock, used by the IP + + clock-names: + items: + - const: dsi_p_clk + - const: dsi_sys_clk + + phys: + maxItems: 1 + + phy-names: + const: dphy + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + const: dsi_p_rst + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: + Output port representing the DSI output. It can have + at most 4 endpoints. The endpoint number is directly encoding + the DSI virtual channel used by this device. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + Input port representing the DPI input. + + required: + - port@1 + +allOf: + - $ref: ../dsi-controller.yaml# + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - phys + - phy-names + - ports + +unevaluatedProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + dsi@fd0c0000 { + compatible = "cdns,dsi"; + reg = <0x0 0xfd0c0000 0x0 0x1000>; + clocks = <&pclk>, <&sysclk>; + clock-names = "dsi_p_clk", "dsi_sys_clk"; + interrupts = <1>; + phys = <&dphy0>; + phy-names = "dphy"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&xxx_dpi_output>; + }; + }; + }; + + panel@0 { + compatible = "panasonic,vvx10f034n00"; + reg = <0>; + power-supply = <&vcc_lcd_reg>; + }; + }; + }; + + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + dsi@fd0c0000 { + compatible = "cdns,dsi"; + reg = <0x0 0xfd0c0000 0x0 0x1000>; + clocks = <&pclk>, <&sysclk>; + clock-names = "dsi_p_clk", "dsi_sys_clk"; + interrupts = <1>; + phys = <&dphy1>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi_panel_input>; + }; + }; + + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&xxx_dpi_output>; + }; + }; + }; + }; + }; From patchwork Fri Oct 21 17:18:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul T R X-Patchwork-Id: 6892 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4242:0:0:0:0:0 with SMTP id s2csp817608wrr; Fri, 21 Oct 2022 10:26:29 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7NbYP59p6Z47u3Rqd9h4uU+gjIIxpBpjkcrV6tBTZzakkZlvnnH5OC+wjAI5/ZufEm5eyT X-Received: by 2002:a17:906:5a6a:b0:78d:d25e:55de with SMTP id my42-20020a1709065a6a00b0078dd25e55demr16153961ejc.130.1666373189396; Fri, 21 Oct 2022 10:26:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666373189; cv=none; d=google.com; s=arc-20160816; b=AKCBv3trWNeRBxR6GrSazSkUgsBaIPq1MAblsPQLxve3XgiZAobdhuemSZQ04rEr/v oof1JJabqUt0tHtmoxyq6/3m8ewihH6zwVUhhmM5mbz5AAHuVOHmj/Mw+mpTVPtoVlQm 23dUkDm5HCxMWKH9xCpobcuBag1S1WHtZxSQOlajffAfHdhh3CzZqQdOMEDOUcH4yssq jPM7UsGNjsLiInfk8W6LArClcnAqAUyd7bZXzj4hfNbe3bb1MLP6P6f7aodLkcX/ZGXE +dJaq+SLn0VPBXGZskUQTR+h+IiS1e3F7qnjFD53sVY2IwWwFOIWOtYXNqeZLznnsF6l OAOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=WHTNduQTN6mCQRbvGwsq1IEXZt28FceTbWv2qs0q8yk=; b=cvSavNxRmc9MLhBovj3Ewiw7mPUV8CEGjooRPGY2l1zffBz7eXTYqF0X36SP1mtxpL PxbVpfQMeYA6GafvIa6C2hhnopoU72kc+4G8QvuVjYIazj+6DZhqBw1xB7TtWT1v2sc9 l5QShQb5zncZ+ojJNL/OKRIk4J/RQnJoL82IuXuCw+vmu63AJhe5n/OqCUkaHaeCeUxS kQtiDoeBwad3eX8ujnqXXBH/V1q6AyT//IPR/sedD1IvYvJ/RMsmgNwYIjQTeu6b4uCh m9hNNc0icCdLgMuUukdatfCrHr9gFHWKere/sKa8AlujKQjeb3EKQQ/vuWEornc5bwMZ LTpA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=HsDzePiF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. 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Fri, 21 Oct 2022 12:18:29 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 29LHISse129481; Fri, 21 Oct 2022 12:18:29 -0500 From: Rahul T R To: , , , CC: , , , , , , , , , , , , , , , , , Rahul T R , Rob Herring Subject: [PATCH v8 2/5] dt-bindings: display: bridge: cdns,dsi: Add compatible for dsi on j721e Date: Fri, 21 Oct 2022 22:48:17 +0530 Message-ID: <20221021171820.15984-3-r-ravikumar@ti.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221021171820.15984-1-r-ravikumar@ti.com> References: <20221021171820.15984-1-r-ravikumar@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747318933235151991?= X-GMAIL-MSGID: =?utf-8?q?1747318933235151991?= Add compatible to support dsi bridge on j721e Signed-off-by: Rahul T R Reviewed-by: Rob Herring --- .../bindings/display/bridge/cdns,dsi.yaml | 25 ++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml index 3161c33093c1..23060324d16e 100644 --- a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml +++ b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml @@ -16,9 +16,15 @@ properties: compatible: enum: - cdns,dsi + - ti,j721e-dsi reg: - maxItems: 1 + minItems: 1 + items: + - description: + Register block for controller's registers. + - description: + Register block for wrapper settings registers in case of TI J7 SoCs. clocks: items: @@ -67,6 +73,23 @@ properties: allOf: - $ref: ../dsi-controller.yaml# + - if: + properties: + compatible: + contains: + const: ti,j721e-dsi + then: + properties: + reg: + minItems: 2 + maxItems: 2 + power-domains: + maxItems: 1 + else: + properties: + reg: + maxItems: 1 + required: - compatible - reg From patchwork Fri Oct 21 17:18:18 2022 Content-Type: text/plain; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id q17-20020a170906361100b00787d08d5ff4si17529785ejb.695.2022.10.21.10.25.41; Fri, 21 Oct 2022 10:26:06 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="P/qq4FXg"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231225AbiJURTX (ORCPT + 99 others); Fri, 21 Oct 2022 13:19:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45842 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230522AbiJURTJ (ORCPT ); Fri, 21 Oct 2022 13:19:09 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3461A1AA25C; Fri, 21 Oct 2022 10:19:08 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 29LHIV8I045956; Fri, 21 Oct 2022 12:18:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1666372711; bh=ELIaDah0pT+RkrdA97Yrk9dhkNR+CdP76fE70Idb4XA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=P/qq4FXgfzblYG1l6OC+BXQKUAkfcgBj1Tz4LxIc36I+AsR7/FS3QdB1esXEFUU3A DyDIQ4RmD9hjm+VrD7ZR1FNguVbsTnuY94sIqbLC6oM/xM5Smynqs29GsCu5EHyVYN GjGx/cM+y+HdnDN352kr9EGLJzq5b0MuusWsNdVo= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 29LHIVqG073192 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 21 Oct 2022 12:18:31 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Fri, 21 Oct 2022 12:18:31 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Fri, 21 Oct 2022 12:18:31 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 29LHIUeX129507; Fri, 21 Oct 2022 12:18:31 -0500 From: Rahul T R To: , , , CC: , , , , , , , , , , , , , , , , , Rahul T R Subject: [PATCH v8 3/5] drm/bridge: cdns-dsi: Move to drm/bridge/cadence Date: Fri, 21 Oct 2022 22:48:18 +0530 Message-ID: <20221021171820.15984-4-r-ravikumar@ti.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221021171820.15984-1-r-ravikumar@ti.com> References: <20221021171820.15984-1-r-ravikumar@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747318909567769878?= X-GMAIL-MSGID: =?utf-8?q?1747318909567769878?= Move the cadence dsi bridge under drm/bridge/cadence directory, to prepare for adding j721e wrapper support Signed-off-by: Rahul T R Reviewed-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/Kconfig | 11 ----------- drivers/gpu/drm/bridge/Makefile | 1 - drivers/gpu/drm/bridge/cadence/Kconfig | 11 +++++++++++ drivers/gpu/drm/bridge/cadence/Makefile | 2 ++ .../bridge/{cdns-dsi.c => cadence/cdns-dsi-core.c} | 0 5 files changed, 13 insertions(+), 12 deletions(-) rename drivers/gpu/drm/bridge/{cdns-dsi.c => cadence/cdns-dsi-core.c} (100%) diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 57946d80b02d..8b2226f72b24 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -15,17 +15,6 @@ config DRM_PANEL_BRIDGE menu "Display Interface Bridges" depends on DRM && DRM_BRIDGE -config DRM_CDNS_DSI - tristate "Cadence DPI/DSI bridge" - select DRM_KMS_HELPER - select DRM_MIPI_DSI - select DRM_PANEL_BRIDGE - select GENERIC_PHY_MIPI_DPHY - depends on OF - help - Support Cadence DPI to DSI bridge. This is an internal - bridge and is meant to be directly embedded in a SoC. - config DRM_CHIPONE_ICN6211 tristate "Chipone ICN6211 MIPI-DSI/RGB Converter bridge" depends on OF diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index 1884803c6860..52f6e8b4a821 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -1,5 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o obj-$(CONFIG_DRM_CHIPONE_ICN6211) += chipone-icn6211.o obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o obj-$(CONFIG_DRM_CROS_EC_ANX7688) += cros-ec-anx7688.o diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig b/drivers/gpu/drm/bridge/cadence/Kconfig index 1d06182bea71..8fbb46c66094 100644 --- a/drivers/gpu/drm/bridge/cadence/Kconfig +++ b/drivers/gpu/drm/bridge/cadence/Kconfig @@ -25,3 +25,14 @@ config DRM_CDNS_MHDP8546_J721E initializes the J721E Display Port and sets up the clock and data muxes. endif + +config DRM_CDNS_DSI + tristate "Cadence DPI/DSI bridge" + select DRM_KMS_HELPER + select DRM_MIPI_DSI + select DRM_PANEL_BRIDGE + select GENERIC_PHY_MIPI_DPHY + depends on OF + help + Support Cadence DPI to DSI bridge. This is an internal + bridge and is meant to be directly embedded in a SoC. diff --git a/drivers/gpu/drm/bridge/cadence/Makefile b/drivers/gpu/drm/bridge/cadence/Makefile index 4d2db8df1bc6..e3d8e9a40784 100644 --- a/drivers/gpu/drm/bridge/cadence/Makefile +++ b/drivers/gpu/drm/bridge/cadence/Makefile @@ -2,3 +2,5 @@ obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o cdns-mhdp8546-y := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o +obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o +cdns-dsi-y := cdns-dsi-core.o diff --git a/drivers/gpu/drm/bridge/cdns-dsi.c b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c similarity index 100% rename from drivers/gpu/drm/bridge/cdns-dsi.c rename to drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c From patchwork Fri Oct 21 17:18:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul T R X-Patchwork-Id: 6895 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4242:0:0:0:0:0 with SMTP id s2csp818283wrr; Fri, 21 Oct 2022 10:28:14 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4MUGDAxtf/1OstamfIGOE5Ipiyp++/hFwB8PJUpOwINZY6iLiLGkROsDMlW7O3FWHREYl1 X-Received: by 2002:a17:907:a054:b0:78d:7822:3108 with SMTP id gz20-20020a170907a05400b0078d78223108mr16184239ejc.764.1666373294684; Fri, 21 Oct 2022 10:28:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666373294; cv=none; d=google.com; s=arc-20160816; b=TZWQaPS+80q8pciQvOXU1AQCCZO6Rv11Xs7UZfIAi7UJzI9K8+A0/WIsH8eyc1HKzV JZP2Rh48OoW9Y/fJ/YARr+uawYBJtIuosnXuvVzMzydWQeg8mHXncMpgcwhERbXRYgRa 0sGNjIMFMkzwyeHcloCWTHw2AS4d6nurQHZ3RODuCkOaTMCMuDCJ83HkcwOE/8tRIFDk QhxF3Fm0hEujMAuL6HECItG5qBx5yDM9ErxlnTFhI5VTrRF9J4JjqNma8ZruYGVnR8XJ h2TtwK6eElxV+cEHjPg3yadmhHvJeMZ78XNrNsySoeV3reL8I/0IABfTvncW00tf3FIf 2CZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=9aCI1sgVGYjuVlnYmx7KARm9I9HiDrQgihhTQArhaeM=; b=d3H5mpj4JDYQ7qeRUj2O9sfjdGWDOv+mOYPsoxElsIZn9HTZcIZGGv6BY/AC4Sa9/x kfWzAA+yKjdBZL6Qs+GPouvi+LV+9pLGHfaRfTBPjdJGj+SKDq17enIiyscgZ70mBoib p8ZtOtXyu3GJTtW3MkLhuSfYt5OTzzuFKp7g3iEnJqVdagtsXUT9TzJEqfgynR/bXLfV FikpfSvTlcXBz8rjzZO/SNK5zwmVSkGoePOwzzmf1EZ13+ctY+q9jngz25OmLfUvzPKG YqGuqAvV3onvCL+2xbfQBnv2JKU/kIzjQ40Mc5ahhnQBwTIIHisM87mjguZNza5dm9jv jWDg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=cnnbL3mo; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id n21-20020aa7c795000000b004513abe8f74si17367640eds.249.2022.10.21.10.27.49; Fri, 21 Oct 2022 10:28:14 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=cnnbL3mo; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231250AbiJURT0 (ORCPT + 99 others); Fri, 21 Oct 2022 13:19:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45884 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231172AbiJURTL (ORCPT ); Fri, 21 Oct 2022 13:19:11 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3473B1ABA3C; Fri, 21 Oct 2022 10:19:08 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 29LHIXPp045962; Fri, 21 Oct 2022 12:18:33 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1666372714; bh=9aCI1sgVGYjuVlnYmx7KARm9I9HiDrQgihhTQArhaeM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=cnnbL3moz4XoSYSgWffbcmgDTsjOgdnFGzzByuVjcdgSmgqO4hfYATskuYHjMVo8Q 7dz5/jaf0bLvfipGF2t3lk7KUKp3vj2E2LG3a0/Jm26RIRvPzKzhKVVOTV0AKJauSo uWSw17f1mmj3Hg3q0i8mEF9r8qdxF9bmQDFxo6oo= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 29LHIXX0101276 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 21 Oct 2022 12:18:33 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Fri, 21 Oct 2022 12:18:33 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Fri, 21 Oct 2022 12:18:33 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 29LHIWEA037363; Fri, 21 Oct 2022 12:18:32 -0500 From: Rahul T R To: , , , CC: , , , , , , , , , , , , , , , , , Rahul T R Subject: [PATCH v8 4/5] drm/bridge: cdns-dsi: Create a header file Date: Fri, 21 Oct 2022 22:48:19 +0530 Message-ID: <20221021171820.15984-5-r-ravikumar@ti.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221021171820.15984-1-r-ravikumar@ti.com> References: <20221021171820.15984-1-r-ravikumar@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS,UPPERCASE_50_75,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747319044044938473?= X-GMAIL-MSGID: =?utf-8?q?1747319044044938473?= Create a header file for cdns dsi and move register offsets and structure to header, to prepare for adding j721e wrapper support Signed-off-by: Rahul T R Reviewed-by: Tomi Valkeinen --- .../gpu/drm/bridge/cadence/cdns-dsi-core.c | 446 +---------------- .../gpu/drm/bridge/cadence/cdns-dsi-core.h | 458 ++++++++++++++++++ 2 files changed, 459 insertions(+), 445 deletions(-) create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-core.h diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c index 20bece84ff8c..cba91247ab26 100644 --- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c +++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c @@ -6,10 +6,7 @@ */ #include -#include #include -#include -#include #include #include