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[2620:137:e000::1:20]) by mx.google.com with ESMTP id g5-20020a17090a640500b0024699492691si5293335pjj.48.2023.04.13.15.32.07; Thu, 13 Apr 2023 15:32:18 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=MpBVIWzm; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230122AbjDMWbV (ORCPT + 99 others); Thu, 13 Apr 2023 18:31:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47034 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229577AbjDMWbN (ORCPT ); Thu, 13 Apr 2023 18:31:13 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 59CB3868D; Thu, 13 Apr 2023 15:31:12 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 33DMUqhN071324; Thu, 13 Apr 2023 17:30:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1681425052; bh=5oQBE1OTbrIAIvuRzCjIYi4IgsqkNGNtrVbvqNRvhWM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=MpBVIWzmC1gsGQHm6fwygE+sXuwZsrmCgxIOw7M5fOq26pgoQBUTEJrrIR7mms2vR qR1dUHaLdVsudfZQPwWxTIbT8m613zz7U93fE+LxhoTwHigQSS/6QG3Q5qRxL1jlpE G8cMLV1QB/25gBPp1Zcr8zx8QSMWE3lLvVOWqd5Y= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 33DMUqHq074962 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 13 Apr 2023 17:30:52 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Thu, 13 Apr 2023 17:30:52 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Thu, 13 Apr 2023 17:30:51 -0500 Received: from a0498204.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 33DMUpa4063427; Thu, 13 Apr 2023 17:30:51 -0500 From: Judith Mendez To: Chandrasekar Ramakrishnan CC: Nishanth Menon , Vignesh Raghavendra , Andrew Davis , Wolfgang Grandegger , Marc Kleine-Budde , Rob Herring , Krzysztof Kozlowski , , , , , Schuyler Patton Subject: [RFC PATCH 1/5] arm64: dts: ti: Add AM62x MCAN MAIN domain transceiver overlay Date: Thu, 13 Apr 2023 17:30:47 -0500 Message-ID: <20230413223051.24455-2-jm@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230413223051.24455-1-jm@ti.com> References: <20230413223051.24455-1-jm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763102046461215430?= X-GMAIL-MSGID: =?utf-8?q?1763102046461215430?= Add an overlay for main domain MCAN on AM62x SK. The AM62x SK board does not have on-board CAN transceiver so instead of changing the dtb permanently, add an overlay to enable MAIN domain MCAN and support for 1 CAN transceiver. Signed-off-by: Judith Mendez --- arch/arm64/boot/dts/ti/Makefile | 2 ++ .../boot/dts/ti/k3-am625-sk-mcan-main.dtso | 35 +++++++++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-sk-mcan-main.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index c83c9d772b81..abe15e76b614 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -9,8 +9,10 @@ # alphabetically. # Boards with AM62x SoC +k3-am625-sk-mcan-dtbs := k3-am625-sk.dtb k3-am625-sk-mcan-main.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-sk-mcan.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb # Boards with AM62Ax SoC diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk-mcan-main.dtso b/arch/arm64/boot/dts/ti/k3-am625-sk-mcan-main.dtso new file mode 100644 index 000000000000..72b68fd51121 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-sk-mcan-main.dtso @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT overlay for MCAN transceiver in main domain on AM625 SK + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + transceiver1: can-phy0 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; +}; + +&main_pmx0 { + main_mcan0_pins_default: main-mcan0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1dc, PIN_INPUT, 0) /* (E15) MCAN0_RX */ + AM62X_IOPAD(0x1d8, PIN_OUTPUT, 0) /* (C15) MCAN0_TX */ + >; + }; +}; + +&main_mcan0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan0_pins_default>; + phys = <&transceiver1>; +}; From patchwork Thu Apr 13 22:30:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Judith Mendez X-Patchwork-Id: 83105 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1362445vqo; Thu, 13 Apr 2023 15:39:41 -0700 (PDT) X-Google-Smtp-Source: AKy350YyRtLU8fUtg2LW3gDAPu7trqtVMLkI2qzdxog/0lLII9ANeiWJw7H2LYYenKXKcp3BXqgS X-Received: by 2002:a05:6a00:1d19:b0:63b:6262:42bd with SMTP id a25-20020a056a001d1900b0063b626242bdmr1151579pfx.3.1681425581475; Thu, 13 Apr 2023 15:39:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681425581; cv=none; d=google.com; s=arc-20160816; b=KjzYXU1pZlmhg0m0tix62iBoWjArq0MKNgF6EFrfmAxD5AXLh4amqLrulirX0bcfnm JJTPRKqvYSm/eephsyqAutQVe4r1c8vIhkaeJk5aqZ1fO6mw+1OL1RLu94nV/k47Wvfd fs8BUcvLMGAI1Z3p+AmwLRMp7YMI8MX9f+VYx0Wj6KH6vLlPneDzkebFNb0z77CLvs1u DP+i7ZizPuNoFRggv55wGvCHM7kWVibQfYWse0ScDrw8PRh4hCN1RelZ9ok3g+y030xx 6jJwxaQak94884rc7VWeVfB6ufV2XVRNr4/1vAmniQRcnuPUtf38pFi3Xs8ACyUCRpki w9XQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=kCdEb/NvZkw25bQuwMNRo9ZrE7qZwdwyaq0NV1d1GTQ=; b=kCy01f14b8pxHIfDDWHcaG46LqbDjZkQ3gKVD3u8DJ+ndiRwkh2bEV8ztleZWIv7w7 bAgtM7A2q34JKMx9hkF1IP53Oa3wZOyUHhfVOepLSGmR1NpKOE3muVww55aY3RKw90kU 2YvoiDdToFOscTk0i8AhVI7aWlx99MD20GQ78EvReUuLAjC7Tc90ssSnMq8Horwbjz5V eW0FkyMucvMktvIdaNHcthHHlhoCVc0PVpAswBeifDD73ZD6GAqrXuSC54oya21hJ+Te 3idi6R6rbwASlv2Uz7XD10dp3ZGqOJ2/SUfdLN2LHHj5nu3Bv6MN8zE9gA0pj0y3SN4v mOgw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Y5pYGYIb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Judith Mendez --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 7790ee42c68a..172a2523051f 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -176,6 +176,8 @@ CONFIG_NET_ACT_GATE=m CONFIG_QRTR_SMD=m CONFIG_QRTR_TUN=m CONFIG_CAN=m +CONFIG_CAN_M_CAN=m +CONFIG_CAN_M_CAN_PLATFORM=m CONFIG_BT=m CONFIG_BT_HIDP=m # CONFIG_BT_LE is not set From patchwork Thu Apr 13 22:30:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Judith Mendez X-Patchwork-Id: 83101 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1359129vqo; Thu, 13 Apr 2023 15:31:47 -0700 (PDT) X-Google-Smtp-Source: AKy350ZDiL7HpPd7ZDtmrhKlG3shcLFXhC8e8OmHDNUGRP8W4zHFcO2l+iEFS/u6PB5ZmPfDnav1 X-Received: by 2002:a17:90a:1b6c:b0:240:95a9:923d with SMTP id q99-20020a17090a1b6c00b0024095a9923dmr3210389pjq.48.1681425107278; Thu, 13 Apr 2023 15:31:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681425107; cv=none; d=google.com; s=arc-20160816; b=JDj6fAoHEQnfbKo8+xs2FzQEm4Exlb8C8+dIKa5NQ5ZKb6lEdB5ys+4L0ZRLc9+Woq XqfvElkR8c3AQ3TxOhMKOx/J2XoAI6QHKokJ6y1K3xHoFzrTIVZ4IuwjYgZDROhhRQyk k+CW9Vc9xIPevnZ+J20eY7E7tKzLNnVTglunUiBpZmjh1bUO8Ds/Tmrqz+6VnoTrn1gw XgAN/sBzLs3A00oXx3xQ6N/C3mEi3PhM9hLacCaf7CpMMPmN3JWqNNG86sdAnSdOtMRZ KfmZ5uVEHO/oee9Fil6jxxU0NrmEa8fLAjt3bLJgGOIdoKCpnEf+ZXUsnLyreZ0jWttn f7fQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=1nmKT2A1OjUy31bEWZZBxae3cEYPA1EAPfeRQOHQjHk=; b=FiNsswCOIFH2StGbFJhp9CfVRq+1OTvNIzqn2xBIHhLtcW9RmolS91mtAkbM70LIxC BdNzRkxqj9nFrWP5Xx0T5LdY8k38OUEqjmRLqGhpWS74D+MQkxZ9BkFJqWZDAk2EYFgm 14jbo5ue6vbyXwICrJsJyIurJBJAZnMiBty7PRzlZsXL/0ZasIHcMWLBpnMljWwbIT6z 1C85ujbVTEWVxwdlQFkPHZcWSweNRBweRe3dOtOuuO4m3DNSGODiReRMd98GdxuOzSPG x6lEKlpra0cqXqO8Ph2OFjLBQnfKAMsK6mJqc2/F25Dg7KHpJ2CuhzIsT3mZJ3Nf5Nnw CGLQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=cVjxfJ5i; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Judith Mendez --- Documentation/devicetree/bindings/net/can/bosch,m_can.yaml | 2 -- 1 file changed, 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml index 67879aab623b..43f1aa9addc0 100644 --- a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml +++ b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml @@ -122,8 +122,6 @@ required: - compatible - reg - reg-names - - interrupts - - interrupt-names - clocks - clock-names - bosch,mram-cfg From patchwork Thu Apr 13 22:30:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Judith Mendez X-Patchwork-Id: 83104 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1361544vqo; Thu, 13 Apr 2023 15:37:22 -0700 (PDT) X-Google-Smtp-Source: AKy350ZLFG8dkDQtEFVms37DgYS9rMXCMfNN9NHcEWQ0yjet4Cpfs+HdqtwTBTJCm2c9+E9DiMeW X-Received: by 2002:a05:6a20:3423:b0:e7:56ad:5a40 with SMTP id i35-20020a056a20342300b000e756ad5a40mr3357227pzd.36.1681425442670; Thu, 13 Apr 2023 15:37:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681425442; cv=none; d=google.com; s=arc-20160816; b=H58X1itDTGIrqD467EHQjSDJN2zjzaqvjBOxn20rg+SZVYY2a1xGY9BwVscO8JF5Xk C1pilrWyrk9PZXwrIA2CLPEvufW9j5AI9EeWp7Q3sdGA7KGQFxh0EPbCSPz5PuRRv4iH W6g/OJRScsx+xwiqHFCIYwzL/oKIPPS8HlKGGjkpLeTC8x2AAaT5aJBO+QsMG98/qOwP Kp8bYHn6zoQJvTcxvEbEnfMcC/sHEdmYbOT6idRTWWszce1N01sugQBB3320KpM21w+m 7YBkobmHjAO/UjI2JV2N/612x4rA3jhukrDEOwgpJlR13kNX0PH+BZUtVeZQiU/hPJPo uazw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=OEDwhwZYUg5c6D6b0NeNY00UKEjgXiSxHW2Wae+XH3Q=; b=s07QAy8AvE/8x2EDCuxbeFqk0yfvRrrtn1LltXRqgrM5yqSW7Vw+uG7WuXnAfohx0X KS3x3N2P5yy8Ir+TMkGxmLtFd0Z+fdCYqvBL6KITBd/p5n5Dao2w/7Qg+ODXCl22sRUx 3hSFcBtGnphNHmOLKYsolhrIHUZv1/TONgCQ2+uOH0hRx8XwMejLbsZRERgQhZh4efE3 MFebqM66ERVIvKGfoYRser0DEU0ggtu61GoxttV2/5/YjVa4zmuRms/CdV6T/mz2DkHP fU9QG+BbVleacOSNqEqaQrcdSzDHdYNzrfYHQbRVmj5bEM74AUs6K4opTYqpx2AgxUok D2Jg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=BXGfjo50; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. 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AM62x does not have on-board CAN transcievers, so instead of changing the DTB permanently, add MCU MCAN nodes and transceiver nodes to a MCU MCAN overlay. If there are no hardware interrupts rounted to the GIC interrupt controller for MCAN IP, A53 Linux will not receive hardware interrupts. If an hrtimer is used to generate software interrupts, the two required interrupt attributes in the MCAN node do not have to be included. Signed-off-by: Judith Mendez --- arch/arm64/boot/dts/ti/Makefile | 2 +- .../boot/dts/ti/k3-am625-sk-mcan-mcu.dtso | 75 +++++++++++++++++++ 2 files changed, 76 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-sk-mcan-mcu.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index abe15e76b614..c76be3888e4d 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -9,7 +9,7 @@ # alphabetically. # Boards with AM62x SoC -k3-am625-sk-mcan-dtbs := k3-am625-sk.dtb k3-am625-sk-mcan-main.dtbo +k3-am625-sk-mcan-dtbs := k3-am625-sk.dtb k3-am625-sk-mcan-main.dtbo k3-am625-sk-mcan-mcu.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk-mcan.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk-mcan-mcu.dtso b/arch/arm64/boot/dts/ti/k3-am625-sk-mcan-mcu.dtso new file mode 100644 index 000000000000..777705aea546 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-sk-mcan-mcu.dtso @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT overlay for MCAN in MCU domain on AM625 SK + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + + +&{/} { + transceiver2: can-phy1 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver3: can-phy2 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; +}; + +&mcu_pmx0 { + mcu_mcan1_pins_default: mcu-mcan1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x038, PIN_INPUT, 0) /* (B3) MCU_MCAN0_RX */ + AM62X_IOPAD(0x034, PIN_OUTPUT, 0) /* (D6) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan2_pins_default: mcu-mcan2-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x040, PIN_INPUT, 0) /* (D4) MCU_MCAN1_RX */ + AM62X_IOPAD(0x03C, PIN_OUTPUT, 0) /* (E5) MCU_MCAN1_TX */ + >; + }; +}; + +&cbass_mcu { + mcu_mcan1: can@4e00000 { + compatible = "bosch,m_can"; + reg = <0x00 0x4e00000 0x00 0x8000>, + <0x00 0x4e08000 0x00 0x200>; + reg-names = "message_ram", "m_can"; + power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 188 6>, <&k3_clks 188 1>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_pins_default>; + phys = <&transceiver2>; + status = "okay"; + }; + + mcu_mcan2: can@4e10000 { + compatible = "bosch,m_can"; + reg = <0x00 0x4e10000 0x00 0x8000>, + <0x00 0x4e18000 0x00 0x200>; + reg-names = "message_ram", "m_can"; + power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 189 6>, <&k3_clks 189 1>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan2_pins_default>; + phys = <&transceiver3>; + status = "okay"; + }; +}; From patchwork Thu Apr 13 22:30:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Judith Mendez X-Patchwork-Id: 83103 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1360931vqo; Thu, 13 Apr 2023 15:35:51 -0700 (PDT) X-Google-Smtp-Source: AKy350YZOv3JVkMOtXtZAU0PcZ+4TIy+jt+9VU2D5WM7EK8J6mfU6ULwe/jgz5UiOeGz6T5qufe4 X-Received: by 2002:a05:6a20:6907:b0:ec:d7cf:bcee with SMTP id q7-20020a056a20690700b000ecd7cfbceemr1411404pzj.22.1681425351514; Thu, 13 Apr 2023 15:35:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681425351; cv=none; d=google.com; s=arc-20160816; b=k2LgoARz27J3a3/bSVTV1/EaTVe/bZG/zgsG6kLMcLZfokmu9w3z+c3uG9PrLxX7kf itQ/qEJqHoqHQaQ8jLILrp+YToN5kThp6pRUbC04ySk6b8BHD/b+Og4Hb4lnQYU9MuTh 1QImJhJvpiJyqAdJ1FFpFF/E87ZPnP/s2bPvsNfUNmfJXhqmmlL2toEQPlNlmgAfXMxp 0SikR4Ib+STb+lJyn/BIWtdf24Sx7m92O/8XHTwnQwA8rJh2tx4vhjuRU1ZKEbfshS0M ZISJMd6r61j1JC1PiILLNF3MEGMLWVbLsxQYXg1Y+jUr84xrpUq6xRzBhc9XVYDuRUO4 u4rA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=QKx0x//24n9yfpt3AvoZRngZsGzu0JmQ1ZYdl2ypn6w=; b=vgyqVZKdpw2rnBbcvwumu2u4IiqmmWF1wBOzcDcnvTGXL7XEmHWtVj4p3LNOVcGcZB +Sy+yIzQ8XhnTyhRAPhDstFhHcpeYaLy6TBVbaBBXms7qsie6Z80XazoIpLlPqRYq7h6 ftkq85kK8OaB025lnV8EWIEn0fOiXKi6ICOrs/MIiOj4zsW1vbfW+KyrGC8nx2g+RTkg +FOR9O7b+NYZm48x9LMXFzjqzmYGrMFPCeX5SmqzyNfWyLoVr9v6FAHU6ZEkaBaml/FA cuV+1q3qbIfpT4DaGJTxwY2vl83SMYaGW2+eQprcEoRJiNq3jelnMDdJ3sxth15FdAYz dWAQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=q9BV75dh; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. 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Each MCAN will have its own hrtimer instantiated if there is no hardware interrupt found. The hrtimer will generate a software interrupt every 1 ms. In hrtimer callback, we check if there is a transaction pending by reading a register, then process by calling the isr if there is. Signed-off-by: Judith Mendez --- drivers/net/can/m_can/m_can.c | 24 ++++++++++++++++++++++-- drivers/net/can/m_can/m_can.h | 3 +++ drivers/net/can/m_can/m_can_platform.c | 9 +++++++-- 3 files changed, 32 insertions(+), 4 deletions(-) diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c index 8e83d6963d85..bb9d53f4d3cc 100644 --- a/drivers/net/can/m_can/m_can.c +++ b/drivers/net/can/m_can/m_can.c @@ -23,6 +23,7 @@ #include #include #include +#include #include "m_can.h" @@ -1584,6 +1585,11 @@ static int m_can_close(struct net_device *dev) if (!cdev->is_peripheral) napi_disable(&cdev->napi); + if (dev->irq < 0) { + dev_info(cdev->dev, "Disabling the hrtimer\n"); + hrtimer_cancel(&cdev->hrtimer); + } + m_can_stop(dev); m_can_clk_stop(cdev); free_irq(dev->irq, dev); @@ -1792,6 +1798,19 @@ static netdev_tx_t m_can_start_xmit(struct sk_buff *skb, return NETDEV_TX_OK; } +enum hrtimer_restart hrtimer_callback(struct hrtimer *timer) +{ + irqreturn_t ret; + struct m_can_classdev *cdev = + container_of(timer, struct m_can_classdev, hrtimer); + + ret = m_can_isr(0, cdev->net); + + hrtimer_forward_now(timer, ns_to_ktime(5 * NSEC_PER_MSEC)); + + return HRTIMER_RESTART; +} + static int m_can_open(struct net_device *dev) { struct m_can_classdev *cdev = netdev_priv(dev); @@ -1836,8 +1855,9 @@ static int m_can_open(struct net_device *dev) } if (err < 0) { - netdev_err(dev, "failed to request interrupt\n"); - goto exit_irq_fail; + dev_info(cdev->dev, "Enabling the hrtimer\n"); + cdev->hrtimer.function = &hrtimer_callback; + hrtimer_start(&cdev->hrtimer, ns_to_ktime(0), HRTIMER_MODE_REL_PINNED); } /* start the m_can controller */ diff --git a/drivers/net/can/m_can/m_can.h b/drivers/net/can/m_can/m_can.h index a839dc71dc9b..ed046d77fdb9 100644 --- a/drivers/net/can/m_can/m_can.h +++ b/drivers/net/can/m_can/m_can.h @@ -28,6 +28,7 @@ #include #include #include +#include /* m_can lec values */ enum m_can_lec_type { @@ -93,6 +94,8 @@ struct m_can_classdev { int is_peripheral; struct mram_cfg mcfg[MRAM_CFG_NUM]; + + struct hrtimer hrtimer; }; struct m_can_classdev *m_can_class_allocate_dev(struct device *dev, int sizeof_priv); diff --git a/drivers/net/can/m_can/m_can_platform.c b/drivers/net/can/m_can/m_can_platform.c index 9c1dcf838006..53e1648e9dab 100644 --- a/drivers/net/can/m_can/m_can_platform.c +++ b/drivers/net/can/m_can/m_can_platform.c @@ -7,6 +7,7 @@ #include #include +#include #include "m_can.h" @@ -98,8 +99,12 @@ static int m_can_plat_probe(struct platform_device *pdev) addr = devm_platform_ioremap_resource_byname(pdev, "m_can"); irq = platform_get_irq_byname(pdev, "int0"); if (IS_ERR(addr) || irq < 0) { - ret = -EINVAL; - goto probe_fail; + if (irq == -EPROBE_DEFER) { + ret = -EPROBE_DEFER; + goto probe_fail; + } + dev_info(mcan_class->dev, "Failed to get irq, initialize hrtimer\n"); + hrtimer_init(&mcan_class->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL_PINNED); } /* message ram could be shared */