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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id u10-20020a1709063b8a00b0094d8b6646c2si1788259ejf.48.2023.04.12.03.03.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 03:03:13 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=V6hzcO9n; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D84B93858C00 for ; Wed, 12 Apr 2023 10:03:11 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D84B93858C00 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1681293791; bh=VEgHj/2/Xy8IBIBVcEtNsOmDwrbhEGBgyT/AWyCeoaM=; h=Date:To:Subject:References:In-Reply-To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=V6hzcO9ngvz1zvrnShCPxV4ZLvaCq3H9Q+iHLA8HmQ3ryGKgRkyhmJXSYSaKTDNus KJmqT3CHEfR28Bq6YF4iimN31UK40J5SM/hR4uSakIgLc35C7rfWoss0TTxZAugHzF 34TkMkm/Pw4vBbMsryxUcRiWxLdr6ffjiUsqIZks= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by sourceware.org (Postfix) with ESMTPS id 0410C3858D32 for ; Wed, 12 Apr 2023 10:02:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0410C3858D32 Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-232-GgWcQt8DO9-7HV2nySnlcQ-1; Wed, 12 Apr 2023 06:02:19 -0400 X-MC-Unique: GgWcQt8DO9-7HV2nySnlcQ-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.rdu2.redhat.com [10.11.54.4]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 214B585A5A3; Wed, 12 Apr 2023 10:02:19 +0000 (UTC) Received: from tucnak.zalov.cz (unknown [10.39.192.16]) by smtp.corp.redhat.com (Postfix) with ESMTPS id CD7602027044; Wed, 12 Apr 2023 10:02:17 +0000 (UTC) Received: from tucnak.zalov.cz (localhost [127.0.0.1]) by tucnak.zalov.cz (8.17.1/8.17.1) with ESMTPS id 33CA2End1641552 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Wed, 12 Apr 2023 12:02:15 +0200 Received: (from jakub@localhost) by tucnak.zalov.cz (8.17.1/8.17.1/Submit) id 33CA2Cil1641551; Wed, 12 Apr 2023 12:02:12 +0200 Date: Wed, 12 Apr 2023 12:02:12 +0200 To: Segher Boessenkool , Jeff Law , Eric Botcazou , gcc-patches@gcc.gnu.org, Richard Biener , Richard Sandiford Subject: [PATCH] combine, v3: Fix AND handling for WORD_REGISTER_OPERATIONS targets [PR109040] Message-ID: References: <2220543.iZASKD2KPV@fomalhaut> <3412470.QJadu78ljV@fomalhaut> <8d3c3861-c291-e762-a2a8-0b520f39a7e3@gmail.com> <965831db-ac9e-cc5e-3459-08b6b70fd577@gmail.com> MIME-Version: 1.0 In-Reply-To: X-Scanned-By: MIMEDefang 3.1 on 10.11.54.4 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Disposition: inline X-Spam-Status: No, score=-3.3 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jakub Jelinek via Gcc-patches From: Jakub Jelinek Reply-To: Jakub Jelinek Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762964320169846779?= X-GMAIL-MSGID: =?utf-8?q?1762964320169846779?= Hi! On Wed, Apr 12, 2023 at 08:21:26AM +0200, Jakub Jelinek via Gcc-patches wrote: > I would have expected something like > WORD_REGISTER_OPERATIONS && known_le (GET_MODE_PRECISION (mode), BITS_PER_WORD) > as the condition to use word_mode, rather than just > WORD_REGISTER_OPERATIONS. In both spots. Because larger modes should be > used as is, not a narrower word_mode instead of them. In patch form that would be following (given that the combine.cc change had scalar_int_mode mode we can as well just use normal comparison, and simplify-rtx.cc has it guarded on HWI_COMPUTABLE_MODE_P, which is also only true for scalar int modes). I've tried the pr108947.c testcase, but I see no differences in the assembly before/after the patch (but dunno if I'm using the right options). The pr109040.c testcase from the patch I don't see the expected zero extension without the patch and do see it with it. As before, I can only test this easily on non-WORD_REGISTER_OPERATIONS targets. 2023-04-12 Jeff Law Jakub Jelinek PR target/109040 * combine.cc (simplify_and_const_int_1): Compute nonzero_bits in word_mode rather than mode if WORD_REGISTER_OPERATIONS and mode is smaller than word_mode. * simplify-rtx.cc (simplify_context::simplify_binary_operation_1) : Likewise. * gcc.c-torture/execute/pr109040.c: New test. Jakub --- gcc/combine.cc.jj 2023-04-07 16:02:06.668051629 +0200 +++ gcc/combine.cc 2023-04-12 11:24:18.458240028 +0200 @@ -10055,9 +10055,12 @@ simplify_and_const_int_1 (scalar_int_mod /* See what bits may be nonzero in VAROP. Unlike the general case of a call to nonzero_bits, here we don't care about bits outside - MODE. */ + MODE unless WORD_REGISTER_OPERATIONS is true. */ - nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode); + scalar_int_mode tmode = mode; + if (WORD_REGISTER_OPERATIONS && GET_MODE_BITSIZE (mode) < BITS_PER_WORD) + tmode = word_mode; + nonzero = nonzero_bits (varop, tmode) & GET_MODE_MASK (tmode); /* Turn off all bits in the constant that are known to already be zero. Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS @@ -10071,7 +10074,7 @@ simplify_and_const_int_1 (scalar_int_mod /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is a power of two, we can replace this with an ASHIFT. */ - if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1 + if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), tmode) == 1 && (i = exact_log2 (constop)) >= 0) return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i); --- gcc/simplify-rtx.cc.jj 2023-03-02 19:09:45.459594212 +0100 +++ gcc/simplify-rtx.cc 2023-04-12 11:26:26.027400305 +0200 @@ -3752,7 +3752,13 @@ simplify_context::simplify_binary_operat return op0; if (HWI_COMPUTABLE_MODE_P (mode)) { - HOST_WIDE_INT nzop0 = nonzero_bits (trueop0, mode); + /* When WORD_REGISTER_OPERATIONS is true, we need to know the + nonzero bits in WORD_MODE rather than MODE. */ + scalar_int_mode tmode = as_a (mode); + if (WORD_REGISTER_OPERATIONS + && GET_MODE_BITSIZE (tmode) < BITS_PER_WORD) + tmode = word_mode; + HOST_WIDE_INT nzop0 = nonzero_bits (trueop0, tmode); HOST_WIDE_INT nzop1; if (CONST_INT_P (trueop1)) { --- gcc/testsuite/gcc.c-torture/execute/pr109040.c.jj 2023-04-12 11:11:56.728938344 +0200 +++ gcc/testsuite/gcc.c-torture/execute/pr109040.c 2023-04-12 11:11:56.728938344 +0200 @@ -0,0 +1,23 @@ +/* PR target/109040 */ + +typedef unsigned short __attribute__((__vector_size__ (32))) V; + +unsigned short a, b, c, d; + +void +foo (V m, unsigned short *ret) +{ + V v = 6 > ((V) { 2124, 8 } & m); + unsigned short uc = v[0] + a + b + c + d; + *ret = uc; +} + +int +main () +{ + unsigned short x; + foo ((V) { 0, 15 }, &x); + if (x != (unsigned short) ~0) + __builtin_abort (); + return 0; +}