From patchwork Tue Apr 11 12:59:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 81950 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2573718vqo; Tue, 11 Apr 2023 06:26:33 -0700 (PDT) X-Google-Smtp-Source: AKy350Zj98zYDSD3KZ74lmx4qOgkjqZcvLZq9tT4BXiTxqb2hJkwFWDdoVwwHzvtnMlkUnhLqonC X-Received: by 2002:aa7:dccd:0:b0:4fb:59bb:ce6f with SMTP id w13-20020aa7dccd000000b004fb59bbce6fmr2540588edu.35.1681219593174; Tue, 11 Apr 2023 06:26:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681219593; cv=none; d=google.com; s=arc-20160816; b=OvHXWz9bnaLIfhB0kDEi3vEIVwCh6VVbemu/u/POH6JcaxDtO7SmCJC8u3PNGx6hq3 h/36l+/y+lVARgoWAUOTp7y2CwGKk19WQ4620nwdrwsfzIyJKkRsRhb/NW/MWf8mmhvw uxw47i46deYP52OPIAarJS6UH/9z36oa1lgZpBjTL+ln8Kj+Xg41gfKVnh17V7cl3Ka7 wkCd7vJ78kHo7t885KI1D8YB5OjGV81nfCGo4GmhcHnv4aT3SHSb+SBD0Td55zd847r5 XiYTEZGOnUh00D1ZU+Ox/azb7q/WO3wrpJFRlVa+tZdnzai7dD1GkMELoECYC4b9KzK/ 49ZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=oA3SCmMmUD/IAk9Z1v5rltTbTYq+SKdjhm6lfHHp658=; b=mtR27RxJgLVidXMcEiqYkBjed7rGSl6JcAaWgb2M2aNh8jhqQv3vk2MZ+D3pIelhH2 xPXBEcR4E0kc3Rz7EioN0suRpPBB51ueKGciLUAeDKrlJsID6Dm51wk+ecQUNyr+jWCA 0H4v2gt2+WQOUWaDy/L47wNRMuDgHsSVm9cYMwF4NON4iLJ8aPMnwFWsZOaCbi5mfe2z lNGRE5miPiQDOmQezH9jvq3PYdF/EJlRFeZ8zBNRyKqepPPDcOZKWYHRbRyOoVrL1DKZ X+UG6reoPbHkhem5h+IKwbxWewpCWOcGlPxOYJGjlbnN+RBZzxdsSC3PMsNspwdStTbh 0HcQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@bgdev-pl.20210112.gappssmtp.com header.s=20210112 header.b=JQNE1Ifc; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id he33-20020a1709073da100b009287477c339si3499054ejc.538.2023.04.11.06.26.08; Tue, 11 Apr 2023 06:26:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@bgdev-pl.20210112.gappssmtp.com header.s=20210112 header.b=JQNE1Ifc; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230167AbjDKM7f (ORCPT + 99 others); Tue, 11 Apr 2023 08:59:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54296 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230077AbjDKM73 (ORCPT ); Tue, 11 Apr 2023 08:59:29 -0400 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 666674EEE for ; Tue, 11 Apr 2023 05:59:17 -0700 (PDT) Received: by mail-wm1-x32f.google.com with SMTP id he13so9485858wmb.2 for ; Tue, 11 Apr 2023 05:59:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20210112.gappssmtp.com; s=20210112; t=1681217956; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oA3SCmMmUD/IAk9Z1v5rltTbTYq+SKdjhm6lfHHp658=; b=JQNE1IfchbIn2GVpDDiaQ/zSPZ4+3Hd8CBeaUohmmz370EsZdeXyd3ZiFZ2RokeCHL GYlLLNw9h7PDbGYhKHqKk9UZURSHFaBYBuuKRO+vlFn+fJ9D0MxAWkpBcePyzlROQxSk UrVHGX3TqwoBBDKvBU4oWlpvdUTapDOx1w13AadmfrMjU0JSu2xWru80cnTKUzTSCuU2 F1URxs3NbTxBIC1lpP9SLwEbAF9RDK4mlTDRyQetTqX1XYXFexQwV+vS0DKma5onroEP Ox1+Ouc5QgxWp8EQIwwcuWBRvDMojNocEQFC346/v3Czk2vepE37cGpv2FValB5YJhzi Izag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681217956; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oA3SCmMmUD/IAk9Z1v5rltTbTYq+SKdjhm6lfHHp658=; b=hJWC4jT25CHNKv2vsakFGS44Kv//eFeOTqI9by8BTDxB8axs0biGbCGVy/3QuAjAWb o1S+GoSSMWeC0tg8l3NCPJZi3ENrPVAGNcCC40ILyv1l16SNOkBcpFB+PilSvYngj2JJ p1MpVv9ybc5CHLZq4j9ZG2zu+WC3reI7U1uTGRagrQpgzc830ebdVxYxiX3ck730smWS 7TO/P6ssLVpv2HavtpeeeSwLeWrofjZLyh7Aok1T2VgEXiUlemaa7v2NTOasRewrGJsb xtbUbFqeThBHJJ4bba5qbezzZmiyJ/afXxH6wkQuHclrVuCVmky/kk8/Fkmohj1RxhDs Z9HA== X-Gm-Message-State: AAQBX9dNyEs5/xYYalghtdfWmiAyjmc/ch6ICwU/Ke9iBqtnahBwClPd jTO7wj+FrVUiI/RUZ0lpuqZRmg== X-Received: by 2002:a7b:c842:0:b0:3ed:88f5:160a with SMTP id c2-20020a7bc842000000b003ed88f5160amr2005327wml.11.1681217955867; Tue, 11 Apr 2023 05:59:15 -0700 (PDT) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:a099:fc1d:c99a:bfc3]) by smtp.gmail.com with ESMTPSA id e24-20020a05600c219800b003eae73f0fc1sm16944591wme.18.2023.04.11.05.59.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Apr 2023 05:59:15 -0700 (PDT) From: Bartosz Golaszewski To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Will Deacon , Robin Murphy , Joerg Roedel , Catalin Marinas , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Bartosz Golaszewski , Krzysztof Kozlowski Subject: [PATCH v3 1/7] dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P Date: Tue, 11 Apr 2023 14:59:04 +0200 Message-Id: <20230411125910.401075-2-brgl@bgdev.pl> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230411125910.401075-1-brgl@bgdev.pl> References: <20230411125910.401075-1-brgl@bgdev.pl> MIME-Version: 1.0 X-Spam-Status: No, score=0.0 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762886515727518097?= X-GMAIL-MSGID: =?utf-8?q?1762886515727518097?= From: Bartosz Golaszewski Add the compatible for the Qualcomm Graphics Clock control module present on sa8775p platforms. It matches the generic QCom GPUCC description. Add device-specific DT bindings defines as well. Signed-off-by: Bartosz Golaszewski Reviewed-by: Krzysztof Kozlowski Acked-by: Stephen Boyd --- .../devicetree/bindings/clock/qcom,gpucc.yaml | 2 + .../dt-bindings/clock/qcom,sa8775p-gpucc.h | 50 +++++++++++++++++++ 2 files changed, 52 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,sa8775p-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml index db53eb288995..1e3dc9deded9 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml @@ -15,6 +15,7 @@ description: | See also:: include/dt-bindings/clock/qcom,gpucc-sdm845.h + include/dt-bindings/clock/qcom,gpucc-sa8775p.h include/dt-bindings/clock/qcom,gpucc-sc7180.h include/dt-bindings/clock/qcom,gpucc-sc7280.h include/dt-bindings/clock/qcom,gpucc-sc8280xp.h @@ -27,6 +28,7 @@ properties: compatible: enum: - qcom,sdm845-gpucc + - qcom,sa8775p-gpucc - qcom,sc7180-gpucc - qcom,sc7280-gpucc - qcom,sc8180x-gpucc diff --git a/include/dt-bindings/clock/qcom,sa8775p-gpucc.h b/include/dt-bindings/clock/qcom,sa8775p-gpucc.h new file mode 100644 index 000000000000..a5fd784b1ea2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sa8775p-gpucc.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPUCC_SA8775P_H +#define _DT_BINDINGS_CLK_QCOM_GPUCC_SA8775P_H + +/* GPU_CC clocks */ +#define GPU_CC_PLL0 0 +#define GPU_CC_PLL1 1 +#define GPU_CC_AHB_CLK 2 +#define GPU_CC_CB_CLK 3 +#define GPU_CC_CRC_AHB_CLK 4 +#define GPU_CC_CX_FF_CLK 5 +#define GPU_CC_CX_GMU_CLK 6 +#define GPU_CC_CX_SNOC_DVM_CLK 7 +#define GPU_CC_CXO_AON_CLK 8 +#define GPU_CC_CXO_CLK 9 +#define GPU_CC_DEMET_CLK 10 +#define GPU_CC_DEMET_DIV_CLK_SRC 11 +#define GPU_CC_FF_CLK_SRC 12 +#define GPU_CC_GMU_CLK_SRC 13 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 14 +#define GPU_CC_HUB_AHB_DIV_CLK_SRC 15 +#define GPU_CC_HUB_AON_CLK 16 +#define GPU_CC_HUB_CLK_SRC 17 +#define GPU_CC_HUB_CX_INT_CLK 18 +#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 19 +#define GPU_CC_MEMNOC_GFX_CLK 20 +#define GPU_CC_SLEEP_CLK 21 +#define GPU_CC_XO_CLK_SRC 22 + +/* GPU_CC resets */ +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CB_BCR 1 +#define GPUCC_GPU_CC_CX_BCR 2 +#define GPUCC_GPU_CC_FAST_HUB_BCR 3 +#define GPUCC_GPU_CC_FF_BCR 4 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 5 +#define GPUCC_GPU_CC_GMU_BCR 6 +#define GPUCC_GPU_CC_GX_BCR 7 +#define GPUCC_GPU_CC_XO_BCR 8 + +/* GPU_CC power domains */ +#define GPU_CC_CX_GDSC 0 +#define GPU_CC_GX_GDSC 1 + +#endif /* _DT_BINDINGS_CLK_QCOM_GPUCC_SA8775P_H */ From patchwork Tue Apr 11 12:59:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 81960 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2580725vqo; Tue, 11 Apr 2023 06:36:16 -0700 (PDT) X-Google-Smtp-Source: AKy350bjgE77g79YAwQQA/JaPElgtPN6wWhtturdF9+SumJWGnyCi1OFd49yDpW6KqrOQuTdh+Wk X-Received: by 2002:a17:906:5953:b0:94b:d57e:9d4b with SMTP id g19-20020a170906595300b0094bd57e9d4bmr4579491ejr.2.1681220176616; Tue, 11 Apr 2023 06:36:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681220176; cv=none; d=google.com; s=arc-20160816; b=zR03us8zpbTur5FFRiYM7NdaUe9xk2njCXJnheEM15zqcLUK+GtIZcg1VU0wtRQ693 0ZdbTpNWWSgh+dMZp6fwEYU7nVFChhpVILZ1txBsCjoX9njmBGCvj4sTgMkjrFvbGkvS V5hl3ouJaC8/P4ulX2GgQTHmMVYWv87ggW9HjLYEjtbSTaM8oM220evbGX27nFbaHYSd xEurGWQsjbhTH8yGl+TH1qfxRO+Ep0JfJjdPVml8QJsH000+8nXpYskj/nNIuE1CgIoU hg3r8xfIPtY/taRW0UnM80ggRw0fpKSnapwVdjxFMMBGEIH51DPNkGsfVAYbIEt2+CKm F5Vw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=5K4aeGEvc/tJ8dubhh3ZC99EFEogKxrAp8rOanjRliI=; b=Gjr0DnPl9OC0msaBFvAbgWXs4c7eFGQDN5mjGZ2UbjC46OxUILVWhdNuSWhepvtnq1 4JKqBjOdGsDBrTwBGjqFq+yCyzHzgR8u3YctFc12EsGrbp3/ENZQiyJmCmVS0MOqROI2 zmSFjNWdyfGAuagsSnSCG3wKUoVSp8sF1agkTyhAedgCKsZUqs66pMfht44jFSDLXewD YlXDHkcoHvOEuhIaml7gUkf0rk+csxmgHjYDfYlvc4Xpw5bek67vjDoOC4OB95p3ZKqZ hw/ArIPPcQn7fB5rkPaR9O1VLvy5zxYbdl2qPNUmTouA296X8AxJtLzLqsRMDBnC8PVu 0LBw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@bgdev-pl.20210112.gappssmtp.com header.s=20210112 header.b=eMUC39iv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id qf18-20020a1709077f1200b0094a74feb184si329174ejc.858.2023.04.11.06.35.52; Tue, 11 Apr 2023 06:36:16 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@bgdev-pl.20210112.gappssmtp.com header.s=20210112 header.b=eMUC39iv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230240AbjDKM7r (ORCPT + 99 others); Tue, 11 Apr 2023 08:59:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54258 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230033AbjDKM7a (ORCPT ); Tue, 11 Apr 2023 08:59:30 -0400 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A903B4C0E for ; Tue, 11 Apr 2023 05:59:18 -0700 (PDT) Received: by mail-wm1-x329.google.com with SMTP id he11-20020a05600c540b00b003ef6d684102so2311769wmb.3 for ; Tue, 11 Apr 2023 05:59:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20210112.gappssmtp.com; s=20210112; t=1681217957; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5K4aeGEvc/tJ8dubhh3ZC99EFEogKxrAp8rOanjRliI=; b=eMUC39ivV89Y0cIie4Lm2vqcCYHxfDwcpfcqgsoeARD01w8Adiac6qrtQOLjKNjxak j9zu/hYkKgjVHvy66ko5s6sqxkOYLccjF8V7JrT+q94pY0nuAYdlUDR+GQDPMVyN4MH0 1Nv3UPYPjxmflRsVIGkZ6DFFapGQ+eJqQ8bz54RenyJL7zfWc4mbPDZ8z0l+q5sUcTjS ETOOyyIoQbrxjewCv5lZvWfsZaOykqFyoF+Bf6gqssRsUqPGhckAD3f6nyNHyR8hfiYp yRk2PaGtI6l0VLAOzeXrKCn2dYA5C4vEJz7idly1aAYu0vRx1dcjZQcuaIlC+u7mrjMc SUqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681217957; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5K4aeGEvc/tJ8dubhh3ZC99EFEogKxrAp8rOanjRliI=; b=Qb2ScsPG7oyItZOda3IhyARHSIMZLeeM4FkeXLcjefTFfbkmPn7gLgMI6r2czDvBLw MywRPytDKQ6OY+Raih74mHeuFqdGAgLelW/28POUReCb3mbRKKQbXWK5qhiQY2qO6JI6 QbG2ThSs8TgpsaO646f28K/fuOm2Cck3y3qKRbFn6G+gMsPyPh2x1Gr1Qb6mOmpDGqr9 YKiHhdaVG0voA6j9QXzre5OrbuiRE0d4Zury/77RCcqgCJmEyD/TApzbkqpJBTVFaN1U GE6Doun6HOlvy/2OAHdZccB0/LNnId/GLsMSTijt1WtnL9qNy/tMc3Mf6S6XZHKsAkLP 3e3A== X-Gm-Message-State: AAQBX9el/DaNlzwd/vLfDGkIZAW9+gL+6zEH1zfu7hBNYXJjrWspKkPi SO5TyYuzhNVPN2oK2RWf7EC+vQ== X-Received: by 2002:a7b:c855:0:b0:3ed:2a41:8525 with SMTP id c21-20020a7bc855000000b003ed2a418525mr10370308wml.22.1681217956956; Tue, 11 Apr 2023 05:59:16 -0700 (PDT) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:a099:fc1d:c99a:bfc3]) by smtp.gmail.com with ESMTPSA id e24-20020a05600c219800b003eae73f0fc1sm16944591wme.18.2023.04.11.05.59.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Apr 2023 05:59:16 -0700 (PDT) From: Bartosz Golaszewski To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Will Deacon , Robin Murphy , Joerg Roedel , Catalin Marinas , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Shazad Hussain , Bartosz Golaszewski Subject: [PATCH v3 2/7] clk: qcom: add the GPUCC driver for sa8775p Date: Tue, 11 Apr 2023 14:59:05 +0200 Message-Id: <20230411125910.401075-3-brgl@bgdev.pl> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230411125910.401075-1-brgl@bgdev.pl> References: <20230411125910.401075-1-brgl@bgdev.pl> MIME-Version: 1.0 X-Spam-Status: No, score=0.0 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762887127787438939?= X-GMAIL-MSGID: =?utf-8?q?1762887127787438939?= From: Shazad Hussain Add the clock driver for the Qualcomm Graphics Clock control module. Signed-off-by: Shazad Hussain [Bartosz: make ready for upstream] Co-authored-by: Bartosz Golaszewski Signed-off-by: Bartosz Golaszewski --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-sa8775p.c | 625 +++++++++++++++++++++++++++++++ 3 files changed, 635 insertions(+) create mode 100644 drivers/clk/qcom/gpucc-sa8775p.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index d71c9d6036bb..12be3e2371b3 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -445,6 +445,15 @@ config SA_GCC_8775P Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, UFS, SDCC, etc. +config SA_GPUCC_8775P + tristate "SA8775P Graphics clock controller" + select QCOM_GDSC + select SA_GCC_8775P + help + Support for the graphics clock controller on SA8775P devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config SC_GCC_7180 tristate "SC7180 Global Clock Controller" select QCOM_GDSC diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index b54085e579a0..9ff4c373ad95 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -72,6 +72,7 @@ obj-$(CONFIG_SC_DISPCC_7180) += dispcc-sc7180.o obj-$(CONFIG_SC_DISPCC_7280) += dispcc-sc7280.o obj-$(CONFIG_SC_DISPCC_8280XP) += dispcc-sc8280xp.o obj-$(CONFIG_SA_GCC_8775P) += gcc-sa8775p.o +obj-$(CONFIG_SA_GPUCC_8775P) += gpucc-sa8775p.o obj-$(CONFIG_SC_GCC_7180) += gcc-sc7180.o obj-$(CONFIG_SC_GCC_7280) += gcc-sc7280.o obj-$(CONFIG_SC_GCC_8180X) += gcc-sc8180x.o diff --git a/drivers/clk/qcom/gpucc-sa8775p.c b/drivers/clk/qcom/gpucc-sa8775p.c new file mode 100644 index 000000000000..18d23be8d435 --- /dev/null +++ b/drivers/clk/qcom/gpucc-sa8775p.c @@ -0,0 +1,625 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "common.h" +#include "reset.h" +#include "gdsc.h" + +/* Need to match the order of clocks in DT binding */ +enum { + DT_BI_TCXO, + DT_GCC_GPU_GPLL0_CLK_SRC, + DT_GCC_GPU_GPLL0_DIV_CLK_SRC, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_OUT_MAIN, + P_GPU_CC_PLL1_OUT_MAIN, +}; + +static const struct clk_parent_data parent_data_tcxo = { .index = DT_BI_TCXO }; + +static const struct pll_vco lucid_evo_vco[] = { + { 249600000, 2020000000, 0 }, +}; + +/* 810MHz configuration */ +static struct alpha_pll_config gpu_cc_pll0_config = { + .l = 0x2a, + .alpha = 0x3000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x32aa299c, + .user_ctl_val = 0x00000001, + .user_ctl_hi_val = 0x00400805, +}; + +static struct clk_alpha_pll gpu_cc_pll0 = { + .offset = 0x0, + .vco_table = lucid_evo_vco, + .num_vco = ARRAY_SIZE(lucid_evo_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr = { + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_pll0", + .parent_data = &parent_data_tcxo, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +/* 1000MHz configuration */ +static struct alpha_pll_config gpu_cc_pll1_config = { + .l = 0x34, + .alpha = 0x1555, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x32aa299c, + .user_ctl_val = 0x00000001, + .user_ctl_hi_val = 0x00400805, +}; + +static struct clk_alpha_pll gpu_cc_pll1 = { + .offset = 0x1000, + .vco_table = lucid_evo_vco, + .num_vco = ARRAY_SIZE(lucid_evo_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr = { + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_pll1", + .parent_data = &parent_data_tcxo, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct parent_map gpu_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_0[] = { + { .index = DT_BI_TCXO }, + { .index = DT_GCC_GPU_GPLL0_CLK_SRC }, + { .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpu_cc_pll0.clkr.hw }, + { .hw = &gpu_cc_pll1.clkr.hw }, + { .index = DT_GCC_GPU_GPLL0_CLK_SRC }, + { .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC }, +}; + +static const struct parent_map gpu_cc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_2[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpu_cc_pll1.clkr.hw }, + { .index = DT_GCC_GPU_GPLL0_CLK_SRC }, + { .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC }, +}; + +static const struct parent_map gpu_cc_parent_map_3[] = { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_3[] = { + { .index = DT_BI_TCXO }, +}; + +static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = { + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_ff_clk_src = { + .cmd_rcgr = 0x9474, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_0, + .freq_tbl = ftbl_gpu_cc_ff_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_ff_clk_src", + .parent_data = gpu_cc_parent_data_0, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { + F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src = { + .cmd_rcgr = 0x9318, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_1, + .freq_tbl = ftbl_gpu_cc_gmu_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_gmu_clk_src", + .parent_data = gpu_cc_parent_data_1, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = { + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_hub_clk_src = { + .cmd_rcgr = 0x93ec, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_2, + .freq_tbl = ftbl_gpu_cc_hub_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_hub_clk_src", + .parent_data = gpu_cc_parent_data_2, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_2), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_xo_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_xo_clk_src = { + .cmd_rcgr = 0x9010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_3, + .freq_tbl = ftbl_gpu_cc_xo_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_xo_clk_src", + .parent_data = gpu_cc_parent_data_3, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_3), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_demet_div_clk_src = { + .reg = 0x9054, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_demet_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = { + .reg = 0x9430, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_hub_ahb_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = { + .reg = 0x942c, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_hub_cx_int_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk = { + .halt_reg = 0x911c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x911c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_ahb_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cb_clk = { + .halt_reg = 0x93a4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x93a4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_cb_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_crc_ahb_clk = { + .halt_reg = 0x9120, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9120, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_crc_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_ahb_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_ff_clk = { + .halt_reg = 0x914c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x914c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_cx_ff_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_ff_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk = { + .halt_reg = 0x913c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x913c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_cx_gmu_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { + .halt_reg = 0x9130, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9130, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_cx_snoc_dvm_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_aon_clk = { + .halt_reg = 0x9004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_cxo_aon_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk = { + .halt_reg = 0x9144, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9144, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_cxo_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_demet_clk = { + .halt_reg = 0x900c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x900c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_demet_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_demet_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { + .halt_reg = 0x7000, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_aon_clk = { + .halt_reg = 0x93e8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x93e8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_hub_aon_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_cx_int_clk = { + .halt_reg = 0x9148, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9148, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_hub_cx_int_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_cx_int_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_memnoc_gfx_clk = { + .halt_reg = 0x9150, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9150, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_memnoc_gfx_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_sleep_clk = { + .halt_reg = 0x9134, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9134, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_sleep_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *gpu_cc_sa8775p_clocks[] = { + [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, + [GPU_CC_CB_CLK] = &gpu_cc_cb_clk.clkr, + [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr, + [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, + [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, + [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, + [GPU_CC_DEMET_CLK] = &gpu_cc_demet_clk.clkr, + [GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr, + [GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr, + [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, + [GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr, + [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr, + [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr, + [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr, + [GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr, + [GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr, + [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, + [GPU_CC_PLL1] = &gpu_cc_pll1.clkr, + [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, + [GPU_CC_XO_CLK_SRC] = &gpu_cc_xo_clk_src.clkr, +}; + +static struct gdsc cx_gdsc = { + .gdscr = 0x9108, + .gds_hw_ctrl = 0x953c, + .pd = { + .name = "cx_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE | RETAIN_FF_ENABLE | ALWAYS_ON, +}; + +static struct gdsc gx_gdsc = { + .gdscr = 0x905c, + .pd = { + .name = "gx_gdsc", + .power_on = gdsc_gx_do_nothing_enable, + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = AON_RESET | RETAIN_FF_ENABLE, +}; + +static struct gdsc *gpu_cc_sa8775p_gdscs[] = { + [GPU_CC_CX_GDSC] = &cx_gdsc, + [GPU_CC_GX_GDSC] = &gx_gdsc, +}; + +static const struct qcom_reset_map gpu_cc_sa8775p_resets[] = { + [GPUCC_GPU_CC_ACD_BCR] = { 0x9358 }, + [GPUCC_GPU_CC_CB_BCR] = { 0x93a0 }, + [GPUCC_GPU_CC_CX_BCR] = { 0x9104 }, + [GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 }, + [GPUCC_GPU_CC_FF_BCR] = { 0x9470 }, + [GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 }, + [GPUCC_GPU_CC_GMU_BCR] = { 0x9314 }, + [GPUCC_GPU_CC_GX_BCR] = { 0x9058 }, + [GPUCC_GPU_CC_XO_BCR] = { 0x9000 }, +}; + +static const struct regmap_config gpu_cc_sa8775p_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x9988, + .fast_io = true, +}; + +static const struct qcom_cc_desc gpu_cc_sa8775p_desc = { + .config = &gpu_cc_sa8775p_regmap_config, + .clks = gpu_cc_sa8775p_clocks, + .num_clks = ARRAY_SIZE(gpu_cc_sa8775p_clocks), + .resets = gpu_cc_sa8775p_resets, + .num_resets = ARRAY_SIZE(gpu_cc_sa8775p_resets), + .gdscs = gpu_cc_sa8775p_gdscs, + .num_gdscs = ARRAY_SIZE(gpu_cc_sa8775p_gdscs), +}; + +static const struct of_device_id gpu_cc_sa8775p_match_table[] = { + { .compatible = "qcom,sa8775p-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_sa8775p_match_table); + +static int gpu_cc_sa8775p_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &gpu_cc_sa8775p_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); + clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); + + return qcom_cc_really_probe(pdev, &gpu_cc_sa8775p_desc, regmap); +} + +static struct platform_driver gpu_cc_sa8775p_driver = { + .probe = gpu_cc_sa8775p_probe, + .driver = { + .name = "gpu_cc-sa8775p", + .of_match_table = gpu_cc_sa8775p_match_table, + }, +}; + +static int __init gpu_cc_sa8775p_init(void) +{ + return platform_driver_register(&gpu_cc_sa8775p_driver); +} +subsys_initcall(gpu_cc_sa8775p_init); + +static void __exit gpu_cc_sa8775p_exit(void) +{ + platform_driver_unregister(&gpu_cc_sa8775p_driver); +} +module_exit(gpu_cc_sa8775p_exit); + +MODULE_DESCRIPTION("SA8775P GPUCC driver"); +MODULE_LICENSE("GPL"); From patchwork Tue Apr 11 12:59:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 81947 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2573191vqo; Tue, 11 Apr 2023 06:25:37 -0700 (PDT) X-Google-Smtp-Source: AKy350bsnyzy0jcxOM9hvqpKQJBqESwlURVSiyBFYrjpDY1+9LttO+M53I7PJLZvUB7ei5Y/UfhU X-Received: by 2002:a17:90b:33c3:b0:236:73d5:82cf with SMTP id lk3-20020a17090b33c300b0023673d582cfmr14621579pjb.9.1681219537632; Tue, 11 Apr 2023 06:25:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681219537; cv=none; d=google.com; s=arc-20160816; b=psm3IX7Bsf4CsTxofYz1+Rqpo38nh4qWwJEPEw+U47qJ69U6lWrHm6eWskNhwk2K0n SUeWbQ1tFVzFnlivEPlfPn6ewaTnZJ4Yuzku2fnR7Vy2Vc6Dl3DDGgysHXUjGaXFRe23 p2VHYaVnMhGM1xZqPnrql4AiQSxGTAjc1v1u38dhrnHgObtxPiZDaB6ZZvMlTFSQYPhe GOEjESgYvjcxOblwZZOmx3yrowkQE0wIC4w3LOWl9xuXu1b7uS9YCMsoyKs6qSNu2SQj ttuf8L7+VS5vN2S+UmlOjXDxBk8nxh00hYS/Soe+e67DS2nIy1BzbmrnkdDLqJhtvcMa f0lg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=GuITCu8i/li8kE8CEtM/U6x5Upz1m7yYpvjZ7zwPQTw=; b=iC5UkBLJM7AGuQiseLj0qPt/KGb4yJxiu6tH+ZyUrr+ln7UahzHeIUYsk6wt7N6ABf K5No7ny3omVkER1aOC0V+AKEs8xyBfINqzkSgT4FlHFwnlrDQnsN8EfCf1Dcud78KnJh U540MSLuXQYxDkdCrg9L5e9KI16NdY5JW0LrxUnZPRhCQz8ivxejhNT/c84wiPA5mWcv 1eYYxO/dqPBR4dYCgFjCawf597Op6/yeIAeIDKRyKQTwkEhKBKlOOgBXhhG+6DKSeubC vzbIdfHoyzAg+qRBGAOA02S+S9e3Tgx7UOdGE2xNKBcTsGrLjOyX/YSeJwLMgjqdJI/u ektg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@bgdev-pl.20210112.gappssmtp.com header.s=20210112 header.b=UZ1Vk5py; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id iz17-20020a170902ef9100b001a4edba687dsi12821384plb.287.2023.04.11.06.25.24; Tue, 11 Apr 2023 06:25:37 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@bgdev-pl.20210112.gappssmtp.com header.s=20210112 header.b=UZ1Vk5py; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230214AbjDKM7j (ORCPT + 99 others); Tue, 11 Apr 2023 08:59:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54350 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230044AbjDKM7a (ORCPT ); Tue, 11 Apr 2023 08:59:30 -0400 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A45DA4C18 for ; Tue, 11 Apr 2023 05:59:19 -0700 (PDT) Received: by mail-wm1-x32c.google.com with SMTP id he11-20020a05600c540b00b003ef6d684102so2311794wmb.3 for ; Tue, 11 Apr 2023 05:59:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20210112.gappssmtp.com; s=20210112; t=1681217958; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GuITCu8i/li8kE8CEtM/U6x5Upz1m7yYpvjZ7zwPQTw=; b=UZ1Vk5pyYZ3AGGb3Eoi/GLfP+DqvCHb2MYHXQou+WKH5OGwsxW4CnW2W8HbAzWMtj8 LbMp29bEw1OJ/kpXcw+VlQ7oH/hSvniHhOPsdiArpE3BNia8s3WXkA9zgyYfHDiocc2E ByHscGAbT8f1luTSe7LxdA0GE3w9MhpMUb97BmmRT6XmTgY4r/kF9cig2TFGKOykmQ8m 2YUl+5AEJIUnh77cPLY8wOApToNRZpkgQoRzUsNMuQRZk9C6agxYtCU9lhTcxv0iPDL2 9xrkhxsSot/1zVCRU0gqWF8j36bRY0AizhYvfinXWKPAiLM0p5ftppacguUTnY2H3QJ5 NChw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681217958; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GuITCu8i/li8kE8CEtM/U6x5Upz1m7yYpvjZ7zwPQTw=; b=tbfmUFdF+LNsEHQ6wbWpvRqGGVZV7C5Pm+yoK2ucwEoQ9nOu1gykKZI32w4SG9U2nA nC3IXBGYs6SeNU/e9suYT9Gumh64kdnszD0JZ9EJRti/gdJ+AmhilyO5FZR7jN2nvbV0 ofQeqyE+6mFJhENc0Ko7PIMyXBHKSRfUsmziazWZmv2h2XdcxRC2b2+IGXq+Qkg3Oo8j H4GENZ8Y2PzxabUe9RdyTMQ/sFH8R6od3UVkW2svwRxf8QDSubqK+Sf7tgDwbfsnbYPD mWeEk2nFWmLjGYNbWysqR4y+229IAa47JNk6bRJwlmtsl4NRSdogiCTx/whL+Av0f3QM e28g== X-Gm-Message-State: AAQBX9c70891Z/VKxvAG0hyH6TLH/U5fvAitRcq/V7G66Zl/O2ewWy4n N5/ZGaH79nF+7N5rmzu/m0+hmw== X-Received: by 2002:a1c:7411:0:b0:3f0:49a3:5878 with SMTP id p17-20020a1c7411000000b003f049a35878mr2023754wmc.12.1681217958106; Tue, 11 Apr 2023 05:59:18 -0700 (PDT) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:a099:fc1d:c99a:bfc3]) by smtp.gmail.com with ESMTPSA id e24-20020a05600c219800b003eae73f0fc1sm16944591wme.18.2023.04.11.05.59.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Apr 2023 05:59:17 -0700 (PDT) From: Bartosz Golaszewski To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Will Deacon , Robin Murphy , Joerg Roedel , Catalin Marinas , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Bartosz Golaszewski Subject: [PATCH v3 3/7] arm64: defconfig: enable the SA8775P GPUCC driver Date: Tue, 11 Apr 2023 14:59:06 +0200 Message-Id: <20230411125910.401075-4-brgl@bgdev.pl> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230411125910.401075-1-brgl@bgdev.pl> References: <20230411125910.401075-1-brgl@bgdev.pl> MIME-Version: 1.0 X-Spam-Status: No, score=0.0 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762886457768692780?= X-GMAIL-MSGID: =?utf-8?q?1762886457768692780?= From: Bartosz Golaszewski Enable the GPUCC module for SA8775P platforms in the arm64 defconfig. Signed-off-by: Bartosz Golaszewski --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index b6342b40c600..e1063ab32658 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1164,6 +1164,7 @@ CONFIG_MSM_GCC_8998=y CONFIG_QCS_GCC_404=y CONFIG_SA_GCC_8775P=y CONFIG_SC_DISPCC_8280XP=m +CONFIG_SA_GPUCC_8775P=m CONFIG_SC_GCC_7180=y CONFIG_SC_GCC_7280=y CONFIG_SC_GCC_8180X=y From patchwork Tue Apr 11 12:59:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 81941 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2555437vqo; Tue, 11 Apr 2023 06:04:11 -0700 (PDT) X-Google-Smtp-Source: AKy350a/dQagyAK44lVhLFulh57d0x+xd3jx/z6RpdyghtTaPcR3C2HkahcvONvXMQ0W1SB4zGja X-Received: by 2002:a17:907:7b06:b0:94c:548f:f81d with SMTP id mn6-20020a1709077b0600b0094c548ff81dmr4359740ejc.71.1681218251405; Tue, 11 Apr 2023 06:04:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681218251; cv=none; d=google.com; s=arc-20160816; b=M5ctzRYf6jUp9e2iW/yvdTdu7W3u+DUr777TyC0RMWNISXFfrJuW1h2TSbMD0DixUJ BInm896gN/ENAXgfuk52VVP4hHjK6BFW6O5oIn3RHoayQFMR6ktH+2JcRwX9Toxix6Ea Q63cKOiimtgk5TSha5B9Qum6oiv+sh/o0l8VLW6RdknwqXZ0GVm+udJ/yRPqlTmxjADU SIMOL9nWgSrUR0QBCL/qyhCu6NFAkOxPkJsxuGCBXcyWF/N6eImKpPYGTW4KPWEFtNk1 qt98ijEUDOi7LwJym3UTy9G33tqxKjO0hpEaCEXwkpnRJykHMOObYXZwQK1LtZ/kgnWI T3lw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=TuLAeQGEV5K3iInBKoewzkhME+2oUBqCQOoUHj0zOJc=; b=kB/ZWmX1dKxzU6fvqAK7ZerumR924zhT5iUu9Bn1h9yanfAN9TVF/a7KH1S+BPv0nD isyuN7N54wSN6OLNx/3O0lCnN591W6FEphnoXeWbH9XPdrHZ2WL+f/G4suJD4Xw4Zm5l V6zNqLRbfltwa/gFyDIhn3tsGMhp2qOq+3h/QZmAKrM8uuZee/4qPPnFoCcQWPXMh43A Fs/4Yc2zomwZW+NwcylO4UNOK6ZyIsjMfAg7kcPIPB+3rd8ValmIHAi3auzzjcxUMv+G t+530oLLn+aMeqTqpzTgvSFgOocwgyxgUszdhhO2wpgHT06osn1e/7v2zKYgbJGDJWL+ 7WQg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@bgdev-pl.20210112.gappssmtp.com header.s=20210112 header.b=PyPA+z9w; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id t17-20020a170906269100b0092bb8b36552si11669534ejc.615.2023.04.11.06.03.46; Tue, 11 Apr 2023 06:04:11 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@bgdev-pl.20210112.gappssmtp.com header.s=20210112 header.b=PyPA+z9w; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230220AbjDKM7m (ORCPT + 99 others); Tue, 11 Apr 2023 08:59:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54422 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230177AbjDKM7c (ORCPT ); Tue, 11 Apr 2023 08:59:32 -0400 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 483A049EF for ; Tue, 11 Apr 2023 05:59:21 -0700 (PDT) Received: by mail-wm1-x32d.google.com with SMTP id i8-20020a05600c354800b003ee93d2c914so5713295wmq.2 for ; Tue, 11 Apr 2023 05:59:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20210112.gappssmtp.com; s=20210112; t=1681217959; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TuLAeQGEV5K3iInBKoewzkhME+2oUBqCQOoUHj0zOJc=; b=PyPA+z9wzuCADbJtJNpxfh193DbvsBKQKRFsnEfdj2lux9LDV4aSpKu/Sl/j/gaY6D ff1p7jAPq70oW11rHUG0e/JHYABUvaI5p6p9GAY8Ed6gQvH3EyelCkOXAmD0OLsu5IvE 3On13qxxWDP8hytuA7PMIGBmRRi3Ajv35irx15owRr11QSYeL1uZ/S+ci5YMEt25UfFz J3jUc7nvNQGsFxBDwZgQVmuwS1wEMY75SVRm9ZLYiWMgtw5rXZ9grW2MwCw+D6srA522 d17sR+X/yCvaFxX6XaJ+jMVpEjFuaX3+dTC4FAUqWUG8Co7PMz4BS3urZXyS0wJGih8n 2Idg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681217959; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TuLAeQGEV5K3iInBKoewzkhME+2oUBqCQOoUHj0zOJc=; b=PCFap2vF7uBKxeiw3iuzy1P2Qm2L7W6fPNV+wZOBoV2fizVmM4gvQOHzrcpnwm7FUX kBH19mcCKUJJ3DYJeYvBr4ucO9LoFITJ+FdxiBLu72JA2RIhv+ZCoHUOWO8jv6/0dHGF UL0h0/jQ42dTnnwhBZ5w0SbXH0DoNHZYXH9udWcSpCVf/kAt2ZjN8MsN4PcnIoUtMMWw 5HLGxpKFS43D/ql6fg02eV84mCa/Z3KXl7Cq9JvHvw9zJUCwCGF9qFwHzvy5ed315/4Q mV7Abr4X7dVSNApYGsLeEXaMK9+zfAyNA00J5Tb5aOIBW438dFlODMOndrL60gr2nsKG Cnhw== X-Gm-Message-State: AAQBX9ehfkHmyZoHcE2kpQ2Hwa+UFOpRHT8WCneC19l3nmzir5KHJtvS W8R4dx8WP/fZbC5ytpswtazgmw== X-Received: by 2002:a05:600c:2189:b0:3ed:5d41:f95c with SMTP id e9-20020a05600c218900b003ed5d41f95cmr10128112wme.11.1681217959220; Tue, 11 Apr 2023 05:59:19 -0700 (PDT) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:a099:fc1d:c99a:bfc3]) by smtp.gmail.com with ESMTPSA id e24-20020a05600c219800b003eae73f0fc1sm16944591wme.18.2023.04.11.05.59.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Apr 2023 05:59:18 -0700 (PDT) From: Bartosz Golaszewski To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Will Deacon , Robin Murphy , Joerg Roedel , Catalin Marinas , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Bartosz Golaszewski Subject: [PATCH v3 4/7] arm64: dts: qcom: sa8775p: add the pcie smmu node Date: Tue, 11 Apr 2023 14:59:07 +0200 Message-Id: <20230411125910.401075-5-brgl@bgdev.pl> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230411125910.401075-1-brgl@bgdev.pl> References: <20230411125910.401075-1-brgl@bgdev.pl> MIME-Version: 1.0 X-Spam-Status: No, score=0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_NONE,UPPERCASE_50_75 autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762885109053880583?= X-GMAIL-MSGID: =?utf-8?q?1762885109053880583?= From: Bartosz Golaszewski Add the PCIe SMMU node for sa8775p platforms. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 74 +++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 2343df7e0ea4..a23175352a20 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -809,6 +809,80 @@ apps_smmu: iommu@15000000 { ; }; + pcie_smmu: iommu@15200000 { + compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x15200000 0x0 0x80000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ From patchwork Tue Apr 11 12:59:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 81953 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2578091vqo; Tue, 11 Apr 2023 06:32:37 -0700 (PDT) X-Google-Smtp-Source: AKy350aYYRbNnfqVQMvdAX8qyb+zVfyJtioUQ2umnMxbL5m8y0/btQ7XgUaQvICMJT60KQj6q47q X-Received: by 2002:a17:907:a0d:b0:94a:4e86:31bc with SMTP id bb13-20020a1709070a0d00b0094a4e8631bcmr8949008ejc.13.1681219957412; Tue, 11 Apr 2023 06:32:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681219957; cv=none; d=google.com; s=arc-20160816; b=Bjr0OEcH78ulkAQ4g7vsrvnziiMgx2Iacue9AYQEPLS26o1UGSVO0XwSd8oJHkfHU4 DjhFJsPglYDm+E39KYj+3y2+zJUiKtiYvjAnp3NgVOBdP65JSV8DcPPcc7YyNjs6lcjZ haUipLxqmdNg2FOUfN3oSOKDoNsso6dt29J9xdLCLcPPP8eguW7lVsuf3ApZ25cWe3aX WfEMcc8fTKf/OiZdd3Mjz3cAsJMlxd5Jt4aXfT4LAOu7BlGK9My2BQKG5OE3DrypzPVZ wvJbSe5Gku85wDH0Evp3aCtwDy8MzWbw1RtkAq0Zurqo5utEVZgIGlppOz0VyPSz/Cyn w4Nw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=2RxXk1daPTunKtbomjZDgpJNAfBR2cR6YhtK/lfK/SI=; b=qR7dI1MrIbwS4Jx8HVUzI8hyGl4YG9p0LZcfqg0mSHJGXA76GAJlXqFCliNEsgAbW3 RiD0Q7wbsUL+iOZf4EZdW8Gt2FWQcfS+TOORIY/Yr8rztj1v1IFMRhj6fUA/jOZOYs4X +dVelwpkTIP2gopE2xWkqXPPMuwvE4sl95vprZvuVQKPVOo10HSL8aVM6kSz3G76RMMK +a7oXZ/UNGpp1bubj5ahcNjbsESoEl4tTmVicfvoBb222MXZMzKfG1VlLvbUg7d/XM5W /jztxMKDHVzP4CQRtjovq4Jmmpj/MmMFVObgnd4RK9WZ2JKVMpRBOfnkDuNCEd27G1Qa g46A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@bgdev-pl.20210112.gappssmtp.com header.s=20210112 header.b=jkNhgbAq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id q7-20020a170906770700b008d0a9a403f8si1493566ejm.796.2023.04.11.06.32.12; Tue, 11 Apr 2023 06:32:37 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@bgdev-pl.20210112.gappssmtp.com header.s=20210112 header.b=jkNhgbAq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230234AbjDKM7o (ORCPT + 99 others); Tue, 11 Apr 2023 08:59:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54430 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230179AbjDKM7c (ORCPT ); Tue, 11 Apr 2023 08:59:32 -0400 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1AB1D4C2F for ; Tue, 11 Apr 2023 05:59:21 -0700 (PDT) Received: by mail-wm1-x32c.google.com with SMTP id m8so18191394wmq.5 for ; Tue, 11 Apr 2023 05:59:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20210112.gappssmtp.com; s=20210112; t=1681217960; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2RxXk1daPTunKtbomjZDgpJNAfBR2cR6YhtK/lfK/SI=; b=jkNhgbAqj8TzggObBJHle31q6oTTOf6YNouhVEYNpiAFkPPJUDhi13yN2zkBMTkbCb Jd5LL4XnPSRxsSDR69wQwpMJgD4zo34dsiqtuEAPt4NiF2NT8t/t7DCs99RsrV+B6dS6 5XiY/o/CZc+jl2jpa03WzBu9VUtl5mHZTBkr2+XDyGBBUdMDrxh8TWrj+MjV5qD6VCxA XbQaYuCghyZbRe+1pp9Zjjh2rkBoR2uj7oMsy3rtP21ly1JHx3AbPkhmLGsIinwE6795 Oozk32Misl05fmnPFUTsf3I1UAbdm/7vd8B8DNMN5DXqVFhGJ4vh6P5BmQZnX4a9AP3W h0ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681217960; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2RxXk1daPTunKtbomjZDgpJNAfBR2cR6YhtK/lfK/SI=; b=3NYwXwQmTlUIMqPVbwwZqCmz7EvUikKfOy3qgUHodKocsPdk0dBsz8Jbumv/Ug7Dg3 CTpqz9P8AWuffXdNtVK+96yV9fVoK1l6VydtQMakvy9Z4cLT8ntKwY94bkxu7UeoIhcj iX+rQikksgsvjfxwHbCfjKaV51/4bFtVzGXK1x6PX/QpWUG1RgHtYi+7Adueinzb8kL/ 0bpOUt1+8W0XksN+F9jGSS+XsJ/2XJxcvgZm/1uHLgrMHRAeTNZzyIybtHlELT5SRFm8 4V+Zof/3qlzSQ+85sc2GBZomy1h2Ygw0EfSwfRVvOsEZ8/PbA4ckliZ/8iV+v39AsVw8 xZPA== X-Gm-Message-State: AAQBX9dX4RjlRjvpAQBJv3voI4vSes1LQu7Q58AhhDc32OgFhnDNDcqU JsXklmuQNtle+Sbz7NLef/T53g== X-Received: by 2002:a05:600c:4e44:b0:3ed:de03:7f0a with SMTP id e4-20020a05600c4e4400b003edde037f0amr9427917wmq.10.1681217960343; Tue, 11 Apr 2023 05:59:20 -0700 (PDT) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:a099:fc1d:c99a:bfc3]) by smtp.gmail.com with ESMTPSA id e24-20020a05600c219800b003eae73f0fc1sm16944591wme.18.2023.04.11.05.59.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Apr 2023 05:59:19 -0700 (PDT) From: Bartosz Golaszewski To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Will Deacon , Robin Murphy , Joerg Roedel , Catalin Marinas , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Bartosz Golaszewski Subject: [PATCH v3 5/7] arm64: dts: qcom: sa8775p: add the GPU clock controller node Date: Tue, 11 Apr 2023 14:59:08 +0200 Message-Id: <20230411125910.401075-6-brgl@bgdev.pl> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230411125910.401075-1-brgl@bgdev.pl> References: <20230411125910.401075-1-brgl@bgdev.pl> MIME-Version: 1.0 X-Spam-Status: No, score=0.0 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762886898416969626?= X-GMAIL-MSGID: =?utf-8?q?1762886898416969626?= From: Bartosz Golaszewski Add the GPUCC node for sa8775p platforms. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index a23175352a20..191b510b5a1a 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -591,6 +591,20 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; + gpucc: clock-controller@3d90000 { + compatible = "qcom,sa8775p-gpucc"; + reg = <0x0 0x03d90000 0x0 0xa000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sa8775p-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x30000>, From patchwork Tue Apr 11 12:59:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 81945 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2572380vqo; Tue, 11 Apr 2023 06:24:19 -0700 (PDT) X-Google-Smtp-Source: AKy350aaAWiotOAxnca/qJOLZ4x7mBLYV7A3SUD0qnlOxH8CQnINOr/v/Dfg+CQGuj8XiIoLJnaR X-Received: by 2002:a17:907:170a:b0:94a:e482:e261 with SMTP id le10-20020a170907170a00b0094ae482e261mr4710650ejc.35.1681219459705; Tue, 11 Apr 2023 06:24:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681219459; cv=none; d=google.com; s=arc-20160816; b=DrgwwXRnFhU5vdB/j5275FaVdPZMCNV9AeqMSfkpAhdWfTYNogKMETeuDMCx2RKjH3 W/dVtDjNXhy+ainyuxm+q3ZHN4zC2si7MnFPeTSNk8ONkwgRzGZo1QsQuP5DxHaF+6i8 E28oj9Uqzu9c+hYw0tYlU1ccap9f6cSEV1BGrNPlJKCHNq55VI9cOEqKDwEC0fddXG8p Z4eOjqtDyWNjAmPgXGtkbonLt0iQTSKCkkROMKGWofNSa9Y/N98fTXX1Srcour+maleU 93MHa4NI5qggzZsWAMGSu8yeOxHL9rrKa+YDo3HsdFSDRIblNrvD0DA2xvFYvtX93zQS CFIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=h5SvLGWiNz4qmlRx78+7Ty5fH+kaR1oDoC8UPKZhMno=; b=CGAyUMyXAJt5oNMGQwxwcVGDQ6JnjXZmZxfnFi1tnzfhjmtQaBe42bHNmiXv7KDHN6 t/jm49Me8sFGNvcvDqmQFxMKU6gpmilB96k032ia3XWMZP980tXzvRXLbDy14vMEEjWx NRYDmce2ffUeNvI1YwJ8qpHItEuT4QN8LpmMwbjl13nw4Qz9VondGQ38SaG+ZTQ+kgLS zHseCrI7fucNUbD/cnG0onlJliZm6DBRL78fi6Gl0B4EN3D3A9OucX6Q5e4IHKWwKqrL yYpIuSqRycF2t8dvRJOuo1Hao/6twZ9Ny/8LkGkE+dIQHFP9xeRfn9xBNK5inZvLuUom /ZXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@bgdev-pl.20210112.gappssmtp.com header.s=20210112 header.b="D/9uWMyG"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id t9-20020a1709061be900b00939ad2676ffsi10266845ejg.762.2023.04.11.06.23.55; Tue, 11 Apr 2023 06:24:19 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@bgdev-pl.20210112.gappssmtp.com header.s=20210112 header.b="D/9uWMyG"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230166AbjDKM75 (ORCPT + 99 others); Tue, 11 Apr 2023 08:59:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54418 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230199AbjDKM7g (ORCPT ); Tue, 11 Apr 2023 08:59:36 -0400 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A6D395242 for ; Tue, 11 Apr 2023 05:59:23 -0700 (PDT) Received: by mail-wm1-x332.google.com with SMTP id v20-20020a05600c471400b003ed8826253aso882685wmo.0 for ; Tue, 11 Apr 2023 05:59:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20210112.gappssmtp.com; s=20210112; t=1681217961; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=h5SvLGWiNz4qmlRx78+7Ty5fH+kaR1oDoC8UPKZhMno=; b=D/9uWMyGk1Hrj+4toN4XStrE8KQKPdXCs1L8wJLAHIIYSv8bWwKpaiXQWgOxKzpsza Eb6qrR7gyKM7gdceNdyi36w0lcrlkUXfM/GTW+57U5c/sYDtGFnDei4eV8UyR3FUyBdE Bsyvk3AoMODLaeR1Dmjbg6+FAqfZH2stDgfZaVJBU8DcWabCsMbYevxGaVyrGwXsTHxr W2hBEZ9lvssrTFnR4pi5nym46WbNcSOAjbixq+SFxPdXMI6N06DiztlF+H/6+BSjraT0 8sJAfVnTjMq7zyhgCx4xSfMXm8XW49KVq7tTKO6Fcu5nzEuzaZfqbuJrva+slA2f4dMc JStw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681217961; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h5SvLGWiNz4qmlRx78+7Ty5fH+kaR1oDoC8UPKZhMno=; b=fHUC1mrHSRFT3SJ9NY/lDehZ74wAyDl3zdJShDLnxDJq93Ywh16jlL1fO9/qs+PBD7 iFg9Bx4q7E//iYCAmhXCQI1k1ilL6aPEaidSu1DQ/BNe3219Stpd0U5OasX+2Llq88zR FMXacZn/Oa2EfIxzRUJtdXQlltufl4n/yH/KEWb8cYHCgBng90I2U/5v9UscDtQb2T9W Qsn3KwomfDcNBEiP59RJgaKjqbDsFfvcnEsMOzkhhqtzDpp9hsiS9/SMCZCazPacVb+k MdFm0I9+FDIzcVH2pdLLWyRHHzBRjUfdNpG0urcGdIoK4GtViolBKKcl8ildpmV+SqTa b6bg== X-Gm-Message-State: AAQBX9eBRsn3SRSVCCcjGmAW3ddn8M6SHXmHOKdkq5he58kknI5ZItxz cIEF+Rg7briMWvVSMlhdZcdUsw== X-Received: by 2002:a05:600c:2214:b0:3eb:2e1e:beae with SMTP id z20-20020a05600c221400b003eb2e1ebeaemr6773198wml.25.1681217961408; Tue, 11 Apr 2023 05:59:21 -0700 (PDT) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:a099:fc1d:c99a:bfc3]) by smtp.gmail.com with ESMTPSA id e24-20020a05600c219800b003eae73f0fc1sm16944591wme.18.2023.04.11.05.59.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Apr 2023 05:59:21 -0700 (PDT) From: Bartosz Golaszewski To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Will Deacon , Robin Murphy , Joerg Roedel , Catalin Marinas , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Bartosz Golaszewski Subject: [PATCH v3 6/7] dt-bindings: iommu: arm,smmu: enable clocks for sa8775p Adreno SMMU Date: Tue, 11 Apr 2023 14:59:09 +0200 Message-Id: <20230411125910.401075-7-brgl@bgdev.pl> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230411125910.401075-1-brgl@bgdev.pl> References: <20230411125910.401075-1-brgl@bgdev.pl> MIME-Version: 1.0 X-Spam-Status: No, score=0.0 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762886376530478369?= X-GMAIL-MSGID: =?utf-8?q?1762886376530478369?= From: Bartosz Golaszewski The GPU SMMU will require the clocks property to be set so put the relevant compatible into the adreno if-then block. Signed-off-by: Bartosz Golaszewski Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 807cb511fe18..d966dc65ce10 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -79,6 +79,7 @@ properties: - description: Qcom Adreno GPUs implementing "arm,smmu-500" items: - enum: + - qcom,sa8775p-smmu-500 - qcom,sc7280-smmu-500 - qcom,sm8150-smmu-500 - qcom,sm8250-smmu-500 @@ -317,7 +318,9 @@ allOf: properties: compatible: contains: - const: qcom,sc7280-smmu-500 + enum: + - qcom,sa8775p-smmu-500 + - qcom,sc7280-smmu-500 then: properties: clock-names: @@ -375,7 +378,6 @@ allOf: - nvidia,smmu-500 - qcom,qcm2290-smmu-500 - qcom,qdu1000-smmu-500 - - qcom,sa8775p-smmu-500 - qcom,sc7180-smmu-500 - qcom,sc8180x-smmu-500 - qcom,sc8280xp-smmu-500 From patchwork Tue Apr 11 12:59:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 81949 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2573255vqo; Tue, 11 Apr 2023 06:25:43 -0700 (PDT) X-Google-Smtp-Source: AKy350Zg+PchZskjPsF4pFTe+ve0N20QIJl3u3oM5MlqPcAaNzEwWQukMLKpA+IGpowqUjoTAPeZ X-Received: by 2002:a05:6402:31ea:b0:504:7aaa:275e with SMTP id dy10-20020a05640231ea00b005047aaa275emr9052409edb.41.1681219543401; Tue, 11 Apr 2023 06:25:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681219543; cv=none; d=google.com; s=arc-20160816; b=vbBqrn0+tvLtGcMtlZwqhNfAUJJo0igibRNEsBjaujl7yPBVijDlzmBN6uX5s4x/1t Dvg0N2qwonyHt4H8GWFoOv8SRBtPL8QgiykQsdOqUSUQay9UG9IkF4ydDQj6T0AHf8Vx 8QXKP6V/KQGmaS30md0HCWGplRQyr7czlfya+Q3PEXfSwGQ9UC5U2aYptfbMhWwng2B3 jQpt9fSF2Fz8EWoTaapZfTbKg2c7JDUuX7UI7Ng2CQdhZGw5nS+VmWq6zIrMhMrtRNY6 JOz9UuAnhvOtoiX514qYrZHZ70BG/a69Tn7o5bQ5Imtv17JOuUUHTFXnKZPHqlghZiac jliA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ti2ysbW8Cc+oBh8xPSaQGRD6NB9f1GZWXnz69twS12o=; b=xMrmyF7CQB95/Deuu8BmxCJjXF+ilOp96I7o9gdbtThT8HfhVqhjPcXMYpLhdNzG9T IT5Cx5f70OVz/KO0iJ/7PWCqnP/a686/+548yihIOViXNxQOzCtxrRlhpLolFdEx7hsx xMaadUr6uCupFn9LhCZR4b2e+DaBatmOeOJrh1ntGYeYDqJXpPfG7iGUTI1plo2WvP6j d/wNv7kEzxj1WKKRd/HVFaEiprIrVhpldztnHZfnsoohJy1prS4PX56bG8/6l4z35NVV dxPrQ8YMWP98gD5/wtHyZ9WPZNuuraL8yEwp0FG6dJK2b2MTYf/aFaNnJCtU9+I2LM3h SxpA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@bgdev-pl.20210112.gappssmtp.com header.s=20210112 header.b=OcPBHkjT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ay25-20020a056402203900b00504aeb5999fsi3595048edb.535.2023.04.11.06.24.11; Tue, 11 Apr 2023 06:25:43 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@bgdev-pl.20210112.gappssmtp.com header.s=20210112 header.b=OcPBHkjT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230324AbjDKNAC (ORCPT + 99 others); Tue, 11 Apr 2023 09:00:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54430 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230205AbjDKM7h (ORCPT ); Tue, 11 Apr 2023 08:59:37 -0400 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 355C3524C for ; Tue, 11 Apr 2023 05:59:23 -0700 (PDT) Received: by mail-wm1-x32c.google.com with SMTP id v14-20020a05600c470e00b003f06520825fso9529889wmo.0 for ; Tue, 11 Apr 2023 05:59:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20210112.gappssmtp.com; s=20210112; t=1681217962; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ti2ysbW8Cc+oBh8xPSaQGRD6NB9f1GZWXnz69twS12o=; b=OcPBHkjTTSWddEDKyoUb2+Rw1AzfeC+W1Z4KEsw+L9fguKR4yDvpigeQSdoc4A4+HQ VVMrOqsX63Ff5/4h3UHRyc22kAmZugXh1CUgBkKmGFMSFlqcvDSAP20oZW/aXMwW1FEN 1F5AgwZ3dEsz7OLIr24DceU49mjUodZkXHjERTF67qXS/0MyT6thWsi23DEa6QbFyKL2 F8Oe3Nzf+USVMvY71bwaeI3Bj+a8LLmUdbuzH4Po2C1l/bf+k0DYolNItPadZpw70aJf JGjw+TNmlEZjB/VG94rJRw45W9drqYB1WbFeatRLbwF1zVLypvmKwqYKdtx5iOQaDmKn YcHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681217962; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ti2ysbW8Cc+oBh8xPSaQGRD6NB9f1GZWXnz69twS12o=; b=3v0ZLnjuiLf9xoiyNOTyociQO+83p4xhzUJEtFvCkNVE87KzUZ3JAg8bfPGMLPU6br ijO6AvUB1zWGTFHsltN5UTej/Eose3AOwA0Zr7C81Ttnh6d6UpWdNT/XJzENA/nPiyIh WIGuMiOaD33kMpkbz/Xnc8UGyi84Sg9LBfkgd4zPEsbmas6OymMDryLJEsh61hrzpRTO q4fW6nIRIeiIZu1gIAc9fAmld1RAmjYOJBCw43NA9QFI1L/eu93V3+5JlKQh4L4DhcQz +T0XRW1z7nXQ1Dq8q2UVB7o4c/RntFQYlsF9n3wamgEklvftcgvKim7M0Fv4gCiW4vkc 0oAQ== X-Gm-Message-State: AAQBX9dwuH9wr4XcDU+TFmWSD0H/9FmE1h+J9E3eDquHR3oHkvMuM+uz 0uNQEgjXA760yM4GA/GHYtbfNQ== X-Received: by 2002:a7b:c354:0:b0:3ed:301c:375c with SMTP id l20-20020a7bc354000000b003ed301c375cmr7357343wmj.21.1681217962443; Tue, 11 Apr 2023 05:59:22 -0700 (PDT) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:a099:fc1d:c99a:bfc3]) by smtp.gmail.com with ESMTPSA id e24-20020a05600c219800b003eae73f0fc1sm16944591wme.18.2023.04.11.05.59.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Apr 2023 05:59:22 -0700 (PDT) From: Bartosz Golaszewski To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Will Deacon , Robin Murphy , Joerg Roedel , Catalin Marinas , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Bartosz Golaszewski Subject: [PATCH v3 7/7] arm64: dts: qcom: sa8775p: add the GPU IOMMU node Date: Tue, 11 Apr 2023 14:59:10 +0200 Message-Id: <20230411125910.401075-8-brgl@bgdev.pl> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230411125910.401075-1-brgl@bgdev.pl> References: <20230411125910.401075-1-brgl@bgdev.pl> MIME-Version: 1.0 X-Spam-Status: No, score=0.0 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762886463711011098?= X-GMAIL-MSGID: =?utf-8?q?1762886463711011098?= From: Bartosz Golaszewski Add the Adreno GPU IOMMU for sa8775p-based platforms. Signed-off-by: Bartosz Golaszewski --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 37 +++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 191b510b5a1a..11f3d80dd869 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -605,6 +606,42 @@ gpucc: clock-controller@3d90000 { #power-domain-cells = <1>; }; + adreno_smmu: iommu@3da0000 { + compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu", + "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x20000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + dma-coherent; + power-domains = <&gpucc GPU_CC_CX_GDSC>; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HUB_AON_CLK>; + clock-names = "gcc_gpu_memnoc_gfx_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gpu_cc_ahb_clk", + "gpu_cc_hlos1_vote_gpu_smmu_clk", + "gpu_cc_cx_gmu_clk", + "gpu_cc_hub_cx_int_clk", + "gpu_cc_hub_aon_clk"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sa8775p-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x30000>,