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Mon, 10 Apr 2023 11:26:50 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, jefferyalaw@gmail.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, Patrick O'Neill Subject: [PATCH v3 01/10] RISCV: Eliminate SYNC memory models Date: Mon, 10 Apr 2023 11:23:39 -0700 Message-Id: <20230410182348.2168356-2-patrick@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230410182348.2168356-1-patrick@rivosinc.com> References: <20230405210118.1969283-1-patrick@rivosinc.com> <20230410182348.2168356-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762371753488530894?= X-GMAIL-MSGID: =?utf-8?q?1762814876495773016?= Remove references to MEMMODEL_SYNC_* models by converting via memmodel_base(). 2023-04-10 Patrick O'Neill * riscv.cc: Remove MEMMODEL_SYNC_* cases and sanitize memmodel input with memmodel_base Signed-off-by: Patrick O'Neill --- gcc/config/riscv/riscv.cc | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 76eee4a55e9..8f5636c93ed 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4288,14 +4288,11 @@ riscv_memmodel_needs_amo_acquire (enum memmodel model) { case MEMMODEL_ACQ_REL: case MEMMODEL_SEQ_CST: - case MEMMODEL_SYNC_SEQ_CST: case MEMMODEL_ACQUIRE: case MEMMODEL_CONSUME: - case MEMMODEL_SYNC_ACQUIRE: return true; case MEMMODEL_RELEASE: - case MEMMODEL_SYNC_RELEASE: case MEMMODEL_RELAXED: return false; @@ -4314,14 +4311,11 @@ riscv_memmodel_needs_release_fence (enum memmodel model) { case MEMMODEL_ACQ_REL: case MEMMODEL_SEQ_CST: - case MEMMODEL_SYNC_SEQ_CST: case MEMMODEL_RELEASE: - case MEMMODEL_SYNC_RELEASE: return true; case MEMMODEL_ACQUIRE: case MEMMODEL_CONSUME: - case MEMMODEL_SYNC_ACQUIRE: case MEMMODEL_RELAXED: return false; @@ -4360,6 +4354,7 @@ riscv_print_operand (FILE *file, rtx op, int letter) } machine_mode mode = GET_MODE (op); enum rtx_code code = GET_CODE (op); + const enum memmodel model = memmodel_base (INTVAL (op)); switch (letter) { @@ -4497,12 +4492,12 @@ riscv_print_operand (FILE *file, rtx op, int letter) break; case 'A': - if (riscv_memmodel_needs_amo_acquire ((enum memmodel) INTVAL (op))) + if (riscv_memmodel_needs_amo_acquire (model)) fputs (".aq", file); break; case 'F': - if (riscv_memmodel_needs_release_fence ((enum memmodel) INTVAL (op))) + if (riscv_memmodel_needs_release_fence (model)) fputs ("fence iorw,ow; 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Mon, 10 Apr 2023 11:26:51 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, jefferyalaw@gmail.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, Patrick O'Neill Subject: [PATCH v3 02/10] RISCV: Enforce Libatomic LR/SC SEQ_CST Date: Mon, 10 Apr 2023 11:23:40 -0700 Message-Id: <20230410182348.2168356-3-patrick@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230410182348.2168356-1-patrick@rivosinc.com> References: <20230405210118.1969283-1-patrick@rivosinc.com> <20230410182348.2168356-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762371993405256455?= X-GMAIL-MSGID: =?utf-8?q?1762814994306252419?= Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs recommended by table A.6 of the ISA manual. 2023-04-10 Patrick O'Neill * atomic.c: Change LR.aq/SC.rl pairs into sequentially consistent LR.aqrl/SC.rl pair. Signed-off-by: Patrick O'Neill --- libgcc/config/riscv/atomic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libgcc/config/riscv/atomic.c b/libgcc/config/riscv/atomic.c index 69f53623509..5f895939b0b 100644 --- a/libgcc/config/riscv/atomic.c +++ b/libgcc/config/riscv/atomic.c @@ -39,7 +39,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see unsigned old, tmp1, tmp2; \ \ asm volatile ("1:\n\t" \ - "lr.w.aq %[old], %[mem]\n\t" \ + "lr.w.aqrl %[old], %[mem]\n\t" \ #insn " %[tmp1], %[old], %[value]\n\t" \ invert \ "and %[tmp1], %[tmp1], %[mask]\n\t" \ @@ -73,7 +73,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see unsigned old, tmp1; \ \ asm volatile ("1:\n\t" \ - "lr.w.aq %[old], %[mem]\n\t" \ + "lr.w.aqrl %[old], %[mem]\n\t" \ "and %[tmp1], %[old], %[mask]\n\t" \ "bne %[tmp1], %[o], 1f\n\t" \ "and %[tmp1], %[old], %[not_mask]\n\t" \ From patchwork Mon Apr 10 18:23:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 81598 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2076935vqo; Mon, 10 Apr 2023 11:30:52 -0700 (PDT) X-Google-Smtp-Source: AKy350afQCCdxeuXz8jnOrOqZu7bec03wJi041emmtl3VcF67XUbMjG8dQjdBYheU2LuFkRmTiCh X-Received: by 2002:a05:6402:524e:b0:500:2a9d:1870 with SMTP id t14-20020a056402524e00b005002a9d1870mr14937686edd.13.1681151451987; Mon, 10 Apr 2023 11:30:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681151451; cv=none; d=google.com; s=arc-20160816; b=ThfE6Y4ajU4mHAS+62yFKVr99g3V0kwP+Tco2R23ekVnBi/UD5bKqK+Y4hGwsj3O5Z yDJ9QudzPfLnk0KEGvYQBVzGk2LCtwhxhDdOU8EPwAEwynSNLN9cg8wn4zeTDNti9KiE nMufvf4g/TWKZ/67orcUrc109+RIO8lAkG4Ol4c/+Zql56dwXhiKKne7KWM5DP09CYni H8/btPVhd8a7gBLqGO/JDjReaaEwO84iSsRN4500wNPzwPvCtap/3q2dSZFiEsBl2R5j 1xo1oPj6TjnBqmdlKU3AYPEfc25ikX05x7RpfzidwmkKeHEv6/AZJhGAGHVf0842zmA/ JsBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=CSSVRusvRjGNWa3aTcqDC/2XDQQ2EwZJbnhNXOwlq9I=; b=FfOL+p+1VG1iu3DRgDPhnc4YOaKd8rvSiZq1SwSu41KUajWrJamPtWfVb8oso/7AaM cxVnJThAfMcnZsNOSMR2qJOAMMpTO7WIX62z2HFvvfcsvJMh0Pcxm3c4QoEU/6vBoBO/ xa4fnAO46gA3D/BgTVM4TwuIsp3VRUZX8+I+xR6N8nJlmt4231iE0oxC4oSb1oux9cRI R2SOEt8DJL1DBL7ltHN63thGIQ5HgDdHjgxsm1O+1lveNfgqEp4k6a1zTpAeAyw5OYly hrTXdQpOWW3iSx1WJYd+CXLf/1oF978UW/q/pA2M3ueg6xYSQ6+lzT8n/jcQUcn69bya YdvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20210112.gappssmtp.com header.s=20210112 header.b="ramEyY/3"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (ip-8-43-85-97.sourceware.org. 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Replace Fence/LR.aq/SC.aq pairs with SEQ_CST LR.aqrl/SC.rl pairs recommended by table A.6 of the ISA manual. 2023-04-10 Patrick O'Neill * sync.md: Change FENCE/LR.aq/SC.aq into sequentially consistent LR.aqrl/SC.rl pair. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/sync.md | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index c932ef87b9d..de42245981b 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -115,9 +115,16 @@ UNSPEC_COMPARE_AND_SWAP)) (clobber (match_scratch:GPR 6 "=&r"))] "TARGET_ATOMIC" - "%F5 1: lr.%A5 %0,%1; bne %0,%z2,1f; sc.%A4 %6,%z3,%1; bnez %6,1b; 1:" + { + return "1:\;" + "lr..aqrl\t%0,%1\;" + "bne\t%0,%z2,1f\;" + "sc..rl\t%6,%z3,%1\;" + "bnez\t%6,1b\;" + "1:"; + } [(set_attr "type" "atomic") - (set (attr "length") (const_int 20))]) + (set (attr "length") (const_int 16))]) (define_expand "atomic_compare_and_swap" [(match_operand:SI 0 "register_operand" "") ;; bool output From patchwork Mon Apr 10 18:23:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 81594 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2076193vqo; Mon, 10 Apr 2023 11:29:34 -0700 (PDT) X-Google-Smtp-Source: AKy350ZvqeYO8N2mdLPNEurrqHTum+z6QsCjge/JHJhayapBXDf2pjl5nQIZhERzF9921MKGqD7Z X-Received: by 2002:a17:907:3e0e:b0:94a:68dc:1c7b with SMTP id hp14-20020a1709073e0e00b0094a68dc1c7bmr6587117ejc.70.1681151374478; Mon, 10 Apr 2023 11:29:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681151374; cv=none; d=google.com; s=arc-20160816; b=abWGk3pXMf1D4ni7jIy5fxeUbHtGymqVV/0fUZoS/c/knDKwcMoMW4wZDf1YluDtDZ 9Wl3Iskcfjbz3ZVzmAzgEDgHQfdpX2CoVHig5XUMYq2OU+8I8W/bNguZix8kkSpjP6hG xg+HtARMWNAY4Z/88Ex80K7NFZT0ybFtPSTv338o3lWVE6DluEbEWnAwTMsht3DfcRRD rm4Znq9tRtyxLstXwUN+XkC91cRwZnA3gmaiSKR3ABxmkmeYTA6V9+qdop+IwF/s1nqa MaSIPVtYKzv30n8bD6OZXz+RxhhNrKKniyykZMBu/YMXMfWe6AJeFD2VwXxJMeN1K/Vn p5zw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=IGP2LgtvtisXp6wBChyNLzJpUiyuNOJa5di9Ua2pGJc=; b=kCvLMr4ASwfBMnEtSPriKx5XaF+kbytxM0qGjNkmE+dGCBMv9/bEQjPavmN95SgWvt h9IbR+NhPZZFlPqwGq0ehB+D2P5oEal/v1xns0TO4rsaFAJ2S+n8YHZaPCRyA2mbb5mq CbMl3GB6q4gm4T0inzpyoAtFwQtytjhePJjKJjmTjjhFxXiKaVZG6vl9qi5jjIy6BL7w 7R28RSnNnpXuP3Q1ai+3W0jP+UgYOkJstbadnVgR/WVtGhO5WdAu83LqE/Ws6c5TfspC 1z+zcVO/m8dnD8TbpyG/UsvWkt7+ZiyhCe380pX3714uIb2om5UngIeAkNVeSelprDMZ 3bTA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20210112.gappssmtp.com header.s=20210112 header.b=VIZ4DXAA; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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Signed-off-by: Patrick O'Neill --- gcc/config/riscv/riscv.cc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 8f5636c93ed..8ffee494fbe 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4492,8 +4492,13 @@ riscv_print_operand (FILE *file, rtx op, int letter) break; case 'A': - if (riscv_memmodel_needs_amo_acquire (model)) + if (riscv_memmodel_needs_amo_acquire (model) && + riscv_memmodel_needs_release_fence (model)) + fputs (".aqrl", file); + else if (riscv_memmodel_needs_amo_acquire (model)) fputs (".aq", file); + else if (riscv_memmodel_needs_release_fence (model)) + fputs (".rl", file); break; case 'F': From patchwork Mon Apr 10 18:23:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 81601 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2077615vqo; Mon, 10 Apr 2023 11:32:00 -0700 (PDT) X-Google-Smtp-Source: AKy350bmkAmshPNy/HgCas04VrRfTn1VT4yxIb3nBxPySbhcf2280hvWu3X4kiYtYWoiwr26TzPg X-Received: by 2002:a17:906:7f07:b0:94a:a1e2:ce29 with SMTP id d7-20020a1709067f0700b0094aa1e2ce29mr2083669ejr.23.1681151519980; Mon, 10 Apr 2023 11:31:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681151519; cv=none; d=google.com; s=arc-20160816; b=TOs2hZVjw9dQf4wHTtaZYCHiwO+8WowkYsgTkbVD8K3D9Mg+Cq2CVEEM0ad7v5sfwh WKHzonJQ1q1Pjv5CbRaXLxWb8P2O9pDMoGK9uU6Kz2GxlP+xPL7H/O/ezxO8XkODgAck 5frx5MU7xCdzN8Ib9DglE7RKBVt/bsjIGlmUdL9SSn1p6bGakauqWYcSV0C9Gi8N4/Nq gXP9Aw23xyCnI+V6n8uTWyvPK8vyuFGax2usGDaLCJePjJLUkeRgUpza+E/uafk8Tlx3 OOpzDqF2bAfrpT8Eb1DBBv6M2JLlERrTpJqQjveQo5vWvSsxBuppuholszVCV3PgwhHv znwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=lQxELVkbvgDoM2334WlZF1piQ+RAUxqqTmxO3BmB9WQ=; b=DJR5spZh3MV/7WFipxDWip+TXXQpMGZ9JcRQkZebm6XTKla5l/59B5zjOabf71jrwB LlHNOXSQfE0q97fin2FGqx3e706f8PcmsY5RFgLDielfu85lLJ25Z+zAdrI8e0ktX/6Y DMxb2obDM/rfT/sPGRLGtpvGjOwoCMG6zmaNnkIbijbFc1v5FPTZi7irdCd5BxhSjTEH zR/Qv2+c/KwDpF4Jthbs36bSfpwGyUB0SBnM4/ZKeIQflg8mugaMvuBypc8ePiA+UPkr hJ1fbZV+vAxub7WyM3tyT04GfaL9F1eDSyrtaiWHbfeA560NyGyL3eerPtVZMKLnA0yl 7AMg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20210112.gappssmtp.com header.s=20210112 header.b=F9pi8+TX; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id h23-20020aa7c617000000b00504a2c8a9a1si2282628edq.157.2023.04.10.11.31.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 11:31:59 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@rivosinc-com.20210112.gappssmtp.com header.s=20210112 header.b=F9pi8+TX; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 81822382C176 for ; Mon, 10 Apr 2023 18:28:57 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pl1-x644.google.com (mail-pl1-x644.google.com [IPv6:2607:f8b0:4864:20::644]) by sourceware.org (Postfix) with ESMTPS id 0B0713858C36 for ; Mon, 10 Apr 2023 18:26:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0B0713858C36 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pl1-x644.google.com with SMTP id n14so30495412plc.8 for ; Mon, 10 Apr 2023 11:26:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; t=1681151216; x=1683743216; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lQxELVkbvgDoM2334WlZF1piQ+RAUxqqTmxO3BmB9WQ=; b=F9pi8+TXLrdQY3rL72g3D1Fkvk8KiJ/wJNa6f5Nb48DuIdB/y0ZRbXIihE2jCnJSi/ SYMVKU9bWcL4elhIEwNgKfTBkQ+21Ut823YA9fy37NG9u5jWT7k+krI/VlDaeoi5/tZG dg5dM/tjMnykv+EKizvjtPJRXhiqDAshcgkK6qTvvLaxsyogiFVYzBgx8JMZR20auDmL 4U6EC9ddwgV98N/F959HMofWgMzcY3lcdoT9oLVM+ZPX3c9m9hDpAJm9HqMWjTcoyso2 jd/gQNcDWitkjnseSaetDycdcFkJmhOEhQ2MgXncucgrokB1aV6+PHRJ5HwfGYW5QBUX JrfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681151216; x=1683743216; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lQxELVkbvgDoM2334WlZF1piQ+RAUxqqTmxO3BmB9WQ=; b=XdoG7sQWc0s0AL5XjzIZtHqq38Po6fTKT7qv2abhsTmOs0GPjpEZvGwjrFK+TpNuGv wANocWE77WBsHyM/0+p+v4mugyw5078FxG9kYyBVA6n1OjHLgFpmddV7sIHb6tromvmY lv5lzxOCeDOg9SLa7HEcg/wrr9bBm/Ve8AMqX0SU+0wj3drk9NJFGltY6OsWN4svP0k5 BpuKVsS3n9jSxsFEuMpcllszzM8ZfOngV5RGL6eHmQDVJMX5RQ5Bq0SgAdW6+Sa3PN5l oPGkEQZfx626/VxuHLL3KBDYzk++rW2dTMJ2z55lhRg350C7N2ESDZ/9yROMtvgs31qK AAxw== X-Gm-Message-State: AAQBX9flM00GJtA3uuFoT3D4LWdb8HE4Wf21jaTbxlpsmgVSgCdXvdM4 U7wvy4tijFiA4dhLJTDoqX7QqkqsiARejBpQuGOM5BheKnA= X-Received: by 2002:a05:6a20:8b29:b0:db:81b:94be with SMTP id l41-20020a056a208b2900b000db081b94bemr11882432pzh.49.1681151215961; Mon, 10 Apr 2023 11:26:55 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id d2-20020aa78e42000000b00627f054a3cdsm4478977pfr.31.2023.04.10.11.26.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 11:26:55 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, jefferyalaw@gmail.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, Patrick O'Neill Subject: [PATCH v3 05/10] RISCV: Strengthen atomic stores Date: Mon, 10 Apr 2023 11:23:43 -0700 Message-Id: <20230410182348.2168356-6-patrick@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230410182348.2168356-1-patrick@rivosinc.com> References: <20230405210118.1969283-1-patrick@rivosinc.com> <20230410182348.2168356-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762815136210833429?= X-GMAIL-MSGID: =?utf-8?q?1762815136210833429?= This change makes atomic stores strictly stronger than table A.6 of the ISA manual. This mapping makes the overall patchset compatible with table A.7 as well. 2023-04-10 Patrick O'Neill PR target/89835 * sync.md (atomic_store): Use simple store instruction in combination with a fence. * pr89835.c: New test. Signed-off-by: Patrick O'Neill --- v3 Changelog: * Use a trailing fence for atomic stores to be compatible with Table A.7 --- gcc/config/riscv/sync.md | 20 +++++++++++++++++--- gcc/testsuite/gcc.target/riscv/pr89835.c | 9 +++++++++ 2 files changed, 26 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/pr89835.c diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index de42245981b..eef083b06e8 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -53,7 +53,8 @@ ;; Atomic memory operations. -;; Implement atomic stores with amoswap. Fall back to fences for atomic loads. +;; Implement atomic stores with conservative fences. Fall back to fences for atomic loads. +;; This allows us to be compatible with the ISA manual Table A.6 and Table A.7. (define_insn "atomic_store" [(set (match_operand:GPR 0 "memory_operand" "=A") (unspec_volatile:GPR @@ -61,9 +62,22 @@ (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_ATOMIC_STORE))] "TARGET_ATOMIC" - "%F2amoswap.%A2 zero,%z1,%0" + { + enum memmodel model = (enum memmodel) INTVAL (operands[2]); + model = memmodel_base (model); + + if (model == MEMMODEL_SEQ_CST) + return "fence\trw,w\;" + "s\t%z1,%0\;" + "fence\trw,rw"; + if (model == MEMMODEL_RELEASE) + return "fence\trw,w\;" + "s\t%z1,%0"; + else + return "s\t%z1,%0"; + } [(set_attr "type" "atomic") - (set (attr "length") (const_int 8))]) + (set (attr "length") (const_int 12))]) (define_insn "atomic_" [(set (match_operand:GPR 0 "memory_operand" "+A") diff --git a/gcc/testsuite/gcc.target/riscv/pr89835.c b/gcc/testsuite/gcc.target/riscv/pr89835.c new file mode 100644 index 00000000000..ab190e11b60 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr89835.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* Verify that relaxed atomic stores use simple store instuctions. */ +/* { dg-final { scan-assembler-not "amoswap" } } */ + +void +foo(int bar, int baz) +{ + __atomic_store_n(&bar, baz, __ATOMIC_RELAXED); +} From patchwork Mon Apr 10 18:23:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 81593 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2075920vqo; Mon, 10 Apr 2023 11:28:52 -0700 (PDT) X-Google-Smtp-Source: AKy350b+nNkw2yiDyaYdGFqQfS/2rtOeSmko7s6kTsQx1RD7tJg9zu4rrTA7bAuZwF+27zGhyBIy X-Received: by 2002:a17:906:1502:b0:933:3814:e0f4 with SMTP id b2-20020a170906150200b009333814e0f4mr8940224ejd.16.1681151332411; Mon, 10 Apr 2023 11:28:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681151332; cv=none; d=google.com; s=arc-20160816; b=VxrLTMRnEl8i+LmSRHl4vxRj0Na60gQ8aUGRzWViKXyOxa9CGJkv4Vz8CHy54FiLaY sJtfS76YKu534s5Tk4SgZ7r7LsAma71ObH6wcfQDcfFVImnN3XwSwVyMYJVIO9DkYZjb Ks60WhVlqGf0dEq3/Q7uJb4GbUd6GVEfSmO0agYZx1j8xd7NvYnrKLF64Bnk519JwyO8 unGkjWI6XOFXCfAXjScLisrtr7eNZ436B2H6iuGlfRTGvTxFdZXm70rnD/fTX1J9ntrN tqCnVou37oetv5VMZH1MUS9SbtcfyKiHNuzS9atHSCvdsjmpztz60PGGSoB401Zv6eP1 d36Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=lVP8IbDjca+kcx7I3tMp6v3BEP4D8BcaOb2FvUjEaeU=; b=yGUfJn+h9QE+vOR5+z4QSHg4h40nSqhoadHVhoGfUgZGLWHXpZHQPsGhTlbQL0MkNP 0lRKiegKe/FHYx87AHEaTAdqxALMBkt45XgL9q8M+8iQP583ZicAopPeeA7RJlHejYGp MmPF0PYBwgR7aP7x26uJRCSFmg3pnIPHw914Akf5UDxVCD0zNo6ghjFXSXHP6igUgzuE 2k9Edomn6u/PkKK84FBSH0MhlIh4YR3rEwo7JvfNLohqIjj+X2OHIywTARRNT69j6oeu eM1NewDhQ8q9cg0UGldgHcuVeOyeeVPbaaLg4JEQ5e6fFvASyBadtiCxNjtiLNOhoKeB 3nrg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20210112.gappssmtp.com header.s=20210112 header.b=ZqLaW+YO; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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Remove unnecessary release fences from atomic ops. This change brings AMO ops in line with table A.6 of the ISA manual. 2023-04-10 Patrick O'Neill * riscv.cc (riscv_memmodel_needs_amo_acquire): Change function name. * riscv.cc (riscv_print_operand): Remove unneeded %F case. * sync.md: Remove unneeded fences. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/riscv.cc | 16 +++++----------- gcc/config/riscv/sync.md | 12 ++++++------ 2 files changed, 11 insertions(+), 17 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 8ffee494fbe..6576e9ae524 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4301,11 +4301,11 @@ riscv_memmodel_needs_amo_acquire (enum memmodel model) } } -/* Return true if a FENCE should be emitted to before a memory access to - implement the release portion of memory model MODEL. */ +/* Return true if the .RL suffix should be added to an AMO to implement the + release portion of memory model MODEL. */ static bool -riscv_memmodel_needs_release_fence (enum memmodel model) +riscv_memmodel_needs_amo_release (enum memmodel model) { switch (model) { @@ -4331,7 +4331,6 @@ riscv_memmodel_needs_release_fence (enum memmodel model) 'R' Print the low-part relocation associated with OP. 'C' Print the integer branch condition for comparison OP. 'A' Print the atomic operation suffix for memory model OP. - 'F' Print a FENCE if the memory model requires a release. 'z' Print x0 if OP is zero, otherwise print OP normally. 'i' Print i if the operand is not a register. 'S' Print shift-index of single-bit mask OP. @@ -4493,19 +4492,14 @@ riscv_print_operand (FILE *file, rtx op, int letter) case 'A': if (riscv_memmodel_needs_amo_acquire (model) && - riscv_memmodel_needs_release_fence (model)) + riscv_memmodel_needs_amo_release (model)) fputs (".aqrl", file); else if (riscv_memmodel_needs_amo_acquire (model)) fputs (".aq", file); - else if (riscv_memmodel_needs_release_fence (model)) + else if (riscv_memmodel_needs_amo_release (model)) fputs (".rl", file); break; - case 'F': - if (riscv_memmodel_needs_release_fence (model)) - fputs ("fence iorw,ow; ", file); - break; - case 'i': if (code != REG) fputs ("i", file); diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index eef083b06e8..fdfc56d64a1 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -87,9 +87,9 @@ (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] "TARGET_ATOMIC" - "%F2amo.%A2 zero,%z1,%0" + "amo.%A2\tzero,%z1,%0" [(set_attr "type" "atomic") - (set (attr "length") (const_int 8))]) + (set (attr "length") (const_int 4))]) (define_insn "atomic_fetch_" [(set (match_operand:GPR 0 "register_operand" "=&r") @@ -101,9 +101,9 @@ (match_operand:SI 3 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] "TARGET_ATOMIC" - "%F3amo.%A3 %0,%z2,%1" + "amo.%A3\t%0,%z2,%1" [(set_attr "type" "atomic") - (set (attr "length") (const_int 8))]) + (set (attr "length") (const_int 4))]) (define_insn "atomic_exchange" [(set (match_operand:GPR 0 "register_operand" "=&r") @@ -114,9 +114,9 @@ (set (match_dup 1) (match_operand:GPR 2 "register_operand" "0"))] "TARGET_ATOMIC" - "%F3amoswap.%A3 %0,%z2,%1" + "amoswap.%A3\t%0,%z2,%1" [(set_attr "type" "atomic") - (set (attr "length") (const_int 8))]) + (set (attr "length") (const_int 4))]) (define_insn "atomic_cas_value_strong" [(set (match_operand:GPR 0 "register_operand" "=&r") From patchwork Mon Apr 10 18:23:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 81597 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2076841vqo; Mon, 10 Apr 2023 11:30:42 -0700 (PDT) X-Google-Smtp-Source: AKy350ZeX34BQrx9F8IP6xAlNILX8EgE3lbo0s2wJC2l5zusZKxGPysFLBg4VlVxRfvkbPpMRxTw X-Received: by 2002:a17:906:2acc:b0:947:40e6:fde3 with SMTP id m12-20020a1709062acc00b0094740e6fde3mr7184804eje.35.1681151441900; Mon, 10 Apr 2023 11:30:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681151441; cv=none; d=google.com; s=arc-20160816; b=RQH/clQVgrIZ7ueZKtN+yoX3ORpMiQcA0smSdXpjFXWbm5jXYz7MvKjSA4IQFU+W1e lIpNcj4q2xCc55fQ00bVTjVTgzU29nFD72R0QZAaRDrfYCz6s22CSHKu0N0HxwHohbag +JGqO7URXPbNVvkN2wY6c8SyLjr2BCL8XP+S27oslpgksJo6kl+lTdzpueAAW3wBI7kS 9xkNbyoavzK8nOuyCzZrU6c9sdqJBuXMSOVgndZtZ7qZGXEmnfIEig4VCAu77VJLhI61 Kp3ZFqC1iYPWZdDOA5lNImEDx+C6A2fW/cbsfhtyWGgGF8XkryzfbHZmgy6pKLiuOUzc xclw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=kU7pait8ke5Qgf9nFrP+Rk6dNO8p5TcyVBjpQmVIRzs=; b=SJ/YUla09BgWhlIdbi9mhG3dQbe4iHaeIgPStesbf1JL2oRhxz5FvG/eQh5aK+Gau5 qUoQ/mc3me4tnD8gBM6bbXVs+21SB1MdSBX1f5ULuiJGz0gP9YzRD6HT1wGafEody7OR jKXQi3jI9rogC0zBx4bbVg/dbdUOTQtGQtZZCu7YeOKNq8lCzEb8X49UFQiaxddKD6O5 GHBLiRU9hcQbwSO5WCFc7YkqBn8H2/3PIqBwbtZipznWQsX70Nn1F4y+iNd3thKUHUmP T+2i5Drot9jFWph4Q++CXgLHPAM1Ey5ax1iFEp1lPAlGJ1V1NnsKb2SwkvPAhOho85NX GTBg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20210112.gappssmtp.com header.s=20210112 header.b=b0lPxkft; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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Atomic compare and exchange ops provide success and failure memory models. C++17 and later place no restrictions on the relative strength of each model, so ensure we cover both by using a model that enforces the ordering of both given models. This change brings compare_exchange LR/SC ops in line with table A.6 of the ISA manual. 2023-04-10 Patrick O'Neill * riscv.cc: Add function to get the union of two memmodels in sync.md. * riscv-protos.h: Likewise. * sync.md (atomic_cas_value_strong): Remove static .aqrl bits on SC op/.rl bits on LR op and replace with optimized %I, %J flags. Signed-off-by: Patrick O'Neill --- v3 Changelog: * Consolidate tests in [PATCH v3 10/10] --- gcc/config/riscv/riscv-protos.h | 3 +++ gcc/config/riscv/riscv.cc | 44 +++++++++++++++++++++++++++++++++ gcc/config/riscv/sync.md | 9 +++++-- 3 files changed, 54 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 4611447ddde..b03edc3e8a5 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -22,6 +22,8 @@ along with GCC; see the file COPYING3. If not see #ifndef GCC_RISCV_PROTOS_H #define GCC_RISCV_PROTOS_H +#include "memmodel.h" + /* Symbol types we understand. The order of this list must match that of the unspec enum in riscv.md, subsequent to UNSPEC_ADDRESS_FIRST. */ enum riscv_symbol_type { @@ -79,6 +81,7 @@ extern void riscv_reinit (void); extern poly_uint64 riscv_regmode_natural_size (machine_mode); extern bool riscv_v_ext_vector_mode_p (machine_mode); extern bool riscv_shamt_matches_mask_p (int, HOST_WIDE_INT); +extern enum memmodel riscv_union_memmodels (enum memmodel, enum memmodel); /* Routines implemented in riscv-c.cc. */ void riscv_cpu_cpp_builtins (cpp_reader *); diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 6576e9ae524..061d2cf42b4 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4278,6 +4278,36 @@ riscv_print_operand_reloc (FILE *file, rtx op, bool hi_reloc) fputc (')', file); } +/* Return the memory model that encapuslates both given models. */ + +enum memmodel +riscv_union_memmodels (enum memmodel model1, enum memmodel model2) +{ + model1 = memmodel_base (model1); + model2 = memmodel_base (model2); + + enum memmodel weaker = model1 <= model2 ? model1: model2; + enum memmodel stronger = model1 > model2 ? model1: model2; + + switch (stronger) + { + case MEMMODEL_SEQ_CST: + case MEMMODEL_ACQ_REL: + return stronger; + case MEMMODEL_RELEASE: + if (weaker == MEMMODEL_ACQUIRE || weaker == MEMMODEL_CONSUME) + return MEMMODEL_ACQ_REL; + else + return stronger; + case MEMMODEL_ACQUIRE: + case MEMMODEL_CONSUME: + case MEMMODEL_RELAXED: + return stronger; + default: + gcc_unreachable (); + } +} + /* Return true if the .AQ suffix should be added to an AMO to implement the acquire portion of memory model MODEL. */ @@ -4331,6 +4361,8 @@ riscv_memmodel_needs_amo_release (enum memmodel model) 'R' Print the low-part relocation associated with OP. 'C' Print the integer branch condition for comparison OP. 'A' Print the atomic operation suffix for memory model OP. + 'I' Print the LR suffix for memory model OP. + 'J' Print the SC suffix for memory model OP. 'z' Print x0 if OP is zero, otherwise print OP normally. 'i' Print i if the operand is not a register. 'S' Print shift-index of single-bit mask OP. @@ -4500,6 +4532,18 @@ riscv_print_operand (FILE *file, rtx op, int letter) fputs (".rl", file); break; + case 'I': + if (model == MEMMODEL_SEQ_CST) + fputs (".aqrl", file); + else if (riscv_memmodel_needs_amo_acquire (model)) + fputs (".aq", file); + break; + + case 'J': + if (riscv_memmodel_needs_amo_release (model)) + fputs (".rl", file); + break; + case 'i': if (code != REG) fputs ("i", file); diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index fdfc56d64a1..a31b8c4f28a 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -130,10 +130,15 @@ (clobber (match_scratch:GPR 6 "=&r"))] "TARGET_ATOMIC" { + enum memmodel model_success = (enum memmodel) INTVAL(operands[4]); + enum memmodel model_failure = (enum memmodel) INTVAL(operands[5]); + /* Find the union of the two memory models so we can satisfy both success + and failure memory models. */ + operands[5] = GEN_INT(riscv_union_memmodels(model_success, model_failure)); return "1:\;" - "lr..aqrl\t%0,%1\;" + "lr.%I5\t%0,%1\;" "bne\t%0,%z2,1f\;" - "sc..rl\t%6,%z3,%1\;" + "sc.%J5\t%6,%z3,%1\;" "bnez\t%6,1b\;" "1:"; } From patchwork Mon Apr 10 18:23:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 81603 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2078237vqo; Mon, 10 Apr 2023 11:33:09 -0700 (PDT) X-Google-Smtp-Source: AKy350aFJns/66z73qa/GeLEA3Xx9qMsDScMetrHrzhR/yXYG2OYd1Juwq4WFosk8H72Qf874rzT X-Received: by 2002:a17:906:a84:b0:8b1:781d:f9a4 with SMTP id y4-20020a1709060a8400b008b1781df9a4mr9056356ejf.21.1681151589049; Mon, 10 Apr 2023 11:33:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681151589; cv=none; d=google.com; s=arc-20160816; b=ILPZ8BoqBIIIBye0KqTz52saQyNLrZMH1ISxAiBYUb4z4iNmMzGynEYQwMookGUoVR szRxGSmWGx7ZPTzFGSQY9PVej/dxYOguBU3Vkpc14EGrJGmiVMu2+Sbhw0RC0ZswXxpQ BnqmhWjy7z4YHpzbXXXQuTwWywqNyNU8/t6pTZbCNcQz3n+R/ZSw3IMrBsW2NvRUgp/J BNpqbO/c0yKhLWzSC8gom2GNMHmiZ7tIp6NBrev1AGUeU3zokeIJ60shzDGmQWeXodF4 NxepT6CIivAnPyem71Yg5sYGhYdDkJkKmeXd8I+VNhK9gFfkJOYZiEDb2RuDUSzoFXym OjKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=mo+bRZ+pfwq9fZONe7Uv95uVmcTBnjKtM3toy3bHl0g=; b=c23o7+1FjCvX5E5aqm46rnAl6QjrMQto6ckLq+zAYcPaAAbprbpAtZ7n6bs9t827i6 05bohuIjHuVH5uR6xRPCB2wsEhIwbUJNy1D24H2GZ+6nxk5i97W0wL/Hkdq5kT1nYcHf 0UENSah2AAZr+R+92GRMzHOtX6urwPaOQkCY5DzInAoZyvLJWXGfF83fIRYxEUUxmWd8 qZvBMGYYzLmXVS+wqWWZu8L4c6V6xSoHMNjnC57HDW+XOHIEZvSJCB8AzmPH8rETdt+g at2vTx6ZmUbjp18kp+uvOBV8PETYA1n8eFC9DNSO+lz8oaWCLZX6HfFhMgpVAU+HQmir fPjA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20210112.gappssmtp.com header.s=20210112 header.b=RX1x74G+; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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Relax mem_thread_fence according to the memmodel given. 2023-04-10 Patrick O'Neill * sync.md (mem_thread_fence_1): Change fence depending on the given memory model. Signed-off-by: Patrick O'Neill --- v3 Changelog: * Consolidate tests in [PATCH v3 10/10] * Remove helper functions --- gcc/config/riscv/sync.md | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index a31b8c4f28a..e91fa29da51 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -42,14 +42,24 @@ DONE; }) -;; Until the RISC-V memory model (hence its mapping from C++) is finalized, -;; conservatively emit a full FENCE. (define_insn "mem_thread_fence_1" [(set (match_operand:BLK 0 "" "") (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER)) (match_operand:SI 1 "const_int_operand" "")] ;; model "" - "fence\tiorw,iorw") + { + enum memmodel model = (enum memmodel) INTVAL (operands[1]); + model = memmodel_base (model); + if (model == MEMMODEL_SEQ_CST) + return "fence\trw,rw"; + else if (model == MEMMODEL_ACQ_REL) + return "fence.tso"; + else if (model == MEMMODEL_ACQUIRE) + return "fence\tr,rw"; + else if (model == MEMMODEL_RELEASE) + return "fence\trw,w"; + } + [(set (attr "length") (const_int 4))]) ;; Atomic memory operations. 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Signed-off-by: Patrick O'Neill --- v3 Changelog: * Add this patch --- gcc/config/riscv/sync.md | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index e91fa29da51..9e3685f5b1c 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -23,6 +23,7 @@ UNSPEC_COMPARE_AND_SWAP UNSPEC_SYNC_OLD_OP UNSPEC_SYNC_EXCHANGE + UNSPEC_ATOMIC_LOAD UNSPEC_ATOMIC_STORE UNSPEC_MEMORY_BARRIER ]) @@ -63,7 +64,31 @@ ;; Atomic memory operations. -;; Implement atomic stores with conservative fences. Fall back to fences for atomic loads. +(define_insn "atomic_load" + [(set (match_operand:GPR 0 "register_operand" "=r") + (unspec_volatile:GPR + [(match_operand:GPR 1 "memory_operand" "A") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_ATOMIC_LOAD))] + "TARGET_ATOMIC" + { + enum memmodel model = (enum memmodel) INTVAL (operands[2]); + model = memmodel_base (model); + + if (model == MEMMODEL_SEQ_CST) + return "fence\trw,rw\;" + "l\t%0,%1\;" + "fence\tr,rw"; + if (model == MEMMODEL_ACQUIRE) + return "l\t%0,%1\;" + "fence\tr,rw"; + else + return "l\t%0,%1"; + } + [(set_attr "type" "atomic") + (set (attr "length") (const_int 12))]) + +;; Implement atomic stores with conservative fences. ;; This allows us to be compatible with the ISA manual Table A.6 and Table A.7. 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Mon, 10 Apr 2023 11:27:01 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, jefferyalaw@gmail.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, Patrick O'Neill Subject: [PATCH v3 10/10] RISCV: Table A.6 conformance tests Date: Mon, 10 Apr 2023 11:23:48 -0700 Message-Id: <20230410182348.2168356-11-patrick@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230410182348.2168356-1-patrick@rivosinc.com> References: <20230405210118.1969283-1-patrick@rivosinc.com> <20230410182348.2168356-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762815194126570113?= X-GMAIL-MSGID: =?utf-8?q?1762815194126570113?= These tests cover basic cases to ensure the atomic mappings follow the strengthened Table A.6 mappings that are compatible with Table A.7. 2023-04-10 Patrick O'Neill * amo-table-a-6-amo-add-1.c: New test. * amo-table-a-6-amo-add-2.c: Likewise. * amo-table-a-6-amo-add-3.c: Likewise. * amo-table-a-6-amo-add-4.c: Likewise. * amo-table-a-6-amo-add-5.c: Likewise. * amo-table-a-6-compare-exchange-1.c: Likewise. * amo-table-a-6-compare-exchange-2.c: Likewise. * amo-table-a-6-compare-exchange-3.c: Likewise. * amo-table-a-6-compare-exchange-4.c: Likewise. * amo-table-a-6-compare-exchange-5.c: Likewise. * amo-table-a-6-fence-1.c: Likewise. * amo-table-a-6-fence-2.c: Likewise. * amo-table-a-6-fence-3.c: Likewise. * amo-table-a-6-fence-4.c: Likewise. * amo-table-a-6-fence-5.c: Likewise. * amo-table-a-6-load-1.c: Likewise. * amo-table-a-6-load-2.c: Likewise. * amo-table-a-6-load-3.c: Likewise. * amo-table-a-6-store-1.c: Likewise. * amo-table-a-6-store-2.c: Likewise. * amo-table-a-6-store-compat-3.c: Likewise. Signed-off-by: Patrick O'Neill --- v3 Changelog: * Consolidate existing tests in this patch * Add new tests for store/load/amoadd --- .../gcc.target/riscv/amo-table-a-6-amo-add-1.c | 8 ++++++++ .../gcc.target/riscv/amo-table-a-6-amo-add-2.c | 8 ++++++++ .../gcc.target/riscv/amo-table-a-6-amo-add-3.c | 8 ++++++++ .../gcc.target/riscv/amo-table-a-6-amo-add-4.c | 8 ++++++++ .../gcc.target/riscv/amo-table-a-6-amo-add-5.c | 8 ++++++++ .../riscv/amo-table-a-6-compare-exchange-1.c | 12 ++++++++++++ .../riscv/amo-table-a-6-compare-exchange-2.c | 12 ++++++++++++ .../riscv/amo-table-a-6-compare-exchange-3.c | 12 ++++++++++++ .../riscv/amo-table-a-6-compare-exchange-4.c | 12 ++++++++++++ .../riscv/amo-table-a-6-compare-exchange-5.c | 12 ++++++++++++ .../gcc.target/riscv/amo-table-a-6-fence-1.c | 9 +++++++++ .../gcc.target/riscv/amo-table-a-6-fence-2.c | 7 +++++++ .../gcc.target/riscv/amo-table-a-6-fence-3.c | 7 +++++++ .../gcc.target/riscv/amo-table-a-6-fence-4.c | 7 +++++++ .../gcc.target/riscv/amo-table-a-6-fence-5.c | 7 +++++++ .../gcc.target/riscv/amo-table-a-6-load-1.c | 9 +++++++++ .../gcc.target/riscv/amo-table-a-6-load-2.c | 10 ++++++++++ .../gcc.target/riscv/amo-table-a-6-load-3.c | 10 ++++++++++ .../gcc.target/riscv/amo-table-a-6-store-1.c | 9 +++++++++ .../gcc.target/riscv/amo-table-a-6-store-2.c | 10 ++++++++++ .../gcc.target/riscv/amo-table-a-6-store-compat-3.c | 10 ++++++++++ 21 files changed, 195 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c new file mode 100644 index 00000000000..ae7e407befc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "amoadd.w\t" } } */ + +void +foo (int* bar, int* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c new file mode 100644 index 00000000000..60d84f32481 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "amoadd.w.aq\t" } } */ + +void +foo (int* bar, int* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c new file mode 100644 index 00000000000..a97231e4e73 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "amoadd.w.rl\t" } } */ + +void +foo (int* bar, int* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c new file mode 100644 index 00000000000..3c843afdd5f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "amoadd.w.aqrl\t" } } */ + +void +foo (int* bar, int* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c new file mode 100644 index 00000000000..3434229f5e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "amoadd.w.aqrl\t" } } */ + +void +foo (int* bar, int* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c new file mode 100644 index 00000000000..d96bc15e23b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-not "lr.w.aq" } } */ +/* { dg-final { scan-assembler-not "lr.w.rl" } } */ +/* { dg-final { scan-assembler-not "sc.w.aq" } } */ +/* { dg-final { scan-assembler-not "sc.w.rl" } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_RELAXED, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c new file mode 100644 index 00000000000..5d173641459 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "lr.w.aq" } } */ +/* { dg-final { scan-assembler-not "lr.w.rl" } } */ +/* { dg-final { scan-assembler-not "sc.w.aq" } } */ +/* { dg-final { scan-assembler-not "sc.w.rl" } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_CONSUME, __ATOMIC_CONSUME); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c new file mode 100644 index 00000000000..36201027ab9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "lr.w.aq" } } */ +/* { dg-final { scan-assembler-not "lr.w.rl" } } */ +/* { dg-final { scan-assembler-not "sc.w.aq" } } */ +/* { dg-final { scan-assembler-not "sc.w.rl" } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c new file mode 100644 index 00000000000..3711bf7ddec --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "lr.w.aqrl" } } */ +/* { dg-final { scan-assembler "sc.w.rl" } } */ +/* { dg-final { scan-assembler-not "lr.w.rl" } } */ +/* { dg-final { scan-assembler-not "sc.w.aq" } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c new file mode 100644 index 00000000000..fb0075a1a33 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "lr.w.aq" } } */ +/* { dg-final { scan-assembler "sc.w.rl" } } */ +/* { dg-final { scan-assembler-not "lr.w.rl" } } */ +/* { dg-final { scan-assembler-not "sc.w.aq" } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_RELEASE, __ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c new file mode 100644 index 00000000000..827a0f6781b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-not "fence\t" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + + +int main() { + __atomic_thread_fence(__ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c new file mode 100644 index 00000000000..2d14a5b9681 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "fence\tr,rw" } } */ + +int main() { + __atomic_thread_fence(__ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c new file mode 100644 index 00000000000..c215dc19c90 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "fence\trw,w" } } */ + +int main() { + __atomic_thread_fence(__ATOMIC_RELEASE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c new file mode 100644 index 00000000000..6dec57593f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "fence.tso" } } */ + +int main() { + __atomic_thread_fence(__ATOMIC_ACQ_REL); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c new file mode 100644 index 00000000000..f05a33b1bcd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "fence\trw,rw" } } */ + +int main() { + __atomic_thread_fence(__ATOMIC_SEQ_CST); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c new file mode 100644 index 00000000000..8278198072e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* Verify that load mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-not "fence\t" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + +void +foo (int* bar, int* baz) { + __atomic_load(bar, baz, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c new file mode 100644 index 00000000000..faef2ce25c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "fence\tr,rw" } } */ +/* { dg-final { scan-assembler-not "fence\trw,rw" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + +void +foo (int* bar, int* baz) { + __atomic_load(bar, baz, __ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c new file mode 100644 index 00000000000..9210fd10a53 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "fence\tr,rw" } } */ +/* { dg-final { scan-assembler "fence\trw,rw" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + +void +foo (int* bar, int* baz) { + __atomic_load(bar, baz, __ATOMIC_SEQ_CST); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c new file mode 100644 index 00000000000..e2fb71b17c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* Verify that load mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-not "fence\t" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + +void +foo (int* bar, int* baz) { + __atomic_store(bar, baz, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c new file mode 100644 index 00000000000..adaace33b30 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "fence\trw,w" } } */ +/* { dg-final { scan-assembler-not "fence\trw,rw" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + +void +foo (int* bar, int* baz) { + __atomic_store(bar, baz, __ATOMIC_RELEASE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c new file mode 100644 index 00000000000..1fff6ce2857 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that store mapping are compatible with Table A.6 & A.7. */ +/* { dg-final { scan-assembler "fence\trw,w" } } */ +/* { dg-final { scan-assembler "fence\trw,rw" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + +void +foo (int* bar, int* baz) { + __atomic_store(bar, baz, __ATOMIC_SEQ_CST); +}