From patchwork Mon Apr 10 11:07:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yangfl X-Patchwork-Id: 81475 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1830592vqo; Mon, 10 Apr 2023 04:34:37 -0700 (PDT) X-Google-Smtp-Source: AKy350aBBwyvtLsKYviikkud3cAdgxFNKYIB+78su/NTRI/BWlmGL0kG99wFKukbE30VCAh842pY X-Received: by 2002:a05:6a20:4c97:b0:d8:997f:b21c with SMTP id fq23-20020a056a204c9700b000d8997fb21cmr6847417pzb.27.1681126477460; Mon, 10 Apr 2023 04:34:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681126477; cv=none; d=google.com; s=arc-20160816; b=E6YWKVWdpMHWA/EMK5wTCizZLIXhOyXcDfBXk2+KbmNkePfm7L4eZc0d/AbK8Canfv 4UlIta8FBdzzaUlaV1jGAJmTZoFxEyRYJ9HZe2Q4AaEd75NEqLy5Hk6Zwsh4cfjvS3/o mquM3tmFVroRPG2uyHNNNvBYCP1a8dWSmNvL3K+lrfEwGxypslXh81Vh0zHsmKez2LWx a3OC1ruKA0N0MwBhlX70MNT4z3qhNnwC8O/HqyI/bCIi3qrrnPxcl6Zn3d1xMiDInH52 UFcwGqpQ8yiT7RqpC6+ob0FoGTNswxE61nNc+pzAHvMgbB76eO0w7UBBaKVmPOywDaZB WLoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=zGYltMygM2Avg7sOhC73hhQt4KoPWEHqx0AmFedwBwI=; b=gZn3EhxloW6QuwkkV40rHkJn1AUD7Nt/a23Pxdx4WXm6CLJiUnnYwO5K/j/9ocERpe uSi/qeAPF9MvZUU4/hWDUv9oF65pRYlax+x9lwo6dphgVaQThZDIHuVa3iAPgOvyndZj ZFNny0vw/rlaFynWHDNE4mq95dw1LGUPzYo3hTZhF8W4sEvrL8CQcYes+RJdbxl2QMZg YMin97tfP2t6AA32rGow3JsTtjY11bsfHp8KJZMbu2K/5M/CIJJ9O5J5gTVDlGyEBUoe LO1G2qJxGeNCwG5myy4BJdijuhLWsaOSfJff9KRgb5OPp6f3Vi1Cdn0O3shl6oQ7wyZj uSRA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b="kjqgIfK/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id t18-20020a635352000000b004a4eae7c943si7857079pgl.535.2023.04.10.04.34.24; Mon, 10 Apr 2023 04:34:37 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b="kjqgIfK/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229557AbjDJLIF (ORCPT + 99 others); Mon, 10 Apr 2023 07:08:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53142 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229739AbjDJLID (ORCPT ); Mon, 10 Apr 2023 07:08:03 -0400 Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 67B6E30F0; Mon, 10 Apr 2023 04:08:01 -0700 (PDT) Received: by mail-pl1-x631.google.com with SMTP id ik20so4260981plb.3; Mon, 10 Apr 2023 04:08:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1681124880; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zGYltMygM2Avg7sOhC73hhQt4KoPWEHqx0AmFedwBwI=; b=kjqgIfK/yuNK3wgV3HdeL9NBcPafQXEb61GuA3Lf8BVJ0yHSaiaVZ72WEkAlJnk/L3 SbzxLNt/RCR7F20iBsCwgtsuPT4Muy1wP5aK5C3/lqx8YpANOj4ekTIzaXFCDM5rZ7wA ZmcvFk2m2QdHRfTQJHp8AXbCQQzDxfCPQBaZhyjFZAmN9spoa1hepHvtTUBdY3Efuctk n6zXBd/9dbCymrYL4ReDCAvfdSrB3DzMehPQZHsI8W6+uw1M6wx9/GGM1X8phE95YD2v j1af2GhvtTNdnJ3x5nc2Z7e9Wt8e/SNvJJpzb/0swNfK27Pd3nAKUZZ4LKq1sWdETRt7 NyQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681124880; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zGYltMygM2Avg7sOhC73hhQt4KoPWEHqx0AmFedwBwI=; b=YC/0dXOTKHId7lkk43iS+jktmUtv6B31GVHps1k29k6vtwI3CzsrgDs8kRxzdiCCJh V/tLhrvdf+mC0uddwZkbAQnKT9BcZg8Slv5A5ycvqhc3+Rh+NnmBwxhGFw++3dru/+Y6 AxQKXVOyZth0K/ZRqfuesPRHJc9kx2kuQKLwdClI4tNHHFXe10yy3B9WK4JFO2tCspCC 8v+vITz6m94EHjAoFCgX81vW3PH1sMbvr9rogXEwfhrqIlHChhXS7tTAO9etYmyg8V/9 0LklD8Dq+iXkEhwWaTnAVRsFeZln6yHFN5wVuE/9bceY50vCA5lu9vW9THeS+qU61+xA 1GEg== X-Gm-Message-State: AAQBX9cHkydulAR4K2Yz6qD5PUs/QJlwq0KIO4UDcEFxmjqExZQN/I1s d6ppb+YewhQqdSURCm1vy9wp187eWRsoxxwT91A= X-Received: by 2002:a17:902:f947:b0:1a1:ca37:5257 with SMTP id kx7-20020a170902f94700b001a1ca375257mr8343304plb.7.1681124880512; Mon, 10 Apr 2023 04:08:00 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.213.201]) by smtp.gmail.com with ESMTPSA id r5-20020a170902be0500b001a076568da9sm7464728pls.216.2023.04.10.04.07.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 04:08:00 -0700 (PDT) From: David Yang To: linux-clk@vger.kernel.org Cc: David Yang , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org Subject: [PATCH v3 01/14] clk: hisilicon: Add helper functions for platform driver Date: Mon, 10 Apr 2023 19:07:13 +0800 Message-Id: <20230410110733.192151-2-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230410110733.192151-1-mmyangfl@gmail.com> References: <20230410110733.192151-1-mmyangfl@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762788877557614933?= X-GMAIL-MSGID: =?utf-8?q?1762788877557614933?= Helper functions extract common operations on platform drivers. During migration to devm APIs, (virtual) fixed clocks were found hard on devm APIs, since they often depended by crucial peripherals, thus require early initialization before device probing, and cannot use devm APIs. One solution to this problem is to add a "fixed-clock" node to device tree, independent to clock device, and make those peripherals depend on that. However, there is also some devices that do use fixed clocks provided by drivers, for example clk-hi3660.c . To simplify codes, we migrate clocks of other types to devm APIs, while keep fixed clocks self-managed, alongside with struct hisi_clock_data, and remove devm-managed hisi_clock_data. `hisi_clk_alloc` will be removed in the following patch. Signed-off-by: David Yang --- drivers/clk/hisilicon/clk.c | 156 ++++++++++++++++++++++++++++++++++ drivers/clk/hisilicon/clk.h | 45 ++++++++++ drivers/clk/hisilicon/crg.h | 5 ++ drivers/clk/hisilicon/reset.c | 43 ++++++++++ 4 files changed, 249 insertions(+) diff --git a/drivers/clk/hisilicon/clk.c b/drivers/clk/hisilicon/clk.c index 54d9fdc93599..cb4444bba2c0 100644 --- a/drivers/clk/hisilicon/clk.c +++ b/drivers/clk/hisilicon/clk.c @@ -88,6 +88,25 @@ struct hisi_clock_data *hisi_clk_init(struct device_node *np, } EXPORT_SYMBOL_GPL(hisi_clk_init); +void hisi_clk_free(struct device_node *np, struct hisi_clock_data *data) +{ + if (data->clks) { + if (data->clks->fixed_rate_clks_num) + hisi_clk_unregister_fixed_rate(data->clks->fixed_rate_clks, + data->clks->fixed_rate_clks_num, + data); + if (data->clks->fixed_factor_clks_num) + hisi_clk_unregister_fixed_factor(data->clks->fixed_factor_clks, + data->clks->fixed_factor_clks_num, + data); + } + + of_clk_del_provider(np); + kfree(data->clk_data.clks); + kfree(data); +} +EXPORT_SYMBOL_GPL(hisi_clk_free); + int hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *clks, int nums, struct hisi_clock_data *data) { @@ -341,3 +360,140 @@ void __init hi6220_clk_register_divider(const struct hi6220_divider_clock *clks, data->clk_data.clks[clks[i].id] = clk; } } + +int hisi_clk_register(struct device *dev, const struct hisi_clocks *clks, + struct hisi_clock_data *data) +{ + int ret; + + if (clks->mux_clks_num) { + ret = hisi_clk_register_mux(clks->mux_clks, + clks->mux_clks_num, data); + if (ret) + return ret; + } + + if (clks->phase_clks_num) { + ret = hisi_clk_register_phase(dev, clks->phase_clks, + clks->phase_clks_num, data); + if (ret) + return ret; + } + + if (clks->divider_clks_num) { + ret = hisi_clk_register_divider(clks->divider_clks, + clks->divider_clks_num, data); + if (ret) + return ret; + } + + if (clks->gate_clks_num) { + ret = hisi_clk_register_gate(clks->gate_clks, + clks->gate_clks_num, data); + if (ret) + return ret; + } + + if (clks->gate_sep_clks_num) { + hisi_clk_register_gate_sep(clks->gate_sep_clks, + clks->gate_sep_clks_num, data); + } + + if (clks->clk_register_customized && clks->customized_clks_num) { + ret = clks->clk_register_customized(dev, clks->customized_clks, + clks->customized_clks_num, data); + if (ret) + return ret; + } + + return 0; +} +EXPORT_SYMBOL_GPL(hisi_clk_register); + +static size_t hisi_clocks_get_nr(const struct hisi_clocks *clks) +{ + return clks->fixed_rate_clks_num + clks->fixed_factor_clks_num + + clks->mux_clks_num + clks->phase_clks_num + + clks->divider_clks_num + clks->gate_clks_num + + clks->gate_sep_clks_num + clks->customized_clks_num; +} + +int hisi_clk_early_init(struct device_node *np, const struct hisi_clocks *clks) +{ + struct hisi_clock_data *data; + int ret; + + data = hisi_clk_init(np, hisi_clocks_get_nr(clks)); + if (!data) + return -ENOMEM; + data->clks = clks; + + ret = hisi_clk_register_fixed_rate(clks->fixed_rate_clks, + clks->fixed_rate_clks_num, data); + if (ret) + goto err; + + ret = hisi_clk_register_fixed_factor(clks->fixed_factor_clks, + clks->fixed_factor_clks_num, data); + if (ret) + goto err; + + np->data = data; + return 0; + +err: + hisi_clk_free(np, data); + return ret; +} +EXPORT_SYMBOL_GPL(hisi_clk_early_init); + +int hisi_clk_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + const struct hisi_clocks *clks; + struct hisi_clock_data *data; + int ret; + + clks = of_device_get_match_data(dev); + if (!clks) + return -ENOENT; + + if (!np->data) { + ret = hisi_clk_early_init(np, clks); + if (ret) + return ret; + } + + data = np->data; + np->data = NULL; + + if (clks->prologue) { + ret = clks->prologue(dev, data); + if (ret) + goto err; + } + + ret = hisi_clk_register(dev, clks, data); + if (ret) + goto err; + + platform_set_drvdata(pdev, data); + return 0; + +err: + hisi_clk_free(np, data); + return ret; +} +EXPORT_SYMBOL_GPL(hisi_clk_probe); + +int hisi_clk_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct hisi_clock_data *data = platform_get_drvdata(pdev); + + hisi_clk_free(np, data); + return 0; +} +EXPORT_SYMBOL_GPL(hisi_clk_remove); diff --git a/drivers/clk/hisilicon/clk.h b/drivers/clk/hisilicon/clk.h index 7a9b42e1b027..c373d7c14ed5 100644 --- a/drivers/clk/hisilicon/clk.h +++ b/drivers/clk/hisilicon/clk.h @@ -17,10 +17,12 @@ #include struct platform_device; +struct hisi_clocks; struct hisi_clock_data { struct clk_onecell_data clk_data; void __iomem *base; + const struct hisi_clocks *clks; }; struct hisi_fixed_rate_clock { @@ -103,6 +105,39 @@ struct hisi_gate_clock { const char *alias; }; +struct hisi_clocks { + /* if 0, sum all *_num */ + size_t nr; + + int (*prologue)(struct device *dev, struct hisi_clock_data *data); + + const struct hisi_fixed_rate_clock *fixed_rate_clks; + size_t fixed_rate_clks_num; + + const struct hisi_fixed_factor_clock *fixed_factor_clks; + size_t fixed_factor_clks_num; + + const struct hisi_mux_clock *mux_clks; + size_t mux_clks_num; + + const struct hisi_phase_clock *phase_clks; + size_t phase_clks_num; + + const struct hisi_divider_clock *divider_clks; + size_t divider_clks_num; + + const struct hisi_gate_clock *gate_clks; + size_t gate_clks_num; + + const struct hisi_gate_clock *gate_sep_clks; + size_t gate_sep_clks_num; + + const void *customized_clks; + size_t customized_clks_num; + int (*clk_register_customized)(struct device *dev, const void *clks, + size_t num, struct hisi_clock_data *data); +}; + struct clk *hisi_register_clkgate_sep(struct device *, const char *, const char *, unsigned long, void __iomem *, u8, @@ -113,6 +148,7 @@ struct clk *hi6220_register_clkdiv(struct device *dev, const char *name, struct hisi_clock_data *hisi_clk_alloc(struct platform_device *, int); struct hisi_clock_data *hisi_clk_init(struct device_node *, int); +void hisi_clk_free(struct device_node *np, struct hisi_clock_data *data); int hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *, int, struct hisi_clock_data *); int hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *, @@ -134,6 +170,15 @@ void hisi_clk_register_gate_sep(const struct hisi_gate_clock *, void hi6220_clk_register_divider(const struct hi6220_divider_clock *, int, struct hisi_clock_data *); +int hisi_clk_register(struct device *dev, const struct hisi_clocks *clks, + struct hisi_clock_data *data); + +/* helper functions for platform driver */ + +int hisi_clk_early_init(struct device_node *np, const struct hisi_clocks *clks); +int hisi_clk_probe(struct platform_device *pdev); +int hisi_clk_remove(struct platform_device *pdev); + #define hisi_clk_unregister(type) \ static inline \ void hisi_clk_unregister_##type(const struct hisi_##type##_clock *clks, \ diff --git a/drivers/clk/hisilicon/crg.h b/drivers/clk/hisilicon/crg.h index 803f6ba6d7a2..d9544f1f2625 100644 --- a/drivers/clk/hisilicon/crg.h +++ b/drivers/clk/hisilicon/crg.h @@ -22,4 +22,9 @@ struct hisi_crg_dev { const struct hisi_crg_funcs *funcs; }; +/* helper functions for platform driver */ + +int hisi_crg_probe(struct platform_device *pdev); +int hisi_crg_remove(struct platform_device *pdev); + #endif /* __HISI_CRG_H */ diff --git a/drivers/clk/hisilicon/reset.c b/drivers/clk/hisilicon/reset.c index 93cee17db8b1..19918cd717fd 100644 --- a/drivers/clk/hisilicon/reset.c +++ b/drivers/clk/hisilicon/reset.c @@ -6,11 +6,15 @@ */ #include +#include #include #include #include #include #include + +#include "clk.h" +#include "crg.h" #include "reset.h" #define HISI_RESET_BIT_MASK 0x1f @@ -116,3 +120,42 @@ void hisi_reset_exit(struct hisi_reset_controller *rstc) reset_controller_unregister(&rstc->rcdev); } EXPORT_SYMBOL_GPL(hisi_reset_exit); + +int hisi_crg_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct hisi_crg_dev *crg; + int ret; + + crg = devm_kmalloc(dev, sizeof(*crg), GFP_KERNEL); + if (!crg) + return -ENOMEM; + + ret = hisi_clk_probe(pdev); + if (ret) + return ret; + + crg->rstc = hisi_reset_init(pdev); + if (!crg->rstc) { + ret = -ENOMEM; + goto err; + } + + platform_set_drvdata(pdev, crg); + return 0; + +err: + hisi_clk_remove(pdev); + return ret; +} +EXPORT_SYMBOL_GPL(hisi_crg_probe); + +int hisi_crg_remove(struct platform_device *pdev) +{ + struct hisi_crg_dev *crg = platform_get_drvdata(pdev); + + hisi_reset_exit(crg->rstc); + hisi_clk_remove(pdev); + return 0; +} +EXPORT_SYMBOL_GPL(hisi_crg_remove); From patchwork Mon Apr 10 11:07:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yangfl X-Patchwork-Id: 81477 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1832362vqo; Mon, 10 Apr 2023 04:38:13 -0700 (PDT) X-Google-Smtp-Source: AKy350Z7hdBDAxP/nWnaCKhc5z0Y/COrRlXuPjrsJhHl/rzsRl8TNwKGJVhA4tpAjVyiRygGb5eM X-Received: by 2002:a50:fb87:0:b0:501:d532:d84e with SMTP id e7-20020a50fb87000000b00501d532d84emr8249791edq.39.1681126692835; Mon, 10 Apr 2023 04:38:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681126692; cv=none; d=google.com; s=arc-20160816; b=nGKDm8XIIGy1mzSUYORIPuo3dJ4gkbU7JZij8z6h2sSlnHd609P+bj6kXysR2ieh0m NKbJfsLAbQdwj3AQBj3L15th1UNsvr2A65SlrdwayvdFfCiDTey5tuED4rfXBQtPeOTv TylIio1EgbQwCghm7MMsuTAVWkHsQfLaylJDWEhLNoj8puoLKcREw6o0XNR5pRUpEziP XVZifnAsh6eIFREG6HrObBWXByJ6oKJ1cgD3HAr3fqEmrP5UOVEtrI9PQf6oqhZICxJs M81xe336I4cjhzjTQAVbQWe3AseoOiNRy4yTBdD7BVKRLJ10KizttLY3weSD/eX8RmY9 up+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=auWwFgc18uZBdz+Z2zX6VHvbovXO8Ck0I+nsGAMXZ1g=; b=dDU5CrAdEL+zXjn7yw+KibH7wx1Vu47/lOXIBEdHo02GEqwsWdTftV8086kLEg5Gvz cZEYugHDw3eUnswNrFgSYVarg0MgsDWwvkLoYqMLdq97hk2KbVcPOLBgf4jUoZ7mfXSx 5/Pa6Lzf2KRv7EUCDDnsQidwZCCc5hBBo9Ot+7s2hoQgxArFqkYXMVkvGKsNSjWeZK0W KRvPNIEZ/MvWeDSK+ATFNFta2klHowtBZabmgvqtHLkaDgzeOrohaRe3dljdBNV5DEx0 Oq7mKLVhJoH5PU9EqIcrij3sdlfsNQAV+JDI3gPNbE9BdVoFLawRP9WvcKYWEvKQgR+f 44+A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=Yj8yUmMA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id k25-20020a056402049900b005047d014eb9si6806266edv.413.2023.04.10.04.37.49; Mon, 10 Apr 2023 04:38:12 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=Yj8yUmMA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229745AbjDJLIS (ORCPT + 99 others); Mon, 10 Apr 2023 07:08:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53402 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229774AbjDJLIN (ORCPT ); Mon, 10 Apr 2023 07:08:13 -0400 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8D4705245; Mon, 10 Apr 2023 04:08:12 -0700 (PDT) Received: by mail-pj1-x102c.google.com with SMTP id px4so1659735pjb.3; Mon, 10 Apr 2023 04:08:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1681124892; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=auWwFgc18uZBdz+Z2zX6VHvbovXO8Ck0I+nsGAMXZ1g=; b=Yj8yUmMA8uZz52Ph8klP9yERACCTGTeiLp0Ngyfi3DHkq+/Ga71UgBP+R5r7dG8zcw U0VE07wJ9Y6NvMN0XtMPjSlwKo9VuklZjXpPS8/c6rarEhoBKGKNZSgIB46PKK2r7SON 94BibRq9nYpEhZeAtfOrJJ8BBcuhjb/AKs0S2lk48JCo6yTNTyKtxO/D7+QL67JoXvXq DIipz7m7njKGcn3IbHJOVpRfQdAMUT0e380Owkskw79av+Q8oJUmf0YnAAaFgKSzjF5g uTKwNzWrDSqk3qWZQi2DOuv6FIAP///sMZywLU65H1t/y5AKIzr4U/bpAK8aTGOTyme0 TBcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681124892; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=auWwFgc18uZBdz+Z2zX6VHvbovXO8Ck0I+nsGAMXZ1g=; b=PI4adJbUWqlIpJekv/NlUL+jl+sJlqeGK13M3MZ6FqcEWHQjuzlI0Tx8tcqfkciW6n +3FE1pjG+RszNcxgHIEDJ/OqP5V1GmhTSRTN/RtWHuM2n4QWVNZvl7oqvG4jJ3YwgX7C 3y7neslvQKeBM0BnJnKwCnUZhIxoAI5Ks+LDZgglN189BkgzPZuicxr6WnlIgD6NmAko xFW23Ud4XSANj4iHBTe6wHNxpPwi5r+nuaGIM04sBWcmY0b9C4y951wKmoaPjEAiLsRW SJ7eb172hdItyK/smDBSs7GSFS+ZElIgyDUcq8OAzQ8pqOz4KpOLTX+AHBdRnW3bRDbO aByA== X-Gm-Message-State: AAQBX9dhM3ROotzsaMyGKQMrJTQYoWm5jP2Q50bU7pKpnCkqASovFrhV rVPuQJWsTeWsi1BIyAqMN8/6+Hh3wqOOb8AWntc= X-Received: by 2002:a17:90b:3803:b0:23d:3931:7b49 with SMTP id mq3-20020a17090b380300b0023d39317b49mr12598238pjb.35.1681124891706; Mon, 10 Apr 2023 04:08:11 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.213.201]) by smtp.gmail.com with ESMTPSA id r5-20020a170902be0500b001a076568da9sm7464728pls.216.2023.04.10.04.08.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 04:08:11 -0700 (PDT) From: David Yang To: linux-clk@vger.kernel.org Cc: David Yang , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org Subject: [PATCH v3 02/14] clk: hisilicon: Rename hisi_clk_unregister macro Date: Mon, 10 Apr 2023 19:07:14 +0800 Message-Id: <20230410110733.192151-3-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230410110733.192151-1-mmyangfl@gmail.com> References: <20230410110733.192151-1-mmyangfl@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762789102589502349?= X-GMAIL-MSGID: =?utf-8?q?1762789102589502349?= hisi_clk_unregister is not a function corresponding to hisi_clk_register, rename it to avoid misunderstanding. Signed-off-by: David Yang --- drivers/clk/hisilicon/clk.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/clk/hisilicon/clk.h b/drivers/clk/hisilicon/clk.h index c373d7c14ed5..cc580915d058 100644 --- a/drivers/clk/hisilicon/clk.h +++ b/drivers/clk/hisilicon/clk.h @@ -179,7 +179,7 @@ int hisi_clk_early_init(struct device_node *np, const struct hisi_clocks *clks); int hisi_clk_probe(struct platform_device *pdev); int hisi_clk_remove(struct platform_device *pdev); -#define hisi_clk_unregister(type) \ +#define hisi_clk_unregister_fn(type) \ static inline \ void hisi_clk_unregister_##type(const struct hisi_##type##_clock *clks, \ int nums, struct hisi_clock_data *data) \ @@ -193,10 +193,10 @@ void hisi_clk_unregister_##type(const struct hisi_##type##_clock *clks, \ } \ } -hisi_clk_unregister(fixed_rate) -hisi_clk_unregister(fixed_factor) -hisi_clk_unregister(mux) -hisi_clk_unregister(divider) -hisi_clk_unregister(gate) +hisi_clk_unregister_fn(fixed_rate) +hisi_clk_unregister_fn(fixed_factor) +hisi_clk_unregister_fn(mux) +hisi_clk_unregister_fn(divider) +hisi_clk_unregister_fn(gate) #endif /* __HISI_CLK_H */ From patchwork Mon Apr 10 11:07:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yangfl X-Patchwork-Id: 81472 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1820458vqo; Mon, 10 Apr 2023 04:14:30 -0700 (PDT) X-Google-Smtp-Source: AKy350Y4hawd1i/M2B4pO82YrgGd9PUGNFgpvdsacqmofHmIKmcp4z6Eyni5vryOkBxoKs90ogDD X-Received: by 2002:a17:903:1104:b0:19e:5cc3:828f with SMTP id n4-20020a170903110400b0019e5cc3828fmr14099959plh.27.1681125270263; Mon, 10 Apr 2023 04:14:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681125270; cv=none; d=google.com; s=arc-20160816; b=0NLD9zqsFmq8rYDGcnZjL6yOjyEXujYZ+AEPrcUe8afPgYPEVOoxxST/Ls2QKYvQbM eRcbHAM6mkTTBPzZVrGszPkv/CetQjAhx7NzxIUBxAxSWW7vrrv0P1/UzvzmnHM3etzM Ah68F0Ybmkx1iAqGjWkHgRy5OJ7CKeaNwOu5r0Ji/ppppHMoYz9VN29MfWqZGI9BOg8u 1YG8DYbD3gu9zlOyCEXVknehR5gVAPzCq7B8IyEJRSxz4AYdun5YWZ7720PkXSUZ9FDM l7cleeAjF+Rpv/omcqlKR6EbeVWd2MGv6mjbhqFOKQvY14vzfQgxw9Y2W8VWX8iwRW/N WWGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=qylkhsUJrqz1P65jb9ADOri9NgFbnTH2A9zHw9WW0qY=; b=RjB9KMBzwTAPuC5XZF8TnpyCTJgPj5noleF89ul1a7c2XjBN0ix0ixhTB4X2V6yEwC XoDIn5X7cT9WDYucsMQSkUirrz6OQliyQ6ZPe0bT9xkatuTkJlK8RuBnDQrmuE9Na5n7 VVvCNTIthF8zs4qB7pYj4/+3eNKFya2LjcMB2V0QvsCxlKyUZvOts+KBmtKUh1WtY0Ti w+2YzaLK/sAQoigIRSOSpHFWsWbKdQX0YR9eA7zgTurBNOlFqjKFtXHI2a82L5rawr6S 63BQdZKvfdVpGpj+xHUcpvWwIxMyU5TUOLfymjHcta5tlKkHFPqZaFWtHkE/ICv0YlQI XdVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b="IEu/n8H7"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id k6-20020a170902c40600b001a1abc91952si11811087plk.194.2023.04.10.04.14.18; Mon, 10 Apr 2023 04:14:30 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b="IEu/n8H7"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229771AbjDJLIg (ORCPT + 99 others); Mon, 10 Apr 2023 07:08:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54138 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229624AbjDJLIe (ORCPT ); Mon, 10 Apr 2023 07:08:34 -0400 Received: from mail-pj1-x1036.google.com (mail-pj1-x1036.google.com [IPv6:2607:f8b0:4864:20::1036]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 650FF5252; Mon, 10 Apr 2023 04:08:25 -0700 (PDT) Received: by mail-pj1-x1036.google.com with SMTP id v9so9169168pjk.0; Mon, 10 Apr 2023 04:08:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1681124905; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qylkhsUJrqz1P65jb9ADOri9NgFbnTH2A9zHw9WW0qY=; b=IEu/n8H7hxAYx7i2FmQBmYLYSnagatlbmV9kCWZ5ubRDIdgyU1qKL/S4HO9Ypv1eU1 HhRFWlfYbCWG0xSx929G3gAPNArRJaCdcYykzmgKlOi64G0CiiVl+8TcX07/zG65J6Lp SA42xwaxEorNnx4BSdi/zyMGY2+iVsb1j+EGugSyBjUF9RNnaqfuawSCytnWnrSNTa0v k7dFCCt7/SuGjVoXuJ06NDo/vUfUvHm0T3QamsAl3IeN4Q1STcVLm/3JavQSmEybwsBY w4pfqJkECYBP1rRBl8MYsFlMNvmgTUx8zl7dXAF7a97jCQ7iwhI4PgvtvbVCT11/cvuj htCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681124905; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qylkhsUJrqz1P65jb9ADOri9NgFbnTH2A9zHw9WW0qY=; b=SNn6yg2qT7KpzdBbRn+7b6zM0mOs+qhNyg2nzl5eSRghbrfHw/4yG7SMGHgzRoILPe oPu8G6kv/Y5sZjPPfISkJ/bEwxqWbQm+voIqcD2zWTTiCZIKi3NKO76ZgIz+IdXTr/Vn yfauFf8+CQy7ALSuqCbiAkMwR2eYC6ItcXxiIQiUUUW8HZpUrwR1CvYxIjhN8prdq2cw J7NdKLK4UFBK4n0oD/I7ru1QJ+wfBGKkeP6AUZZkmIzQkVtWp/5KBOqC7bdgiGFez87F fKvDvVf5tsYXm1TSvBUEO3Ta81BjX9TKhDLq60s1r5TjLAo20gc8gEJNNQ7TXyJBds9G 0ucw== X-Gm-Message-State: AAQBX9dxLh5n9nDspQ0Blpp7RCAFfRiA1K8BH1BFbYq8Erg9iDGpKV8R kH9JoiFqCtnbjVBgWqXyvL1Jwy5MAlmITT0pxlk= X-Received: by 2002:a17:90a:5e4d:b0:246:9439:3cb1 with SMTP id u13-20020a17090a5e4d00b0024694393cb1mr5545228pji.21.1681124904699; Mon, 10 Apr 2023 04:08:24 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.213.201]) by smtp.gmail.com with ESMTPSA id r5-20020a170902be0500b001a076568da9sm7464728pls.216.2023.04.10.04.08.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 04:08:24 -0700 (PDT) From: David Yang To: linux-clk@vger.kernel.org Cc: David Yang , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org Subject: [PATCH v3 03/14] clk: hisilicon: hi3516cv300: Use helper functions Date: Mon, 10 Apr 2023 19:07:15 +0800 Message-Id: <20230410110733.192151-4-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230410110733.192151-1-mmyangfl@gmail.com> References: <20230410110733.192151-1-mmyangfl@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762787611319566013?= X-GMAIL-MSGID: =?utf-8?q?1762787611319566013?= Use common helper functions and register clks with a single of_device_id data. Signed-off-by: David Yang --- drivers/clk/hisilicon/crg-hi3516cv300.c | 172 +++--------------------- 1 file changed, 17 insertions(+), 155 deletions(-) diff --git a/drivers/clk/hisilicon/crg-hi3516cv300.c b/drivers/clk/hisilicon/crg-hi3516cv300.c index 5d4e61c7a429..992b9c16ce7e 100644 --- a/drivers/clk/hisilicon/crg-hi3516cv300.c +++ b/drivers/clk/hisilicon/crg-hi3516cv300.c @@ -12,7 +12,6 @@ #include #include "clk.h" #include "crg.h" -#include "reset.h" /* hi3516CV300 core CRG */ #define HI3516CV300_INNER_CLK_OFFSET 64 @@ -126,67 +125,14 @@ static const struct hisi_gate_clock hi3516cv300_gate_clks[] = { { HI3516CV300_USB2_PHY_CLK, "clk_usb2_phy", NULL, 0, 0xb8, 7, 0, }, }; -static struct hisi_clock_data *hi3516cv300_clk_register( - struct platform_device *pdev) -{ - struct hisi_clock_data *clk_data; - int ret; - - clk_data = hisi_clk_alloc(pdev, HI3516CV300_CRG_NR_CLKS); - if (!clk_data) - return ERR_PTR(-ENOMEM); - - ret = hisi_clk_register_fixed_rate(hi3516cv300_fixed_rate_clks, - ARRAY_SIZE(hi3516cv300_fixed_rate_clks), clk_data); - if (ret) - return ERR_PTR(ret); - - ret = hisi_clk_register_mux(hi3516cv300_mux_clks, - ARRAY_SIZE(hi3516cv300_mux_clks), clk_data); - if (ret) - goto unregister_fixed_rate; - - ret = hisi_clk_register_gate(hi3516cv300_gate_clks, - ARRAY_SIZE(hi3516cv300_gate_clks), clk_data); - if (ret) - goto unregister_mux; - - ret = of_clk_add_provider(pdev->dev.of_node, - of_clk_src_onecell_get, &clk_data->clk_data); - if (ret) - goto unregister_gate; - - return clk_data; - -unregister_gate: - hisi_clk_unregister_gate(hi3516cv300_gate_clks, - ARRAY_SIZE(hi3516cv300_gate_clks), clk_data); -unregister_mux: - hisi_clk_unregister_mux(hi3516cv300_mux_clks, - ARRAY_SIZE(hi3516cv300_mux_clks), clk_data); -unregister_fixed_rate: - hisi_clk_unregister_fixed_rate(hi3516cv300_fixed_rate_clks, - ARRAY_SIZE(hi3516cv300_fixed_rate_clks), clk_data); - return ERR_PTR(ret); -} - -static void hi3516cv300_clk_unregister(struct platform_device *pdev) -{ - struct hisi_crg_dev *crg = platform_get_drvdata(pdev); - - of_clk_del_provider(pdev->dev.of_node); - - hisi_clk_unregister_gate(hi3516cv300_gate_clks, - ARRAY_SIZE(hi3516cv300_gate_clks), crg->clk_data); - hisi_clk_unregister_mux(hi3516cv300_mux_clks, - ARRAY_SIZE(hi3516cv300_mux_clks), crg->clk_data); - hisi_clk_unregister_fixed_rate(hi3516cv300_fixed_rate_clks, - ARRAY_SIZE(hi3516cv300_fixed_rate_clks), crg->clk_data); -} - -static const struct hisi_crg_funcs hi3516cv300_crg_funcs = { - .register_clks = hi3516cv300_clk_register, - .unregister_clks = hi3516cv300_clk_unregister, +static const struct hisi_clocks hi3516cv300_crg_clks = { + .nr = HI3516CV300_CRG_NR_CLKS, + .fixed_rate_clks = hi3516cv300_fixed_rate_clks, + .fixed_rate_clks_num = ARRAY_SIZE(hi3516cv300_fixed_rate_clks), + .mux_clks = hi3516cv300_mux_clks, + .mux_clks_num = ARRAY_SIZE(hi3516cv300_mux_clks), + .gate_clks = hi3516cv300_gate_clks, + .gate_clks_num = ARRAY_SIZE(hi3516cv300_gate_clks), }; /* hi3516CV300 sysctrl CRG */ @@ -200,119 +146,35 @@ static const struct hisi_mux_clock hi3516cv300_sysctrl_mux_clks[] = { CLK_SET_RATE_PARENT, 0x0, 23, 1, 0, wdt_mux_table, }, }; -static struct hisi_clock_data *hi3516cv300_sysctrl_clk_register( - struct platform_device *pdev) -{ - struct hisi_clock_data *clk_data; - int ret; - - clk_data = hisi_clk_alloc(pdev, HI3516CV300_SYSCTRL_NR_CLKS); - if (!clk_data) - return ERR_PTR(-ENOMEM); - - ret = hisi_clk_register_mux(hi3516cv300_sysctrl_mux_clks, - ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks), clk_data); - if (ret) - return ERR_PTR(ret); - - - ret = of_clk_add_provider(pdev->dev.of_node, - of_clk_src_onecell_get, &clk_data->clk_data); - if (ret) - goto unregister_mux; - - return clk_data; - -unregister_mux: - hisi_clk_unregister_mux(hi3516cv300_sysctrl_mux_clks, - ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks), clk_data); - return ERR_PTR(ret); -} - -static void hi3516cv300_sysctrl_clk_unregister(struct platform_device *pdev) -{ - struct hisi_crg_dev *crg = platform_get_drvdata(pdev); - - of_clk_del_provider(pdev->dev.of_node); - - hisi_clk_unregister_mux(hi3516cv300_sysctrl_mux_clks, - ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks), - crg->clk_data); -} - -static const struct hisi_crg_funcs hi3516cv300_sysctrl_funcs = { - .register_clks = hi3516cv300_sysctrl_clk_register, - .unregister_clks = hi3516cv300_sysctrl_clk_unregister, +static const struct hisi_clocks hi3516cv300_sysctrl_clks = { + .nr = HI3516CV300_SYSCTRL_NR_CLKS, + .mux_clks = hi3516cv300_sysctrl_mux_clks, + .mux_clks_num = ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks), }; static const struct of_device_id hi3516cv300_crg_match_table[] = { { .compatible = "hisilicon,hi3516cv300-crg", - .data = &hi3516cv300_crg_funcs + .data = &hi3516cv300_crg_clks, }, { .compatible = "hisilicon,hi3516cv300-sysctrl", - .data = &hi3516cv300_sysctrl_funcs + .data = &hi3516cv300_sysctrl_clks, }, { } }; MODULE_DEVICE_TABLE(of, hi3516cv300_crg_match_table); -static int hi3516cv300_crg_probe(struct platform_device *pdev) -{ - struct hisi_crg_dev *crg; - - crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL); - if (!crg) - return -ENOMEM; - - crg->funcs = of_device_get_match_data(&pdev->dev); - if (!crg->funcs) - return -ENOENT; - - crg->rstc = hisi_reset_init(pdev); - if (!crg->rstc) - return -ENOMEM; - - crg->clk_data = crg->funcs->register_clks(pdev); - if (IS_ERR(crg->clk_data)) { - hisi_reset_exit(crg->rstc); - return PTR_ERR(crg->clk_data); - } - - platform_set_drvdata(pdev, crg); - return 0; -} - -static int hi3516cv300_crg_remove(struct platform_device *pdev) -{ - struct hisi_crg_dev *crg = platform_get_drvdata(pdev); - - hisi_reset_exit(crg->rstc); - crg->funcs->unregister_clks(pdev); - return 0; -} - static struct platform_driver hi3516cv300_crg_driver = { - .probe = hi3516cv300_crg_probe, - .remove = hi3516cv300_crg_remove, + .probe = hisi_crg_probe, + .remove = hisi_crg_remove, .driver = { .name = "hi3516cv300-crg", .of_match_table = hi3516cv300_crg_match_table, }, }; -static int __init hi3516cv300_crg_init(void) -{ - return platform_driver_register(&hi3516cv300_crg_driver); -} -core_initcall(hi3516cv300_crg_init); - -static void __exit hi3516cv300_crg_exit(void) -{ - platform_driver_unregister(&hi3516cv300_crg_driver); -} -module_exit(hi3516cv300_crg_exit); +module_platform_driver(hi3516cv300_crg_driver); MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("HiSilicon Hi3516CV300 CRG Driver"); From patchwork Mon Apr 10 11:07:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yangfl X-Patchwork-Id: 81468 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1818540vqo; Mon, 10 Apr 2023 04:10:46 -0700 (PDT) X-Google-Smtp-Source: AKy350Z7r2HvXOq+eBpo0nivefjB+PeS7cRqlx1CIuMWdtH1g5If7sA6Xs4kAoER06Sjiaul+5jT X-Received: by 2002:aa7:9821:0:b0:627:e701:8ca9 with SMTP id q1-20020aa79821000000b00627e7018ca9mr10856323pfl.2.1681125045967; Mon, 10 Apr 2023 04:10:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681125045; cv=none; d=google.com; s=arc-20160816; b=D4MJzA8TabMl8anZ3gac5MIlfLuQ2KrKfPykmP99YDVHLAOMjYZhDzGv3BizSMe4KZ 3aNe49+8KUPf8tTs1aVpuHbCGdqWsvG4W+KdWqoKfsEIwkEnnNu6W1EXYDDux+8LCdC+ u2Hh6zVDVTky5A35P+vkcKFLA1IraEBAUE6DjiJcBgJ9RTO6g1LpnxlYuku5wbH1Xh6L oapgMsIKPdgrDkqAc13RJwGFeW8dMtIeWCXgxsWA7Lab9uy3IG23wcKGgIX72CiH/QKy MBUSbVO8BuabVSRmpXNN3ikGd2vLRnHEkEgu1T+I231cgMiVqnRgE62h8kvvCCBe9RXj HJLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ZWyQ5Pjpw8KX3nyQXwtTt+inCkDHJTaq2DC+SwS9XK8=; b=b0JI1SBJSc63ZW0vBUt1dDE1Ar7/ct60mjdbXmWFK0+tisT3pw8/wHaGE0mDAmaCcs BU1beTqLDScBv3QLBKozn2raQlJZ/V6iwGLHzP1+l8Ia86KDtWF4yDt0oLzu0MZOcMJ1 3laHoLnB/sTjrazpBcHgxKdJoJpJR9qqyFwaNtNBOzugOgWjQ3VV2QnWnJqaLJFVxy3c rYVWVY4N5q6sRNCQAbLLGqevWX3ZrYvpjJXxoJddLrT9QAmfNMHlk389V5vQ2gFxTW5b k0foP1HuZVg945KE1P3oCYlctitxup4z3mdqcfDWsHgoC9m8VIOoCmLCmeuqnCkQum12 xgWQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b="F41/cBOa"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id r24-20020a63ce58000000b00513b3372e2csi10184501pgi.586.2023.04.10.04.10.33; Mon, 10 Apr 2023 04:10:45 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b="F41/cBOa"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229585AbjDJLIt (ORCPT + 99 others); Mon, 10 Apr 2023 07:08:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54584 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229776AbjDJLIr (ORCPT ); Mon, 10 Apr 2023 07:08:47 -0400 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 85A5D5247; Mon, 10 Apr 2023 04:08:38 -0700 (PDT) Received: by mail-pj1-x102c.google.com with SMTP id bp17-20020a17090b0c1100b0023f187954acso4137028pjb.2; Mon, 10 Apr 2023 04:08:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1681124918; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZWyQ5Pjpw8KX3nyQXwtTt+inCkDHJTaq2DC+SwS9XK8=; b=F41/cBOahuvvd/fGLSqfquMTyeimw4QF5oHc/80R6SmoXpfT+0pd91MKbBlbwsoNWc KkBaNhY7D4ealZ60ylLnrq2d9zb8QLcTC0AsJMnQsg0f314V/LXMYXFiq5x9r5XIeXvU s7c1Kz8XzQ1a3KFTQ+iWs2saJyxYVdPNcj2Qf//A8tDQaVhbqes77N13zrVFOFDm9XXm o6UnkMu22p6A3OK4MdZKyKoc7qlM9kVys8crZ2+P5KjcxDKiJZI+U3jE/njEaCzxFguc 0u7BCEIifdkyBcgiaQ5dtjwinzDvjFJpK9cfL87l3S8XQv2C3oPjKDRw/z1Idnk0+Jlt BKuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681124918; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZWyQ5Pjpw8KX3nyQXwtTt+inCkDHJTaq2DC+SwS9XK8=; b=zK62GL264/VUazV7reA+OZIYd6IaAoPB1+za0cwtOc1Kln3nvLC6xkGhlc+ZV6SPXp slclQOr+ulxuO03HNH9qUMf76/E4CAeQnO3oOs0aTc2ozL20X+Qs8WytqXIWBjkSFn+H YS2TMfmquqiGdPMfC1aEo0S7B0v5tUI7KgE/8hBgesZ0HZKWtM13FelMwxWbgHhXckTh G7gIZaXP1EGOySVfoE6I2tfn2VnRMuTjnnj60WScT8S9UNMpxvleUEcBupPhvue02BEE IrSIe41amTTCSJJ+jlhTT5P7Xvaa6sdcI3GVuFXhgAe+tt0za9Hqn1QnDYlBK4vClE2n nX+A== X-Gm-Message-State: AAQBX9dJpwe85inzQOhkDV5duzmDpmNoM1lSXG+D51C46CLeJJiGE4BY n35aMM/aHecbuJ/Wvy+UpRfi7bBSVkXTMp/l+YA= X-Received: by 2002:a17:903:1c3:b0:19e:bc01:610e with SMTP id e3-20020a17090301c300b0019ebc01610emr14511838plh.33.1681124917790; Mon, 10 Apr 2023 04:08:37 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.213.201]) by smtp.gmail.com with ESMTPSA id r5-20020a170902be0500b001a076568da9sm7464728pls.216.2023.04.10.04.08.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 04:08:37 -0700 (PDT) From: David Yang To: linux-clk@vger.kernel.org Cc: David Yang , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org Subject: [PATCH v3 04/14] clk: hisilicon: hi3798cv200: Use helper functions Date: Mon, 10 Apr 2023 19:07:16 +0800 Message-Id: <20230410110733.192151-5-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230410110733.192151-1-mmyangfl@gmail.com> References: <20230410110733.192151-1-mmyangfl@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762787376392370351?= X-GMAIL-MSGID: =?utf-8?q?1762787376392370351?= Use common helper functions and register clks with a single of_device_id data. Signed-off-by: David Yang --- drivers/clk/hisilicon/crg-hi3798cv200.c | 201 +++--------------------- 1 file changed, 22 insertions(+), 179 deletions(-) diff --git a/drivers/clk/hisilicon/crg-hi3798cv200.c b/drivers/clk/hisilicon/crg-hi3798cv200.c index 08a19ba776e6..cf0944774ae9 100644 --- a/drivers/clk/hisilicon/crg-hi3798cv200.c +++ b/drivers/clk/hisilicon/crg-hi3798cv200.c @@ -12,7 +12,6 @@ #include #include "clk.h" #include "crg.h" -#include "reset.h" /* hi3798CV200 core CRG */ #define HI3798CV200_INNER_CLK_OFFSET 64 @@ -41,6 +40,7 @@ #define HI3798CV200_CRG_NR_CLKS 128 +#define HI3798CV200_SYSCTRL_NR_CLKS 16 static const struct hisi_fixed_rate_clock hi3798cv200_fixed_rate_clks[] = { { HISTB_OSC_CLK, "clk_osc", NULL, 0, 24000000, }, { HISTB_APB_CLK, "clk_apb", NULL, 0, 100000000, }, @@ -193,90 +193,18 @@ static const struct hisi_gate_clock hi3798cv200_gate_clks[] = { CLK_SET_RATE_PARENT, 0xb0, 18, 0 }, }; -static struct hisi_clock_data *hi3798cv200_clk_register( - struct platform_device *pdev) -{ - struct hisi_clock_data *clk_data; - int ret; - - clk_data = hisi_clk_alloc(pdev, HI3798CV200_CRG_NR_CLKS); - if (!clk_data) - return ERR_PTR(-ENOMEM); - - /* hisi_phase_clock is resource managed */ - ret = hisi_clk_register_phase(&pdev->dev, - hi3798cv200_phase_clks, - ARRAY_SIZE(hi3798cv200_phase_clks), - clk_data); - if (ret) - return ERR_PTR(ret); - - ret = hisi_clk_register_fixed_rate(hi3798cv200_fixed_rate_clks, - ARRAY_SIZE(hi3798cv200_fixed_rate_clks), - clk_data); - if (ret) - return ERR_PTR(ret); - - ret = hisi_clk_register_mux(hi3798cv200_mux_clks, - ARRAY_SIZE(hi3798cv200_mux_clks), - clk_data); - if (ret) - goto unregister_fixed_rate; - - ret = hisi_clk_register_gate(hi3798cv200_gate_clks, - ARRAY_SIZE(hi3798cv200_gate_clks), - clk_data); - if (ret) - goto unregister_mux; - - ret = of_clk_add_provider(pdev->dev.of_node, - of_clk_src_onecell_get, &clk_data->clk_data); - if (ret) - goto unregister_gate; - - return clk_data; - -unregister_gate: - hisi_clk_unregister_gate(hi3798cv200_gate_clks, - ARRAY_SIZE(hi3798cv200_gate_clks), - clk_data); -unregister_mux: - hisi_clk_unregister_mux(hi3798cv200_mux_clks, - ARRAY_SIZE(hi3798cv200_mux_clks), - clk_data); -unregister_fixed_rate: - hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks, - ARRAY_SIZE(hi3798cv200_fixed_rate_clks), - clk_data); - return ERR_PTR(ret); -} - -static void hi3798cv200_clk_unregister(struct platform_device *pdev) -{ - struct hisi_crg_dev *crg = platform_get_drvdata(pdev); - - of_clk_del_provider(pdev->dev.of_node); - - hisi_clk_unregister_gate(hi3798cv200_gate_clks, - ARRAY_SIZE(hi3798cv200_gate_clks), - crg->clk_data); - hisi_clk_unregister_mux(hi3798cv200_mux_clks, - ARRAY_SIZE(hi3798cv200_mux_clks), - crg->clk_data); - hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks, - ARRAY_SIZE(hi3798cv200_fixed_rate_clks), - crg->clk_data); -} - -static const struct hisi_crg_funcs hi3798cv200_crg_funcs = { - .register_clks = hi3798cv200_clk_register, - .unregister_clks = hi3798cv200_clk_unregister, +static const struct hisi_clocks hi3798cv200_crg_clks = { + .nr = HI3798CV200_CRG_NR_CLKS, + .fixed_rate_clks = hi3798cv200_fixed_rate_clks, + .fixed_rate_clks_num = ARRAY_SIZE(hi3798cv200_fixed_rate_clks), + .mux_clks = hi3798cv200_mux_clks, + .mux_clks_num = ARRAY_SIZE(hi3798cv200_mux_clks), + .phase_clks = hi3798cv200_phase_clks, + .phase_clks_num = ARRAY_SIZE(hi3798cv200_phase_clks), + .gate_clks = hi3798cv200_gate_clks, + .gate_clks_num = ARRAY_SIZE(hi3798cv200_gate_clks), }; -/* hi3798CV200 sysctrl CRG */ - -#define HI3798CV200_SYSCTRL_NR_CLKS 16 - static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = { { HISTB_IR_CLK, "clk_ir", "24m", CLK_SET_RATE_PARENT, 0x48, 4, 0, }, @@ -286,116 +214,31 @@ static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = { CLK_SET_RATE_PARENT, 0x48, 10, 0, }, }; -static struct hisi_clock_data *hi3798cv200_sysctrl_clk_register( - struct platform_device *pdev) -{ - struct hisi_clock_data *clk_data; - int ret; - - clk_data = hisi_clk_alloc(pdev, HI3798CV200_SYSCTRL_NR_CLKS); - if (!clk_data) - return ERR_PTR(-ENOMEM); - - ret = hisi_clk_register_gate(hi3798cv200_sysctrl_gate_clks, - ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks), - clk_data); - if (ret) - return ERR_PTR(ret); - - ret = of_clk_add_provider(pdev->dev.of_node, - of_clk_src_onecell_get, &clk_data->clk_data); - if (ret) - goto unregister_gate; - - return clk_data; - -unregister_gate: - hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks, - ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks), - clk_data); - return ERR_PTR(ret); -} - -static void hi3798cv200_sysctrl_clk_unregister(struct platform_device *pdev) -{ - struct hisi_crg_dev *crg = platform_get_drvdata(pdev); - - of_clk_del_provider(pdev->dev.of_node); - - hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks, - ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks), - crg->clk_data); -} - -static const struct hisi_crg_funcs hi3798cv200_sysctrl_funcs = { - .register_clks = hi3798cv200_sysctrl_clk_register, - .unregister_clks = hi3798cv200_sysctrl_clk_unregister, +static const struct hisi_clocks hi3798cv200_sysctrl_clks = { + .nr = HI3798CV200_SYSCTRL_NR_CLKS, + .gate_clks = hi3798cv200_sysctrl_gate_clks, + .gate_clks_num = ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks), }; static const struct of_device_id hi3798cv200_crg_match_table[] = { { .compatible = "hisilicon,hi3798cv200-crg", - .data = &hi3798cv200_crg_funcs }, + .data = &hi3798cv200_crg_clks }, { .compatible = "hisilicon,hi3798cv200-sysctrl", - .data = &hi3798cv200_sysctrl_funcs }, + .data = &hi3798cv200_sysctrl_clks }, { } }; MODULE_DEVICE_TABLE(of, hi3798cv200_crg_match_table); -static int hi3798cv200_crg_probe(struct platform_device *pdev) -{ - struct hisi_crg_dev *crg; - - crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL); - if (!crg) - return -ENOMEM; - - crg->funcs = of_device_get_match_data(&pdev->dev); - if (!crg->funcs) - return -ENOENT; - - crg->rstc = hisi_reset_init(pdev); - if (!crg->rstc) - return -ENOMEM; - - crg->clk_data = crg->funcs->register_clks(pdev); - if (IS_ERR(crg->clk_data)) { - hisi_reset_exit(crg->rstc); - return PTR_ERR(crg->clk_data); - } - - platform_set_drvdata(pdev, crg); - return 0; -} - -static int hi3798cv200_crg_remove(struct platform_device *pdev) -{ - struct hisi_crg_dev *crg = platform_get_drvdata(pdev); - - hisi_reset_exit(crg->rstc); - crg->funcs->unregister_clks(pdev); - return 0; -} - static struct platform_driver hi3798cv200_crg_driver = { - .probe = hi3798cv200_crg_probe, - .remove = hi3798cv200_crg_remove, - .driver = { - .name = "hi3798cv200-crg", + .probe = hisi_crg_probe, + .remove = hisi_crg_remove, + .driver = { + .name = "hi3798cv200-crg", .of_match_table = hi3798cv200_crg_match_table, }, }; -static int __init hi3798cv200_crg_init(void) -{ - return platform_driver_register(&hi3798cv200_crg_driver); -} -core_initcall(hi3798cv200_crg_init); - -static void __exit hi3798cv200_crg_exit(void) -{ - platform_driver_unregister(&hi3798cv200_crg_driver); -} -module_exit(hi3798cv200_crg_exit); +module_platform_driver(hi3798cv200_crg_driver); MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("HiSilicon Hi3798CV200 CRG Driver"); From patchwork Mon Apr 10 11:07:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yangfl X-Patchwork-Id: 81471 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1819623vqo; Mon, 10 Apr 2023 04:12:53 -0700 (PDT) X-Google-Smtp-Source: AKy350bj+9KHgfNTdpll0T4myXhJXsQgHmaPBIVk+jPuQmLQRFbxXqW37fW0i31Jg7a12iQSnnUW X-Received: by 2002:a17:902:e80c:b0:19f:2328:beee with SMTP id u12-20020a170902e80c00b0019f2328beeemr8765158plg.11.1681125172761; Mon, 10 Apr 2023 04:12:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681125172; cv=none; d=google.com; s=arc-20160816; b=GWQFyAe53W2wX9rXXuwZ1Qg27mCjDwtmdi445TVcxB3E9IO1ZeHDz2D53DO0kps751 0W2BQoBKLbyla7kMD72zMUZs27Y5gUUyfuk1lI+qfbHpzZEhF1lySKjrA5/XNafUb71l CK9jmq2/EIjURxU0wmGxMEaPWjwdfy14egO7W2r9CBS0zMkM3sGlMZiwrnWvhbtnpJZX bUxV5H4Y1LangTWKHVcTJqprK1e/SRIEJyr7FCu9kaTHX0F39xWD0U0DKWEk+G4sPcZe 6AuEvW5OYyvuTfznmuJ3FyXh+DSHK6OdJKYG4swzc7/V+B2mDuOcwFND1Ky78BJ73pAI JlNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Mm55R+I6Fh9QyLAsUWe4zvnL0s5hklOWhWWeIyefJts=; b=L0qqKJwvP7kMTmEvFtrzCSxsC/ebhfvEzrEKP7e+v9cEPbRBhyOlCU9dGQvO99V3YD /SqTlLkbmm/P37sZWcq4aNCmCXF3DxpafGAWsXrEjLPfldFt8S5s0YUAtQL3yla3sUNt T4I+E/Xb4vvOo+r9rN0GiXiR4K+Px1UaH39w4XH3ALG989HlcrV3g4H+tQJau1OMNKwQ 9RQGixf7y2XVap1FetZHNNBKHaAQPjs7v8y3hUomFDu46URCjcIFiuCQQ+aAj1hhUm10 H7DmtZcmPpPV0oS+zBfDn8NhIgNQO5dcQ0NwQOkAdF1Kvo/U47E0dNYUJn5dCzwibFNa 833A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=QZZwomqA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id f12-20020a170902f38c00b001a52bb7ef82si5084543ple.119.2023.04.10.04.12.40; Mon, 10 Apr 2023 04:12:52 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=QZZwomqA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229814AbjDJLJE (ORCPT + 99 others); Mon, 10 Apr 2023 07:09:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54888 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229739AbjDJLJB (ORCPT ); Mon, 10 Apr 2023 07:09:01 -0400 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB1C12D64; Mon, 10 Apr 2023 04:08:49 -0700 (PDT) Received: by mail-pj1-x1029.google.com with SMTP id jx2-20020a17090b46c200b002469a9ff94aso2399376pjb.3; Mon, 10 Apr 2023 04:08:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1681124929; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Mm55R+I6Fh9QyLAsUWe4zvnL0s5hklOWhWWeIyefJts=; b=QZZwomqAKqgPrLmHpiNCTDhpASuGXyGlV2gMesa5ET0pUu7XtMR5IFyi8Ptdy56juA SqRglU0cn053f6hO8ZXkPP/Hs2+UWSDS0Hdvnog+giVh2/5iEY0iOb7QXuCwLsHHvUGI vVFNguvZ7Bhy3h1pV0ndpMbcZYyCBumAblU3dYu46VVvcUcE8RdP8exx5ui9GjL949LL OtjDAfnSUkyc4xzhn4uescN8wW1ZWW7AV6SFWf2bAFjkPJejDji7OvseElBlvrgEgF/j QhhIt985WglWCVwmznMdplJYfNbTw8jgviyJj8SDkiBtdP3d7DltCKRg9gz2JsBz699X GL9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681124929; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Mm55R+I6Fh9QyLAsUWe4zvnL0s5hklOWhWWeIyefJts=; b=JwN36lSvwTZkoF+ffZv3Lg2VNIHFTvossZaD5s7AjTxRMka4l78MfopDJeB/6talTg sYsq5RlF3QrJf1UfhJLewwlYrYiwUxVAR60LX7IR6OO+QRw0AZsQ+O9WmMdt0AzC+tbs wwD4gG1vpd4ULHOP2muz5zgZ7UTT2bwzXgGkFESSYTnHKEAIJsRMVwiMH9S7VkH4GiCl F8xXlIBt708CirnJ+SzXdLLeoqRQGY87n9OtxOWPp8CpckYduv1db9ytZc8u4lQe4DOE XyC0zcJdy6HBfatcrxCGuK1LPdX/fHO09ODjraV+uNIqU1xBGFnJEDI1SG2Pss2owrcb 4YuA== X-Gm-Message-State: AAQBX9dY4YjasTk4p4Ul37QbCfykKUJBw09hnlrqa1HFoygvOcW66xz3 qpzRSIqfrF7zDA2EXCl4cxYy942oXZKzLyWH/2k= X-Received: by 2002:a17:90b:4ac5:b0:246:9374:febb with SMTP id mh5-20020a17090b4ac500b002469374febbmr5819566pjb.19.1681124929054; Mon, 10 Apr 2023 04:08:49 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.213.201]) by smtp.gmail.com with ESMTPSA id r5-20020a170902be0500b001a076568da9sm7464728pls.216.2023.04.10.04.08.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 04:08:48 -0700 (PDT) From: David Yang To: linux-clk@vger.kernel.org Cc: David Yang , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org Subject: [PATCH v3 05/14] clk: hisilicon: Remove hisi_crg_funcs Date: Mon, 10 Apr 2023 19:07:17 +0800 Message-Id: <20230410110733.192151-6-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230410110733.192151-1-mmyangfl@gmail.com> References: <20230410110733.192151-1-mmyangfl@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762787509166104301?= X-GMAIL-MSGID: =?utf-8?q?1762787509166104301?= After refactor, no one use hisi_crg_funcs. Signed-off-by: David Yang --- drivers/clk/hisilicon/crg.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/clk/hisilicon/crg.h b/drivers/clk/hisilicon/crg.h index d9544f1f2625..49142759d63b 100644 --- a/drivers/clk/hisilicon/crg.h +++ b/drivers/clk/hisilicon/crg.h @@ -11,15 +11,9 @@ struct hisi_clock_data; struct hisi_reset_controller; -struct hisi_crg_funcs { - struct hisi_clock_data* (*register_clks)(struct platform_device *pdev); - void (*unregister_clks)(struct platform_device *pdev); -}; - struct hisi_crg_dev { struct hisi_clock_data *clk_data; struct hisi_reset_controller *rstc; - const struct hisi_crg_funcs *funcs; }; /* helper functions for platform driver */ From patchwork Mon Apr 10 11:07:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yangfl X-Patchwork-Id: 81483 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1834220vqo; Mon, 10 Apr 2023 04:42:25 -0700 (PDT) X-Google-Smtp-Source: AKy350blbZZEhYy+nvKyYEXXqxFBjV7sCKSF0b0dhflLCeGrGDQXY9pcq1cehjz2fHmHFY5ZrFEw X-Received: by 2002:a05:6402:12cd:b0:501:cced:9c6c with SMTP id k13-20020a05640212cd00b00501cced9c6cmr5340831edx.7.1681126944791; Mon, 10 Apr 2023 04:42:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681126944; cv=none; d=google.com; s=arc-20160816; b=xHPkAd5Iop2kTkosEjfVTqD3Z1jL+omCKSmXoG7cKeEPb8yB3KdT/yQq1W5GSAAeEE FQ+PR/jQntzvyI0kC/QVDyzqOpDCChq3wQ05CGJpsU1vOYd/6p2dfVu84HM9eWrzafMs hFXXVATfQV0zWdXkf3YBDiGP239ezA7bHjWHJBI8dZlhWeN3vpjvizR9h9NCMfflSeZ3 ++ei1e4AnmOXcuiyOCIynjHsNs1TQrPcdEIXsqtSpAZg/Nq7eITkIaCZKZmsC7rQk85m 0gJJN2Ry4Nq7d6zQNnP01qzWiKuGtiKV8pYYjXeAGVhLcI9b4t24sjf5E3d5z43vNvu2 3sgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=hOql+bAuTzb4sNeAYIK71k2lMY+HYwNHUIwpssNISEY=; b=HHesSmwWUvVklSGEgK+9cuTNnoGaq9wLwktjpSgMzz90PYjv2+7e5rIp7jEx4CYbQf WWtnRYNYreAkFoqEEcsOvAU7zmVGJjcp3aRQVomMAKwbK90LWAiyJs9YniocRV2qzHjY 6nrSbCU9/fdAKdpKtM89pTfy5lW/53WDl9jVDe9YdLApuT1AorzrptbK1jCR7NtJQqyn 3X9fmVtZuJyGQBpgIiZ/kCJ1q23p3/FwaCxJv7JsR6zS79VTJie6+9xNHvyup0H0c0LD FGmAbPuldR+cYQ6j2VnqAtrEbynCFWAZod9PdNgtcdz5KFwPw4uq6e9x2gigbXgQ33NB Knmg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=LIJvdbqR; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id w22-20020aa7da56000000b00504a2e5d950si1923570eds.90.2023.04.10.04.42.00; Mon, 10 Apr 2023 04:42:24 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=LIJvdbqR; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229812AbjDJLJ1 (ORCPT + 99 others); Mon, 10 Apr 2023 07:09:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55900 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229727AbjDJLJZ (ORCPT ); Mon, 10 Apr 2023 07:09:25 -0400 Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 59B4DE6F; Mon, 10 Apr 2023 04:09:03 -0700 (PDT) Received: by mail-pj1-x102e.google.com with SMTP id h24-20020a17090a9c1800b002404be7920aso4036664pjp.5; Mon, 10 Apr 2023 04:09:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1681124942; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hOql+bAuTzb4sNeAYIK71k2lMY+HYwNHUIwpssNISEY=; b=LIJvdbqRE/Z8QTufS+xs6GERTZy2dopVF8Z8woK9L7lhbNTknTxq8V/fW1Y/AwgeGl CtnySdYBQEQTVawIxEy/9RIYwMCh7ubWT/RpudZG2QD60efTn44hJmXeKqKwf1GRdwGF JNJO1uMljxZSyZh6PksPb4P5No/xH2FlmjYaHYR0VWMBzCg4ZET1w3s8Jz0f/O75Zkoa z26zAUdlEPfQFuKEyHp5a8SPOjKxSUzi+qiiHukkauL/mfMsPpxzkONJYlmRiMjcabk9 saG5UtDeKyI9lc9zxO4QozYrH5uGBu8bIYbI+P1Ii6cJJiA2BBLa2L5VJop/JtPMOv6B dZqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681124942; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hOql+bAuTzb4sNeAYIK71k2lMY+HYwNHUIwpssNISEY=; b=blLNToktEDXb1c39Uj1tHMahZVtIS4yKOG2t9y+5QcPmSoA9nOkuW0iPY6jI9u9Fix bI/YuXzEH3DKvIGJNssn+wvHqLf9ALzVTqQKQPoPezjjUFuWdsLw84954rdxZ69MyviX 8ADawayvry0OpsW7oihXRQMu/23d+xdFcVFqNkVffknQIlfU34VNBhzIhFvojZ+LPsoZ j1evc9HRXpTmK3vWi1lDbpIn9zeq3a9bPvlWXvDHIOqDZwOD4nF2LHo7gpgN2dA+Lo5z 2xVl41UHVxNX9uK3aEDXvWeoUmYGaoIKBkBm6bLr4I8m+3yQN9jwHa53azKAHR761Ubf 2Hcw== X-Gm-Message-State: AAQBX9ckJt3+94ktSoyYyonzmKwP8SPLBU8ABYP6lOOEru4ol4A5pBn/ KVvCVq4L6kU54lLdGvuJjJHABfwDnDM5TvLD5mg= X-Received: by 2002:a17:903:8cf:b0:1a5:167f:620f with SMTP id lk15-20020a17090308cf00b001a5167f620fmr8065493plb.15.1681124942145; Mon, 10 Apr 2023 04:09:02 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.213.201]) by smtp.gmail.com with ESMTPSA id r5-20020a170902be0500b001a076568da9sm7464728pls.216.2023.04.10.04.08.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 04:09:01 -0700 (PDT) From: David Yang To: linux-clk@vger.kernel.org Cc: David Yang , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org Subject: [PATCH v3 06/14] clk: hisilicon: hi3519: Use helper functions Date: Mon, 10 Apr 2023 19:07:18 +0800 Message-Id: <20230410110733.192151-7-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230410110733.192151-1-mmyangfl@gmail.com> References: <20230410110733.192151-1-mmyangfl@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762789367437133595?= X-GMAIL-MSGID: =?utf-8?q?1762789367437133595?= Use common helper functions and register clks with a single of_device_id data. Signed-off-by: David Yang --- drivers/clk/hisilicon/clk-hi3519.c | 128 ++++------------------------- 1 file changed, 15 insertions(+), 113 deletions(-) diff --git a/drivers/clk/hisilicon/clk-hi3519.c b/drivers/clk/hisilicon/clk-hi3519.c index ad0c7f350cf0..eac66bde1361 100644 --- a/drivers/clk/hisilicon/clk-hi3519.c +++ b/drivers/clk/hisilicon/clk-hi3519.c @@ -10,7 +10,7 @@ #include #include #include "clk.h" -#include "reset.h" +#include "crg.h" #define HI3519_INNER_CLK_OFFSET 64 #define HI3519_FIXED_24M 65 @@ -73,131 +73,33 @@ static const struct hisi_gate_clock hi3519_gate_clks[] = { CLK_SET_RATE_PARENT, 0xe4, 18, 0, }, }; -static struct hisi_clock_data *hi3519_clk_register(struct platform_device *pdev) -{ - struct hisi_clock_data *clk_data; - int ret; - - clk_data = hisi_clk_alloc(pdev, HI3519_NR_CLKS); - if (!clk_data) - return ERR_PTR(-ENOMEM); - - ret = hisi_clk_register_fixed_rate(hi3519_fixed_rate_clks, - ARRAY_SIZE(hi3519_fixed_rate_clks), - clk_data); - if (ret) - return ERR_PTR(ret); - - ret = hisi_clk_register_mux(hi3519_mux_clks, - ARRAY_SIZE(hi3519_mux_clks), - clk_data); - if (ret) - goto unregister_fixed_rate; - - ret = hisi_clk_register_gate(hi3519_gate_clks, - ARRAY_SIZE(hi3519_gate_clks), - clk_data); - if (ret) - goto unregister_mux; - - ret = of_clk_add_provider(pdev->dev.of_node, - of_clk_src_onecell_get, &clk_data->clk_data); - if (ret) - goto unregister_gate; - - return clk_data; - -unregister_fixed_rate: - hisi_clk_unregister_fixed_rate(hi3519_fixed_rate_clks, - ARRAY_SIZE(hi3519_fixed_rate_clks), - clk_data); - -unregister_mux: - hisi_clk_unregister_mux(hi3519_mux_clks, - ARRAY_SIZE(hi3519_mux_clks), - clk_data); -unregister_gate: - hisi_clk_unregister_gate(hi3519_gate_clks, - ARRAY_SIZE(hi3519_gate_clks), - clk_data); - return ERR_PTR(ret); -} - -static void hi3519_clk_unregister(struct platform_device *pdev) -{ - struct hi3519_crg_data *crg = platform_get_drvdata(pdev); - - of_clk_del_provider(pdev->dev.of_node); - - hisi_clk_unregister_gate(hi3519_gate_clks, - ARRAY_SIZE(hi3519_mux_clks), - crg->clk_data); - hisi_clk_unregister_mux(hi3519_mux_clks, - ARRAY_SIZE(hi3519_mux_clks), - crg->clk_data); - hisi_clk_unregister_fixed_rate(hi3519_fixed_rate_clks, - ARRAY_SIZE(hi3519_fixed_rate_clks), - crg->clk_data); -} - -static int hi3519_clk_probe(struct platform_device *pdev) -{ - struct hi3519_crg_data *crg; - - crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL); - if (!crg) - return -ENOMEM; - - crg->rstc = hisi_reset_init(pdev); - if (!crg->rstc) - return -ENOMEM; - - crg->clk_data = hi3519_clk_register(pdev); - if (IS_ERR(crg->clk_data)) { - hisi_reset_exit(crg->rstc); - return PTR_ERR(crg->clk_data); - } - - platform_set_drvdata(pdev, crg); - return 0; -} - -static int hi3519_clk_remove(struct platform_device *pdev) -{ - struct hi3519_crg_data *crg = platform_get_drvdata(pdev); - - hisi_reset_exit(crg->rstc); - hi3519_clk_unregister(pdev); - return 0; -} - +static const struct hisi_clocks hi3519_crg_clks = { + .nr = HI3519_NR_CLKS, + .fixed_rate_clks = hi3519_fixed_rate_clks, + .fixed_rate_clks_num = ARRAY_SIZE(hi3519_fixed_rate_clks), + .mux_clks = hi3519_mux_clks, + .mux_clks_num = ARRAY_SIZE(hi3519_mux_clks), + .gate_clks = hi3519_gate_clks, + .gate_clks_num = ARRAY_SIZE(hi3519_gate_clks), +}; static const struct of_device_id hi3519_clk_match_table[] = { - { .compatible = "hisilicon,hi3519-crg" }, + { .compatible = "hisilicon,hi3519-crg", + .data = &hi3519_crg_clks }, { } }; MODULE_DEVICE_TABLE(of, hi3519_clk_match_table); static struct platform_driver hi3519_clk_driver = { - .probe = hi3519_clk_probe, - .remove = hi3519_clk_remove, + .probe = hisi_crg_probe, + .remove = hisi_crg_remove, .driver = { .name = "hi3519-clk", .of_match_table = hi3519_clk_match_table, }, }; -static int __init hi3519_clk_init(void) -{ - return platform_driver_register(&hi3519_clk_driver); -} -core_initcall(hi3519_clk_init); - -static void __exit hi3519_clk_exit(void) -{ - platform_driver_unregister(&hi3519_clk_driver); -} -module_exit(hi3519_clk_exit); +module_platform_driver(hi3519_clk_driver); MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("HiSilicon Hi3519 Clock Driver"); From patchwork Mon Apr 10 11:07:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yangfl X-Patchwork-Id: 81470 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1819463vqo; Mon, 10 Apr 2023 04:12:34 -0700 (PDT) X-Google-Smtp-Source: AKy350bUkv1ggwmFJ3IXqnVe3CQGVXYgs6nygsmIW7WoBrDgVhNnBOqqe7zkxvujPjMMzVoo7fDT X-Received: by 2002:a17:902:f684:b0:1a5:1109:f58e with SMTP id l4-20020a170902f68400b001a51109f58emr9954084plg.29.1681125153949; Mon, 10 Apr 2023 04:12:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681125153; cv=none; d=google.com; s=arc-20160816; b=uoudDMhSLAOe/yL4eyQ+BBfTQ9gNU3fYAHQbgSoTNrZHE2uhLchHi3ORx85MA3S5wc KKx0KCLfGD6f7GCHmtcVOKouj8tYOFlwdsOBjNhv6H1Ev3tOpAMvGSBJIIluWKzRATTf yMwx0EJNW8hD9glEgpj+HiSnMTZCyTqnov6tQ7MRoM37IP4angVHG/Bt64q7ppYaathp Gkdehmw3DM6ZfHyZGQxMFpkSp1kRA7Dv9G13LE1t79DCofo6FUSw1oXTbbjRkzgSYtB/ 7ki3aLwZi6lK6Xh/dnsu++hg29OcwljRvahaWcgmWa5rljRVfh4kGg/Q6h3T5+u3TsMt rIeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=mWJIHJN97kYoJ38RctmRsN2DU2i8m+C9aLZTSJfRMII=; b=RlscxpzvhzM9rrhvYT9Tx6aJ7Y0KMtM8MJGGMFJs+L6iBEJmlEs/3AV31aSooShDtc 9BfBNijzOJswQwLAtOEEflzmP1sGsGRNOwC0VfLAhgSkfxFR+p2Co1TRvNrRQYiQBh6V X0Pm+BoZ+VW6A32tn3RCLOkzESzSwAVW5oAthwftMTcV0TMYZ95LS/g7TH4TE/hmbHrB jmSjyK82oH+/01fExcGSZ0HV/LU2d8rpdhdqPkqtncNe3JY0MGBcGPyvIBNJGHXg1dd1 Q5crBIPPKxYG+jvlNKOY0TgX/w4ynggnlzZ5eusc7vwDBSR8/yUMN5fxt1thfSNpdNdl PEiA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=VHrNTTn9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id lh7-20020a170903290700b0019e8456b5f2si6831911plb.619.2023.04.10.04.12.21; Mon, 10 Apr 2023 04:12:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=VHrNTTn9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229727AbjDJLJq (ORCPT + 99 others); Mon, 10 Apr 2023 07:09:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56424 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229660AbjDJLJo (ORCPT ); Mon, 10 Apr 2023 07:09:44 -0400 Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5EBAB5BB5; Mon, 10 Apr 2023 04:09:17 -0700 (PDT) Received: by mail-pl1-x62b.google.com with SMTP id h24so4525542plr.1; Mon, 10 Apr 2023 04:09:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1681124956; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mWJIHJN97kYoJ38RctmRsN2DU2i8m+C9aLZTSJfRMII=; b=VHrNTTn9O0v4eIr0DKLvDoXcuFbN4T2kdw8XCIZgNmiWxqggFSG5V9P8B2olsSRcN7 f8qHSZa+K4+dLPujdOiOd/PFZfL5SLOEHHjgMa9MriyOI7N/DrC4YuSegwgdyV+oedkr WIZ/QGfDiAJes5+/SvM00Ho7edEbIZ0qm8Xk/yV7z+d3g+zQq6Pn5Z9u0q0C19ZMa6fc zLVicXxfQ0/xnM+al9MT3CP522vL/9n0Q8dXouJDCKHSnc0y4e/YcNGs3/b1Vtj/Ds5h W4KWRVrV4Uzjo7Ilz7PiIywN9z0OffelklZvBX6NDnovfvi6fFGsVOhkn3NNZ+praw0+ ArZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681124956; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mWJIHJN97kYoJ38RctmRsN2DU2i8m+C9aLZTSJfRMII=; b=2MCbgplYRS8ipCCl+L8NaOzVwxYF285dAnYgrE1t5LXBwUXaOHpxD/gY5LUZVCLw9o I4EHGlv6ybkJY/lj2GxRkQyWcVDmSas6Z5BJ2koE6dQWJ0gFAKFWYpdDb6uo5Ko3IFVx XDpjfmbfT8ZVwkd375tnbz8suv7A8hDsLHYGN/x2qx/Ouvvp4sR3SNfppTs2v9Slc8CO mDdiRQe3F6AxD9mnCyJDeY+I1EJvD8g/xXNZdGnCibka66lRbRMsTb5ruIzCyvSp0t2p hPhJzRum/do5ao4cF5bMiGL9gFqIS48Cu84GlfPkygKn34/IlgoiNwerDILvxn+bR8Z4 I6LQ== X-Gm-Message-State: AAQBX9cxXEsr5Zze68axAaQQCmZInOBCRrIfD1vYlspmzVGcS945Bw/+ 5D6gt27GQdsvVUyL9qzDrdCDJ4T1b9oNSwysjxQ= X-Received: by 2002:a17:902:d488:b0:19a:9610:b234 with SMTP id c8-20020a170902d48800b0019a9610b234mr12176120plg.1.1681124956396; Mon, 10 Apr 2023 04:09:16 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.213.201]) by smtp.gmail.com with ESMTPSA id r5-20020a170902be0500b001a076568da9sm7464728pls.216.2023.04.10.04.09.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 04:09:16 -0700 (PDT) From: David Yang To: linux-clk@vger.kernel.org Cc: David Yang , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org, Conor Dooley , Nick Alcock Subject: [PATCH v3 07/14] clk: hisilicon: hi3559a: Use helper functions Date: Mon, 10 Apr 2023 19:07:19 +0800 Message-Id: <20230410110733.192151-8-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230410110733.192151-1-mmyangfl@gmail.com> References: <20230410110733.192151-1-mmyangfl@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762787489298744754?= X-GMAIL-MSGID: =?utf-8?q?1762787489298744754?= Use common helper functions and register clks with a single of_device_id data. Signed-off-by: David Yang --- drivers/clk/hisilicon/clk-hi3559a.c | 232 +++++----------------------- 1 file changed, 37 insertions(+), 195 deletions(-) diff --git a/drivers/clk/hisilicon/clk-hi3559a.c b/drivers/clk/hisilicon/clk-hi3559a.c index 8036bd8cbb0a..9844e86ec146 100644 --- a/drivers/clk/hisilicon/clk-hi3559a.c +++ b/drivers/clk/hisilicon/clk-hi3559a.c @@ -11,7 +11,6 @@ #include #include #include -#include #include @@ -452,21 +451,23 @@ static const struct clk_ops hisi_clk_pll_ops = { .recalc_rate = clk_pll_recalc_rate, }; -static void hisi_clk_register_pll(struct hi3559av100_pll_clock *clks, - int nums, struct hisi_clock_data *data, struct device *dev) +static int +hisi_clk_register_pll(struct device *dev, const void *clocks, + size_t num, struct hisi_clock_data *data) { + const struct hi3559av100_pll_clock *clks = clocks; void __iomem *base = data->base; struct hi3559av100_clk_pll *p_clk = NULL; struct clk *clk = NULL; struct clk_init_data init; int i; - p_clk = devm_kzalloc(dev, sizeof(*p_clk) * nums, GFP_KERNEL); + p_clk = devm_kzalloc(dev, sizeof(*p_clk) * num, GFP_KERNEL); if (!p_clk) - return; + return -ENOMEM; - for (i = 0; i < nums; i++) { + for (i = 0; i < num; i++) { init.name = clks[i].name; init.flags = 0; init.parent_names = @@ -494,78 +495,27 @@ static void hisi_clk_register_pll(struct hi3559av100_pll_clock *clks, devm_kfree(dev, p_clk); dev_err(dev, "%s: failed to register clock %s\n", __func__, clks[i].name); - continue; + return PTR_ERR(clk); } data->clk_data.clks[clks[i].id] = clk; p_clk++; } -} - -static struct hisi_clock_data *hi3559av100_clk_register( - struct platform_device *pdev) -{ - struct hisi_clock_data *clk_data; - int ret; - - clk_data = hisi_clk_alloc(pdev, HI3559AV100_CRG_NR_CLKS); - if (!clk_data) - return ERR_PTR(-ENOMEM); - - ret = hisi_clk_register_fixed_rate(hi3559av100_fixed_rate_clks_crg, - ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), clk_data); - if (ret) - return ERR_PTR(ret); - - hisi_clk_register_pll(hi3559av100_pll_clks, - ARRAY_SIZE(hi3559av100_pll_clks), clk_data, &pdev->dev); - - ret = hisi_clk_register_mux(hi3559av100_mux_clks_crg, - ARRAY_SIZE(hi3559av100_mux_clks_crg), clk_data); - if (ret) - goto unregister_fixed_rate; - - ret = hisi_clk_register_gate(hi3559av100_gate_clks, - ARRAY_SIZE(hi3559av100_gate_clks), clk_data); - if (ret) - goto unregister_mux; - - ret = of_clk_add_provider(pdev->dev.of_node, - of_clk_src_onecell_get, &clk_data->clk_data); - if (ret) - goto unregister_gate; - - return clk_data; - -unregister_gate: - hisi_clk_unregister_gate(hi3559av100_gate_clks, - ARRAY_SIZE(hi3559av100_gate_clks), clk_data); -unregister_mux: - hisi_clk_unregister_mux(hi3559av100_mux_clks_crg, - ARRAY_SIZE(hi3559av100_mux_clks_crg), clk_data); -unregister_fixed_rate: - hisi_clk_unregister_fixed_rate(hi3559av100_fixed_rate_clks_crg, - ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), clk_data); - return ERR_PTR(ret); -} -static void hi3559av100_clk_unregister(struct platform_device *pdev) -{ - struct hisi_crg_dev *crg = platform_get_drvdata(pdev); - - of_clk_del_provider(pdev->dev.of_node); - - hisi_clk_unregister_gate(hi3559av100_gate_clks, - ARRAY_SIZE(hi3559av100_gate_clks), crg->clk_data); - hisi_clk_unregister_mux(hi3559av100_mux_clks_crg, - ARRAY_SIZE(hi3559av100_mux_clks_crg), crg->clk_data); - hisi_clk_unregister_fixed_rate(hi3559av100_fixed_rate_clks_crg, - ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), crg->clk_data); + return 0; } -static const struct hisi_crg_funcs hi3559av100_crg_funcs = { - .register_clks = hi3559av100_clk_register, - .unregister_clks = hi3559av100_clk_unregister, +static const struct hisi_clocks hi3559av100_clks = { + .nr = HI3559AV100_CRG_NR_CLKS, + .fixed_rate_clks = hi3559av100_fixed_rate_clks_crg, + .fixed_rate_clks_num = ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), + .mux_clks = hi3559av100_mux_clks_crg, + .mux_clks_num = ARRAY_SIZE(hi3559av100_mux_clks_crg), + .gate_clks = hi3559av100_gate_clks, + .gate_clks_num = ARRAY_SIZE(hi3559av100_gate_clks), + .customized_clks = hi3559av100_pll_clks, + .customized_clks_num = ARRAY_SIZE(hi3559av100_pll_clks), + .clk_register_customized = hisi_clk_register_pll, }; static struct hisi_fixed_rate_clock hi3559av100_shub_fixed_rate_clks[] = { @@ -673,7 +623,7 @@ static struct hisi_gate_clock hi3559av100_shub_gate_clks[] = { }, }; -static int hi3559av100_shub_default_clk_set(void) +static int hi3559av100_shub_default_clk_set(struct device *dev, struct hisi_clock_data *data) { void __iomem *crg_base; unsigned int val; @@ -696,149 +646,41 @@ static int hi3559av100_shub_default_clk_set(void) return 0; } -static struct hisi_clock_data *hi3559av100_shub_clk_register( - struct platform_device *pdev) -{ - struct hisi_clock_data *clk_data = NULL; - int ret; - - hi3559av100_shub_default_clk_set(); - - clk_data = hisi_clk_alloc(pdev, HI3559AV100_SHUB_NR_CLKS); - if (!clk_data) - return ERR_PTR(-ENOMEM); - - ret = hisi_clk_register_fixed_rate(hi3559av100_shub_fixed_rate_clks, - ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), clk_data); - if (ret) - return ERR_PTR(ret); - - ret = hisi_clk_register_mux(hi3559av100_shub_mux_clks, - ARRAY_SIZE(hi3559av100_shub_mux_clks), clk_data); - if (ret) - goto unregister_fixed_rate; - - ret = hisi_clk_register_divider(hi3559av100_shub_div_clks, - ARRAY_SIZE(hi3559av100_shub_div_clks), clk_data); - if (ret) - goto unregister_mux; - - ret = hisi_clk_register_gate(hi3559av100_shub_gate_clks, - ARRAY_SIZE(hi3559av100_shub_gate_clks), clk_data); - if (ret) - goto unregister_factor; - - ret = of_clk_add_provider(pdev->dev.of_node, - of_clk_src_onecell_get, &clk_data->clk_data); - if (ret) - goto unregister_gate; - - return clk_data; - -unregister_gate: - hisi_clk_unregister_gate(hi3559av100_shub_gate_clks, - ARRAY_SIZE(hi3559av100_shub_gate_clks), clk_data); -unregister_factor: - hisi_clk_unregister_divider(hi3559av100_shub_div_clks, - ARRAY_SIZE(hi3559av100_shub_div_clks), clk_data); -unregister_mux: - hisi_clk_unregister_mux(hi3559av100_shub_mux_clks, - ARRAY_SIZE(hi3559av100_shub_mux_clks), clk_data); -unregister_fixed_rate: - hisi_clk_unregister_fixed_rate(hi3559av100_shub_fixed_rate_clks, - ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), clk_data); - return ERR_PTR(ret); -} - -static void hi3559av100_shub_clk_unregister(struct platform_device *pdev) -{ - struct hisi_crg_dev *crg = platform_get_drvdata(pdev); - - of_clk_del_provider(pdev->dev.of_node); - - hisi_clk_unregister_gate(hi3559av100_shub_gate_clks, - ARRAY_SIZE(hi3559av100_shub_gate_clks), crg->clk_data); - hisi_clk_unregister_divider(hi3559av100_shub_div_clks, - ARRAY_SIZE(hi3559av100_shub_div_clks), crg->clk_data); - hisi_clk_unregister_mux(hi3559av100_shub_mux_clks, - ARRAY_SIZE(hi3559av100_shub_mux_clks), crg->clk_data); - hisi_clk_unregister_fixed_rate(hi3559av100_shub_fixed_rate_clks, - ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), crg->clk_data); -} - -static const struct hisi_crg_funcs hi3559av100_shub_crg_funcs = { - .register_clks = hi3559av100_shub_clk_register, - .unregister_clks = hi3559av100_shub_clk_unregister, +static const struct hisi_clocks hi3559av100_shub_clks = { + .nr = HI3559AV100_SHUB_NR_CLKS, + .prologue = hi3559av100_shub_default_clk_set, + .fixed_rate_clks = hi3559av100_shub_fixed_rate_clks, + .fixed_rate_clks_num = ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), + .mux_clks = hi3559av100_shub_mux_clks, + .mux_clks_num = ARRAY_SIZE(hi3559av100_shub_mux_clks), + .divider_clks = hi3559av100_shub_div_clks, + .divider_clks_num = ARRAY_SIZE(hi3559av100_shub_div_clks), + .gate_clks = hi3559av100_shub_gate_clks, + .gate_clks_num = ARRAY_SIZE(hi3559av100_shub_gate_clks), }; static const struct of_device_id hi3559av100_crg_match_table[] = { { .compatible = "hisilicon,hi3559av100-clock", - .data = &hi3559av100_crg_funcs + .data = &hi3559av100_clks }, { .compatible = "hisilicon,hi3559av100-shub-clock", - .data = &hi3559av100_shub_crg_funcs + .data = &hi3559av100_shub_clks }, { } }; MODULE_DEVICE_TABLE(of, hi3559av100_crg_match_table); -static int hi3559av100_crg_probe(struct platform_device *pdev) -{ - struct hisi_crg_dev *crg; - - crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL); - if (!crg) - return -ENOMEM; - - crg->funcs = of_device_get_match_data(&pdev->dev); - if (!crg->funcs) - return -ENOENT; - - crg->rstc = hisi_reset_init(pdev); - if (!crg->rstc) - return -ENOMEM; - - crg->clk_data = crg->funcs->register_clks(pdev); - if (IS_ERR(crg->clk_data)) { - hisi_reset_exit(crg->rstc); - return PTR_ERR(crg->clk_data); - } - - platform_set_drvdata(pdev, crg); - return 0; -} - -static int hi3559av100_crg_remove(struct platform_device *pdev) -{ - struct hisi_crg_dev *crg = platform_get_drvdata(pdev); - - hisi_reset_exit(crg->rstc); - crg->funcs->unregister_clks(pdev); - return 0; -} - static struct platform_driver hi3559av100_crg_driver = { - .probe = hi3559av100_crg_probe, - .remove = hi3559av100_crg_remove, + .probe = hisi_crg_probe, + .remove = hisi_crg_remove, .driver = { .name = "hi3559av100-clock", .of_match_table = hi3559av100_crg_match_table, }, }; -static int __init hi3559av100_crg_init(void) -{ - return platform_driver_register(&hi3559av100_crg_driver); -} -core_initcall(hi3559av100_crg_init); - -static void __exit hi3559av100_crg_exit(void) -{ - platform_driver_unregister(&hi3559av100_crg_driver); -} -module_exit(hi3559av100_crg_exit); - +module_platform_driver(hi3559av100_crg_driver); MODULE_DESCRIPTION("HiSilicon Hi3559AV100 CRG Driver"); From patchwork Mon Apr 10 11:07:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yangfl X-Patchwork-Id: 81484 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1834630vqo; Mon, 10 Apr 2023 04:43:22 -0700 (PDT) X-Google-Smtp-Source: AKy350ZPuBfa+aXjh6aTfwF5MBvVHjh0rlQwNXSCiL/pjqm3KK4QlahTI+0IoS1ayy5/L/hEqkV+ X-Received: by 2002:a17:907:3e99:b0:93d:425a:b935 with SMTP id hs25-20020a1709073e9900b0093d425ab935mr9075197ejc.25.1681127002620; Mon, 10 Apr 2023 04:43:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681127002; cv=none; d=google.com; s=arc-20160816; b=vreUKNl8S9EDAgXURi2VtA3npRD4F4FqlIlOnvJ3HiqihQGas31+hLfL//leXiYPWD kU3KgnMkPa8vJZ0MrXWw7Zk4295/bYThqXZ1t+RJ8Yltzb9XROuFBhbvW//cGW5bujyO cwntgGEB/ndqqDH0KuqoK7T90XlnWNWponCbvV4QYwnLV9GiolEYCy6PVh+OMyJk45OP dgQp8s9mUq1XG2akuz3yk2pszUziKcOW42iXJKFU9g5wBNPSypfgsnDsySuJRnOUYCq+ 57Gu+12/POoEzSfojdPO6sBPs6OxRA48i8dYJ4VYlLnFQn4sGr73dTPD5/VRiWZ/1A0J d4IQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=L4LZi4v8BP7uhMO1g5FIUEMzxer6nFR6wrcwU4BODNA=; b=OVrj0fYeQOXHYAZkDihzvvkrjzs43DuIeTD/wKrPYKNjgtsqmVOQZWgP1kcOyOSAG1 VBfxsLcyF3j17yxB9Kjh1p3NX2R9JGa9a3LevYI+mD9eFHw1zxUBjCY3n8KdIp7/NH3q /gydQfPE8v5UQHnYBzXFU9ojrmPkJ9ad9fs8uvLUfXnvwZIHsM81TEf5koj+gyVFofwJ eKIQbakduFvqfsV07QwLh7x2qdS7wd+ytOrc6SWsdY7pXMil18Q0QCYET8cB2DxTHptD 8UzQXh9MOkFje3mAhubY+6bloPQ9faqCr/2rUHipBh4oRE6vFzttfemdQIEdCdsXvR19 3l5A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b="V/Mo8lp6"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id n18-20020a170906689200b0094a75839eb8si2555189ejr.706.2023.04.10.04.42.57; Mon, 10 Apr 2023 04:43:22 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b="V/Mo8lp6"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229834AbjDJLJx (ORCPT + 99 others); Mon, 10 Apr 2023 07:09:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229840AbjDJLJv (ORCPT ); Mon, 10 Apr 2023 07:09:51 -0400 Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B90D86590; Mon, 10 Apr 2023 04:09:30 -0700 (PDT) Received: by mail-pl1-x631.google.com with SMTP id 20so6193403plk.10; Mon, 10 Apr 2023 04:09:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1681124970; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=L4LZi4v8BP7uhMO1g5FIUEMzxer6nFR6wrcwU4BODNA=; b=V/Mo8lp6DYQY4Vh7rXY3tciBhihRppXEisbu+VKKF1wQSRGQF9zFU1cxLZM0Q8NsL6 JzNKBCc8V0j70NHd41yuHmsDbQZ60LE0/JU4JlJbVUBwAJjcy5ZZecDod63ZJY6x/Wyx uE1iLCdhFgRbMNCeMbIEvyrOtlhxzgyG03Q3b33k9tACuAaGyJaFa4RVPbh+XT4S8j8S KybgfCKmR9ykxMNzNUSN7Txl3bbWU8O/NnIYacb1UScRunv41s0vG2yrT2SIQ2BwWsP2 1Gw9+FBdZQGFomX+w0JeKL7Foek3t3SeTW3DsvOiWhuhsQ92ePUrC7AjJl3tQC2u6zS3 oNGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681124970; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=L4LZi4v8BP7uhMO1g5FIUEMzxer6nFR6wrcwU4BODNA=; b=SG5pF+yZdv3C+Ltypnx2jvDvrTIyQ/6gVY1YEZ46Jx9KjnQdv0tndgU3ZIohS+G3i4 1Lskx68RBvnHC0r+rz9dTAWEztBc2l2G24jb2n7tFN3Pcth/AQKx/nfFUaHjJhM2yXkp 6oCLPgI8sfx4zJ0ewBshKqtoYC6YIG47byq1GGxYhMeDp4un4KtWfxD+0prydyVLuigX t32lZD4+47WHPPhDip5PrkVGjE2WYXnIg5t+exQHfFxGRDLP3yU2YsQxdu1i5X2v5twX n4uzAPvodSo/WnGl97zgcizeFMCpr6aMqSVecw2Ihx47+f8XdKY7osjolWmG9qI+1XeH 2rxw== X-Gm-Message-State: AAQBX9dEEvYK8YdNFJqb+A9Z7J04TDyl6rlBEcl354jysBqIAB5Acbli d3GsYWgic59cbWrLLc6BiIxBgYjzUkqV/UGx/jY= X-Received: by 2002:a17:902:e74f:b0:1a6:3799:ec36 with SMTP id p15-20020a170902e74f00b001a63799ec36mr4148786plf.33.1681124970057; Mon, 10 Apr 2023 04:09:30 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.213.201]) by smtp.gmail.com with ESMTPSA id r5-20020a170902be0500b001a076568da9sm7464728pls.216.2023.04.10.04.09.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 04:09:29 -0700 (PDT) From: David Yang To: linux-clk@vger.kernel.org Cc: David Yang , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org Subject: [PATCH v3 08/14] clk: hisilicon: hi3660: Convert into module Date: Mon, 10 Apr 2023 19:07:20 +0800 Message-Id: <20230410110733.192151-9-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230410110733.192151-1-mmyangfl@gmail.com> References: <20230410110733.192151-1-mmyangfl@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762789427414373981?= X-GMAIL-MSGID: =?utf-8?q?1762789427414373981?= Use common helper functions and register clks with a single of_device_id data. Signed-off-by: David Yang --- drivers/clk/hisilicon/clk-hi3660.c | 192 ++++++++--------------------- 1 file changed, 53 insertions(+), 139 deletions(-) diff --git a/drivers/clk/hisilicon/clk-hi3660.c b/drivers/clk/hisilicon/clk-hi3660.c index 41f61726ab19..ce911b35bf68 100644 --- a/drivers/clk/hisilicon/clk-hi3660.c +++ b/drivers/clk/hisilicon/clk-hi3660.c @@ -5,9 +5,13 @@ */ #include + #include +#include +#include #include #include + #include "clk.h" static const struct hisi_fixed_rate_clock hi3660_fixed_rate_clks[] = { @@ -469,169 +473,79 @@ static const struct hisi_gate_clock hi3660_iomcu_gate_sep_clks[] = { CLK_SET_RATE_PARENT, 0x90, 0, 0, }, }; -static struct hisi_clock_data *clk_crgctrl_data; - -static void hi3660_clk_iomcu_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - int nr = ARRAY_SIZE(hi3660_iomcu_gate_sep_clks); - - clk_data = hisi_clk_init(np, nr); - if (!clk_data) - return; - - hisi_clk_register_gate_sep(hi3660_iomcu_gate_sep_clks, - ARRAY_SIZE(hi3660_iomcu_gate_sep_clks), - clk_data); -} - -static void hi3660_clk_pmuctrl_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - int nr = ARRAY_SIZE(hi3660_pmu_gate_clks); - - clk_data = hisi_clk_init(np, nr); - if (!clk_data) - return; - - hisi_clk_register_gate(hi3660_pmu_gate_clks, - ARRAY_SIZE(hi3660_pmu_gate_clks), clk_data); -} +static const struct hisi_clocks hi3660_clk_iomcu_clks = { + .gate_sep_clks = hi3660_iomcu_gate_sep_clks, + .gate_sep_clks_num = ARRAY_SIZE(hi3660_iomcu_gate_sep_clks), +}; -static void hi3660_clk_pctrl_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - int nr = ARRAY_SIZE(hi3660_pctrl_gate_clks); +static const struct hisi_clocks hi3660_clk_pmuctrl_clks = { + .gate_clks = hi3660_pmu_gate_clks, + .gate_clks_num = ARRAY_SIZE(hi3660_pmu_gate_clks), +}; - clk_data = hisi_clk_init(np, nr); - if (!clk_data) - return; - hisi_clk_register_gate(hi3660_pctrl_gate_clks, - ARRAY_SIZE(hi3660_pctrl_gate_clks), clk_data); -} +static const struct hisi_clocks hi3660_clk_pctrl_clks = { + .gate_clks = hi3660_pctrl_gate_clks, + .gate_clks_num = ARRAY_SIZE(hi3660_pctrl_gate_clks), +}; -static void hi3660_clk_sctrl_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - int nr = ARRAY_SIZE(hi3660_sctrl_gate_clks) + - ARRAY_SIZE(hi3660_sctrl_gate_sep_clks) + - ARRAY_SIZE(hi3660_sctrl_mux_clks) + - ARRAY_SIZE(hi3660_sctrl_divider_clks); +static const struct hisi_clocks hi3660_clk_sctrl_clks = { + .mux_clks = hi3660_sctrl_mux_clks, + .mux_clks_num = ARRAY_SIZE(hi3660_sctrl_mux_clks), + .divider_clks = hi3660_sctrl_divider_clks, + .divider_clks_num = ARRAY_SIZE(hi3660_sctrl_divider_clks), + .gate_clks = hi3660_sctrl_gate_clks, + .gate_clks_num = ARRAY_SIZE(hi3660_sctrl_gate_clks), + .gate_sep_clks = hi3660_sctrl_gate_sep_clks, + .gate_sep_clks_num = ARRAY_SIZE(hi3660_sctrl_gate_sep_clks), +}; - clk_data = hisi_clk_init(np, nr); - if (!clk_data) - return; - hisi_clk_register_gate(hi3660_sctrl_gate_clks, - ARRAY_SIZE(hi3660_sctrl_gate_clks), clk_data); - hisi_clk_register_gate_sep(hi3660_sctrl_gate_sep_clks, - ARRAY_SIZE(hi3660_sctrl_gate_sep_clks), - clk_data); - hisi_clk_register_mux(hi3660_sctrl_mux_clks, - ARRAY_SIZE(hi3660_sctrl_mux_clks), clk_data); - hisi_clk_register_divider(hi3660_sctrl_divider_clks, - ARRAY_SIZE(hi3660_sctrl_divider_clks), - clk_data); -} +static const struct hisi_clocks hi3660_clk_crgctrl_clks = { + .fixed_rate_clks = hi3660_fixed_rate_clks, + .fixed_rate_clks_num = ARRAY_SIZE(hi3660_fixed_rate_clks), + .fixed_factor_clks = hi3660_crg_fixed_factor_clks, + .fixed_factor_clks_num = ARRAY_SIZE(hi3660_crg_fixed_factor_clks), + .mux_clks = hi3660_crgctrl_mux_clks, + .mux_clks_num = ARRAY_SIZE(hi3660_crgctrl_mux_clks), + .divider_clks = hi3660_crgctrl_divider_clks, + .divider_clks_num = ARRAY_SIZE(hi3660_crgctrl_divider_clks), + .gate_clks = hi3660_crgctrl_gate_clks, + .gate_clks_num = ARRAY_SIZE(hi3660_crgctrl_gate_clks), + .gate_sep_clks = hi3660_crgctrl_gate_sep_clks, + .gate_sep_clks_num = ARRAY_SIZE(hi3660_crgctrl_gate_sep_clks), +}; static void hi3660_clk_crgctrl_early_init(struct device_node *np) { - int nr = ARRAY_SIZE(hi3660_fixed_rate_clks) + - ARRAY_SIZE(hi3660_crgctrl_gate_sep_clks) + - ARRAY_SIZE(hi3660_crgctrl_gate_clks) + - ARRAY_SIZE(hi3660_crgctrl_mux_clks) + - ARRAY_SIZE(hi3660_crg_fixed_factor_clks) + - ARRAY_SIZE(hi3660_crgctrl_divider_clks); - int i; - - clk_crgctrl_data = hisi_clk_init(np, nr); - if (!clk_crgctrl_data) - return; - - for (i = 0; i < nr; i++) - clk_crgctrl_data->clk_data.clks[i] = ERR_PTR(-EPROBE_DEFER); - - hisi_clk_register_fixed_rate(hi3660_fixed_rate_clks, - ARRAY_SIZE(hi3660_fixed_rate_clks), - clk_crgctrl_data); + hisi_clk_early_init(np, &hi3660_clk_crgctrl_clks); } CLK_OF_DECLARE_DRIVER(hi3660_clk_crgctrl, "hisilicon,hi3660-crgctrl", hi3660_clk_crgctrl_early_init); -static void hi3660_clk_crgctrl_init(struct device_node *np) -{ - struct clk **clks; - int i; - - if (!clk_crgctrl_data) - hi3660_clk_crgctrl_early_init(np); - - /* clk_crgctrl_data initialization failed */ - if (!clk_crgctrl_data) - return; - - hisi_clk_register_gate_sep(hi3660_crgctrl_gate_sep_clks, - ARRAY_SIZE(hi3660_crgctrl_gate_sep_clks), - clk_crgctrl_data); - hisi_clk_register_gate(hi3660_crgctrl_gate_clks, - ARRAY_SIZE(hi3660_crgctrl_gate_clks), - clk_crgctrl_data); - hisi_clk_register_mux(hi3660_crgctrl_mux_clks, - ARRAY_SIZE(hi3660_crgctrl_mux_clks), - clk_crgctrl_data); - hisi_clk_register_fixed_factor(hi3660_crg_fixed_factor_clks, - ARRAY_SIZE(hi3660_crg_fixed_factor_clks), - clk_crgctrl_data); - hisi_clk_register_divider(hi3660_crgctrl_divider_clks, - ARRAY_SIZE(hi3660_crgctrl_divider_clks), - clk_crgctrl_data); - - clks = clk_crgctrl_data->clk_data.clks; - for (i = 0; i < clk_crgctrl_data->clk_data.clk_num; i++) { - if (IS_ERR(clks[i]) && PTR_ERR(clks[i]) != -EPROBE_DEFER) - pr_err("Failed to register crgctrl clock[%d] err=%ld\n", - i, PTR_ERR(clks[i])); - } -} - static const struct of_device_id hi3660_clk_match_table[] = { { .compatible = "hisilicon,hi3660-crgctrl", - .data = hi3660_clk_crgctrl_init }, + .data = &hi3660_clk_crgctrl_clks }, { .compatible = "hisilicon,hi3660-pctrl", - .data = hi3660_clk_pctrl_init }, + .data = &hi3660_clk_pctrl_clks }, { .compatible = "hisilicon,hi3660-pmuctrl", - .data = hi3660_clk_pmuctrl_init }, + .data = &hi3660_clk_pmuctrl_clks }, { .compatible = "hisilicon,hi3660-sctrl", - .data = hi3660_clk_sctrl_init }, + .data = &hi3660_clk_sctrl_clks }, { .compatible = "hisilicon,hi3660-iomcu", - .data = hi3660_clk_iomcu_init }, + .data = &hi3660_clk_iomcu_clks }, { } }; - -static int hi3660_clk_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct device_node *np = pdev->dev.of_node; - void (*init_func)(struct device_node *np); - - init_func = of_device_get_match_data(dev); - if (!init_func) - return -ENODEV; - - init_func(np); - - return 0; -} +MODULE_DEVICE_TABLE(of, hi3660_clk_match_table); static struct platform_driver hi3660_clk_driver = { - .probe = hi3660_clk_probe, + .probe = hisi_clk_probe, + .remove = hisi_clk_remove, .driver = { .name = "hi3660-clk", .of_match_table = hi3660_clk_match_table, }, }; -static int __init hi3660_clk_init(void) -{ - return platform_driver_register(&hi3660_clk_driver); -} -core_initcall(hi3660_clk_init); +module_platform_driver(hi3660_clk_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("HiSilicon Hi3660 Clock Driver"); From patchwork Mon Apr 10 11:07:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yangfl X-Patchwork-Id: 81476 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1831341vqo; Mon, 10 Apr 2023 04:36:06 -0700 (PDT) X-Google-Smtp-Source: AKy350bpdzSF2lAK0XkWVUgQZF0C3LEN962INz+ehbIeFg4Lty1NKA4pMzqOlAMVa4+uImqnrsLF X-Received: by 2002:a05:6a20:6d22:b0:cd:1709:8d57 with SMTP id fv34-20020a056a206d2200b000cd17098d57mr12733283pzb.1.1681126565876; Mon, 10 Apr 2023 04:36:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681126565; cv=none; d=google.com; s=arc-20160816; b=ax/RZN6huuRf6neGk0HJu/6tYNlr87fiWblQDCpV9rRGkxKYnvli/ldEW1uiqurPjr //GRAW6K/OEx6PNPsJIOHW4ftPdbI6PLtCqgyfEfWvcjHtKVBvyI/M5Xp+nkkN2HwA6r A8rp9klKgWe6TDT2NTFuv8AJ+OaztKF5BVAmi/+WuFWlgtJx5g3A8B2pljy/ihA0vWT4 88qIY2j5MG8LEo85QOT9esAhYaSsRMTCmiuu/Y9PTC9nLj8FRFhhrxPi1PuLs+oSBZLD ia9ux4ky2v9eSTVOvIlVilMxays18XDZBoAf0AfZT4qmnv81UybyqR5OtJ4kK12Ugf3l kZNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=qwqE0RY+d2Z3fW8hobJjBV2lhIcDbGGn7/wlLPI8IMA=; b=zAgzXDGu7afqg75wWYwN7LXYjr97ReWgO+oW1t5xcr1zp4de+6ggZyIK15jBo3ZLl/ HSQbf/F00+kxuDEZfTV1tux9ZMR+mMy68tAg6Fgnro0nwHxoRqIWPppGL7arTlV368x5 ReY/DoTp+avhrcPjBt2sYFhegccKUtCNORm7mM/IgvE7eg8/1+vLGRG3vRKHsd4NhqUT UQ9b11JAL0gcVSL+Uzks8x1EAE6rLMSQHL3BouSmwdZOaKqNm/kevhwGSe15bi+JvcUI J2kd0M6/ZqcdjyMRXL3UTfR3o9u9yY1hIbt1n0MV0UjpjykBi5J9XtInsp9uJydD+OTU E3Mg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=g+hK0fZB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id y5-20020aa79e05000000b005808bb470a0si10736152pfq.180.2023.04.10.04.35.54; Mon, 10 Apr 2023 04:36:05 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=g+hK0fZB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229869AbjDJLKG (ORCPT + 99 others); Mon, 10 Apr 2023 07:10:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229839AbjDJLKE (ORCPT ); Mon, 10 Apr 2023 07:10:04 -0400 Received: from mail-pj1-x102b.google.com (mail-pj1-x102b.google.com [IPv6:2607:f8b0:4864:20::102b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD80F4EF5; Mon, 10 Apr 2023 04:09:43 -0700 (PDT) Received: by mail-pj1-x102b.google.com with SMTP id w11so4362807pjh.5; Mon, 10 Apr 2023 04:09:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1681124983; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qwqE0RY+d2Z3fW8hobJjBV2lhIcDbGGn7/wlLPI8IMA=; b=g+hK0fZBu96vdO9OZgr2GI9X5HgClJ6FqFVFcTZJ43ncLnCtZGFTr7tNLUXbM+gpTg F/aGfdgx5HpMQjIaHbnU7Z58YiZ6Uh+lWGPYbeCA4BC+2Gx8gLu5qyXmxVJLE+TYYX7Y HEoPhPudKAl5Fcuk38GfXAaRhahBODgGdeAEfgFjY9Aw8vUq5mm3sb72p9zua5NuwrAK BnKmUCa+PayN9D7IGDl5jNrUR8sYVpbpdl4QMzufolDT+co4KqbLwhZ6hz8n1EiaG3DP MiMedpX4ixsnbjXRnQcsfZytaWbbTd1VMeJmnTkAcgwOSRYW1sCH8hvpR0wDq4g9OYcj zv4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681124983; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qwqE0RY+d2Z3fW8hobJjBV2lhIcDbGGn7/wlLPI8IMA=; b=yY/ASk6KQynYQojEZePvyJ6SQm1eIHU1hPfAPrWpoSAfBUUlg/WJBlY6nbHrWbmWSX t3/IgIBkATqWvbFXMR2pD3e6t6eU+RTW0Ze8hXuz6nuBPC4FCyVIHOsciYgXBO4b2ld/ +gXYY3tkBmqifElo68mkIaWSk2gGo72i0Nxek5QzeAF/IXXPATb5y13SV1SGsSOZBYnG /l8mxlXAJIJmAyFRAjhtLwbj7OJUuHsxs4a5AYAowZVqaWEvBftlSsdXgpePfFvVUe2s ur7YHlasVKbr3WEzMsbN4IIcyktaZ2rXMHOJYvsx4iu+axDY0M1m8283fr6HIPkfxE2A zQoA== X-Gm-Message-State: AAQBX9fwvBNX4lt6ByadtqNIi08pj6iyHVFiudytYt49+x5PTqy5lZUC o9eux1xmDxLw7e49XbMpHAAxPkTuFOg98k+Fmsw= X-Received: by 2002:a17:902:d511:b0:1a1:b172:5428 with SMTP id b17-20020a170902d51100b001a1b1725428mr15586562plg.18.1681124983028; Mon, 10 Apr 2023 04:09:43 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.213.201]) by smtp.gmail.com with ESMTPSA id r5-20020a170902be0500b001a076568da9sm7464728pls.216.2023.04.10.04.09.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 04:09:42 -0700 (PDT) From: David Yang To: linux-clk@vger.kernel.org Cc: David Yang , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org Subject: [PATCH v3 09/14] clk: hisilicon: hi3670: Convert into module Date: Mon, 10 Apr 2023 19:07:21 +0800 Message-Id: <20230410110733.192151-10-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230410110733.192151-1-mmyangfl@gmail.com> References: <20230410110733.192151-1-mmyangfl@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762788969516419516?= X-GMAIL-MSGID: =?utf-8?q?1762788969516419516?= Use common helper functions and register clks with a single of_device_id data. Signed-off-by: David Yang --- drivers/clk/hisilicon/clk-hi3670.c | 248 +++++++++-------------------- 1 file changed, 75 insertions(+), 173 deletions(-) diff --git a/drivers/clk/hisilicon/clk-hi3670.c b/drivers/clk/hisilicon/clk-hi3670.c index 4d05a71683a5..2677c0f16586 100644 --- a/drivers/clk/hisilicon/clk-hi3670.c +++ b/drivers/clk/hisilicon/clk-hi3670.c @@ -9,8 +9,11 @@ #include #include +#include +#include #include #include + #include "clk.h" static const struct hisi_fixed_rate_clock hi3670_fixed_rate_clks[] = { @@ -822,195 +825,94 @@ static const struct hisi_gate_clock hi3670_media2_gate_sep_clks[] = { CLK_SET_RATE_PARENT, 0x00, 2, 0, }, }; -static void hi3670_clk_crgctrl_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - - int nr = ARRAY_SIZE(hi3670_fixed_rate_clks) + - ARRAY_SIZE(hi3670_crgctrl_gate_sep_clks) + - ARRAY_SIZE(hi3670_crgctrl_gate_clks) + - ARRAY_SIZE(hi3670_crgctrl_mux_clks) + - ARRAY_SIZE(hi3670_crg_fixed_factor_clks) + - ARRAY_SIZE(hi3670_crgctrl_divider_clks); - - clk_data = hisi_clk_init(np, nr); - if (!clk_data) - return; - - hisi_clk_register_fixed_rate(hi3670_fixed_rate_clks, - ARRAY_SIZE(hi3670_fixed_rate_clks), - clk_data); - hisi_clk_register_gate_sep(hi3670_crgctrl_gate_sep_clks, - ARRAY_SIZE(hi3670_crgctrl_gate_sep_clks), - clk_data); - hisi_clk_register_gate(hi3670_crgctrl_gate_clks, - ARRAY_SIZE(hi3670_crgctrl_gate_clks), - clk_data); - hisi_clk_register_mux(hi3670_crgctrl_mux_clks, - ARRAY_SIZE(hi3670_crgctrl_mux_clks), - clk_data); - hisi_clk_register_fixed_factor(hi3670_crg_fixed_factor_clks, - ARRAY_SIZE(hi3670_crg_fixed_factor_clks), - clk_data); - hisi_clk_register_divider(hi3670_crgctrl_divider_clks, - ARRAY_SIZE(hi3670_crgctrl_divider_clks), - clk_data); -} - -static void hi3670_clk_pctrl_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - int nr = ARRAY_SIZE(hi3670_pctrl_gate_clks); - - clk_data = hisi_clk_init(np, nr); - if (!clk_data) - return; - hisi_clk_register_gate(hi3670_pctrl_gate_clks, - ARRAY_SIZE(hi3670_pctrl_gate_clks), clk_data); -} - -static void hi3670_clk_pmuctrl_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - int nr = ARRAY_SIZE(hi3670_pmu_gate_clks); - - clk_data = hisi_clk_init(np, nr); - if (!clk_data) - return; - - hisi_clk_register_gate(hi3670_pmu_gate_clks, - ARRAY_SIZE(hi3670_pmu_gate_clks), clk_data); -} - -static void hi3670_clk_sctrl_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - int nr = ARRAY_SIZE(hi3670_sctrl_gate_sep_clks) + - ARRAY_SIZE(hi3670_sctrl_gate_clks) + - ARRAY_SIZE(hi3670_sctrl_mux_clks) + - ARRAY_SIZE(hi3670_sctrl_divider_clks); - - clk_data = hisi_clk_init(np, nr); - if (!clk_data) - return; - - hisi_clk_register_gate_sep(hi3670_sctrl_gate_sep_clks, - ARRAY_SIZE(hi3670_sctrl_gate_sep_clks), - clk_data); - hisi_clk_register_gate(hi3670_sctrl_gate_clks, - ARRAY_SIZE(hi3670_sctrl_gate_clks), - clk_data); - hisi_clk_register_mux(hi3670_sctrl_mux_clks, - ARRAY_SIZE(hi3670_sctrl_mux_clks), - clk_data); - hisi_clk_register_divider(hi3670_sctrl_divider_clks, - ARRAY_SIZE(hi3670_sctrl_divider_clks), - clk_data); -} - -static void hi3670_clk_iomcu_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - int nr = ARRAY_SIZE(hi3670_iomcu_gate_sep_clks) + - ARRAY_SIZE(hi3670_iomcu_fixed_factor_clks); - - clk_data = hisi_clk_init(np, nr); - if (!clk_data) - return; - - hisi_clk_register_gate(hi3670_iomcu_gate_sep_clks, - ARRAY_SIZE(hi3670_iomcu_gate_sep_clks), clk_data); - - hisi_clk_register_fixed_factor(hi3670_iomcu_fixed_factor_clks, - ARRAY_SIZE(hi3670_iomcu_fixed_factor_clks), - clk_data); -} - -static void hi3670_clk_media1_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - - int nr = ARRAY_SIZE(hi3670_media1_gate_sep_clks) + - ARRAY_SIZE(hi3670_media1_gate_clks) + - ARRAY_SIZE(hi3670_media1_mux_clks) + - ARRAY_SIZE(hi3670_media1_divider_clks); - - clk_data = hisi_clk_init(np, nr); - if (!clk_data) - return; - - hisi_clk_register_gate_sep(hi3670_media1_gate_sep_clks, - ARRAY_SIZE(hi3670_media1_gate_sep_clks), - clk_data); - hisi_clk_register_gate(hi3670_media1_gate_clks, - ARRAY_SIZE(hi3670_media1_gate_clks), - clk_data); - hisi_clk_register_mux(hi3670_media1_mux_clks, - ARRAY_SIZE(hi3670_media1_mux_clks), - clk_data); - hisi_clk_register_divider(hi3670_media1_divider_clks, - ARRAY_SIZE(hi3670_media1_divider_clks), - clk_data); -} - -static void hi3670_clk_media2_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - - int nr = ARRAY_SIZE(hi3670_media2_gate_sep_clks); - - clk_data = hisi_clk_init(np, nr); - if (!clk_data) - return; - - hisi_clk_register_gate_sep(hi3670_media2_gate_sep_clks, - ARRAY_SIZE(hi3670_media2_gate_sep_clks), - clk_data); -} +static const struct hisi_clocks hi3670_clk_crgctrl_clks = { + .fixed_rate_clks = hi3670_fixed_rate_clks, + .fixed_rate_clks_num = ARRAY_SIZE(hi3670_fixed_rate_clks), + .fixed_factor_clks = hi3670_crg_fixed_factor_clks, + .fixed_factor_clks_num = ARRAY_SIZE(hi3670_crg_fixed_factor_clks), + .mux_clks = hi3670_crgctrl_mux_clks, + .mux_clks_num = ARRAY_SIZE(hi3670_crgctrl_mux_clks), + .divider_clks = hi3670_crgctrl_divider_clks, + .divider_clks_num = ARRAY_SIZE(hi3670_crgctrl_divider_clks), + .gate_clks = hi3670_crgctrl_gate_clks, + .gate_clks_num = ARRAY_SIZE(hi3670_crgctrl_gate_clks), + .gate_sep_clks = hi3670_crgctrl_gate_sep_clks, + .gate_sep_clks_num = ARRAY_SIZE(hi3670_crgctrl_gate_sep_clks), +}; + +static const struct hisi_clocks hi3670_clk_pctrl_clks = { + .gate_clks = hi3670_pctrl_gate_clks, + .gate_clks_num = ARRAY_SIZE(hi3670_pctrl_gate_clks), +}; + +static const struct hisi_clocks hi3670_clk_pmuctrl_clks = { + .gate_clks = hi3670_pmu_gate_clks, + .gate_clks_num = ARRAY_SIZE(hi3670_pmu_gate_clks), +}; + +static const struct hisi_clocks hi3670_clk_sctrl_clks = { + .mux_clks = hi3670_sctrl_mux_clks, + .mux_clks_num = ARRAY_SIZE(hi3670_sctrl_mux_clks), + .divider_clks = hi3670_sctrl_divider_clks, + .divider_clks_num = ARRAY_SIZE(hi3670_sctrl_divider_clks), + .gate_clks = hi3670_sctrl_gate_clks, + .gate_clks_num = ARRAY_SIZE(hi3670_sctrl_gate_clks), + .gate_sep_clks = hi3670_sctrl_gate_sep_clks, + .gate_sep_clks_num = ARRAY_SIZE(hi3670_sctrl_gate_sep_clks), +}; + +static const struct hisi_clocks hi3670_clk_iomcu_clks = { + .fixed_factor_clks = hi3670_iomcu_fixed_factor_clks, + .fixed_factor_clks_num = ARRAY_SIZE(hi3670_iomcu_fixed_factor_clks), + .gate_clks = hi3670_iomcu_gate_sep_clks, + .gate_clks_num = ARRAY_SIZE(hi3670_iomcu_gate_sep_clks), +}; + +static const struct hisi_clocks hi3670_clk_media1_clks = { + .mux_clks = hi3670_media1_mux_clks, + .mux_clks_num = ARRAY_SIZE(hi3670_media1_mux_clks), + .divider_clks = hi3670_media1_divider_clks, + .divider_clks_num = ARRAY_SIZE(hi3670_media1_divider_clks), + .gate_clks = hi3670_media1_gate_clks, + .gate_clks_num = ARRAY_SIZE(hi3670_media1_gate_clks), + .gate_sep_clks = hi3670_media1_gate_sep_clks, + .gate_sep_clks_num = ARRAY_SIZE(hi3670_media1_gate_sep_clks), +}; + +static const struct hisi_clocks hi3670_clk_media2_clks = { + .gate_sep_clks = hi3670_media2_gate_sep_clks, + .gate_sep_clks_num = ARRAY_SIZE(hi3670_media2_gate_sep_clks), +}; static const struct of_device_id hi3670_clk_match_table[] = { { .compatible = "hisilicon,hi3670-crgctrl", - .data = hi3670_clk_crgctrl_init }, + .data = &hi3670_clk_crgctrl_clks }, { .compatible = "hisilicon,hi3670-pctrl", - .data = hi3670_clk_pctrl_init }, + .data = &hi3670_clk_pctrl_clks }, { .compatible = "hisilicon,hi3670-pmuctrl", - .data = hi3670_clk_pmuctrl_init }, + .data = &hi3670_clk_pmuctrl_clks }, { .compatible = "hisilicon,hi3670-sctrl", - .data = hi3670_clk_sctrl_init }, + .data = &hi3670_clk_sctrl_clks }, { .compatible = "hisilicon,hi3670-iomcu", - .data = hi3670_clk_iomcu_init }, + .data = &hi3670_clk_iomcu_clks }, { .compatible = "hisilicon,hi3670-media1-crg", - .data = hi3670_clk_media1_init }, + .data = &hi3670_clk_media1_clks }, { .compatible = "hisilicon,hi3670-media2-crg", - .data = hi3670_clk_media2_init }, + .data = &hi3670_clk_media2_clks }, { } }; - -static int hi3670_clk_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct device_node *np = pdev->dev.of_node; - void (*init_func)(struct device_node *np); - - init_func = of_device_get_match_data(dev); - if (!init_func) - return -ENODEV; - - init_func(np); - - return 0; -} +MODULE_DEVICE_TABLE(of, hi3670_clk_match_table); static struct platform_driver hi3670_clk_driver = { - .probe = hi3670_clk_probe, + .probe = hisi_clk_probe, + .remove = hisi_clk_remove, .driver = { .name = "hi3670-clk", .of_match_table = hi3670_clk_match_table, }, }; -static int __init hi3670_clk_init(void) -{ - return platform_driver_register(&hi3670_clk_driver); -} -core_initcall(hi3670_clk_init); +module_platform_driver(hi3670_clk_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("HiSilicon Hi3670 Clock Driver"); From patchwork Mon Apr 10 11:07:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yangfl X-Patchwork-Id: 81479 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1832792vqo; Mon, 10 Apr 2023 04:39:20 -0700 (PDT) X-Google-Smtp-Source: AKy350ZOLzDc/wT/3lhyydYcs6sTEYurqqKpuXs/aTBD06rgmJ22yuRLui0O/Yt9W1vyg6dPv8nL X-Received: by 2002:a50:ed08:0:b0:504:a29c:3989 with SMTP id j8-20020a50ed08000000b00504a29c3989mr2181949eds.37.1681126760660; Mon, 10 Apr 2023 04:39:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681126760; cv=none; d=google.com; s=arc-20160816; b=CDz+dnX+K3o8h8u7acQKnCAX14y8FnqcphR3kes5a2iaWrvdKdMe9xw6u9tnz6fwdu QLcxBVYkKwdJ72EqmlG94O4EjuB7/x/yGw9+n2Xnxrpvg2oSgPE0qm4L8eeqPxMWBYPa 3xYGeDXou0OLKdzPebqWNsknxZ0zboEWSUG4S6cD8vc4izYCw/PtDBwZVCxhuaWcXzrT Nhntub4iD3zXiVPwPSL5k9eitTu3x07drndr/peGVlvNSWsSKT3JbGhAPz4YalE5+2J4 Y5h/QEaIsCLtjnpz/Xo2b7aG47NNzaBEdQXejsGu8939rTE9ANwmVoHVtbqGfAhxFFfO y19Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=d8THw7JnJanTYN5Mzg50ak80LMXfCHljznWSdJ2R52o=; b=YXs+NcyeoogWErD8lyXk0jkCcWEDBspR4/Mpm1lhC0RKiU3T6SOZgoMXWrgn7polWW 92MaiDGGr0W6z7invTXn3W/M9tNiR5uBAOocLaMAFlbrhMG+esOf5pnIVosN6jp3SPLP 28brwF1uuYRIPZD+3T+eXDiAmeqZlTt0mZRI4ynFbDFShjbGBE66IXy9R6cQcnXiTuIC bke+yt44G8JBX4Jw4j+lpS5ADQRvOh+a7uAAOYVfalG6CrXl/rHrnuqw3VJgbyZxnlb0 EjUu7P5IVEhzu/uXN+/lv32OtSsD6Y9vLdNvvYAk9bCCX9YpdCt32qXSBKaWHnGefAGT OY/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=nQ3uGdQP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id t10-20020a17090605ca00b0094a8a93302esi1777299ejt.596.2023.04.10.04.38.56; Mon, 10 Apr 2023 04:39:20 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=nQ3uGdQP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229841AbjDJLKR (ORCPT + 99 others); Mon, 10 Apr 2023 07:10:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57560 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229864AbjDJLKP (ORCPT ); Mon, 10 Apr 2023 07:10:15 -0400 Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 198485FDF; Mon, 10 Apr 2023 04:09:57 -0700 (PDT) Received: by mail-pj1-x102f.google.com with SMTP id c3so4791254pjg.1; Mon, 10 Apr 2023 04:09:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1681124996; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=d8THw7JnJanTYN5Mzg50ak80LMXfCHljznWSdJ2R52o=; b=nQ3uGdQPuHWOy4+3+Bj7HH/gwg3VDoIyru+LSV+JW0wY+eEULQhqjC07pEW79inaUg 5uYYoU9DOCv7YKRVBi8u+N+5HOuHRRKpeehmUrMXOEFuEVI7wKo7WD/gOugYZK4wxp56 KunEZQXR+BdEDEpwGxBNQhYsS5qdzB86K9PdEvPkmPAuJSZwnUez4AAOxcm2EXq+NIr2 BoZPHkszAIBf+5heFtkfnQMlAlOZwbzUjNTCQ+qshyMv8lyUagx59pnvRNdLmYhBh+C9 R4mdBoq9CEasMdvkcspffVN0wzlsJglTefOIY7Yus3gi4MvnjlFKTK504vq1WWhyP5RB ebNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681124996; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d8THw7JnJanTYN5Mzg50ak80LMXfCHljznWSdJ2R52o=; b=I1P30nEfbqa6kN2jRSNNAamU1kr/Wqbw9oX3Kf8y+4PNPDE+rZVyBxJj0Sp1TMMU/i 6NZVIc8NfUSZvSGLHUrGWdDtSqkZJNvUk4xqko1TayAPCubA/U7DuoreiMehNtv7jxKN EM0Qv7E7y5qQZ2jbvXji5lVfmdkyrFqMl2O776Ig4XVp1yvR3EtZ1JKbB/Cc9czXbcRK 47cXjuaLOA1VwfnYPB9X1lyWZcm9dTlLzvd5xofe+2/empFATLBexT3cXPjGOyyCW99U R1tsNeT2wHUTOQj2p4b70tgM8GKtCPoRuKvpFY4N75C0dh6sIkSsafK6kK5uekIJC+73 ysFA== X-Gm-Message-State: AAQBX9deOVrD5y/6gidJL/cfpkH0uFsz2qmDd5kSmmn+dCsiFU/8tv2L 1dLCG176OgiULTi7+fzUcZT9d8QV8LBo19TIquc= X-Received: by 2002:a17:902:d488:b0:19a:9610:b234 with SMTP id c8-20020a170902d48800b0019a9610b234mr12178694plg.1.1681124996166; Mon, 10 Apr 2023 04:09:56 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.213.201]) by smtp.gmail.com with ESMTPSA id r5-20020a170902be0500b001a076568da9sm7464728pls.216.2023.04.10.04.09.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 04:09:55 -0700 (PDT) From: David Yang To: linux-clk@vger.kernel.org Cc: David Yang , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org Subject: [PATCH v3 10/14] clk: hisilicon: hi3620: Convert into platform driver module Date: Mon, 10 Apr 2023 19:07:22 +0800 Message-Id: <20230410110733.192151-11-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230410110733.192151-1-mmyangfl@gmail.com> References: <20230410110733.192151-1-mmyangfl@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762789174137629726?= X-GMAIL-MSGID: =?utf-8?q?1762789174137629726?= Use common helper functions and register clks with a single of_device_id data. Signed-off-by: David Yang --- drivers/clk/hisilicon/clk-hi3620.c | 189 +++++++++++++++-------------- 1 file changed, 96 insertions(+), 93 deletions(-) diff --git a/drivers/clk/hisilicon/clk-hi3620.c b/drivers/clk/hisilicon/clk-hi3620.c index a3d04c7c3da8..464b7887415c 100644 --- a/drivers/clk/hisilicon/clk-hi3620.c +++ b/drivers/clk/hisilicon/clk-hi3620.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -22,48 +23,48 @@ #include "clk.h" /* clock parent list */ -static const char *const timer0_mux_p[] __initconst = { "osc32k", "timerclk01", }; -static const char *const timer1_mux_p[] __initconst = { "osc32k", "timerclk01", }; -static const char *const timer2_mux_p[] __initconst = { "osc32k", "timerclk23", }; -static const char *const timer3_mux_p[] __initconst = { "osc32k", "timerclk23", }; -static const char *const timer4_mux_p[] __initconst = { "osc32k", "timerclk45", }; -static const char *const timer5_mux_p[] __initconst = { "osc32k", "timerclk45", }; -static const char *const timer6_mux_p[] __initconst = { "osc32k", "timerclk67", }; -static const char *const timer7_mux_p[] __initconst = { "osc32k", "timerclk67", }; -static const char *const timer8_mux_p[] __initconst = { "osc32k", "timerclk89", }; -static const char *const timer9_mux_p[] __initconst = { "osc32k", "timerclk89", }; -static const char *const uart0_mux_p[] __initconst = { "osc26m", "pclk", }; -static const char *const uart1_mux_p[] __initconst = { "osc26m", "pclk", }; -static const char *const uart2_mux_p[] __initconst = { "osc26m", "pclk", }; -static const char *const uart3_mux_p[] __initconst = { "osc26m", "pclk", }; -static const char *const uart4_mux_p[] __initconst = { "osc26m", "pclk", }; -static const char *const spi0_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", }; -static const char *const spi1_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", }; -static const char *const spi2_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", }; +static const char *const timer0_mux_p[] = { "osc32k", "timerclk01", }; +static const char *const timer1_mux_p[] = { "osc32k", "timerclk01", }; +static const char *const timer2_mux_p[] = { "osc32k", "timerclk23", }; +static const char *const timer3_mux_p[] = { "osc32k", "timerclk23", }; +static const char *const timer4_mux_p[] = { "osc32k", "timerclk45", }; +static const char *const timer5_mux_p[] = { "osc32k", "timerclk45", }; +static const char *const timer6_mux_p[] = { "osc32k", "timerclk67", }; +static const char *const timer7_mux_p[] = { "osc32k", "timerclk67", }; +static const char *const timer8_mux_p[] = { "osc32k", "timerclk89", }; +static const char *const timer9_mux_p[] = { "osc32k", "timerclk89", }; +static const char *const uart0_mux_p[] = { "osc26m", "pclk", }; +static const char *const uart1_mux_p[] = { "osc26m", "pclk", }; +static const char *const uart2_mux_p[] = { "osc26m", "pclk", }; +static const char *const uart3_mux_p[] = { "osc26m", "pclk", }; +static const char *const uart4_mux_p[] = { "osc26m", "pclk", }; +static const char *const spi0_mux_p[] = { "osc26m", "rclk_cfgaxi", }; +static const char *const spi1_mux_p[] = { "osc26m", "rclk_cfgaxi", }; +static const char *const spi2_mux_p[] = { "osc26m", "rclk_cfgaxi", }; /* share axi parent */ -static const char *const saxi_mux_p[] __initconst = { "armpll3", "armpll2", }; -static const char *const pwm0_mux_p[] __initconst = { "osc32k", "osc26m", }; -static const char *const pwm1_mux_p[] __initconst = { "osc32k", "osc26m", }; -static const char *const sd_mux_p[] __initconst = { "armpll2", "armpll3", }; -static const char *const mmc1_mux_p[] __initconst = { "armpll2", "armpll3", }; -static const char *const mmc1_mux2_p[] __initconst = { "osc26m", "mmc1_div", }; -static const char *const g2d_mux_p[] __initconst = { "armpll2", "armpll3", }; -static const char *const venc_mux_p[] __initconst = { "armpll2", "armpll3", }; -static const char *const vdec_mux_p[] __initconst = { "armpll2", "armpll3", }; -static const char *const vpp_mux_p[] __initconst = { "armpll2", "armpll3", }; -static const char *const edc0_mux_p[] __initconst = { "armpll2", "armpll3", }; -static const char *const ldi0_mux_p[] __initconst = { "armpll2", "armpll4", +static const char *const saxi_mux_p[] = { "armpll3", "armpll2", }; +static const char *const pwm0_mux_p[] = { "osc32k", "osc26m", }; +static const char *const pwm1_mux_p[] = { "osc32k", "osc26m", }; +static const char *const sd_mux_p[] = { "armpll2", "armpll3", }; +static const char *const mmc1_mux_p[] = { "armpll2", "armpll3", }; +static const char *const mmc1_mux2_p[] = { "osc26m", "mmc1_div", }; +static const char *const g2d_mux_p[] = { "armpll2", "armpll3", }; +static const char *const venc_mux_p[] = { "armpll2", "armpll3", }; +static const char *const vdec_mux_p[] = { "armpll2", "armpll3", }; +static const char *const vpp_mux_p[] = { "armpll2", "armpll3", }; +static const char *const edc0_mux_p[] = { "armpll2", "armpll3", }; +static const char *const ldi0_mux_p[] = { "armpll2", "armpll4", "armpll3", "armpll5", }; -static const char *const edc1_mux_p[] __initconst = { "armpll2", "armpll3", }; -static const char *const ldi1_mux_p[] __initconst = { "armpll2", "armpll4", +static const char *const edc1_mux_p[] = { "armpll2", "armpll3", }; +static const char *const ldi1_mux_p[] = { "armpll2", "armpll4", "armpll3", "armpll5", }; -static const char *const rclk_hsic_p[] __initconst = { "armpll3", "armpll2", }; -static const char *const mmc2_mux_p[] __initconst = { "armpll2", "armpll3", }; -static const char *const mmc3_mux_p[] __initconst = { "armpll2", "armpll3", }; +static const char *const rclk_hsic_p[] = { "armpll3", "armpll2", }; +static const char *const mmc2_mux_p[] = { "armpll2", "armpll3", }; +static const char *const mmc3_mux_p[] = { "armpll2", "armpll3", }; /* fixed rate clocks */ -static struct hisi_fixed_rate_clock hi3620_fixed_rate_clks[] __initdata = { +static struct hisi_fixed_rate_clock hi3620_fixed_rate_clks[] = { { HI3620_OSC32K, "osc32k", NULL, 0, 32768, }, { HI3620_OSC26M, "osc26m", NULL, 0, 26000000, }, { HI3620_PCLK, "pclk", NULL, 0, 26000000, }, @@ -76,13 +77,13 @@ static struct hisi_fixed_rate_clock hi3620_fixed_rate_clks[] __initdata = { }; /* fixed factor clocks */ -static struct hisi_fixed_factor_clock hi3620_fixed_factor_clks[] __initdata = { +static struct hisi_fixed_factor_clock hi3620_fixed_factor_clks[] = { { HI3620_RCLK_TCXO, "rclk_tcxo", "osc26m", 1, 4, 0, }, { HI3620_RCLK_CFGAXI, "rclk_cfgaxi", "armpll2", 1, 30, 0, }, { HI3620_RCLK_PICO, "rclk_pico", "hsic_div", 1, 40, 0, }, }; -static struct hisi_mux_clock hi3620_mux_clks[] __initdata = { +static struct hisi_mux_clock hi3620_mux_clks[] = { { HI3620_TIMER0_MUX, "timer0_mux", timer0_mux_p, ARRAY_SIZE(timer0_mux_p), CLK_SET_RATE_PARENT, 0, 15, 2, 0, }, { HI3620_TIMER1_MUX, "timer1_mux", timer1_mux_p, ARRAY_SIZE(timer1_mux_p), CLK_SET_RATE_PARENT, 0, 17, 2, 0, }, { HI3620_TIMER2_MUX, "timer2_mux", timer2_mux_p, ARRAY_SIZE(timer2_mux_p), CLK_SET_RATE_PARENT, 0, 19, 2, 0, }, @@ -120,7 +121,7 @@ static struct hisi_mux_clock hi3620_mux_clks[] __initdata = { { HI3620_MMC3_MUX, "mmc3_mux", mmc3_mux_p, ARRAY_SIZE(mmc3_mux_p), CLK_SET_RATE_PARENT, 0x140, 9, 1, CLK_MUX_HIWORD_MASK, }, }; -static struct hisi_divider_clock hi3620_div_clks[] __initdata = { +static struct hisi_divider_clock hi3620_div_clks[] = { { HI3620_SHAREAXI_DIV, "saxi_div", "saxi_mux", 0, 0x100, 0, 5, CLK_DIVIDER_HIWORD_MASK, NULL, }, { HI3620_CFGAXI_DIV, "cfgaxi_div", "saxi_div", 0, 0x100, 5, 2, CLK_DIVIDER_HIWORD_MASK, NULL, }, { HI3620_SD_DIV, "sd_div", "sd_mux", 0, 0x108, 0, 4, CLK_DIVIDER_HIWORD_MASK, NULL, }, @@ -130,7 +131,7 @@ static struct hisi_divider_clock hi3620_div_clks[] __initdata = { { HI3620_MMC3_DIV, "mmc3_div", "mmc3_mux", 0, 0x140, 5, 4, CLK_DIVIDER_HIWORD_MASK, NULL, }, }; -static struct hisi_gate_clock hi3620_separated_gate_clks[] __initdata = { +static struct hisi_gate_clock hi3620_separated_gate_clks[] = { { HI3620_TIMERCLK01, "timerclk01", "timer_rclk01", CLK_SET_RATE_PARENT, 0x20, 0, 0, }, { HI3620_TIMER_RCLK01, "timer_rclk01", "rclk_tcxo", CLK_SET_RATE_PARENT, 0x20, 1, 0, }, { HI3620_TIMERCLK23, "timerclk23", "timer_rclk23", CLK_SET_RATE_PARENT, 0x20, 2, 0, }, @@ -192,29 +193,19 @@ static struct hisi_gate_clock hi3620_separated_gate_clks[] __initdata = { { HI3620_MCU_CLK, "mcu_clk", "acp_clk", CLK_SET_RATE_PARENT, 0x50, 24, 0, }, }; -static void __init hi3620_clk_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - - clk_data = hisi_clk_init(np, HI3620_NR_CLKS); - if (!clk_data) - return; - - hisi_clk_register_fixed_rate(hi3620_fixed_rate_clks, - ARRAY_SIZE(hi3620_fixed_rate_clks), - clk_data); - hisi_clk_register_fixed_factor(hi3620_fixed_factor_clks, - ARRAY_SIZE(hi3620_fixed_factor_clks), - clk_data); - hisi_clk_register_mux(hi3620_mux_clks, ARRAY_SIZE(hi3620_mux_clks), - clk_data); - hisi_clk_register_divider(hi3620_div_clks, ARRAY_SIZE(hi3620_div_clks), - clk_data); - hisi_clk_register_gate_sep(hi3620_separated_gate_clks, - ARRAY_SIZE(hi3620_separated_gate_clks), - clk_data); -} -CLK_OF_DECLARE(hi3620_clk, "hisilicon,hi3620-clock", hi3620_clk_init); +static const struct hisi_clocks hi3620_clks = { + .nr = HI3620_NR_CLKS, + .fixed_rate_clks = hi3620_fixed_rate_clks, + .fixed_rate_clks_num = ARRAY_SIZE(hi3620_fixed_rate_clks), + .fixed_factor_clks = hi3620_fixed_factor_clks, + .fixed_factor_clks_num = ARRAY_SIZE(hi3620_fixed_factor_clks), + .mux_clks = hi3620_mux_clks, + .mux_clks_num = ARRAY_SIZE(hi3620_mux_clks), + .divider_clks = hi3620_div_clks, + .divider_clks_num = ARRAY_SIZE(hi3620_div_clks), + .gate_sep_clks = hi3620_separated_gate_clks, + .gate_sep_clks_num = ARRAY_SIZE(hi3620_separated_gate_clks), +}; struct hisi_mmc_clock { unsigned int id; @@ -252,7 +243,7 @@ struct clk_mmc { #define to_mmc(_hw) container_of(_hw, struct clk_mmc, hw) -static struct hisi_mmc_clock hi3620_mmc_clks[] __initdata = { +static struct hisi_mmc_clock hi3620_mmc_clks[] = { { HI3620_SD_CIUCLK, "sd_bclk1", "sd_clk", CLK_SET_RATE_PARENT, 0x1f8, 0, 0x1f8, 1, 3, 0x1f8, 4, 4, 0x1f8, 8, 4}, { HI3620_MMC_CIUCLK1, "mmc_bclk1", "mmc_clk1", CLK_SET_RATE_PARENT, 0x1f8, 12, 0x1f8, 13, 3, 0x1f8, 16, 4, 0x1f8, 20, 4}, { HI3620_MMC_CIUCLK2, "mmc_bclk2", "mmc_clk2", CLK_SET_RATE_PARENT, 0x1f8, 24, 0x1f8, 25, 3, 0x1f8, 28, 4, 0x1fc, 0, 4}, @@ -408,8 +399,9 @@ static const struct clk_ops clk_mmc_ops = { .recalc_rate = mmc_clk_recalc_rate, }; -static struct clk *hisi_register_clk_mmc(struct hisi_mmc_clock *mmc_clk, - void __iomem *base, struct device_node *np) +static struct clk * +clk_register_hisi_mmc(struct device *dev, const struct hisi_mmc_clock *mmc_clk, + void __iomem *base) { struct clk_mmc *mclk; struct clk *clk; @@ -445,39 +437,50 @@ static struct clk *hisi_register_clk_mmc(struct hisi_mmc_clock *mmc_clk, return clk; } -static void __init hi3620_mmc_clk_init(struct device_node *node) +static int hisi_register_clk_mmc(struct device *dev, const void *clocks, + size_t num, struct hisi_clock_data *data) { - void __iomem *base; - int i, num = ARRAY_SIZE(hi3620_mmc_clks); - struct clk_onecell_data *clk_data; + const struct hisi_mmc_clock *clks = clocks; - if (!node) { - pr_err("failed to find pctrl node in DTS\n"); - return; - } + for (int i = 0; i < num; i++) { + struct clk *clk = clk_register_hisi_mmc(dev, &clks[i], data->base); - base = of_iomap(node, 0); - if (!base) { - pr_err("failed to map pctrl\n"); - return; + if (IS_ERR(clk)) { + pr_err("%s: failed to register clock %s\n", + __func__, clks[i].name); + return PTR_ERR(clk); + } + data->clk_data.clks[clks[i].id] = clk; } - clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL); - if (WARN_ON(!clk_data)) - return; + return 0; +} - clk_data->clks = kcalloc(num, sizeof(*clk_data->clks), GFP_KERNEL); - if (!clk_data->clks) - return; +static const struct hisi_clocks hi3620_clks_mmc = { + .customized_clks = hi3620_mmc_clks, + .customized_clks_num = ARRAY_SIZE(hi3620_mmc_clks), + .clk_register_customized = hisi_register_clk_mmc, +}; - for (i = 0; i < num; i++) { - struct hisi_mmc_clock *mmc_clk = &hi3620_mmc_clks[i]; - clk_data->clks[mmc_clk->id] = - hisi_register_clk_mmc(mmc_clk, base, node); - } +static const struct of_device_id hi3620_clk_match_table[] = { + { .compatible = "hisilicon,hi3620-clock", + .data = &hi3620_clks }, + { .compatible = "hisilicon,hi3620-mmc-clock", + .data = &hi3620_clks_mmc }, + { } +}; +MODULE_DEVICE_TABLE(of, hi3620_clk_match_table); + +static struct platform_driver hi3620_clk_driver = { + .probe = hisi_clk_probe, + .remove = hisi_clk_remove, + .driver = { + .name = "hi3620-clock", + .of_match_table = hi3620_clk_match_table, + }, +}; - clk_data->clk_num = num; - of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); -} +module_platform_driver(hi3620_clk_driver); -CLK_OF_DECLARE(hi3620_mmc_clk, "hisilicon,hi3620-mmc-clock", hi3620_mmc_clk_init); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("HiSilicon Hi3620 Clock Driver"); From patchwork Mon Apr 10 11:07:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yangfl X-Patchwork-Id: 81469 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1818872vqo; Mon, 10 Apr 2023 04:11:25 -0700 (PDT) X-Google-Smtp-Source: AKy350b95UEyhC0ijjEUoRadeNgXXDs2uynPet3bXLLl3ctROpv36C985V/upjtFyenVB8cQNDyv X-Received: by 2002:a17:902:dac3:b0:1a6:4e7b:702d with SMTP id q3-20020a170902dac300b001a64e7b702dmr207699plx.42.1681125084828; Mon, 10 Apr 2023 04:11:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681125084; cv=none; d=google.com; s=arc-20160816; b=XgxqVXhoDNYP1TOA1MzK8PNdlj6UFRJ+HHV7ZedkK55Zh52GBbVEZR+cy1VLjL9C1j x1As9wOJsF9AIZntVflOGEMJLesHl3gJKykGjSSAMSS4fMGxdPZw7H3N3h3BzIrKcK59 dfkbIjpD3j0o9OO+ze3u2TT+BWGV9sdJvvomZEJQ6IkPhSTNtMg3Xt/YocPkESFJT1ak 9E4HW3beB1wKPy0BXF+SRAs3Lr+2afGnN3DDIBrSq7bYetRE3uKbuYt0GqZi36CtnXcZ s5sja/XFyyZHq87BfH11He6wlOITqqzx+0Eq+gQecNE+3MHsMLFDh0bn4belhRUMZZqk l1ww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=w3Z/cKsqQ3XSBYGRPGVO1JYi/6hdlwVlc0ZqunEW/Cc=; b=d+1CClw1N2jhXp0zUI4kOKqqw5InNkCALoT/+ii5v7gKfK7fgxRtJA6MG5SQ4gYUc4 5HF4VxXmoN3mrJAg9PYH5WnIHPvienK0jjdYLzqLx+EwXPkQ+zQK3EN9SguJL5stvwjB 05x8JHvd1J6byw2MOnT5e32fExcPhGQ8N1J3J/BKphFBAm+Y3oxm/QH+8pRI6LqOFr9v a69D242DowCu3wKjffrHC9HJ5TEuE1f8r19bsk2kA0utQWxRLHiI9fFUur/iUoEHRwwN Rp2QsBrKRcIKSjppR0aSQnrJfx/6vv1Vi7UeeOnqWWeouu0itD0R+vWSb1qQvqKhfXqr zylg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=LMLChRTl; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id r24-20020a63ce58000000b00513b3372e2csi10184501pgi.586.2023.04.10.04.11.12; Mon, 10 Apr 2023 04:11:24 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=LMLChRTl; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229882AbjDJLKm (ORCPT + 99 others); Mon, 10 Apr 2023 07:10:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58108 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229871AbjDJLKk (ORCPT ); Mon, 10 Apr 2023 07:10:40 -0400 Received: from mail-pj1-x1033.google.com (mail-pj1-x1033.google.com [IPv6:2607:f8b0:4864:20::1033]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 91351E4C; Mon, 10 Apr 2023 04:10:11 -0700 (PDT) Received: by mail-pj1-x1033.google.com with SMTP id c3so4791750pjg.1; Mon, 10 Apr 2023 04:10:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1681125009; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=w3Z/cKsqQ3XSBYGRPGVO1JYi/6hdlwVlc0ZqunEW/Cc=; b=LMLChRTlheSCDu/eGnlpGwXbdyYCqCgc0HbvZruBnxzqtk/xW24wYOey4eNvc3ZW2w C7Y+q6XMhYqSmc0htO0yY2p4DUxARt7Z9JtcMOubM5MfrZIm/c8A0QlherELjBIVNCEX Tb3bxdtx0c2qlILpWiXonoa4PD1Owx40ATx6FxWjuFcZbeB7SHegb0EHtz55ZWLdp3jv HWR+8CbnyDsDgj99LF1Q+VeHxUnfV/NO4vvboh1/w/jAOQAKa8IRW0hAss8zKwubBkXE +Ma5uRo6/OxoOxT0tCVe0WIVbeWVVqV+CJZ+hMDUT4EFDAA45NUg2fJq5H3NxQBfZglM CRTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681125009; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=w3Z/cKsqQ3XSBYGRPGVO1JYi/6hdlwVlc0ZqunEW/Cc=; b=uqet8RHO86Li44mINQM07jyBFsyHpCkt45dYZ2E3f4dkFrhsfYewZHy9CDPSLHSn+O bXFA+bWOQ2bDFE+zyfmRbuxZylJmADwKnPSqaQT6YwqFvBY1k8kmqjlg7wBZwsD9sMxF 6WSMXBbSqa0A58vA3FD/12bU48m7YWG0HLciuCC1B78H+o8cgS4atiGJMx+hYydn9c4p 5qoTAi0QBEN+KtzuD4Heqrwj0gjZ6ua1Fugp9BQMHClCeFD/entYhiRHLOpj+IoS8H9E EKxTP2xl08UqPaJIxCbkLQxnkJCsPt76b57SfKRRmjlzUQhX0jIMRn9UKI8JpsRi+zCH iyZg== X-Gm-Message-State: AAQBX9d1HTrapsQwsjs+Frt7OeH63NYGAqQWXC2YHT2Gw1AXgO1ufZiz vgmpWOfilOkSxvDnJOaIuXs3dAL3wSEhnjpQflA= X-Received: by 2002:a17:903:2810:b0:1a3:c8a9:7eff with SMTP id kp16-20020a170903281000b001a3c8a97effmr9752703plb.55.1681125009592; Mon, 10 Apr 2023 04:10:09 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.213.201]) by smtp.gmail.com with ESMTPSA id r5-20020a170902be0500b001a076568da9sm7464728pls.216.2023.04.10.04.10.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 04:10:09 -0700 (PDT) From: David Yang To: linux-clk@vger.kernel.org Cc: David Yang , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org Subject: [PATCH v3 11/14] clk: hisilicon: hi6220: Convert into platform driver module Date: Mon, 10 Apr 2023 19:07:23 +0800 Message-Id: <20230410110733.192151-12-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230410110733.192151-1-mmyangfl@gmail.com> References: <20230410110733.192151-1-mmyangfl@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762787417207258940?= X-GMAIL-MSGID: =?utf-8?q?1762787417207258940?= Use common helper functions and register clks with a single of_device_id data. Signed-off-by: David Yang --- drivers/clk/hisilicon/clk-hi6220.c | 231 ++++++++++++++--------------- 1 file changed, 112 insertions(+), 119 deletions(-) diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c index e7cdf72d4b06..edf83e996bd5 100644 --- a/drivers/clk/hisilicon/clk-hi6220.c +++ b/drivers/clk/hisilicon/clk-hi6220.c @@ -9,20 +9,24 @@ #include #include -#include -#include -#include -#include +#include #include -#include #include #include "clk.h" +static int +hi6220_clk_register_divider_stub(struct device *dev, const void *clks, + size_t num, struct hisi_clock_data *data) +{ + /* INCOMPLETE PATCH */ + hi6220_clk_register_divider(clks, num, data); + return 0; +} /* clocks in AO (always on) controller */ -static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = { +static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] = { { HI6220_REF32K, "ref32k", NULL, 0, 32764, }, { HI6220_CLK_TCXO, "clk_tcxo", NULL, 0, 19200000, }, { HI6220_MMC1_PAD, "mmc1_pad", NULL, 0, 100000000, }, @@ -38,7 +42,7 @@ static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = { { HI6220_PLL_DDR, "ddrpll0", NULL, 0, 1600000000,}, }; -static struct hisi_fixed_factor_clock hi6220_fixed_factor_clks[] __initdata = { +static struct hisi_fixed_factor_clock hi6220_fixed_factor_clks[] = { { HI6220_300M, "clk_300m", "syspll", 1, 4, 0, }, { HI6220_150M, "clk_150m", "clk_300m", 1, 2, 0, }, { HI6220_PICOPHY_SRC, "picophy_src", "clk_150m", 1, 4, 0, }, @@ -51,7 +55,7 @@ static struct hisi_fixed_factor_clock hi6220_fixed_factor_clks[] __initdata = { { HI6220_MMC2_SMP, "mmc2_sample", "mmc2_sel", 1, 8, 0, }, }; -static struct hisi_gate_clock hi6220_separated_gate_clks_ao[] __initdata = { +static struct hisi_gate_clock hi6220_separated_gate_clks_ao[] = { { HI6220_WDT0_PCLK, "wdt0_pclk", "ref32k", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 12, 0, }, { HI6220_WDT1_PCLK, "wdt1_pclk", "ref32k", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 13, 0, }, { HI6220_WDT2_PCLK, "wdt2_pclk", "ref32k", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 14, 0, }, @@ -69,47 +73,43 @@ static struct hisi_gate_clock hi6220_separated_gate_clks_ao[] __initdata = { { HI6220_RTC1_PCLK, "rtc1_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 26, 0, }, }; -static void __init hi6220_clk_ao_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data_ao; - - clk_data_ao = hisi_clk_init(np, HI6220_AO_NR_CLKS); - if (!clk_data_ao) - return; - - hisi_clk_register_fixed_rate(hi6220_fixed_rate_clks, - ARRAY_SIZE(hi6220_fixed_rate_clks), clk_data_ao); - - hisi_clk_register_fixed_factor(hi6220_fixed_factor_clks, - ARRAY_SIZE(hi6220_fixed_factor_clks), clk_data_ao); +static const struct hisi_clocks hi6220_ao_clks = { + .nr = HI6220_AO_NR_CLKS, + .fixed_rate_clks = hi6220_fixed_rate_clks, + .fixed_rate_clks_num = ARRAY_SIZE(hi6220_fixed_rate_clks), + .fixed_factor_clks = hi6220_fixed_factor_clks, + .fixed_factor_clks_num = ARRAY_SIZE(hi6220_fixed_factor_clks), + .gate_sep_clks = hi6220_separated_gate_clks_ao, + .gate_sep_clks_num = ARRAY_SIZE(hi6220_separated_gate_clks_ao), +}; - hisi_clk_register_gate_sep(hi6220_separated_gate_clks_ao, - ARRAY_SIZE(hi6220_separated_gate_clks_ao), clk_data_ao); +static void hi6220_clk_ao_early_init(struct device_node *np) +{ + hisi_clk_early_init(np, &hi6220_ao_clks); } /* Allow reset driver to probe as well */ -CLK_OF_DECLARE_DRIVER(hi6220_clk_ao, "hisilicon,hi6220-aoctrl", hi6220_clk_ao_init); - +CLK_OF_DECLARE_DRIVER(hi6220_clk_ao, "hisilicon,hi6220-aoctrl", hi6220_clk_ao_early_init); /* clocks in sysctrl */ -static const char *mmc0_mux0_p[] __initdata = { "pll_ddr_gate", "syspll", }; -static const char *mmc0_mux1_p[] __initdata = { "mmc0_mux0", "pll_media_gate", }; -static const char *mmc0_src_p[] __initdata = { "mmc0srcsel", "mmc0_div", }; -static const char *mmc1_mux0_p[] __initdata = { "pll_ddr_gate", "syspll", }; -static const char *mmc1_mux1_p[] __initdata = { "mmc1_mux0", "pll_media_gate", }; -static const char *mmc1_src_p[] __initdata = { "mmc1srcsel", "mmc1_div", }; -static const char *mmc2_mux0_p[] __initdata = { "pll_ddr_gate", "syspll", }; -static const char *mmc2_mux1_p[] __initdata = { "mmc2_mux0", "pll_media_gate", }; -static const char *mmc2_src_p[] __initdata = { "mmc2srcsel", "mmc2_div", }; -static const char *mmc0_sample_in[] __initdata = { "mmc0_sample", "mmc0_pad", }; -static const char *mmc1_sample_in[] __initdata = { "mmc1_sample", "mmc1_pad", }; -static const char *mmc2_sample_in[] __initdata = { "mmc2_sample", "mmc2_pad", }; -static const char *uart1_src[] __initdata = { "clk_tcxo", "clk_150m", }; -static const char *uart2_src[] __initdata = { "clk_tcxo", "clk_150m", }; -static const char *uart3_src[] __initdata = { "clk_tcxo", "clk_150m", }; -static const char *uart4_src[] __initdata = { "clk_tcxo", "clk_150m", }; -static const char *hifi_src[] __initdata = { "syspll", "pll_media_gate", }; - -static struct hisi_gate_clock hi6220_separated_gate_clks_sys[] __initdata = { +static const char *const mmc0_mux0_p[] = { "pll_ddr_gate", "syspll", }; +static const char *const mmc0_mux1_p[] = { "mmc0_mux0", "pll_media_gate", }; +static const char *const mmc0_src_p[] = { "mmc0srcsel", "mmc0_div", }; +static const char *const mmc1_mux0_p[] = { "pll_ddr_gate", "syspll", }; +static const char *const mmc1_mux1_p[] = { "mmc1_mux0", "pll_media_gate", }; +static const char *const mmc1_src_p[] = { "mmc1srcsel", "mmc1_div", }; +static const char *const mmc2_mux0_p[] = { "pll_ddr_gate", "syspll", }; +static const char *const mmc2_mux1_p[] = { "mmc2_mux0", "pll_media_gate", }; +static const char *const mmc2_src_p[] = { "mmc2srcsel", "mmc2_div", }; +static const char *const mmc0_sample_in[] = { "mmc0_sample", "mmc0_pad", }; +static const char *const mmc1_sample_in[] = { "mmc1_sample", "mmc1_pad", }; +static const char *const mmc2_sample_in[] = { "mmc2_sample", "mmc2_pad", }; +static const char *const uart1_src[] = { "clk_tcxo", "clk_150m", }; +static const char *const uart2_src[] = { "clk_tcxo", "clk_150m", }; +static const char *const uart3_src[] = { "clk_tcxo", "clk_150m", }; +static const char *const uart4_src[] = { "clk_tcxo", "clk_150m", }; +static const char *const hifi_src[] = { "syspll", "pll_media_gate", }; + +static struct hisi_gate_clock hi6220_separated_gate_clks_sys[] = { { HI6220_MMC0_CLK, "mmc0_clk", "mmc0_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 0, 0, }, { HI6220_MMC0_CIUCLK, "mmc0_ciuclk", "mmc0_smp_in", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 0, 0, }, { HI6220_MMC1_CLK, "mmc1_clk", "mmc1_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 1, 0, }, @@ -146,7 +146,7 @@ static struct hisi_gate_clock hi6220_separated_gate_clks_sys[] __initdata = { { HI6220_CS_ATB_SYSPLL, "cs_atb_syspll", "syspll", CLK_SET_RATE_PARENT|CLK_IS_CRITICAL, 0x270, 12, 0, }, }; -static struct hisi_mux_clock hi6220_mux_clks_sys[] __initdata = { +static struct hisi_mux_clock hi6220_mux_clks_sys[] = { { HI6220_MMC0_SRC, "mmc0_src", mmc0_src_p, ARRAY_SIZE(mmc0_src_p), CLK_SET_RATE_PARENT, 0x4, 0, 1, 0, }, { HI6220_MMC0_SMP_IN, "mmc0_smp_in", mmc0_sample_in, ARRAY_SIZE(mmc0_sample_in), CLK_SET_RATE_PARENT, 0x4, 0, 1, 0, }, { HI6220_MMC1_SRC, "mmc1_src", mmc1_src_p, ARRAY_SIZE(mmc1_src_p), CLK_SET_RATE_PARENT, 0x4, 2, 1, 0, }, @@ -166,7 +166,7 @@ static struct hisi_mux_clock hi6220_mux_clks_sys[] __initdata = { { HI6220_MMC2_MUX1, "mmc2_mux1", mmc2_mux1_p, ARRAY_SIZE(mmc2_mux1_p), CLK_SET_RATE_PARENT, 0x400, 15, 1, CLK_MUX_HIWORD_MASK,}, }; -static struct hi6220_divider_clock hi6220_div_clks_sys[] __initdata = { +static struct hi6220_divider_clock hi6220_div_clks_sys[] = { { HI6220_CLK_BUS, "clk_bus", "clk_300m", CLK_SET_RATE_PARENT, 0x490, 0, 4, 7, }, { HI6220_MMC0_DIV, "mmc0_div", "mmc0_syspll", CLK_SET_RATE_PARENT, 0x494, 0, 6, 7, }, { HI6220_MMC1_DIV, "mmc1_div", "mmc1_syspll", CLK_SET_RATE_PARENT, 0x498, 0, 6, 7, }, @@ -177,32 +177,23 @@ static struct hi6220_divider_clock hi6220_div_clks_sys[] __initdata = { { HI6220_CS_ATB_DIV, "cs_atb_div", "cs_atb_syspll", CLK_SET_RATE_PARENT, 0x4a4, 0, 4, 7, }, }; -static void __init hi6220_clk_sys_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - - clk_data = hisi_clk_init(np, HI6220_SYS_NR_CLKS); - if (!clk_data) - return; - - hisi_clk_register_gate_sep(hi6220_separated_gate_clks_sys, - ARRAY_SIZE(hi6220_separated_gate_clks_sys), clk_data); - - hisi_clk_register_mux(hi6220_mux_clks_sys, - ARRAY_SIZE(hi6220_mux_clks_sys), clk_data); - - hi6220_clk_register_divider(hi6220_div_clks_sys, - ARRAY_SIZE(hi6220_div_clks_sys), clk_data); -} -CLK_OF_DECLARE_DRIVER(hi6220_clk_sys, "hisilicon,hi6220-sysctrl", hi6220_clk_sys_init); - +static const struct hisi_clocks hi6220_sys_clks = { + .nr = HI6220_SYS_NR_CLKS, + .mux_clks = hi6220_mux_clks_sys, + .mux_clks_num = ARRAY_SIZE(hi6220_mux_clks_sys), + .gate_sep_clks = hi6220_separated_gate_clks_sys, + .gate_sep_clks_num = ARRAY_SIZE(hi6220_separated_gate_clks_sys), + .customized_clks = hi6220_div_clks_sys, + .customized_clks_num = ARRAY_SIZE(hi6220_div_clks_sys), + .clk_register_customized = hi6220_clk_register_divider_stub, +}; /* clocks in media controller */ -static const char *clk_1000_1200_src[] __initdata = { "pll_gpu_gate", "media_syspll_src", }; -static const char *clk_1440_1200_src[] __initdata = { "media_syspll_src", "media_pll_src", }; -static const char *clk_1000_1440_src[] __initdata = { "pll_gpu_gate", "media_pll_src", }; +static const char *const clk_1000_1200_src[] = { "pll_gpu_gate", "media_syspll_src", }; +static const char *const clk_1440_1200_src[] = { "media_syspll_src", "media_pll_src", }; +static const char *const clk_1000_1440_src[] = { "pll_gpu_gate", "media_pll_src", }; -static struct hisi_gate_clock hi6220_separated_gate_clks_media[] __initdata = { +static struct hisi_gate_clock hi6220_separated_gate_clks_media[] = { { HI6220_DSI_PCLK, "dsi_pclk", "vpucodec", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 0, 0, }, { HI6220_G3D_PCLK, "g3d_pclk", "vpucodec", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 1, 0, }, { HI6220_ACLK_CODEC_VPU, "aclk_codec_vpu", "ade_core_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 3, 0, }, @@ -218,13 +209,13 @@ static struct hisi_gate_clock hi6220_separated_gate_clks_media[] __initdata = { { HI6220_MED_SYSPLL, "media_syspll_src", "media_syspll", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 17, 0, }, }; -static struct hisi_mux_clock hi6220_mux_clks_media[] __initdata = { +static struct hisi_mux_clock hi6220_mux_clks_media[] = { { HI6220_1440_1200, "clk_1440_1200", clk_1440_1200_src, ARRAY_SIZE(clk_1440_1200_src), CLK_SET_RATE_PARENT, 0x51c, 0, 1, 0, }, { HI6220_1000_1200, "clk_1000_1200", clk_1000_1200_src, ARRAY_SIZE(clk_1000_1200_src), CLK_SET_RATE_PARENT, 0x51c, 1, 1, 0, }, { HI6220_1000_1440, "clk_1000_1440", clk_1000_1440_src, ARRAY_SIZE(clk_1000_1440_src), CLK_SET_RATE_PARENT, 0x51c, 6, 1, 0, }, }; -static struct hi6220_divider_clock hi6220_div_clks_media[] __initdata = { +static struct hi6220_divider_clock hi6220_div_clks_media[] = { { HI6220_CODEC_JPEG, "codec_jpeg_aclk", "media_pll_src", CLK_SET_RATE_PARENT, 0xcbc, 0, 4, 23, }, { HI6220_ISP_SCLK_SRC, "isp_sclk_src", "isp_sclk_gate", CLK_SET_RATE_PARENT, 0xcbc, 8, 4, 15, }, { HI6220_ISP_SCLK1, "isp_sclk1", "isp_sclk_gate1", CLK_SET_RATE_PARENT, 0xcbc, 24, 4, 31, }, @@ -234,28 +225,19 @@ static struct hi6220_divider_clock hi6220_div_clks_media[] __initdata = { { HI6220_CODEC_VPU_SRC, "codec_vpu_src", "codec_vpu_gate", CLK_SET_RATE_PARENT, 0xcc4, 24, 6, 31, }, }; -static void __init hi6220_clk_media_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - - clk_data = hisi_clk_init(np, HI6220_MEDIA_NR_CLKS); - if (!clk_data) - return; - - hisi_clk_register_gate_sep(hi6220_separated_gate_clks_media, - ARRAY_SIZE(hi6220_separated_gate_clks_media), clk_data); - - hisi_clk_register_mux(hi6220_mux_clks_media, - ARRAY_SIZE(hi6220_mux_clks_media), clk_data); - - hi6220_clk_register_divider(hi6220_div_clks_media, - ARRAY_SIZE(hi6220_div_clks_media), clk_data); -} -CLK_OF_DECLARE_DRIVER(hi6220_clk_media, "hisilicon,hi6220-mediactrl", hi6220_clk_media_init); - +static const struct hisi_clocks hi6220_media_clks = { + .nr = HI6220_MEDIA_NR_CLKS, + .mux_clks = hi6220_mux_clks_media, + .mux_clks_num = ARRAY_SIZE(hi6220_mux_clks_media), + .gate_sep_clks = hi6220_separated_gate_clks_media, + .gate_sep_clks_num = ARRAY_SIZE(hi6220_separated_gate_clks_media), + .customized_clks = hi6220_div_clks_media, + .customized_clks_num = ARRAY_SIZE(hi6220_div_clks_media), + .clk_register_customized = hi6220_clk_register_divider_stub, +}; /* clocks in pmctrl */ -static struct hisi_gate_clock hi6220_gate_clks_power[] __initdata = { +static struct hisi_gate_clock hi6220_gate_clks_power[] = { { HI6220_PLL_GPU_GATE, "pll_gpu_gate", "gpupll", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x8, 0, 0, }, { HI6220_PLL1_DDR_GATE, "pll1_ddr_gate", "ddrpll1", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x10, 0, 0, }, { HI6220_PLL_DDR_GATE, "pll_ddr_gate", "ddrpll0", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x18, 0, 0, }, @@ -263,26 +245,19 @@ static struct hisi_gate_clock hi6220_gate_clks_power[] __initdata = { { HI6220_PLL0_BBP_GATE, "pll0_bbp_gate", "bbppll0", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x48, 0, 0, }, }; -static struct hi6220_divider_clock hi6220_div_clks_power[] __initdata = { +static struct hi6220_divider_clock hi6220_div_clks_power[] = { { HI6220_DDRC_SRC, "ddrc_src", "ddr_sel_src", CLK_SET_RATE_PARENT, 0x5a8, 0, 4, 0, }, { HI6220_DDRC_AXI1, "ddrc_axi1", "ddrc_src", CLK_SET_RATE_PARENT, 0x5a8, 8, 2, 0, }, }; -static void __init hi6220_clk_power_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - - clk_data = hisi_clk_init(np, HI6220_POWER_NR_CLKS); - if (!clk_data) - return; - - hisi_clk_register_gate(hi6220_gate_clks_power, - ARRAY_SIZE(hi6220_gate_clks_power), clk_data); - - hi6220_clk_register_divider(hi6220_div_clks_power, - ARRAY_SIZE(hi6220_div_clks_power), clk_data); -} -CLK_OF_DECLARE(hi6220_clk_power, "hisilicon,hi6220-pmctrl", hi6220_clk_power_init); +static const struct hisi_clocks hi6220_power_clks = { + .nr = HI6220_POWER_NR_CLKS, + .gate_clks = hi6220_gate_clks_power, + .gate_clks_num = ARRAY_SIZE(hi6220_gate_clks_power), + .customized_clks = hi6220_div_clks_power, + .customized_clks_num = ARRAY_SIZE(hi6220_div_clks_power), + .clk_register_customized = hi6220_clk_register_divider_stub, +}; /* clocks in acpu */ static const struct hisi_gate_clock hi6220_acpu_sc_gate_sep_clks[] = { @@ -290,18 +265,36 @@ static const struct hisi_gate_clock hi6220_acpu_sc_gate_sep_clks[] = { CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0xc, 11, 0, }, }; -static void __init hi6220_clk_acpu_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - int nr = ARRAY_SIZE(hi6220_acpu_sc_gate_sep_clks); +static const struct hisi_clocks hi6220_acpu_clks = { + .gate_sep_clks = hi6220_acpu_sc_gate_sep_clks, + .gate_sep_clks_num = ARRAY_SIZE(hi6220_acpu_sc_gate_sep_clks), +}; - clk_data = hisi_clk_init(np, nr); - if (!clk_data) - return; +static const struct of_device_id hi6220_clk_match_table[] = { + { .compatible = "hisilicon,hi6220-aoctrl", + .data = &hi6220_ao_clks }, + { .compatible = "hisilicon,hi6220-sysctrl", + .data = &hi6220_sys_clks }, + { .compatible = "hisilicon,hi6220-mediactrl", + .data = &hi6220_media_clks }, + { .compatible = "hisilicon,hi6220-pmctrl", + .data = &hi6220_power_clks }, + { .compatible = "hisilicon,hi6220-acpu-sctrl", + .data = &hi6220_acpu_clks }, + { } +}; +MODULE_DEVICE_TABLE(of, hi6220_clk_match_table); + +static struct platform_driver hi6220_clk_driver = { + .probe = hisi_clk_probe, + .remove = hisi_clk_remove, + .driver = { + .name = "hi6220-clock", + .of_match_table = hi6220_clk_match_table, + }, +}; - hisi_clk_register_gate_sep(hi6220_acpu_sc_gate_sep_clks, - ARRAY_SIZE(hi6220_acpu_sc_gate_sep_clks), - clk_data); -} +module_platform_driver(hi6220_clk_driver); -CLK_OF_DECLARE(hi6220_clk_acpu, "hisilicon,hi6220-acpu-sctrl", hi6220_clk_acpu_init); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("HiSilicon Hi6220 Clock Driver"); From patchwork Mon Apr 10 11:07:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yangfl X-Patchwork-Id: 81474 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1827677vqo; Mon, 10 Apr 2023 04:29:14 -0700 (PDT) X-Google-Smtp-Source: AKy350ZzcJoPz0m+2f4xK3LjEEp/GJLcJsmdePfj9zrGknkfD2FlB0cH7aQBVUDkh+xdOqiE/5Uy X-Received: by 2002:a17:903:1209:b0:1a2:63af:e980 with SMTP id l9-20020a170903120900b001a263afe980mr15873886plh.13.1681126154565; Mon, 10 Apr 2023 04:29:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681126154; cv=none; d=google.com; s=arc-20160816; b=ZC/5YTNduiROpN6UEitlPLcA4zHgwu5/+GBi1U9XDGI2i+uZ01LX0ctv88egZYTn8T vRv2Tom5xBs7gB6ADNRXrbQxktY5QROVDaAHV5IcbO6oX/l0T3oBS7Hc5gbvQHhbO36L JptGhM2N+P3ZDkDeMrIwIqGNQupqMJdIhHq0rPxv5cYMpeYRV5/qcfgq3lx5C3PsVTJS XBkFfo4AMHi6bIrlvna+zCP7JBd8AuhnhmSqlnBdMCo/gG4Vs1t23kEUwiGcRF9EP5mj t833cf4qRdkLQO48li368cR8Gf7j40byImsFetvKTHyUF9SWs35Wd3Q4EQCSXEcmgOL7 E9uA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=IrGWkObbHZex0RD5jh5ZL+1MH7Eazo5YGcbtvBP2RIo=; b=OVdWYhH6ao6PQgcRIgvd89OruRNXrgcpyJPVz0RH8lfk29japFKMEb2I86LLrKux3V MIpYj4iG59wP7584OWd98rCM7BTbhHv35l0ngcGewdIQR5gIgvt5WrpdSs9pjwIPBTOn E8CvuvMHD89VB0iti9FMY/PgI43LuM01QV0EJRgA9UCG71vwow7c0UAvN1n2B4rtPTWe qlhLRzU/sAMo5QtzRbs3OogMnsRPnRRqCkaOpxdORaajON5tLXKWa6QJ7kmvypCFiHQf nytzFxIT+Jjkhb2IqBfnFTqBJ9O76OMxkRCgbj0y3HeheblehCmWki2V2q+rgUgqDsAo EuoQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=nXhSYENd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id r5-20020a170902be0500b001a6400e8c22si2024080pls.543.2023.04.10.04.29.01; Mon, 10 Apr 2023 04:29:14 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=nXhSYENd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229886AbjDJLKx (ORCPT + 99 others); Mon, 10 Apr 2023 07:10:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58742 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229883AbjDJLKw (ORCPT ); Mon, 10 Apr 2023 07:10:52 -0400 Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D488E5264; Mon, 10 Apr 2023 04:10:25 -0700 (PDT) Received: by mail-pl1-x62d.google.com with SMTP id e13so4071906plc.12; Mon, 10 Apr 2023 04:10:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1681125022; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IrGWkObbHZex0RD5jh5ZL+1MH7Eazo5YGcbtvBP2RIo=; b=nXhSYENdtZfSXY+Agxl/fbkiNyw9tIFWVmquf0aZfF/3vNm+BYJg5fAWkLbPTDc7yO mlNzhWYc4l0fP/vRMPwc7HFeC8vxxI9Aof7k+1VMwKkXKtPEF+X2QvJhT65AWcRHb/vb NvPzIxgsE7PKdKlagy5+ivXJsSCslcpo1v2Bk70GVau/lNsojdcE6mQyDlM66qH74iYH yDurkIHeGjUfkNWTmYJPEmfzniHPRhCsUeAaergp5piTIH3CxqoJ6vnvv82k5xynuEQ+ kkExJrzhWpy+r5fr87ExIpbIcHj6njdJ15lpyRopHWBDVTs6prV/hMLlBFTD5nmNd8VC Xd7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681125022; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IrGWkObbHZex0RD5jh5ZL+1MH7Eazo5YGcbtvBP2RIo=; b=Xfajs5EzfY852nuDtPYLfSzYHpz1x0LZ23z0uwMbfxKrB9/mFQiDl54pT74GRoGyE3 nTZrM9G+pZndXpRKCd5Ngu1eKnYk9MAAUajYRJKZ9gZDH85mJJm84C4VeMXHWrhZyQG1 K2xdwOtWWuFhqQXQ9r5BaWE4tu3p4LzBETMcVD8yyINv6ZA4xckGhowNLCWpmA1Y0KQ0 xEfwLG8LZkFsaKx1vCfx1nZ2OKoe9nX0K6CbguqMcRzi8MDBNEcLz2fIGrVmSUWo/95h YgD9e158MP18ohqtPW6zRj9LVKZg9mg04RueFrBndscXHm94K1CBZukNjPBDtr4oziCA dGmg== X-Gm-Message-State: AAQBX9cJ5rP/VhcsBwfVReAZXUN7C5AUOEAhTYkmy/Rh17IoPO5tsHuE ywS/m+JC1xNLtO17HXKQjGzixJhrydKk4lN9Sv0= X-Received: by 2002:a17:903:234c:b0:1a1:8d4e:a71d with SMTP id c12-20020a170903234c00b001a18d4ea71dmr15818760plh.46.1681125022671; Mon, 10 Apr 2023 04:10:22 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.213.201]) by smtp.gmail.com with ESMTPSA id r5-20020a170902be0500b001a076568da9sm7464728pls.216.2023.04.10.04.10.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 04:10:22 -0700 (PDT) From: David Yang To: linux-clk@vger.kernel.org Cc: David Yang , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org Subject: [PATCH v3 12/14] clk: hisilicon: hip04: Convert into platform driver module Date: Mon, 10 Apr 2023 19:07:24 +0800 Message-Id: <20230410110733.192151-13-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230410110733.192151-1-mmyangfl@gmail.com> References: <20230410110733.192151-1-mmyangfl@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762788538844145174?= X-GMAIL-MSGID: =?utf-8?q?1762788538844145174?= Use common helper functions and register clks with a single of_device_id data. Signed-off-by: David Yang --- drivers/clk/hisilicon/clk-hip04.c | 39 +++++++++++++++++++------------ 1 file changed, 24 insertions(+), 15 deletions(-) diff --git a/drivers/clk/hisilicon/clk-hip04.c b/drivers/clk/hisilicon/clk-hip04.c index 785b9faf3ea5..230702057e3b 100644 --- a/drivers/clk/hisilicon/clk-hip04.c +++ b/drivers/clk/hisilicon/clk-hip04.c @@ -10,11 +10,8 @@ #include #include -#include -#include -#include +#include #include -#include #include @@ -27,16 +24,28 @@ static struct hisi_fixed_rate_clock hip04_fixed_rate_clks[] __initdata = { { HIP04_CLK_168M, "clk168m", NULL, 0, 168750000, }, }; -static void __init hip04_clk_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; +static const struct hisi_clocks hip04_clks = { + .fixed_rate_clks = hip04_fixed_rate_clks, + .fixed_factor_clks_num = ARRAY_SIZE(hip04_fixed_rate_clks), +}; + +static const struct of_device_id hip04_clk_match_table[] = { + { .compatible = "hisilicon,hip04-clock", + .data = &hip04_clks }, + { } +}; +MODULE_DEVICE_TABLE(of, hip04_clk_match_table); + +static struct platform_driver hip04_clk_driver = { + .probe = hisi_clk_probe, + .remove = hisi_clk_remove, + .driver = { + .name = "hip04-clock", + .of_match_table = hip04_clk_match_table, + }, +}; - clk_data = hisi_clk_init(np, HIP04_NR_CLKS); - if (!clk_data) - return; +module_platform_driver(hip04_clk_driver); - hisi_clk_register_fixed_rate(hip04_fixed_rate_clks, - ARRAY_SIZE(hip04_fixed_rate_clks), - clk_data); -} -CLK_OF_DECLARE(hip04_clk, "hisilicon,hip04-clock", hip04_clk_init); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("HiSilicon HiP04 Clock Driver"); From patchwork Mon Apr 10 11:07:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yangfl X-Patchwork-Id: 81473 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1826368vqo; Mon, 10 Apr 2023 04:26:22 -0700 (PDT) X-Google-Smtp-Source: AKy350YJQpf/+YgifWp2NXHgU4QZGsVidsIIDLQZlJdW07N4iOgBRLY/gLE1lnU8wutLN1m267Ki X-Received: by 2002:a62:1d12:0:b0:626:2ce1:263c with SMTP id d18-20020a621d12000000b006262ce1263cmr10641602pfd.5.1681125982046; Mon, 10 Apr 2023 04:26:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681125982; cv=none; d=google.com; s=arc-20160816; b=GA3QzJ/N2B+Abt8/jny81mmX3rU+qNRNVIx4YX+9/dxz/EbNN8IWGTja0ycckaD1lr 2wzczH6i43yFCJALqoeWW040Fzg0Iq16KFddV8T/RFAZJ0Zg9CiA/VbWrTzc0ZWnoXDq Oq2qfjv7/wHyXnLOS/v+gFuB5Y42c+EGvlx+OeKhpvUqSwNtgig71Tr2Hf7ECQ9rYpGJ eKlAIdJEG1KUvE1EFcwiNowfN695wmMssQmh/q3BnnE4r3gVMhWJornOBLCW4g+d2JUU 9MI9LDyqEPvUAPuOvixaCTGXCj7rC/kPaz2OrFv/3iHTFB+Y1qJX6O/yzsghe2gFT7LB Fg2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=eAEODm1kNNhfhQehFrRwXlq3FhwRoxU54wQDsxuZLBY=; b=E5Fb6gOAPg4ZELeKbWCBImVuaZ+xeYRuLBTrXqIF+czCT0if/s+WrCNIT1gwuNxRdH Tuz2TU0BQ3igeR41yyoz4M+KrOCq8ht1Sj75UquSJDHMNTHH3IkZ2YSl9WTxn4eHgyxQ KGMZxGK4WjAmuAxzSmHbOw1sYc/zjjEfDma5D1zipXxn/6tT8/uSKeZz4cDZgpaqiNhr t8qO8KzCdZyEGjfmbjIqrHLImEoZudRPV+HxMpnWTakl694QV2vDS5wfNklp57I/riGx T4qe5yrzfSUkZTDtQb/i35OlUSIhEkD75d32mfOvZ5udX6mo7tuB5Ag3TioQ9KkT4LNI MlOg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b="mneeEP5/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id f2-20020a6547c2000000b00503a2ab160esi9878963pgs.553.2023.04.10.04.26.07; Mon, 10 Apr 2023 04:26:22 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b="mneeEP5/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229894AbjDJLLD (ORCPT + 99 others); Mon, 10 Apr 2023 07:11:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59018 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229902AbjDJLLB (ORCPT ); Mon, 10 Apr 2023 07:11:01 -0400 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1DE395252; Mon, 10 Apr 2023 04:10:37 -0700 (PDT) Received: by mail-pj1-x1032.google.com with SMTP id c3so4792813pjg.1; Mon, 10 Apr 2023 04:10:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1681125036; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eAEODm1kNNhfhQehFrRwXlq3FhwRoxU54wQDsxuZLBY=; b=mneeEP5/S/ifs7vAoq84uXh0uh/1PHr3A6Rlsz4YpVabICVyO58KO8z0pkVTYOO6Vv YPFwZ1G7z6SaeeqYhGd0hI7mt3kfv2bwUxsIIJE1s+ikd4033gOl7n/UNJT7E2IJDSAq kFsOO/c4lU5pwZhOxVaUzM4/50eMvrIu3CXobF75qL8c4N8NJiK+hkqRX1x+uP/ghZeO tIxZVoxZJeDDgzcQ9LeCCG30TjJh9GfT+gaVfJyZlI42UX6iuF6r6I9AihEQTdvUf0F7 Rv5QrwlWnmoWllJ1aeJkyMK0VyY+FgSQpGQB5R8oIjeziyMxWinB2VLknPXe0/Z0wNWw rtyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681125036; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eAEODm1kNNhfhQehFrRwXlq3FhwRoxU54wQDsxuZLBY=; b=q4+S11hYOpML72rA1ehDQKNE+J3pDPTKpPyGO3E60NfhQKLVKhRpGmYo3Q/4qW94td VbnVloQ9cVDOu0/XzpFV/jwZijgNtGHolG0noSUGGIUnU63wmn1UYgxN2uBNE8BjFNBG NvYopAFb6AyxivEnMyYa1BMZT1Vm0Jej9uhlKjQOGW9O+QTXg/cFlHUTl4X2uAlDVXtI x90oJA2dF11Ym5qprJ/DLZ20xJ2wmv4/KMb2ESAq4l45nvAxmlH56hrIv5XRdjxbIIQr kmDs8xORffT+Hcop8BaS7vWSyxmRxcK6IO1jDhMVX4Fc+pV85+dnb7Ym/DuvQ1ZJFmDB 63CA== X-Gm-Message-State: AAQBX9dQDQzdztmZHaMKpErH5Glq/n7aj1OoTDYIMojXWjcpgRjM1Y3y JNchRYtLxQ5wpn6NtOwUbnVvVP9D/s9OOURsm7Q= X-Received: by 2002:a17:902:e749:b0:1a1:e93c:8937 with SMTP id p9-20020a170902e74900b001a1e93c8937mr14101810plf.35.1681125036086; Mon, 10 Apr 2023 04:10:36 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.213.201]) by smtp.gmail.com with ESMTPSA id r5-20020a170902be0500b001a076568da9sm7464728pls.216.2023.04.10.04.10.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 04:10:35 -0700 (PDT) From: David Yang To: linux-clk@vger.kernel.org Cc: David Yang , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org Subject: [PATCH v3 13/14] clk: hisilicon: hix5hd2: Convert into platform driver module Date: Mon, 10 Apr 2023 19:07:25 +0800 Message-Id: <20230410110733.192151-14-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230410110733.192151-1-mmyangfl@gmail.com> References: <20230410110733.192151-1-mmyangfl@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762788357417684952?= X-GMAIL-MSGID: =?utf-8?q?1762788357417684952?= Use common helper functions and register clks with a single of_device_id data. Signed-off-by: David Yang --- drivers/clk/hisilicon/clk-hix5hd2.c | 85 ++++++++++++++++++----------- 1 file changed, 52 insertions(+), 33 deletions(-) diff --git a/drivers/clk/hisilicon/clk-hix5hd2.c b/drivers/clk/hisilicon/clk-hix5hd2.c index 64bdd3f05725..fb0f5d2745b2 100644 --- a/drivers/clk/hisilicon/clk-hix5hd2.c +++ b/drivers/clk/hisilicon/clk-hix5hd2.c @@ -4,13 +4,17 @@ * Copyright (c) 2014 Hisilicon Limited. */ -#include #include + #include #include +#include +#include +#include + #include "clk.h" -static struct hisi_fixed_rate_clock hix5hd2_fixed_rate_clks[] __initdata = { +static struct hisi_fixed_rate_clock hix5hd2_fixed_rate_clks[] = { { HIX5HD2_FIXED_1200M, "1200m", NULL, 0, 1200000000, }, { HIX5HD2_FIXED_400M, "400m", NULL, 0, 400000000, }, { HIX5HD2_FIXED_48M, "48m", NULL, 0, 48000000, }, @@ -43,19 +47,19 @@ static struct hisi_fixed_rate_clock hix5hd2_fixed_rate_clks[] __initdata = { { HIX5HD2_FIXED_83M, "83m", NULL, 0, 83333333, }, }; -static const char *const sfc_mux_p[] __initconst = { +static const char *const sfc_mux_p[] = { "24m", "150m", "200m", "100m", "75m", }; static u32 sfc_mux_table[] = {0, 4, 5, 6, 7}; -static const char *const sdio_mux_p[] __initconst = { +static const char *const sdio_mux_p[] = { "75m", "100m", "50m", "15m", }; static u32 sdio_mux_table[] = {0, 1, 2, 3}; -static const char *const fephy_mux_p[] __initconst = { "25m", "125m"}; +static const char *const fephy_mux_p[] = { "25m", "125m"}; static u32 fephy_mux_table[] = {0, 1}; -static struct hisi_mux_clock hix5hd2_mux_clks[] __initdata = { +static struct hisi_mux_clock hix5hd2_mux_clks[] = { { HIX5HD2_SFC_MUX, "sfc_mux", sfc_mux_p, ARRAY_SIZE(sfc_mux_p), CLK_SET_RATE_PARENT, 0x5c, 8, 3, 0, sfc_mux_table, }, { HIX5HD2_MMC_MUX, "mmc_mux", sdio_mux_p, ARRAY_SIZE(sdio_mux_p), @@ -67,7 +71,7 @@ static struct hisi_mux_clock hix5hd2_mux_clks[] __initdata = { CLK_SET_RATE_PARENT, 0x120, 8, 2, 0, fephy_mux_table, }, }; -static struct hisi_gate_clock hix5hd2_gate_clks[] __initdata = { +static struct hisi_gate_clock hix5hd2_gate_clks[] = { /* sfc */ { HIX5HD2_SFC_CLK, "clk_sfc", "sfc_mux", CLK_SET_RATE_PARENT, 0x5c, 0, 0, }, @@ -153,7 +157,7 @@ struct hix5hd2_clk_complex { u32 phy_rst_mask; }; -static struct hix5hd2_complex_clock hix5hd2_complex_clks[] __initdata = { +static struct hix5hd2_complex_clock hix5hd2_complex_clks[] = { {"clk_mac0", "clk_fephy", HIX5HD2_MAC0_CLK, 0xcc, 0xa, 0x500, 0x120, 0, 0x10, TYPE_ETHER}, {"clk_mac1", "clk_fwd_sys", HIX5HD2_MAC1_CLK, @@ -249,21 +253,22 @@ static const struct clk_ops clk_complex_ops = { .disable = clk_complex_disable, }; -static void __init -hix5hd2_clk_register_complex(struct hix5hd2_complex_clock *clks, int nums, +static int +hix5hd2_clk_register_complex(struct device *dev, const void *clocks, size_t num, struct hisi_clock_data *data) { + const struct hix5hd2_complex_clock *clks = clocks; void __iomem *base = data->base; int i; - for (i = 0; i < nums; i++) { + for (i = 0; i < num; i++) { struct hix5hd2_clk_complex *p_clk; struct clk *clk; struct clk_init_data init; p_clk = kzalloc(sizeof(*p_clk), GFP_KERNEL); if (!p_clk) - return; + return -ENOMEM; init.name = clks[i].name; if (clks[i].type == TYPE_ETHER) @@ -289,31 +294,45 @@ hix5hd2_clk_register_complex(struct hix5hd2_complex_clock *clks, int nums, kfree(p_clk); pr_err("%s: failed to register clock %s\n", __func__, clks[i].name); - continue; + return PTR_ERR(p_clk); } data->clk_data.clks[clks[i].id] = clk; } -} -static void __init hix5hd2_clk_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - - clk_data = hisi_clk_init(np, HIX5HD2_NR_CLKS); - if (!clk_data) - return; - - hisi_clk_register_fixed_rate(hix5hd2_fixed_rate_clks, - ARRAY_SIZE(hix5hd2_fixed_rate_clks), - clk_data); - hisi_clk_register_mux(hix5hd2_mux_clks, ARRAY_SIZE(hix5hd2_mux_clks), - clk_data); - hisi_clk_register_gate(hix5hd2_gate_clks, - ARRAY_SIZE(hix5hd2_gate_clks), clk_data); - hix5hd2_clk_register_complex(hix5hd2_complex_clks, - ARRAY_SIZE(hix5hd2_complex_clks), - clk_data); + return 0; } -CLK_OF_DECLARE(hix5hd2_clk, "hisilicon,hix5hd2-clock", hix5hd2_clk_init); +static const struct hisi_clocks hix5hd2_clks = { + .nr = HIX5HD2_NR_CLKS, + .fixed_rate_clks = hix5hd2_fixed_rate_clks, + .fixed_factor_clks_num = ARRAY_SIZE(hix5hd2_fixed_rate_clks), + .mux_clks = hix5hd2_mux_clks, + .mux_clks_num = ARRAY_SIZE(hix5hd2_mux_clks), + .gate_clks = hix5hd2_gate_clks, + .gate_clks_num = ARRAY_SIZE(hix5hd2_gate_clks), + .customized_clks = hix5hd2_complex_clks, + .customized_clks_num = ARRAY_SIZE(hix5hd2_complex_clks), + .clk_register_customized = hix5hd2_clk_register_complex, +}; + +static const struct of_device_id hix5hd2_clk_match_table[] = { + { .compatible = "hisilicon,hix5hd2-clock", + .data = &hix5hd2_clks }, + { } +}; +MODULE_DEVICE_TABLE(of, hix5hd2_clk_match_table); + +static struct platform_driver hix5hd2_clk_driver = { + .probe = hisi_clk_probe, + .remove = hisi_clk_remove, + .driver = { + .name = "hix5hd2-clock", + .of_match_table = hix5hd2_clk_match_table, + }, +}; + +module_platform_driver(hix5hd2_clk_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("HiSilicon Hix5hd2 Clock Driver"); From patchwork Mon Apr 10 11:07:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yangfl X-Patchwork-Id: 81480 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1833351vqo; Mon, 10 Apr 2023 04:40:30 -0700 (PDT) X-Google-Smtp-Source: AKy350Yj44t+nSqQ5aYZElkLTWGnR8aebopHl2dZdfV+yxXrsQ+Fe2zKKZUW98OZ+LnlxJjETfvt X-Received: by 2002:a05:6402:120f:b0:4fd:c5e:79b8 with SMTP id c15-20020a056402120f00b004fd0c5e79b8mr9095172edw.32.1681126830193; Mon, 10 Apr 2023 04:40:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681126830; cv=none; d=google.com; s=arc-20160816; b=InfcJBctszWYCp1msy/QSrLUXc5sdVGPU/0v/bUxZ6deK+ierIw70Ebl40oIgOeZL6 VEzvaZtluiuCaGpTwRqFPG02rmEwn0cv+umiQ1tHrCM89AMptZu2WqDQI4FdGiJfCa2y TpJnqwHTgdFzXCLyct8TeDZvA998puoP25ngGJOHNmA4/0i04MyGa5HUE058GZB6U64u 0T6bmuxt9iyMlJ5yRQ5xpEmPdiRK3deczHk0MSPzEChUfyPnqerLEYDs8MokNOtStNn8 dLNotMjLaIoVZ220CJOTIULkMWaJXjGbpjsUtixwaIMBGHSN5665HbciSr97g4l+3HHf P31w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Y4YkqjVQYX/c3jxukKHUZf0PehPmtJM6Cs6Goz5bGvE=; b=saYoBcbChnPo+SNMC+GM0NI/9VVDSOitoUGBOsxqkk4CZ3eW3/vB1nlr/Uwdoevr8G vpdSyAYJUSEV/7O7gIJBgh1ySAOH9SaKMpJMaLPf8ilrsFst3XilmwqLp2ciVp+jaCUk g0waM18czpcQyAKT+R50hJWKWyR3+S0aHlfUMunFXdP8CP94BGyxKNZhIFl8XOGl0V/Q DFU4rR/CL8I5cGE7sfaNY1JHTrbHZl+Q93SQzbOSsg9D9M3jT20WRem+OqaDYSuBgEYW rMBnXVsMcMWBIazANWhHkMv3OPMQTj+7LwmB6P3NlfqHyYJe1/mclrz+vKyQF1QoqQWP OJrg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=n6FBKVDD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id l18-20020a056402029200b00504a32f988csi1862968edv.692.2023.04.10.04.40.06; Mon, 10 Apr 2023 04:40:30 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=n6FBKVDD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229909AbjDJLLe (ORCPT + 99 others); Mon, 10 Apr 2023 07:11:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229900AbjDJLLc (ORCPT ); Mon, 10 Apr 2023 07:11:32 -0400 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A2D3559D2; Mon, 10 Apr 2023 04:11:04 -0700 (PDT) Received: by mail-pj1-x1032.google.com with SMTP id c10-20020a17090abf0a00b0023d1bbd9f9eso7051481pjs.0; Mon, 10 Apr 2023 04:11:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1681125064; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Y4YkqjVQYX/c3jxukKHUZf0PehPmtJM6Cs6Goz5bGvE=; b=n6FBKVDDKlujVfojCTrck2K5ATQmGn7Cl9UMp34+nUuirI2fTOXjFOc1moQa/pnMYQ 9v/AVRzNgxPn/ZC0PQypf0SKKrAGPXGn9LpKzKMVLOQbjwHh+pgwK+O91Ys3pE9k9Ur2 lwOleCx/T30GDRyClvAHHLwAVBnzCjyQHYcf0VhzvRvT4TBv+4FREsnvrGPwTCDONzoJ pi+QDre/amlNL4i2X4R/AzurXBGd+8bwX6r54YTVqB/8pXySKF8ZVIHx33pm8VuMzh+1 +AcqDRrE7eTo9tYZWxk9ub+EFexRm3MXqvswjrX3GHeeKseUQAcAOCo01Y820oFLYy8e xtPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681125064; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Y4YkqjVQYX/c3jxukKHUZf0PehPmtJM6Cs6Goz5bGvE=; b=c0+0hkCrXXlwcYbrzjhp2I8VpYusx+XIsF3wNb4FoqU6Zd6mdm4IR57CTh0kGaytrT jRJVcu5P/qii1D0q1WHG+HP6l8MNVL7KDybTp+kVdZK2iRiZFY7B2L8ThZPpSs7Se15+ 2tq6RmPgbwgoSrR5d7PwH7b77SWqxxV2J3YtLUS+zFhGec+gftrCyH+jyZ4VP7Q10sSH zZadq8hXzBo0THNHJxmhjBTr41Rt+r0Lq4IQ9ce2zXfMh2V6pBKNel78RYzcCUtr1cSl RfTxd5jsYEJakVJCShcskI7hF2HFX2qj0jvvPdE2d1vHipr1T4DjrSkMb6MMh1Usq3cB CXAw== X-Gm-Message-State: AAQBX9evO/FTuJfyPoyJSbpQXNS7hy2CE+/VbMqTUkTT71ljJ8by4/BU 3Va4p4T5bHoqYNEE/eIjY7Pg2qdMc9Ni515+FrQ= X-Received: by 2002:a17:902:ea0a:b0:1a6:492c:df22 with SMTP id s10-20020a170902ea0a00b001a6492cdf22mr1197609plg.17.1681125063481; Mon, 10 Apr 2023 04:11:03 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.213.201]) by smtp.gmail.com with ESMTPSA id r5-20020a170902be0500b001a076568da9sm7464728pls.216.2023.04.10.04.10.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 04:11:03 -0700 (PDT) From: David Yang To: linux-clk@vger.kernel.org Cc: David Yang , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org, Conor Dooley , Nick Alcock Subject: [PATCH v3 14/14] clk: hisilicon: Migrate devm APIs Date: Mon, 10 Apr 2023 19:07:26 +0800 Message-Id: <20230410110733.192151-15-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230410110733.192151-1-mmyangfl@gmail.com> References: <20230410110733.192151-1-mmyangfl@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762787268485105794?= X-GMAIL-MSGID: =?utf-8?q?1762789247071241844?= Migrates devm APIs for HiSilicon clock drivers. Signed-off-by: David Yang --- drivers/clk/hisilicon/clk-hi3559a.c | 29 +- drivers/clk/hisilicon/clk-hi3620.c | 29 +- drivers/clk/hisilicon/clk-hi6220-stub.c | 9 +- drivers/clk/hisilicon/clk-hi6220.c | 4 +- drivers/clk/hisilicon/clk-hisi-phase.c | 13 +- drivers/clk/hisilicon/clk-hix5hd2.c | 15 +- drivers/clk/hisilicon/clk.c | 416 +++++++--------------- drivers/clk/hisilicon/clk.h | 96 ++--- drivers/clk/hisilicon/clkdivider-hi6220.c | 24 +- drivers/clk/hisilicon/clkgate-separated.c | 26 +- 10 files changed, 258 insertions(+), 403 deletions(-) diff --git a/drivers/clk/hisilicon/clk-hi3559a.c b/drivers/clk/hisilicon/clk-hi3559a.c index 9844e86ec146..3af5413c16ee 100644 --- a/drivers/clk/hisilicon/clk-hi3559a.c +++ b/drivers/clk/hisilicon/clk-hi3559a.c @@ -457,17 +457,16 @@ hisi_clk_register_pll(struct device *dev, const void *clocks, { const struct hi3559av100_pll_clock *clks = clocks; void __iomem *base = data->base; - struct hi3559av100_clk_pll *p_clk = NULL; - struct clk *clk = NULL; + struct hi3559av100_clk_pll *p_clk; struct clk_init_data init; int i; - - p_clk = devm_kzalloc(dev, sizeof(*p_clk) * num, GFP_KERNEL); - - if (!p_clk) - return -ENOMEM; + int ret; for (i = 0; i < num; i++) { + p_clk = devm_kzalloc(dev, sizeof(*p_clk), GFP_KERNEL); + if (!p_clk) + return -ENOMEM; + init.name = clks[i].name; init.flags = 0; init.parent_names = @@ -490,16 +489,14 @@ hisi_clk_register_pll(struct device *dev, const void *clocks, p_clk->refdiv_width = clks[i].refdiv_width; p_clk->hw.init = &init; - clk = clk_register(NULL, &p_clk->hw); - if (IS_ERR(clk)) { - devm_kfree(dev, p_clk); + ret = devm_clk_hw_register(dev, &p_clk->hw); + if (ret) { dev_err(dev, "%s: failed to register clock %s\n", - __func__, clks[i].name); - return PTR_ERR(clk); + __func__, clks[i].name); + return ret; } - data->clk_data.clks[clks[i].id] = clk; - p_clk++; + data->clk_data->hws[clks[i].id] = &p_clk->hw; } return 0; @@ -628,7 +625,7 @@ static int hi3559av100_shub_default_clk_set(struct device *dev, struct hisi_cloc void __iomem *crg_base; unsigned int val; - crg_base = ioremap(CRG_BASE_ADDR, SZ_4K); + crg_base = devm_ioremap(dev, CRG_BASE_ADDR, SZ_4K); /* SSP: 192M/2 */ val = readl_relaxed(crg_base + 0x20); @@ -640,7 +637,7 @@ static int hi3559av100_shub_default_clk_set(struct device *dev, struct hisi_cloc val |= (0x1 << 28); writel_relaxed(val, crg_base + 0x1C); - iounmap(crg_base); + devm_iounmap(dev, crg_base); crg_base = NULL; return 0; diff --git a/drivers/clk/hisilicon/clk-hi3620.c b/drivers/clk/hisilicon/clk-hi3620.c index 464b7887415c..e775457f7678 100644 --- a/drivers/clk/hisilicon/clk-hi3620.c +++ b/drivers/clk/hisilicon/clk-hi3620.c @@ -11,12 +11,10 @@ #include #include +#include #include #include -#include -#include #include -#include #include @@ -399,15 +397,15 @@ static const struct clk_ops clk_mmc_ops = { .recalc_rate = mmc_clk_recalc_rate, }; -static struct clk * +static struct clk_hw * clk_register_hisi_mmc(struct device *dev, const struct hisi_mmc_clock *mmc_clk, void __iomem *base) { struct clk_mmc *mclk; - struct clk *clk; struct clk_init_data init; + int ret; - mclk = kzalloc(sizeof(*mclk), GFP_KERNEL); + mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL); if (!mclk) return ERR_PTR(-ENOMEM); @@ -431,26 +429,31 @@ clk_register_hisi_mmc(struct device *dev, const struct hisi_mmc_clock *mmc_clk, mclk->sam_off = mmc_clk->sam_off; mclk->sam_bits = mmc_clk->sam_bits; - clk = clk_register(NULL, &mclk->hw); - if (WARN_ON(IS_ERR(clk))) - kfree(mclk); - return clk; + ret = devm_clk_hw_register(dev, &mclk->hw); + if (ret) { + dev_err(dev, "%s: failed to register clock %s\n", + __func__, init.name); + return ERR_PTR(ret); + } + + return &mclk->hw; } static int hisi_register_clk_mmc(struct device *dev, const void *clocks, size_t num, struct hisi_clock_data *data) { const struct hisi_mmc_clock *clks = clocks; + int i; - for (int i = 0; i < num; i++) { - struct clk *clk = clk_register_hisi_mmc(dev, &clks[i], data->base); + for (i = 0; i < num; i++) { + struct clk_hw *clk = clk_register_hisi_mmc(dev, &clks[i], data->base); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", __func__, clks[i].name); return PTR_ERR(clk); } - data->clk_data.clks[clks[i].id] = clk; + data->clk_data->hws[clks[i].id] = clk; } return 0; diff --git a/drivers/clk/hisilicon/clk-hi6220-stub.c b/drivers/clk/hisilicon/clk-hi6220-stub.c index 4fdee4424d82..dd996a43958e 100644 --- a/drivers/clk/hisilicon/clk-hi6220-stub.c +++ b/drivers/clk/hisilicon/clk-hi6220-stub.c @@ -195,7 +195,6 @@ static int hi6220_stub_clk_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct clk_init_data init; struct hi6220_stub_clk *stub_clk; - struct clk *clk; struct device_node *np = pdev->dev.of_node; int ret; @@ -233,11 +232,11 @@ static int hi6220_stub_clk_probe(struct platform_device *pdev) init.num_parents = 0; init.flags = 0; - clk = devm_clk_register(dev, &stub_clk->hw); - if (IS_ERR(clk)) - return PTR_ERR(clk); + ret = devm_clk_hw_register(dev, &stub_clk->hw); + if (ret) + return ret; - ret = of_clk_add_provider(np, of_clk_src_simple_get, clk); + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &stub_clk->hw); if (ret) { dev_err(dev, "failed to register OF clock provider\n"); return ret; diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c index edf83e996bd5..8e63bc140fa4 100644 --- a/drivers/clk/hisilicon/clk-hi6220.c +++ b/drivers/clk/hisilicon/clk-hi6220.c @@ -20,9 +20,7 @@ static int hi6220_clk_register_divider_stub(struct device *dev, const void *clks, size_t num, struct hisi_clock_data *data) { - /* INCOMPLETE PATCH */ - hi6220_clk_register_divider(clks, num, data); - return 0; + return hi6220_clk_register_divider(dev, clks, num, data); } /* clocks in AO (always on) controller */ diff --git a/drivers/clk/hisilicon/clk-hisi-phase.c b/drivers/clk/hisilicon/clk-hisi-phase.c index ba6afad66a2b..15a23dd6edb1 100644 --- a/drivers/clk/hisilicon/clk-hisi-phase.c +++ b/drivers/clk/hisilicon/clk-hisi-phase.c @@ -5,11 +5,11 @@ * Simple HiSilicon phase clock implementation. */ +#include #include #include #include #include -#include #include "clk.h" @@ -90,12 +90,13 @@ static const struct clk_ops clk_phase_ops = { .set_phase = hisi_clk_set_phase, }; -struct clk *clk_register_hisi_phase(struct device *dev, +struct clk_hw *devm_clk_hw_register_hisi_phase(struct device *dev, const struct hisi_phase_clock *clks, void __iomem *base, spinlock_t *lock) { struct clk_hisi_phase *phase; struct clk_init_data init; + int ret; phase = devm_kzalloc(dev, sizeof(struct clk_hisi_phase), GFP_KERNEL); if (!phase) @@ -116,6 +117,10 @@ struct clk *clk_register_hisi_phase(struct device *dev, phase->phase_num = clks->phase_num; phase->hw.init = &init; - return devm_clk_register(dev, &phase->hw); + ret = devm_clk_hw_register(dev, &phase->hw); + if (ret) + return ERR_PTR(ret); + + return &phase->hw; } -EXPORT_SYMBOL_GPL(clk_register_hisi_phase); +EXPORT_SYMBOL_GPL(devm_clk_hw_register_hisi_phase); diff --git a/drivers/clk/hisilicon/clk-hix5hd2.c b/drivers/clk/hisilicon/clk-hix5hd2.c index fb0f5d2745b2..e2630f03b966 100644 --- a/drivers/clk/hisilicon/clk-hix5hd2.c +++ b/drivers/clk/hisilicon/clk-hix5hd2.c @@ -6,7 +6,7 @@ #include -#include +#include #include #include #include @@ -260,13 +260,13 @@ hix5hd2_clk_register_complex(struct device *dev, const void *clocks, size_t num, const struct hix5hd2_complex_clock *clks = clocks; void __iomem *base = data->base; int i; + int ret; for (i = 0; i < num; i++) { struct hix5hd2_clk_complex *p_clk; - struct clk *clk; struct clk_init_data init; - p_clk = kzalloc(sizeof(*p_clk), GFP_KERNEL); + p_clk = devm_kzalloc(dev, sizeof(*p_clk), GFP_KERNEL); if (!p_clk) return -ENOMEM; @@ -289,15 +289,14 @@ hix5hd2_clk_register_complex(struct device *dev, const void *clocks, size_t num, p_clk->phy_rst_mask = clks[i].phy_rst_mask; p_clk->hw.init = &init; - clk = clk_register(NULL, &p_clk->hw); - if (IS_ERR(clk)) { - kfree(p_clk); + ret = devm_clk_hw_register(dev, &p_clk->hw); + if (ret) { pr_err("%s: failed to register clock %s\n", __func__, clks[i].name); - return PTR_ERR(p_clk); + return ret; } - data->clk_data.clks[clks[i].id] = clk; + data->clk_data->hws[clks[i].id] = &p_clk->hw; } return 0; diff --git a/drivers/clk/hisilicon/clk.c b/drivers/clk/hisilicon/clk.c index cb4444bba2c0..8ac55e809013 100644 --- a/drivers/clk/hisilicon/clk.c +++ b/drivers/clk/hisilicon/clk.c @@ -4,6 +4,7 @@ * * Copyright (c) 2012-2013 Hisilicon Limited. * Copyright (c) 2012-2013 Linaro Limited. + * Copyright (c) 2023 David Yang * * Author: Haojian Zhuang * Xin Li @@ -13,6 +14,8 @@ #include #include #include +#include +#include #include #include #include @@ -23,67 +26,44 @@ static DEFINE_SPINLOCK(hisi_clk_lock); -struct hisi_clock_data *hisi_clk_alloc(struct platform_device *pdev, - int nr_clks) +struct hisi_clock_data *hisi_clk_init(struct device_node *np, int nr) { - struct hisi_clock_data *clk_data; - struct resource *res; - struct clk **clk_table; - - clk_data = devm_kmalloc(&pdev->dev, sizeof(*clk_data), GFP_KERNEL); - if (!clk_data) - return NULL; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) - return NULL; - clk_data->base = devm_ioremap(&pdev->dev, - res->start, resource_size(res)); - if (!clk_data->base) - return NULL; - - clk_table = devm_kmalloc_array(&pdev->dev, nr_clks, - sizeof(*clk_table), - GFP_KERNEL); - if (!clk_table) - return NULL; - - clk_data->clk_data.clks = clk_table; - clk_data->clk_data.clk_num = nr_clks; - - return clk_data; -} -EXPORT_SYMBOL_GPL(hisi_clk_alloc); - -struct hisi_clock_data *hisi_clk_init(struct device_node *np, - int nr_clks) -{ - struct hisi_clock_data *clk_data; - struct clk **clk_table; void __iomem *base; + struct hisi_clock_data *data; + int ret; + int i; base = of_iomap(np, 0); if (!base) { pr_err("%s: failed to map clock registers\n", __func__); - goto err; + return NULL; } - clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL); - if (!clk_data) - goto err; + data = kmalloc(sizeof(*data), GFP_KERNEL); + if (!data) + return NULL; - clk_data->base = base; - clk_table = kcalloc(nr_clks, sizeof(*clk_table), GFP_KERNEL); - if (!clk_table) + data->clk_data = kzalloc(sizeof(*data->clk_data) + nr * sizeof(data->clk_data->hws[0]), + GFP_KERNEL); + if (!data->clk_data) goto err_data; - clk_data->clk_data.clks = clk_table; - clk_data->clk_data.clk_num = nr_clks; - of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data); - return clk_data; + ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, data->clk_data); + if (ret) + goto err_clk; + + data->base = base; + data->clks = NULL; + data->clk_data->num = nr; + for (i = 0; i < nr; i++) + data->clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); + + return data; + +err_clk: + kfree(data->clk_data); err_data: - kfree(clk_data); -err: + kfree(data); return NULL; } EXPORT_SYMBOL_GPL(hisi_clk_init); @@ -92,312 +72,174 @@ void hisi_clk_free(struct device_node *np, struct hisi_clock_data *data) { if (data->clks) { if (data->clks->fixed_rate_clks_num) - hisi_clk_unregister_fixed_rate(data->clks->fixed_rate_clks, - data->clks->fixed_rate_clks_num, - data); + hisi_clk_unregister_fixed_rate(data); if (data->clks->fixed_factor_clks_num) - hisi_clk_unregister_fixed_factor(data->clks->fixed_factor_clks, - data->clks->fixed_factor_clks_num, - data); + hisi_clk_unregister_fixed_factor(data); } of_clk_del_provider(np); - kfree(data->clk_data.clks); + kfree(data->clk_data); kfree(data); } EXPORT_SYMBOL_GPL(hisi_clk_free); int hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *clks, - int nums, struct hisi_clock_data *data) + size_t num, struct hisi_clock_data *data) { - struct clk *clk; + struct clk_hw *clk; int i; - for (i = 0; i < nums; i++) { - clk = clk_register_fixed_rate(NULL, clks[i].name, - clks[i].parent_name, - clks[i].flags, - clks[i].fixed_rate); + for (i = 0; i < num; i++) { + const struct hisi_fixed_rate_clock *p_clk = &clks[i]; + + clk = clk_hw_register_fixed_rate(NULL, p_clk->name, p_clk->parent_name, + p_clk->flags, p_clk->fixed_rate); + if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", - __func__, clks[i].name); + __func__, p_clk->name); goto err; } - data->clk_data.clks[clks[i].id] = clk; + + data->clk_data->hws[p_clk->id] = clk; } return 0; err: while (i--) - clk_unregister_fixed_rate(data->clk_data.clks[clks[i].id]); - + clk_hw_unregister_fixed_rate(data->clk_data->hws[clks[i].id]); return PTR_ERR(clk); } EXPORT_SYMBOL_GPL(hisi_clk_register_fixed_rate); int hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *clks, - int nums, - struct hisi_clock_data *data) + size_t num, struct hisi_clock_data *data) { - struct clk *clk; + struct clk_hw *clk; int i; - for (i = 0; i < nums; i++) { - clk = clk_register_fixed_factor(NULL, clks[i].name, - clks[i].parent_name, - clks[i].flags, clks[i].mult, - clks[i].div); - if (IS_ERR(clk)) { - pr_err("%s: failed to register clock %s\n", - __func__, clks[i].name); - goto err; - } - data->clk_data.clks[clks[i].id] = clk; - } - - return 0; + for (i = 0; i < num; i++) { + const struct hisi_fixed_factor_clock *p_clk = &clks[i]; -err: - while (i--) - clk_unregister_fixed_factor(data->clk_data.clks[clks[i].id]); - - return PTR_ERR(clk); -} -EXPORT_SYMBOL_GPL(hisi_clk_register_fixed_factor); + clk = clk_hw_register_fixed_factor(NULL, p_clk->name, p_clk->parent_name, + p_clk->flags, p_clk->mult, p_clk->div); -int hisi_clk_register_mux(const struct hisi_mux_clock *clks, - int nums, struct hisi_clock_data *data) -{ - struct clk *clk; - void __iomem *base = data->base; - int i; - - for (i = 0; i < nums; i++) { - u32 mask = BIT(clks[i].width) - 1; - - clk = clk_register_mux_table(NULL, clks[i].name, - clks[i].parent_names, - clks[i].num_parents, clks[i].flags, - base + clks[i].offset, clks[i].shift, - mask, clks[i].mux_flags, - clks[i].table, &hisi_clk_lock); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", - __func__, clks[i].name); + __func__, p_clk->name); goto err; } - if (clks[i].alias) - clk_register_clkdev(clk, clks[i].alias, NULL); - - data->clk_data.clks[clks[i].id] = clk; + data->clk_data->hws[p_clk->id] = clk; } return 0; err: while (i--) - clk_unregister_mux(data->clk_data.clks[clks[i].id]); - + clk_hw_unregister_fixed_rate(data->clk_data->hws[clks[i].id]); return PTR_ERR(clk); } -EXPORT_SYMBOL_GPL(hisi_clk_register_mux); +EXPORT_SYMBOL_GPL(hisi_clk_register_fixed_factor); + +/* + * We ARE function creater. Commit message from checkpatch: + * Avoid warning on macros that use argument concatenation as + * those macros commonly create another function + */ +#define hisi_clk_register_fn(fn, type, stmt) \ +int fn(struct device *dev, const struct type *clks, \ + size_t num, struct hisi_clock_data *data) \ +{ \ + void __iomem *base = data->base; \ +\ + for (int i = 0; i < num; i++) { \ + const struct type *p_clk = &clks[i]; \ + struct clk_hw *clk = stmt; \ +\ + if (IS_ERR(clk)) { \ + pr_err("%s: failed to register clock %s\n", \ + __func__, p_clk->name); \ + return PTR_ERR(clk); \ + } \ +\ + if (p_clk->alias) \ + clk_hw_register_clkdev(clk, p_clk->alias, NULL); \ +\ + data->clk_data->hws[p_clk->id] = clk; \ + } \ +\ + return 0; \ +} \ +EXPORT_SYMBOL_GPL(fn); + +hisi_clk_register_fn(hisi_clk_register_mux, hisi_mux_clock, + __devm_clk_hw_register_mux(dev, NULL, p_clk->name, + p_clk->num_parents, p_clk->parent_names, NULL, NULL, + p_clk->flags, base + p_clk->offset, p_clk->shift, BIT(p_clk->width) - 1, + p_clk->mux_flags, p_clk->table, &hisi_clk_lock)) int hisi_clk_register_phase(struct device *dev, const struct hisi_phase_clock *clks, - int nums, struct hisi_clock_data *data) + size_t num, struct hisi_clock_data *data) { void __iomem *base = data->base; - struct clk *clk; - int i; - for (i = 0; i < nums; i++) { - clk = clk_register_hisi_phase(dev, &clks[i], base, - &hisi_clk_lock); + for (int i = 0; i < num; i++) { + const struct hisi_phase_clock *p_clk = &clks[i]; + struct clk_hw *clk = devm_clk_hw_register_hisi_phase(dev, + p_clk, base, &hisi_clk_lock); + if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", __func__, - clks[i].name); + p_clk->name); return PTR_ERR(clk); } - data->clk_data.clks[clks[i].id] = clk; + data->clk_data->hws[p_clk->id] = clk; } return 0; } EXPORT_SYMBOL_GPL(hisi_clk_register_phase); -int hisi_clk_register_divider(const struct hisi_divider_clock *clks, - int nums, struct hisi_clock_data *data) -{ - struct clk *clk; - void __iomem *base = data->base; - int i; - - for (i = 0; i < nums; i++) { - clk = clk_register_divider_table(NULL, clks[i].name, - clks[i].parent_name, - clks[i].flags, - base + clks[i].offset, - clks[i].shift, clks[i].width, - clks[i].div_flags, - clks[i].table, - &hisi_clk_lock); - if (IS_ERR(clk)) { - pr_err("%s: failed to register clock %s\n", - __func__, clks[i].name); - goto err; - } - - if (clks[i].alias) - clk_register_clkdev(clk, clks[i].alias, NULL); - - data->clk_data.clks[clks[i].id] = clk; - } - - return 0; - -err: - while (i--) - clk_unregister_divider(data->clk_data.clks[clks[i].id]); - - return PTR_ERR(clk); -} -EXPORT_SYMBOL_GPL(hisi_clk_register_divider); - -int hisi_clk_register_gate(const struct hisi_gate_clock *clks, - int nums, struct hisi_clock_data *data) -{ - struct clk *clk; - void __iomem *base = data->base; - int i; - - for (i = 0; i < nums; i++) { - clk = clk_register_gate(NULL, clks[i].name, - clks[i].parent_name, - clks[i].flags, - base + clks[i].offset, - clks[i].bit_idx, - clks[i].gate_flags, - &hisi_clk_lock); - if (IS_ERR(clk)) { - pr_err("%s: failed to register clock %s\n", - __func__, clks[i].name); - goto err; - } - - if (clks[i].alias) - clk_register_clkdev(clk, clks[i].alias, NULL); - - data->clk_data.clks[clks[i].id] = clk; - } - - return 0; - -err: - while (i--) - clk_unregister_gate(data->clk_data.clks[clks[i].id]); - - return PTR_ERR(clk); -} -EXPORT_SYMBOL_GPL(hisi_clk_register_gate); - -void hisi_clk_register_gate_sep(const struct hisi_gate_clock *clks, - int nums, struct hisi_clock_data *data) -{ - struct clk *clk; - void __iomem *base = data->base; - int i; - - for (i = 0; i < nums; i++) { - clk = hisi_register_clkgate_sep(NULL, clks[i].name, - clks[i].parent_name, - clks[i].flags, - base + clks[i].offset, - clks[i].bit_idx, - clks[i].gate_flags, - &hisi_clk_lock); - if (IS_ERR(clk)) { - pr_err("%s: failed to register clock %s\n", - __func__, clks[i].name); - continue; - } - - if (clks[i].alias) - clk_register_clkdev(clk, clks[i].alias, NULL); - - data->clk_data.clks[clks[i].id] = clk; - } -} -EXPORT_SYMBOL_GPL(hisi_clk_register_gate_sep); - -void __init hi6220_clk_register_divider(const struct hi6220_divider_clock *clks, - int nums, struct hisi_clock_data *data) -{ - struct clk *clk; - void __iomem *base = data->base; - int i; - - for (i = 0; i < nums; i++) { - clk = hi6220_register_clkdiv(NULL, clks[i].name, - clks[i].parent_name, - clks[i].flags, - base + clks[i].offset, - clks[i].shift, - clks[i].width, - clks[i].mask_bit, - &hisi_clk_lock); - if (IS_ERR(clk)) { - pr_err("%s: failed to register clock %s\n", - __func__, clks[i].name); - continue; - } - - if (clks[i].alias) - clk_register_clkdev(clk, clks[i].alias, NULL); - - data->clk_data.clks[clks[i].id] = clk; - } -} +hisi_clk_register_fn(hisi_clk_register_divider, hisi_divider_clock, + devm_clk_hw_register_divider_table(dev, p_clk->name, p_clk->parent_name, + p_clk->flags, base + p_clk->offset, p_clk->shift, p_clk->width, + p_clk->div_flags, p_clk->table, &hisi_clk_lock)) +hisi_clk_register_fn(hisi_clk_register_gate, hisi_gate_clock, + devm_clk_hw_register_gate(dev, p_clk->name, p_clk->parent_name, + p_clk->flags, base + p_clk->offset, p_clk->bit_idx, + p_clk->gate_flags, &hisi_clk_lock)) +hisi_clk_register_fn(hisi_clk_register_gate_sep, hisi_gate_clock, + devm_clk_hw_register_hisi_gate_sep(dev, p_clk->name, p_clk->parent_name, + p_clk->flags, base + p_clk->offset, p_clk->bit_idx, + p_clk->gate_flags, &hisi_clk_lock)) +hisi_clk_register_fn(hi6220_clk_register_divider, hi6220_divider_clock, + devm_clk_hw_register_hi6220_divider(dev, p_clk->name, p_clk->parent_name, + p_clk->flags, base + p_clk->offset, p_clk->shift, p_clk->width, + p_clk->mask_bit, &hisi_clk_lock)) int hisi_clk_register(struct device *dev, const struct hisi_clocks *clks, struct hisi_clock_data *data) { int ret; - if (clks->mux_clks_num) { - ret = hisi_clk_register_mux(clks->mux_clks, - clks->mux_clks_num, data); - if (ret) - return ret; - } - - if (clks->phase_clks_num) { - ret = hisi_clk_register_phase(dev, clks->phase_clks, - clks->phase_clks_num, data); - if (ret) - return ret; - } - - if (clks->divider_clks_num) { - ret = hisi_clk_register_divider(clks->divider_clks, - clks->divider_clks_num, data); - if (ret) - return ret; - } - - if (clks->gate_clks_num) { - ret = hisi_clk_register_gate(clks->gate_clks, - clks->gate_clks_num, data); - if (ret) - return ret; - } - - if (clks->gate_sep_clks_num) { - hisi_clk_register_gate_sep(clks->gate_sep_clks, - clks->gate_sep_clks_num, data); - } +#define do_hisi_clk_register(type) do { \ + if (clks->type##_clks_num) { \ + ret = hisi_clk_register_##type(dev, clks->type##_clks, \ + clks->type##_clks_num, data); \ + if (ret) \ + return ret; \ + } \ +} while (0) + + do_hisi_clk_register(mux); + do_hisi_clk_register(phase); + do_hisi_clk_register(divider); + do_hisi_clk_register(gate); + do_hisi_clk_register(gate_sep); if (clks->clk_register_customized && clks->customized_clks_num) { ret = clks->clk_register_customized(dev, clks->customized_clks, diff --git a/drivers/clk/hisilicon/clk.h b/drivers/clk/hisilicon/clk.h index cc580915d058..903197397fcf 100644 --- a/drivers/clk/hisilicon/clk.h +++ b/drivers/clk/hisilicon/clk.h @@ -4,6 +4,7 @@ * * Copyright (c) 2012-2013 Hisilicon Limited. * Copyright (c) 2012-2013 Linaro Limited. + * Copyright (c) 2023 David Yang * * Author: Haojian Zhuang * Xin Li @@ -19,9 +20,19 @@ struct platform_device; struct hisi_clocks; +/* + * (Virtual) fixed clocks, often depended by crucial peripherals, require + * early initialization before device probing, thus cannot use devm APIs. + * Otherwise, kernel will defer those peripherals, causing boot failure. + * + * fixed_rate and fixed_factor clocks are driver-managed. They are freed by + * `hisi_clk_free` altogether. + * + * Other clocks are devm-managed. + */ struct hisi_clock_data { - struct clk_onecell_data clk_data; - void __iomem *base; + struct clk_hw_onecell_data *clk_data; + void __iomem *base; const struct hisi_clocks *clks; }; @@ -138,37 +149,45 @@ struct hisi_clocks { size_t num, struct hisi_clock_data *data); }; -struct clk *hisi_register_clkgate_sep(struct device *, const char *, - const char *, unsigned long, - void __iomem *, u8, - u8, spinlock_t *); -struct clk *hi6220_register_clkdiv(struct device *dev, const char *name, - const char *parent_name, unsigned long flags, void __iomem *reg, - u8 shift, u8 width, u32 mask_bit, spinlock_t *lock); - -struct hisi_clock_data *hisi_clk_alloc(struct platform_device *, int); -struct hisi_clock_data *hisi_clk_init(struct device_node *, int); -void hisi_clk_free(struct device_node *np, struct hisi_clock_data *data); -int hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *, - int, struct hisi_clock_data *); -int hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *, - int, struct hisi_clock_data *); -int hisi_clk_register_mux(const struct hisi_mux_clock *, int, - struct hisi_clock_data *); -struct clk *clk_register_hisi_phase(struct device *dev, - const struct hisi_phase_clock *clks, +struct clk_hw * +devm_clk_hw_register_hisi_phase(struct device *dev, const struct hisi_phase_clock *clks, void __iomem *base, spinlock_t *lock); +struct clk_hw * +devm_clk_hw_register_hisi_gate_sep(struct device *dev, const char *name, + const char *parent_name, unsigned long flags, + void __iomem *reg, u8 bit_idx, + u8 clk_gate_flags, spinlock_t *lock); +struct clk_hw * +devm_clk_hw_register_hi6220_divider(struct device *dev, const char *name, + const char *parent_name, unsigned long flags, + void __iomem *reg, u8 shift, + u8 width, u32 mask_bit, spinlock_t *lock); + +struct hisi_clock_data *hisi_clk_init(struct device_node *np, int nr); +void hisi_clk_free(struct device_node *np, struct hisi_clock_data *data); + +int hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *clks, + size_t num, struct hisi_clock_data *data); +int hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *clks, + size_t num, struct hisi_clock_data *data); + +int hisi_clk_register_mux(struct device *dev, const struct hisi_mux_clock *clks, + size_t num, struct hisi_clock_data *data); int hisi_clk_register_phase(struct device *dev, - const struct hisi_phase_clock *clks, - int nums, struct hisi_clock_data *data); -int hisi_clk_register_divider(const struct hisi_divider_clock *, - int, struct hisi_clock_data *); -int hisi_clk_register_gate(const struct hisi_gate_clock *, - int, struct hisi_clock_data *); -void hisi_clk_register_gate_sep(const struct hisi_gate_clock *, - int, struct hisi_clock_data *); -void hi6220_clk_register_divider(const struct hi6220_divider_clock *, - int, struct hisi_clock_data *); + const struct hisi_phase_clock *clks, + size_t num, struct hisi_clock_data *data); +int hisi_clk_register_divider(struct device *dev, + const struct hisi_divider_clock *clks, + size_t num, struct hisi_clock_data *data); +int hisi_clk_register_gate(struct device *dev, + const struct hisi_gate_clock *clks, + size_t num, struct hisi_clock_data *data); +int hisi_clk_register_gate_sep(struct device *dev, + const struct hisi_gate_clock *clks, + size_t num, struct hisi_clock_data *data); +int hi6220_clk_register_divider(struct device *dev, + const struct hi6220_divider_clock *clks, + size_t num, struct hisi_clock_data *data); int hisi_clk_register(struct device *dev, const struct hisi_clocks *clks, struct hisi_clock_data *data); @@ -181,22 +200,17 @@ int hisi_clk_remove(struct platform_device *pdev); #define hisi_clk_unregister_fn(type) \ static inline \ -void hisi_clk_unregister_##type(const struct hisi_##type##_clock *clks, \ - int nums, struct hisi_clock_data *data) \ +void hisi_clk_unregister_##type(struct hisi_clock_data *data) \ { \ - struct clk **clocks = data->clk_data.clks; \ int i; \ - for (i = 0; i < nums; i++) { \ - int id = clks[i].id; \ - if (clocks[id]) \ - clk_unregister_##type(clocks[id]); \ + for (i = 0; i < data->clks->type##_clks_num; i++) { \ + struct clk_hw *clk = data->clk_data->hws[data->clks->type##_clks[i].id]; \ + if (clk && !IS_ERR(clk)) \ + clk_hw_unregister_##type(clk); \ } \ } hisi_clk_unregister_fn(fixed_rate) hisi_clk_unregister_fn(fixed_factor) -hisi_clk_unregister_fn(mux) -hisi_clk_unregister_fn(divider) -hisi_clk_unregister_fn(gate) #endif /* __HISI_CLK_H */ diff --git a/drivers/clk/hisilicon/clkdivider-hi6220.c b/drivers/clk/hisilicon/clkdivider-hi6220.c index 5348bafe694f..3c03b3e5b841 100644 --- a/drivers/clk/hisilicon/clkdivider-hi6220.c +++ b/drivers/clk/hisilicon/clkdivider-hi6220.c @@ -9,7 +9,7 @@ #include #include -#include +#include #include #include #include @@ -97,19 +97,19 @@ static const struct clk_ops hi6220_clkdiv_ops = { .set_rate = hi6220_clkdiv_set_rate, }; -struct clk *hi6220_register_clkdiv(struct device *dev, const char *name, +struct clk_hw *devm_clk_hw_register_hi6220_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u32 mask_bit, spinlock_t *lock) { struct hi6220_clk_divider *div; - struct clk *clk; struct clk_init_data init; struct clk_div_table *table; u32 max_div, min_div; int i; + int ret; /* allocate the divider */ - div = kzalloc(sizeof(*div), GFP_KERNEL); + div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); if (!div) return ERR_PTR(-ENOMEM); @@ -117,11 +117,9 @@ struct clk *hi6220_register_clkdiv(struct device *dev, const char *name, max_div = div_mask(width) + 1; min_div = 1; - table = kcalloc(max_div + 1, sizeof(*table), GFP_KERNEL); - if (!table) { - kfree(div); + table = devm_kcalloc(dev, max_div + 1, sizeof(*table), GFP_KERNEL); + if (!table) return ERR_PTR(-ENOMEM); - } for (i = 0; i < max_div; i++) { table[i].div = min_div + i; @@ -144,11 +142,9 @@ struct clk *hi6220_register_clkdiv(struct device *dev, const char *name, div->table = table; /* register the clock */ - clk = clk_register(dev, &div->hw); - if (IS_ERR(clk)) { - kfree(table); - kfree(div); - } + ret = devm_clk_hw_register(dev, &div->hw); + if (ret) + return ERR_PTR(ret); - return clk; + return &div->hw; } diff --git a/drivers/clk/hisilicon/clkgate-separated.c b/drivers/clk/hisilicon/clkgate-separated.c index 90d858522967..dc64a8a0ab58 100644 --- a/drivers/clk/hisilicon/clkgate-separated.c +++ b/drivers/clk/hisilicon/clkgate-separated.c @@ -11,8 +11,8 @@ #include #include +#include #include -#include #include "clk.h" @@ -80,17 +80,18 @@ static const struct clk_ops clkgate_separated_ops = { .is_enabled = clkgate_separated_is_enabled, }; -struct clk *hisi_register_clkgate_sep(struct device *dev, const char *name, - const char *parent_name, - unsigned long flags, - void __iomem *reg, u8 bit_idx, - u8 clk_gate_flags, spinlock_t *lock) +struct clk_hw * +devm_clk_hw_register_hisi_gate_sep(struct device *dev, const char *name, + const char *parent_name, + unsigned long flags, + void __iomem *reg, u8 bit_idx, + u8 clk_gate_flags, spinlock_t *lock) { struct clkgate_separated *sclk; - struct clk *clk; struct clk_init_data init; + int ret; - sclk = kzalloc(sizeof(*sclk), GFP_KERNEL); + sclk = devm_kzalloc(dev, sizeof(*sclk), GFP_KERNEL); if (!sclk) return ERR_PTR(-ENOMEM); @@ -106,8 +107,9 @@ struct clk *hisi_register_clkgate_sep(struct device *dev, const char *name, sclk->hw.init = &init; sclk->lock = lock; - clk = clk_register(dev, &sclk->hw); - if (IS_ERR(clk)) - kfree(sclk); - return clk; + ret = devm_clk_hw_register(dev, &sclk->hw); + if (ret) + return ERR_PTR(ret); + + return &sclk->hw; }