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[90.24.137.155]) by smtp.gmail.com with ESMTPSA id k5-20020a05600c0b4500b003c41144b3cfsm2040233wmr.20.2022.10.21.01.47.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Oct 2022 01:47:56 -0700 (PDT) From: bchihi@baylibre.com To: sean.wang@kernel.org, linus.walleij@linaro.org, matthias.bgg@gmail.com Cc: linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [v2, 1/2] pinctrl: mediatek: common: add mt8365_set_clr_mode() callback for broken SET/CLR modes Date: Fri, 21 Oct 2022 10:47:07 +0200 Message-Id: <20221021084708.1109986-2-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221021084708.1109986-1-bchihi@baylibre.com> References: <20221021084708.1109986-1-bchihi@baylibre.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747286876815825259?= X-GMAIL-MSGID: =?utf-8?q?1747286876815825259?= From: Balsam CHIHI On MT8365, the SET/CLR of the mode is broken and some pin modes won't be set correctly. Add mt8365_set_clr_mode() callback for such SoCs, so that instead of using the SET/CLR register, use the main R/W register to read/update/write the modes. Co-developed-by: Fabien Parent Signed-off-by: Fabien Parent Signed-off-by: Balsam CHIHI --- drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 15 +++++++++++++++ drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 8 +++++++- 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index f25b3e09386b..076ae0b38e3d 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -330,6 +330,21 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl, return -EINVAL; } + if (pctl->devdata->mt8365_set_clr_mode) { + bit = pin & pctl->devdata->mode_mask; + reg_pullen = mtk_get_port(pctl, pin) + + pctl->devdata->pullen_offset; + reg_pullsel = mtk_get_port(pctl, pin) + + pctl->devdata->pullsel_offset; + ret = pctl->devdata->mt8365_set_clr_mode(mtk_get_regmap(pctl, pin), + bit, reg_pullen, reg_pullsel, + enable, isup); + if (ret) + return -EINVAL; + + return 0; + } + bit = BIT(pin & pctl->devdata->mode_mask); if (enable) reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) + diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h index 6fe8564334c9..11afa12a96cb 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h @@ -216,7 +216,10 @@ struct mtk_eint_offsets { * @spec_dir_set: In very few SoCs, direction control registers are not * arranged continuously, they may be cut to parts. So they need special * dir setting. - + * @mt8365_set_clr_mode: In mt8365, some pins won't set correcty because they + * need to use the main R/W register to read/update/write the modes instead of + * the SET/CLR register. + * * @dir_offset: The direction register offset. * @pullen_offset: The pull-up/pull-down enable register offset. * @pinmux_offset: The pinmux register offset. @@ -252,6 +255,9 @@ struct mtk_pinctrl_devdata { void (*spec_pinmux_set)(struct regmap *reg, unsigned int pin, unsigned int mode); void (*spec_dir_set)(unsigned int *reg_addr, unsigned int pin); + int (*mt8365_set_clr_mode)(struct regmap *regmap, + unsigned int bit, unsigned int reg_pullen, unsigned int reg_pullsel, + bool enable, bool isup); unsigned int dir_offset; unsigned int ies_offset; unsigned int smt_offset; From patchwork Fri Oct 21 08:47:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Balsam CHIHI X-Patchwork-Id: 6580 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4242:0:0:0:0:0 with SMTP id s2csp573948wrr; Fri, 21 Oct 2022 01:57:48 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4iJ59fxQMHxSe+ZVX6fSOwos3ncFRH56gFBARGuV8DrdZZfn+zEGlcCt4X9z40CRcokm+0 X-Received: by 2002:a17:907:60d3:b0:78d:f874:3267 with SMTP id hv19-20020a17090760d300b0078df8743267mr14495774ejc.409.1666342668020; Fri, 21 Oct 2022 01:57:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666342668; cv=none; d=google.com; s=arc-20160816; b=vH36uM/a7snBK24jC72joyqeyZMh/8G0ZBpyXrrLkY1H8kZOFOB7xG+ckkLX40f5Zj UCoyzqkzssIrXNpFJao9XezTMZBE7d20GQg1FOGIq1qV2bjMvTOzDdKKnxoUigZ1u7pi uu49V7+ktQW79WXSgEZs+WNkSWCQfjm6k7sSBOAA3h81+JFaIo6w3y7lrRA8JQYqVYkL jQ2+M2I2m9sasbY1tyZOD1vdJpIj0Tz4QI3Xbb20RkVk0WkVTUhGII9rsVkn1v7KhQBs Ztl0Pr8MtFi21JpSf5HYxpcKJBsVFDLZG7nkbMzCnUj+35NHJZA+WlDaBRK9tWgmDRL0 r/8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=IbWZD88Csa/gnzCp+HMy/jlXVSOibosOwLIHUydjLSM=; b=xaBqfdkfQUzrJsiSGKN/7X0uheaLuUIwjk3llUqkDP28Y+jgoLGPc3TxuHl/DGaO1J YIJa/Ma9PeHJNKeeRSyjHqTIrEaDDx/BY2iLUQgSO29Qe26S8KFsnjmzYqepnf+xx4ry 4AjD+l+d2R+7GLHmh71J+F4oW9eeqP1POO4uF+mAJAzgK01wEKFtAbrB0w0LckSfM4cS K0/3gKE7P2HasOAZ+bGF+mTqDb3NhFFmw8d8bs2BE7YA2Jg1Xb8sZVqpt0tkV5iSMjgc qqm2uIzUJLJ5+unaEIFfpUWjjSI21ubrjnz5+Rl4Nja51RjUE4eKFwZvX2D3DNjfwiXa I4mw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=SsKIYrb7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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[90.24.137.155]) by smtp.gmail.com with ESMTPSA id k5-20020a05600c0b4500b003c41144b3cfsm2040233wmr.20.2022.10.21.01.47.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Oct 2022 01:47:57 -0700 (PDT) From: bchihi@baylibre.com To: sean.wang@kernel.org, linus.walleij@linaro.org, matthias.bgg@gmail.com Cc: linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [v2, 2/2] pinctrl: mediatek: mt8365: use mt8365_set_clr_mode() callback Date: Fri, 21 Oct 2022 10:47:08 +0200 Message-Id: <20221021084708.1109986-3-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221021084708.1109986-1-bchihi@baylibre.com> References: <20221021084708.1109986-1-bchihi@baylibre.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747286929709898400?= X-GMAIL-MSGID: =?utf-8?q?1747286929709898400?= From: Balsam CHIHI On MT8365, the SET/CLR of the mode is broken and some pin modes won't be set correctly. Use the mt8365_set_clr_mode() callback to fix the issue. Co-developed-by: Fabien Parent Signed-off-by: Fabien Parent Signed-off-by: Balsam CHIHI --- drivers/pinctrl/mediatek/pinctrl-mt8365.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8365.c b/drivers/pinctrl/mediatek/pinctrl-mt8365.c index 57f37a294063..42b48136ab77 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8365.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c @@ -416,6 +416,23 @@ static const struct mtk_pin_ies_smt_set mt8365_smt_set[] = { MTK_PIN_IES_SMT_SPEC(144, 144, 0x480, 22), }; +static int mt8365_set_clr_mode(struct regmap *regmap, + unsigned int bit, unsigned int reg_pullen, unsigned int reg_pullsel, + bool enable, bool isup) +{ + int ret; + + ret = regmap_update_bits(regmap, reg_pullen, BIT(bit), enable << bit); + if (ret) + return -EINVAL; + + ret = regmap_update_bits(regmap, reg_pullsel, BIT(bit), isup << bit); + if (ret) + return -EINVAL; + + return 0; +} + static const struct mtk_pinctrl_devdata mt8365_pinctrl_data = { .pins = mtk_pins_mt8365, .npins = ARRAY_SIZE(mtk_pins_mt8365), @@ -431,6 +448,7 @@ static const struct mtk_pinctrl_devdata mt8365_pinctrl_data = { .n_spec_pupd = ARRAY_SIZE(mt8365_spec_pupd), .spec_pull_set = mtk_pctrl_spec_pull_set_samereg, .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range, + .mt8365_set_clr_mode = mt8365_set_clr_mode, .dir_offset = 0x0140, .dout_offset = 0x00A0, .din_offset = 0x0000,