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Howlett" Subject: [PATCH v2 1/3] genirq: Use hlist for managing resend handlers Date: Sat, 8 Apr 2023 12:15:24 -0500 Message-ID: <20230408171526.3059039-2-sdonthineni@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230408171526.3059039-1-sdonthineni@nvidia.com> References: <20230408171526.3059039-1-sdonthineni@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT027:EE_|CH2PR12MB4056:EE_ X-MS-Office365-Filtering-Correlation-Id: 73f28643-dead-461b-5435-08db3854dd3f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: iE1j07dxMaB+NZH23TRvpE67ZGHjjzEiME2zt0dmxLxI1CrN5ilmTrKwBf19JJXIr67Nf8eBMJ4W33T8hRz2wqpIeQBiKedzBxdJohALNHXUPdMoZRApPhMxJQsEYdY996WnVV3lzRN1oPLDz2eDBCH6/cunUWpjOspLymezpU7ISzb3Q1+/V8uKqMb3jHQiUzI0H2G55yrbOCwMXOP4ddeMgCp5OGMlXErTa+lUuI96fULc223v9mYX8kjwdPMIgZqfLdbHaWTfj12+b1OCzVm7JnEFOllu/CtqvkjM6xANZXSIGpkgFfpIpP/g0iW2FDmUuLjpr72kILu9SUTJiJ0iVHbUVtV+4MWO+Yg8WG6KnKNXZDMDpH/ZYaFMHfsLXEXPGz5j7ztJ15dC3uokDp7UVeDsaphiV17tqTKNlxJknmji6MQX5D2fopa1UBHt4cCJt6GI396/QhXPwUE6kPLKpUZD22q9EFedJ3iH5qiOH2bUTcxgHvHVIAHrNL38rO/GPviEEOI0nQ3pVazuvNnKeSM5a20/mOcTlwTDh4IFqSNBDrCn0n09NP/LufbyZYhGxx0SihC/64vLemdEtscxq0hm2bpyAuvl6pB/XACoS3d5Vr4XDdKPL+3fadhAIsj0XqhMrKgutyD+rcAilTd3yzJ7i+0sSBKhKZS8bkbwvMxSuw8l8rDN5EWZVTsqhU1QDIt3SBe38U/bcXqj2WySwAsGgliv6n1n4Xw59iE0s+TvBv6c3Z1tXo8c8swV X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230028)(4636009)(39860400002)(136003)(396003)(346002)(376002)(451199021)(46966006)(36840700001)(40470700004)(316002)(66899021)(40480700001)(6666004)(36756003)(41300700001)(82310400005)(40460700003)(8936002)(47076005)(110136005)(7696005)(86362001)(2616005)(54906003)(186003)(336012)(426003)(82740400003)(1076003)(356005)(5660300002)(26005)(83380400001)(36860700001)(7636003)(2906002)(70206006)(478600001)(70586007)(4326008)(8676002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Apr 2023 17:15:34.1505 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 73f28643-dead-461b-5435-08db3854dd3f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT027.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4056 X-Spam-Status: No, score=0.8 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762631801814132173?= X-GMAIL-MSGID: =?utf-8?q?1762631801814132173?= The current implementation utilizes a bitmap for managing IRQ resend handlers, which is allocated based on the SPARSE_IRQ/NR_IRQS macros. However, this method may not efficiently utilize memory during runtime, particularly when IRQ_BITMAP_BITS is large. This proposed patch aims to address this issue by using hlist to manage IRQ resend handlers instead of relying on static memory allocation. Additionally, a new function, clear_irq_resend(), is introduced and called from irq_shutdown to ensure a graceful teardown of IRQD. Signed-off-by: Shanker Donthineni --- include/linux/irqdesc.h | 3 +++ kernel/irq/chip.c | 1 + kernel/irq/internals.h | 1 + kernel/irq/irqdesc.c | 6 ++++++ kernel/irq/resend.c | 41 ++++++++++++++++++++++++----------------- 5 files changed, 35 insertions(+), 17 deletions(-) diff --git a/include/linux/irqdesc.h b/include/linux/irqdesc.h index 844a8e30e6de..d9451d456a73 100644 --- a/include/linux/irqdesc.h +++ b/include/linux/irqdesc.h @@ -102,6 +102,9 @@ struct irq_desc { int parent_irq; struct module *owner; const char *name; +#ifdef CONFIG_HARDIRQS_SW_RESEND + struct hlist_node resend_node; +#endif } ____cacheline_internodealigned_in_smp; #ifdef CONFIG_SPARSE_IRQ diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c index 49e7bc871fec..2eac5532c3c8 100644 --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -306,6 +306,7 @@ static void __irq_disable(struct irq_desc *desc, bool mask); void irq_shutdown(struct irq_desc *desc) { if (irqd_is_started(&desc->irq_data)) { + clear_irq_resend(desc); desc->depth = 1; if (desc->irq_data.chip->irq_shutdown) { desc->irq_data.chip->irq_shutdown(&desc->irq_data); diff --git a/kernel/irq/internals.h b/kernel/irq/internals.h index 5fdc0b557579..2fd17057ed4b 100644 --- a/kernel/irq/internals.h +++ b/kernel/irq/internals.h @@ -113,6 +113,7 @@ irqreturn_t handle_irq_event(struct irq_desc *desc); /* Resending of interrupts :*/ int check_irq_resend(struct irq_desc *desc, bool inject); +void clear_irq_resend(struct irq_desc *desc); bool irq_wait_for_poll(struct irq_desc *desc); void __irq_wake_thread(struct irq_desc *desc, struct irqaction *action); diff --git a/kernel/irq/irqdesc.c b/kernel/irq/irqdesc.c index 240e145e969f..47543b5a0edb 100644 --- a/kernel/irq/irqdesc.c +++ b/kernel/irq/irqdesc.c @@ -415,6 +415,9 @@ static struct irq_desc *alloc_desc(int irq, int node, unsigned int flags, desc_set_defaults(irq, desc, node, affinity, owner); irqd_set(&desc->irq_data, flags); kobject_init(&desc->kobj, &irq_kobj_type); +#ifdef CONFIG_HARDIRQS_SW_RESEND + INIT_HLIST_NODE(&desc->resend_node); +#endif return desc; @@ -581,6 +584,9 @@ int __init early_irq_init(void) mutex_init(&desc[i].request_mutex); init_waitqueue_head(&desc[i].wait_for_threads); desc_set_defaults(i, &desc[i], node, NULL, NULL); +#ifdef CONFIG_HARDIRQS_SW_RESEND + INIT_HLIST_NODE(&desc->resend_node); +#endif } return arch_early_irq_init(); } diff --git a/kernel/irq/resend.c b/kernel/irq/resend.c index 0c46e9fe3a89..d3db2628a720 100644 --- a/kernel/irq/resend.c +++ b/kernel/irq/resend.c @@ -21,8 +21,9 @@ #ifdef CONFIG_HARDIRQS_SW_RESEND -/* Bitmap to handle software resend of interrupts: */ -static DECLARE_BITMAP(irqs_resend, IRQ_BITMAP_BITS); +/* hlist_head to handle software resend of interrupts: */ +static HLIST_HEAD(irq_resend_list); +static DEFINE_RAW_SPINLOCK(irq_resend_lock); /* * Run software resends of IRQ's @@ -30,18 +31,17 @@ static DECLARE_BITMAP(irqs_resend, IRQ_BITMAP_BITS); static void resend_irqs(struct tasklet_struct *unused) { struct irq_desc *desc; - int irq; - - while (!bitmap_empty(irqs_resend, nr_irqs)) { - irq = find_first_bit(irqs_resend, nr_irqs); - clear_bit(irq, irqs_resend); - desc = irq_to_desc(irq); - if (!desc) - continue; - local_irq_disable(); + + raw_spin_lock_irq(&irq_resend_lock); + while (!hlist_empty(&irq_resend_list)) { + desc = hlist_entry(irq_resend_list.first, struct irq_desc, + resend_node); + hlist_del_init(&desc->resend_node); + raw_spin_unlock(&irq_resend_lock); desc->handle_irq(desc); - local_irq_enable(); + raw_spin_lock(&irq_resend_lock); } + raw_spin_unlock_irq(&irq_resend_lock); } /* Tasklet to handle resend: */ @@ -49,8 +49,6 @@ static DECLARE_TASKLET(resend_tasklet, resend_irqs); static int irq_sw_resend(struct irq_desc *desc) { - unsigned int irq = irq_desc_get_irq(desc); - /* * Validate whether this interrupt can be safely injected from * non interrupt context @@ -70,16 +68,25 @@ static int irq_sw_resend(struct irq_desc *desc) */ if (!desc->parent_irq) return -EINVAL; - irq = desc->parent_irq; } - /* Set it pending and activate the softirq: */ - set_bit(irq, irqs_resend); + /* Add to resend_list and activate the softirq: */ + raw_spin_lock(&irq_resend_lock); + hlist_add_head(&desc->resend_node, &irq_resend_list); + raw_spin_unlock(&irq_resend_lock); tasklet_schedule(&resend_tasklet); return 0; } +void clear_irq_resend(struct irq_desc *desc) +{ + raw_spin_lock(&irq_resend_lock); + hlist_del_init(&desc->resend_node); + raw_spin_unlock(&irq_resend_lock); +} #else +void clear_irq_resend(struct irq_desc *desc) {} + static int irq_sw_resend(struct irq_desc *desc) { return -EINVAL; From patchwork Sat Apr 8 17:15:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shanker Donthineni X-Patchwork-Id: 81256 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp986967vqo; Sat, 8 Apr 2023 10:28:06 -0700 (PDT) X-Google-Smtp-Source: AKy350Z2Z6AA6swhY9suNENoyMvbQtGks6EO7ZTfcfcCaDdZq6BJ90b11TiiK0se4KlXHxAjFahP X-Received: by 2002:aa7:cf14:0:b0:4fa:ba60:8188 with SMTP id a20-20020aa7cf14000000b004faba608188mr4256598edy.8.1680974886680; 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Howlett" Subject: [PATCH v2 2/3] genirq: Encapsulate sparse bitmap handling Date: Sat, 8 Apr 2023 12:15:25 -0500 Message-ID: <20230408171526.3059039-3-sdonthineni@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230408171526.3059039-1-sdonthineni@nvidia.com> References: <20230408171526.3059039-1-sdonthineni@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT085:EE_|SA3PR12MB7857:EE_ X-MS-Office365-Filtering-Correlation-Id: 047281f5-dee2-461e-40f5-08db3854db70 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: uKvmiux4rl3vsnm92UoRs8n5/OpWhCUYkJSZ9ngDkxECtiZdXQD1cI3KB5xaBaoR/SjTjq6D5zQuPk8kipMKA5Cqe53/mKLJ+EFLqmeK0WPyi/0Kivzc+V7GqZcD7HQIO7PkxchaN/McpOYF30+sWr8y6VIXbl8HDqrWILhgapIUPCc6Zs62dDlS8MUfC6ZQALMbs9sZRZUT6H/ihgMZtwUXo9o53w9TEYr6xxfIwpB3S3V39ZugbLCz78RnbCkEX3OCp3oWU7HJ8PWnAffY0fjedQGTaLTq5F/7VtFtceDFUGGjiwIeXm0Tu9mDhW79z8db0t7k9DqrTO2r56JFnB9q+KZT5wV4eB0fpvvqKgI1aDqmPF40ub5ue+IKu2gM8UtizQt2mMwzIwjLylTfMASKmugVgVxkLZhrFiGQ9AlLCIIl9HHHh6jUwWqvNu5oCvn0SXxNlgdxGRu8fCfKoBd7BFBub8EaGQVl0XBi+tEQIGUgg0VVJXvH7/7LCyNt2b6OHYoOWxy8mFYP05+6d3M7ApWHQF0WG6Ci/Qn1/YlsHWKEQJH/GdNwIAHwXCvpZURQSYdAawFT1I8EhItCGwm/yS/lAc2QQVkJ2y1L8As6ZmLsmU20j5AeyFvWdoibkrYOdQUIYFwrrGcBwKWm0KmSmhp8fMMw/VeUj96gtilfPwlPTZvRKfYqrS50Sk3XUM/28pUBd76SB75FQuXK1s42eXM5RXaYQkTVYSbizUQ= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230028)(4636009)(39860400002)(376002)(396003)(136003)(346002)(451199021)(46966006)(36840700001)(7696005)(478600001)(86362001)(40480700001)(47076005)(83380400001)(36756003)(82740400003)(7636003)(356005)(2616005)(36860700001)(426003)(336012)(6666004)(2906002)(54906003)(110136005)(316002)(186003)(1076003)(26005)(8676002)(41300700001)(8936002)(5660300002)(82310400005)(4326008)(70586007)(70206006);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Apr 2023 17:15:31.2095 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 047281f5-dee2-461e-40f5-08db3854db70 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT085.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7857 X-Spam-Status: No, score=0.8 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762629922682139978?= X-GMAIL-MSGID: =?utf-8?q?1762629922682139978?= Move the open coded sparse bitmap handling into helper functions as a preparatory step for converting the sparse interrupt management to a maple tree. No functional change. Signed-off-by: Shanker Donthineni --- kernel/irq/internals.h | 4 ++-- kernel/irq/irqdesc.c | 28 +++++++++++++++++++--------- 2 files changed, 21 insertions(+), 11 deletions(-) diff --git a/kernel/irq/internals.h b/kernel/irq/internals.h index 2fd17057ed4b..5d741b0e7d5e 100644 --- a/kernel/irq/internals.h +++ b/kernel/irq/internals.h @@ -12,9 +12,9 @@ #include #ifdef CONFIG_SPARSE_IRQ -# define IRQ_BITMAP_BITS (NR_IRQS + 8196) +# define MAX_SPARSE_IRQS (NR_IRQS + 8196) #else -# define IRQ_BITMAP_BITS NR_IRQS +# define MAX_SPARSE_IRQS NR_IRQS #endif #define istate core_internal_state__do_not_mess_with_it diff --git a/kernel/irq/irqdesc.c b/kernel/irq/irqdesc.c index 47543b5a0edb..e0c259769d3a 100644 --- a/kernel/irq/irqdesc.c +++ b/kernel/irq/irqdesc.c @@ -131,7 +131,18 @@ int nr_irqs = NR_IRQS; EXPORT_SYMBOL_GPL(nr_irqs); static DEFINE_MUTEX(sparse_irq_lock); -static DECLARE_BITMAP(allocated_irqs, IRQ_BITMAP_BITS); +static DECLARE_BITMAP(allocated_irqs, MAX_SPARSE_IRQS); + +static int irq_find_free_area(unsigned int from, unsigned int cnt) +{ + return bitmap_find_next_zero_area(allocated_irqs, MAX_SPARSE_IRQS, + from, cnt, 0); +} + +static unsigned int irq_find_next_irq(unsigned int offset) +{ + return find_next_bit(allocated_irqs, nr_irqs, offset); +} #ifdef CONFIG_SPARSE_IRQ @@ -519,7 +530,7 @@ static int alloc_descs(unsigned int start, unsigned int cnt, int node, static int irq_expand_nr_irqs(unsigned int nr) { - if (nr > IRQ_BITMAP_BITS) + if (nr > MAX_SPARSE_IRQS) return -ENOMEM; nr_irqs = nr; return 0; @@ -537,11 +548,11 @@ int __init early_irq_init(void) printk(KERN_INFO "NR_IRQS: %d, nr_irqs: %d, preallocated irqs: %d\n", NR_IRQS, nr_irqs, initcnt); - if (WARN_ON(nr_irqs > IRQ_BITMAP_BITS)) - nr_irqs = IRQ_BITMAP_BITS; + if (WARN_ON(nr_irqs > MAX_SPARSE_IRQS)) + nr_irqs = MAX_SPARSE_IRQS; - if (WARN_ON(initcnt > IRQ_BITMAP_BITS)) - initcnt = IRQ_BITMAP_BITS; + if (WARN_ON(initcnt > MAX_SPARSE_IRQS)) + initcnt = MAX_SPARSE_IRQS; if (initcnt > nr_irqs) nr_irqs = initcnt; @@ -816,8 +827,7 @@ __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, mutex_lock(&sparse_irq_lock); - start = bitmap_find_next_zero_area(allocated_irqs, IRQ_BITMAP_BITS, - from, cnt, 0); + start = irq_find_free_area(from, cnt); ret = -EEXIST; if (irq >=0 && start != irq) goto unlock; @@ -842,7 +852,7 @@ EXPORT_SYMBOL_GPL(__irq_alloc_descs); */ unsigned int irq_get_next_irq(unsigned int offset) { - return find_next_bit(allocated_irqs, nr_irqs, offset); + return irq_find_next_irq(offset); } struct irq_desc * From patchwork Sat Apr 8 17:15:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shanker Donthineni X-Patchwork-Id: 81260 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1010358vqo; Sat, 8 Apr 2023 11:30:02 -0700 (PDT) X-Google-Smtp-Source: AKy350ateUoShrMkwLSsMaUE3fySSGO/U7PvxAWkjPfqrAsFivgd58ZlMPlcFmWFon1l2pel22g0 X-Received: by 2002:a17:906:1c08:b0:926:8992:4310 with SMTP id k8-20020a1709061c0800b0092689924310mr2731898ejg.38.1680978602523; Sat, 08 Apr 2023 11:30:02 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1680978602; cv=pass; d=google.com; s=arc-20160816; b=obLehaS1YonTRoAspjgB7tnppXnlq8nJn9EYN6kKNliPn7GPVuCwKL5qHKtbn+1QVB 43V/yRDtu1RtToeM5wyspn6sOXf04Ep0iiF6BkpoVFSvXOuSW8lrj7lhINdDuEIXrZ0n IzYnDyii0OLDfWAbvKrzSgJB1RyuoAVY0amud7k/pIPwg62I/MTF5eliwqytW8Q3dHB2 RK6wLUwxJVFjhi7rK4W8KykZaV6jgBsmbm1Ad+6tC34Rz+Zhd8KO8Mi5F4IqHWkS0XSk UJ/5KIobWQln9M6LAOefdacT5176kKoDxyWmtTHxhUsBCpot+3rt3AGa4sniG4Tz/imw k9Jg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=7UgW6KESOHc5sgbPe0hUdQL5gOYOFE3Axyj/hr6Gioo=; b=MieMRsA9G2tBJRyMGisA3cDNHsd5+Q5tW6Aq+rAMRrvHTP3fOrEuR4cyk2BLgzMJNI MrqPhZ8XPIDCfb1LXH/oykottf5QN/QRfGFLmboS4StcpHW0Kn0pp25Xr1Zr+rKux5Oh dIKArel8vytiAfAtdCfw1H6yTsCaHpHwBUeko0ROon02tdvAV+UbDQANNw9vRTVMFBGr i+qv+z8HA+6BR7srIDsD+EMEWjpIEMOpNRmOVBMD6XAAtA3RPB4D65xEd4xaTCEnuPPM KUfU1c4FTFrKQfUDEB9XPzkxpWOIvf9izg7BVE7bmIil4kQSrubAmeZOPCyo6PPbC1T2 tYVg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=qB3whkMb; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Howlett" Subject: [PATCH v2 3/3] genirq: Use the maple tree for IRQ descriptors management Date: Sat, 8 Apr 2023 12:15:26 -0500 Message-ID: <20230408171526.3059039-4-sdonthineni@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230408171526.3059039-1-sdonthineni@nvidia.com> References: <20230408171526.3059039-1-sdonthineni@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT041:EE_|IA1PR12MB8539:EE_ X-MS-Office365-Filtering-Correlation-Id: 61f94f58-20b0-4310-7fff-08db3854defa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 5TKMETXxdRVoSpxqZFbm9TpaY+D8bmYvQ73Hk2HNU7/sPt8mbud2cyGMABs58hqN7a+s/arlp1FajIWv4Pup219JnJ7kFHJXLY8ccg4eAdXQnWHLrNG2kPxVm18u1zcqK2qqlxK4zRXAyWcryzJ30knuVpspz35im7T9PiVbEfhD5S5NRALUCeVRIoJmqiP4bgjvis+69ITmZEiPHy1tNGSNdx1UZfWRk/rLYxIUiMFpBNEKQRKFXLP2Valzcfm+yju+3JENq+0H93e2tP5btwqMaCSOsyfo1jwaLJT2Cv3+eFIQsC7DsO2osX5m7xKZ7ugsfErhSkjf4QgHnImZ5r44TToD1RojlUhn8rJmCL8zQWOsDHgnE0ukQurwzW2Eyd3w6gWQYEWBAZAGccGL6lkn8fpT6mJlPFh2D+UvT3PyCBOb3AwZvhcvxwIDVShB0HRN9OCOdnOA2gw2bPCWYxIi+opEAjsKvMuPRSX7Vx3Fhkx6o8Gg5hNVWTA4CjozeJcJ1ikGgq18vczwIJaVy3+8wvF20ygfNpfh+72TJK/XB+WWIORPv42dwu6z/7HVbtUHA7JKOH7RwRLmQvaek2DDGMlhIoQUmyiMCK6bRgZDoeJQsnfhBBeIk3bTeTCIKMFDXF9PMwOkbg3EBIcPRnaTLStjmQ9Vpx96NZUQmLIJzb1c8Q38n6ZO7cG1RlYZ0HzxhepbvWhPh6u39TcstYMFljsq77AFa018PLRo7NlREGCyEbwWAE5Q9U6DpWhH X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230028)(4636009)(346002)(39860400002)(376002)(136003)(396003)(451199021)(40470700004)(36840700001)(46966006)(36756003)(6666004)(86362001)(82310400005)(66899021)(2906002)(5660300002)(426003)(40480700001)(1076003)(478600001)(2616005)(186003)(47076005)(7696005)(83380400001)(336012)(26005)(70206006)(36860700001)(7636003)(4326008)(70586007)(110136005)(41300700001)(8676002)(54906003)(8936002)(356005)(82740400003)(40460700003)(316002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Apr 2023 17:15:37.0549 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 61f94f58-20b0-4310-7fff-08db3854defa X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT041.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8539 X-Spam-Status: No, score=0.8 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762633819520869208?= X-GMAIL-MSGID: =?utf-8?q?1762633819520869208?= The current implementation uses a static bitmap and a radix tree to manage IRQ allocation and irq_desc pointer store respectively. However, the size of the bitmap is constrained by the build time macro MAX_SPARSE_IRQS, which may not be sufficient to support the high-end servers, particularly those with GICv4.1 hardware, which require a large interrupt space to cover LPIs and vSGIs The maple tree is a highly efficient data structure for storing non-overlapping ranges and can handle a large number of entries, up to ULONG_MAX. It can be utilized for both storing IRQD and identifying available free spaces. The interrupt descriptors management can be simplified by switching to a maple tree data structure, which offers greater flexibility and scalability. To support modern servers, the maximum number of IRQs has been increased to INT_MAX, which provides a more adequate value than the previous limit of NR_IRQS+8192. Signed-off-by: Shanker Donthineni --- kernel/irq/internals.h | 2 +- kernel/irq/irqdesc.c | 54 +++++++++++++++++++++++------------------- 2 files changed, 31 insertions(+), 25 deletions(-) diff --git a/kernel/irq/internals.h b/kernel/irq/internals.h index 5d741b0e7d5e..e35de737802c 100644 --- a/kernel/irq/internals.h +++ b/kernel/irq/internals.h @@ -12,7 +12,7 @@ #include #ifdef CONFIG_SPARSE_IRQ -# define MAX_SPARSE_IRQS (NR_IRQS + 8196) +# define MAX_SPARSE_IRQS INT_MAX #else # define MAX_SPARSE_IRQS NR_IRQS #endif diff --git a/kernel/irq/irqdesc.c b/kernel/irq/irqdesc.c index e0c259769d3a..e2e95e937c11 100644 --- a/kernel/irq/irqdesc.c +++ b/kernel/irq/irqdesc.c @@ -12,8 +12,7 @@ #include #include #include -#include -#include +#include #include #include @@ -131,17 +130,38 @@ int nr_irqs = NR_IRQS; EXPORT_SYMBOL_GPL(nr_irqs); static DEFINE_MUTEX(sparse_irq_lock); -static DECLARE_BITMAP(allocated_irqs, MAX_SPARSE_IRQS); +static struct maple_tree sparse_irqs = MTREE_INIT_EXT(sparse_irqs, + MT_FLAGS_ALLOC_RANGE | + MT_FLAGS_LOCK_EXTERN | + MT_FLAGS_USE_RCU, + sparse_irq_lock); static int irq_find_free_area(unsigned int from, unsigned int cnt) { - return bitmap_find_next_zero_area(allocated_irqs, MAX_SPARSE_IRQS, - from, cnt, 0); + MA_STATE(mas, &sparse_irqs, 0, 0); + + if (mas_empty_area(&mas, from, MAX_SPARSE_IRQS, cnt)) + return -ENOSPC; + return mas.index; } static unsigned int irq_find_next_irq(unsigned int offset) { - return find_next_bit(allocated_irqs, nr_irqs, offset); + struct irq_desc *desc = mt_next(&sparse_irqs, offset, nr_irqs); + + return desc ? irq_desc_get_irq(desc) : nr_irqs; +} + +static void irq_insert_desc(unsigned int irq, struct irq_desc *desc) +{ + MA_STATE(mas, &sparse_irqs, irq, irq); + WARN_ON(mas_store_gfp(&mas, desc, GFP_KERNEL) != 0); +} + +static void delete_irq_desc(unsigned int irq) +{ + MA_STATE(mas, &sparse_irqs, irq, irq); + mas_erase(&mas); } #ifdef CONFIG_SPARSE_IRQ @@ -355,26 +375,14 @@ static void irq_sysfs_del(struct irq_desc *desc) {} #endif /* CONFIG_SYSFS */ -static RADIX_TREE(irq_desc_tree, GFP_KERNEL); - -static void irq_insert_desc(unsigned int irq, struct irq_desc *desc) -{ - radix_tree_insert(&irq_desc_tree, irq, desc); -} - struct irq_desc *irq_to_desc(unsigned int irq) { - return radix_tree_lookup(&irq_desc_tree, irq); + return mtree_load(&sparse_irqs, irq); } #ifdef CONFIG_KVM_BOOK3S_64_HV_MODULE EXPORT_SYMBOL_GPL(irq_to_desc); #endif -static void delete_irq_desc(unsigned int irq) -{ - radix_tree_delete(&irq_desc_tree, irq); -} - #ifdef CONFIG_SMP static void free_masks(struct irq_desc *desc) { @@ -519,7 +527,6 @@ static int alloc_descs(unsigned int start, unsigned int cnt, int node, irq_sysfs_add(start + i, desc); irq_add_debugfs_entry(start + i, desc); } - bitmap_set(allocated_irqs, start, cnt); return start; err: @@ -559,7 +566,6 @@ int __init early_irq_init(void) for (i = 0; i < initcnt; i++) { desc = alloc_desc(i, node, 0, NULL, NULL); - set_bit(i, allocated_irqs); irq_insert_desc(i, desc); } return arch_early_irq_init(); @@ -616,6 +622,7 @@ static void free_desc(unsigned int irq) raw_spin_lock_irqsave(&desc->lock, flags); desc_set_defaults(irq, desc, irq_desc_get_node(desc), NULL, NULL); raw_spin_unlock_irqrestore(&desc->lock, flags); + delete_irq_desc(irq); } static inline int alloc_descs(unsigned int start, unsigned int cnt, int node, @@ -628,8 +635,8 @@ static inline int alloc_descs(unsigned int start, unsigned int cnt, int node, struct irq_desc *desc = irq_to_desc(start + i); desc->owner = owner; + irq_insert_desc(start + i, desc); } - bitmap_set(allocated_irqs, start, cnt); return start; } @@ -641,7 +648,7 @@ static int irq_expand_nr_irqs(unsigned int nr) void irq_mark_irq(unsigned int irq) { mutex_lock(&sparse_irq_lock); - bitmap_set(allocated_irqs, irq, 1); + irq_insert_desc(irq, irq_desc + irq); mutex_unlock(&sparse_irq_lock); } @@ -785,7 +792,6 @@ void irq_free_descs(unsigned int from, unsigned int cnt) for (i = 0; i < cnt; i++) free_desc(from + i); - bitmap_clear(allocated_irqs, from, cnt); mutex_unlock(&sparse_irq_lock); } EXPORT_SYMBOL_GPL(irq_free_descs);