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[2620:137:e000::1:20]) by mx.google.com with ESMTP id r22-20020a635156000000b00513965a1e60si5384327pgl.902.2023.04.08.03.55.33; Sat, 08 Apr 2023 03:55:46 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="P2m3FO/d"; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230255AbjDHKtX (ORCPT + 99 others); Sat, 8 Apr 2023 06:49:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50444 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230091AbjDHKsx (ORCPT ); Sat, 8 Apr 2023 06:48:53 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 69E814C17 for ; Sat, 8 Apr 2023 03:48:16 -0700 (PDT) Date: Sat, 08 Apr 2023 10:45:18 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1680950719; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/R+i6qSM/tz3QsWrNskcebHFoqQAOulOwqXrKjDR7Fc=; b=P2m3FO/dZsFf7odZi68T5eXGJb7FK6tZDDzEu0JEHb+heEZHqCdnQsqU6UPRXKHkNpxig9 96fVzyF2Bjw6xsVT0Q4HMzuatPjDz2tP6lSpiyygHhiIylYWz62sNU52swvOxbxUi5OPix CyBRYW+uUGsORhEvM8h5vIFL8NmsLR5B182zGYDlFAm/6u2Uq9ZLv4Jq+kKulbwbGopagP U5bbzCLMHNx6wtyXMMo4vdSAid9brTIkTC8e0D9BcPkY35Mf3B70yXbKfLYrBHJ0L4jkSl ZtmadDuwcHjGygDlcHFGLBPZeyY2HAzyInVBbU8fzsajjwAiMrqe55v/ECbxXQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1680950719; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/R+i6qSM/tz3QsWrNskcebHFoqQAOulOwqXrKjDR7Fc=; b=zyOUaqQaAZG+Pdxt3okUJQjfJ37tLkot4jU2nirX5vxC9jGauPJ95A9AFRZPZS6t4bUUC3 9H6S536Mow0FbyBQ== From: "irqchip-bot for Anup Patel" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-kernel@vger.kernel.org Subject: [irqchip: irq/irqchip-next] irqchip/riscv-intc: Allow drivers to directly discover INTC hwnode Cc: Anup Patel , Atish Patra , Palmer Dabbelt , Marc Zyngier , tglx@linutronix.de In-Reply-To: <20230328035223.1480939-3-apatel@ventanamicro.com> References: <20230328035223.1480939-3-apatel@ventanamicro.com> MIME-Version: 1.0 Message-ID: <168095071883.404.14287970482078156616.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761585089999112119?= X-GMAIL-MSGID: =?utf-8?q?1762605238830490065?= The following commit has been merged into the irq/irqchip-next branch of irqchip: Commit-ID: 0c60a31ce62ca3e93550868fd699dfc4dfc4e795 Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/0c60a31ce62ca3e93550868fd699dfc4dfc4e795 Author: Anup Patel AuthorDate: Tue, 28 Mar 2023 09:22:18 +05:30 Committer: Marc Zyngier CommitterDate: Sat, 08 Apr 2023 11:26:24 +01:00 irqchip/riscv-intc: Allow drivers to directly discover INTC hwnode Various RISC-V drivers (such as SBI IPI, SBI Timer, SBI PMU, and KVM RISC-V) don't have associated DT node but these drivers need standard per-CPU (local) interrupts defined by the RISC-V privileged specification. We add riscv_get_intc_hwnode() in arch/riscv which allows RISC-V drivers not having DT node to discover INTC hwnode which in-turn helps these drivers to map per-CPU (local) interrupts provided by the INTC driver. Signed-off-by: Anup Patel Reviewed-by: Atish Patra Acked-by: Palmer Dabbelt Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20230328035223.1480939-3-apatel@ventanamicro.com --- arch/riscv/include/asm/irq.h | 4 ++++ arch/riscv/kernel/irq.c | 18 ++++++++++++++++++ drivers/irqchip/irq-riscv-intc.c | 7 +++++++ 3 files changed, 29 insertions(+) diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h index e4c4355..43b9ebf 100644 --- a/arch/riscv/include/asm/irq.h +++ b/arch/riscv/include/asm/irq.h @@ -12,6 +12,10 @@ #include +void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void)); + +struct fwnode_handle *riscv_get_intc_hwnode(void); + extern void __init init_IRQ(void); #endif /* _ASM_RISCV_IRQ_H */ diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c index 7207fa0..96d3171 100644 --- a/arch/riscv/kernel/irq.c +++ b/arch/riscv/kernel/irq.c @@ -7,9 +7,27 @@ #include #include +#include +#include #include #include +static struct fwnode_handle *(*__get_intc_node)(void); + +void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void)) +{ + __get_intc_node = fn; +} + +struct fwnode_handle *riscv_get_intc_hwnode(void) +{ + if (__get_intc_node) + return __get_intc_node(); + + return NULL; +} +EXPORT_SYMBOL_GPL(riscv_get_intc_hwnode); + int arch_show_interrupts(struct seq_file *p, int prec) { show_ipi_stats(p, prec); diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index 499e5f8..9066467 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -92,6 +92,11 @@ static const struct irq_domain_ops riscv_intc_domain_ops = { .xlate = irq_domain_xlate_onecell, }; +static struct fwnode_handle *riscv_intc_hwnode(void) +{ + return intc_domain->fwnode; +} + static int __init riscv_intc_init(struct device_node *node, struct device_node *parent) { @@ -126,6 +131,8 @@ static int __init riscv_intc_init(struct device_node *node, return rc; } + riscv_set_intc_hwnode_fn(riscv_intc_hwnode); + cpuhp_setup_state(CPUHP_AP_IRQ_RISCV_STARTING, "irqchip/riscv/intc:starting", riscv_intc_cpu_starting,