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Reviewed-by: Rob Herring Signed-off-by: Devi Priya --- Changes in V4: - No change .../devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml b/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml index 8c45f53212b1..a8ca8e0b27f8 100644 --- a/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml @@ -22,7 +22,7 @@ description: Each sub-node is identified using the node's name, with valid values listed for each of the pmics below. - For mp5496, s2 + For mp5496, s1, s2 For pm2250, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22 From patchwork Fri Apr 7 15:57:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Devi Priya X-Patchwork-Id: 80900 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp384870vqo; Fri, 7 Apr 2023 09:07:55 -0700 (PDT) X-Google-Smtp-Source: AKy350Y8pp0s4yC0rVOn4kf0hhA9S6ltxOLEYUpxIxZnjTLv+BcYNJMI23r8oeSb0uq0pWTi2UDm X-Received: by 2002:a17:903:1209:b0:1a2:63af:e980 with SMTP id l9-20020a170903120900b001a263afe980mr3992759plh.13.1680883674955; Fri, 07 Apr 2023 09:07:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680883674; cv=none; d=google.com; s=arc-20160816; b=CRMZOmNIUlfYZ+iY+pAU4NRN9+wilhtcc92vUo+iNTtOquemHuLgwHCWA3V2ZTR3gj ytGHFw988Y7JBV+nSwisQZaSLuMEa6bcaIxGtIZPFnY3lFseI7bk+GYmDIdWTe+WdQvo EFf3wOEmsfCu7UhltJukJsZDTQrWXefafbfGLp1ZjFAN76NzrkWLtA7ZgleJKAScYA4t VfhYp8Abao9vnH3lPHQJ7+5FCxKRuYvP6YYnGKb4YYFy2q6gNasGRgIFEjo9aZidt/ki QqczFgG5piYs6oDhljcS9Hni55kJ6YAJglvvvcqPBPdmptUrMfvZnrHvw1EGN5xk2DuG JTlQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=QTbFrIMzCg8UtDOevSdkHy1kXuqTFzn8jG+YsklXcAQ=; b=rWQ0Hr1QZUH5wfxGrp5b5EEZS2pl4TsH3jtptpZ3VqPlpeJDt9+YqjHF0fw1fD+6hu xYgAX0W7jy+059DISMbVdfQqGkFi9u7jdilAtBhZa6yaPTz1nDnktmi/lqe3gs8DuzeQ NpC0E+e0TsZjvUNu7RAgmUc/e0GzwmYv9el7lRVt8a5IVxBwC1CJfO23SJCvnjLsUknz g4rDZjqYmv9ucLt8Z6zIXhWWRI+g0H0Wb8IugN8ef9WyFKBhzUY/cvUZOS7+jNcpRtwl dqznJESYQ9F72CZ2M606fuOz4EDC4To9Ya1fIY9vSm9oL3dNaLpRDlR1b8f5Z5oHAy6H unPA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=FoVWdTtV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Co-developed-by: Praveenkumar I Signed-off-by: Praveenkumar I Signed-off-by: Devi Priya Reviewed-by: Konrad Dybcio --- Changes in V4: - Dropped struct mp5496_smpa1 which was the same as mp5496_smpa2 and renamed mp5496_smpa2 to mp5496_smps as suggested by Konrad drivers/regulator/qcom_smd-regulator.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/regulator/qcom_smd-regulator.c b/drivers/regulator/qcom_smd-regulator.c index 6f722b2d682e..18189f35db68 100644 --- a/drivers/regulator/qcom_smd-regulator.c +++ b/drivers/regulator/qcom_smd-regulator.c @@ -749,7 +749,7 @@ static const struct regulator_desc pms405_pldo600 = { .ops = &rpm_smps_ldo_ops, }; -static const struct regulator_desc mp5496_smpa2 = { +static const struct regulator_desc mp5496_smps = { .linear_ranges = (struct linear_range[]) { REGULATOR_LINEAR_RANGE(600000, 0, 127, 12500), }, @@ -794,7 +794,8 @@ struct rpm_regulator_data { }; static const struct rpm_regulator_data rpm_mp5496_regulators[] = { - { "s2", QCOM_SMD_RPM_SMPA, 2, &mp5496_smpa2, "s2" }, + { "s1", QCOM_SMD_RPM_SMPA, 1, &mp5496_smps, "s1" }, + { "s2", QCOM_SMD_RPM_SMPA, 2, &mp5496_smps, "s2" }, { "l2", QCOM_SMD_RPM_LDOA, 2, &mp5496_ldoa2, "l2" }, {} }; From patchwork Fri Apr 7 15:57:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Devi Priya X-Patchwork-Id: 80899 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp384278vqo; Fri, 7 Apr 2023 09:07:16 -0700 (PDT) X-Google-Smtp-Source: AKy350YUSV0+NQ6+jZQhnYArH/cEl0Df6fsnoxagRwfoMVslwo/Dj2ked/BdHOAjfwjexaXbjKP/ X-Received: by 2002:a17:906:585:b0:925:6bcb:4796 with SMTP id 5-20020a170906058500b009256bcb4796mr8756052ejn.38.1680883635963; Fri, 07 Apr 2023 09:07:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680883635; cv=none; d=google.com; s=arc-20160816; b=GPpQrlHMqw4BU1PWidJ5K+6nfCIVxuD+c3wlI6I/KSavJJWekRtDQKOVVEVSEHWZZv BFzbrpp2B/QLbpodpymfPY1SkRwG9Zg4sYuchR0eEsCZBjAn3KcOy7HbOUNggvjKzJkH 8OPVWyAVYtuhO6OgTr8fWhlXH/SADKauyhQwpxT4FwFrissrUS6kJihtPqiszhpF8Zsl Wj606wszngHqEDXQhI2W7zL1pFAEr+8tQtD3CvaAFvqMzVbbU5qJ6OFG36V0RJUIG6k6 8XeJY/8U/STRcyDDbY0DgDRPhTwRYO9hZ99Xv5e6zZHxUuK6a3JRnyQ5KboJDox7Bvbu i2Cg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=J/PAJLZyHK4/8iCjH7cAWkmm0zmFPNYmpA8/KQydMpY=; b=Cmae60Bm6grkC73wKLJ9TsblLuuyE0IZ/j6yKjWMCWYuZOWsQ9iteuA9Ngzel4NknR NyznBcaOP+qBKZlsvh8UjgpSW7wFxVoSIAc9sXRkKH3VVrMz5JFT0lqkWHvlcXt0wR8u 2Q30PISYbkUlBFwrnnJRJwE2L5TaV+jbrtT9BA5Fn21yTJAzy0x2bhBVg/ZXHTsDiLO6 ghDaLU+aQjNjnLwhXYMOOBWroR2/r53SRWkGNNbdZyWWrRFaMboOHU7Qz+P8AnN5ueWm znpxoIPZbTWrw6wU7ESLq1IPjHynwUm/bzbR59jZHFlwQjirZsud60UDzBgDIopTk8/4 l0LA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b="Nz/7V28x"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Reviewed-by: Konrad Dybcio Co-developed-by: Praveenkumar I Signed-off-by: Praveenkumar I Signed-off-by: Devi Priya --- Changes in V4: - Picked up the R-b tag arch/arm64/boot/dts/qcom/ipq9574.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 7c820463a79d..1f9b7529e7ed 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -110,12 +110,29 @@ }; }; + rpm-glink { + compatible = "qcom,glink-rpm"; + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-ipq9574"; + qcom,glink-channels = "rpm_requests"; + }; + }; + soc: soc@0 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + rpm_msg_ram: sram@60000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x00060000 0x6000>; + }; + pcie0_phy: phy@84000 { compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy"; reg = <0x00084000 0x1000>; From patchwork Fri Apr 7 15:57:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Devi Priya X-Patchwork-Id: 80896 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp383620vqo; Fri, 7 Apr 2023 09:06:25 -0700 (PDT) X-Google-Smtp-Source: AKy350ZNGuqatOxHqNAYVn6tdWFdS6mhdk5H/cuTrv7P+0Htupgt8KjJvLA//rPFrppr51feivKJ X-Received: by 2002:a17:902:f14d:b0:1a1:add5:c355 with SMTP id d13-20020a170902f14d00b001a1add5c355mr2577373plb.5.1680883585433; Fri, 07 Apr 2023 09:06:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680883585; cv=none; d=google.com; s=arc-20160816; b=KexVRYCv3ikWTD5L9WSLyVnznrre2jo3971BhCitpF+DVxJT7tl13BQTkSvphBHROX lh6Kwh5XHyQiqjv483sA9/axAzKCR1puYrjSpMIA6dIEAL5TSbg5jkmKxkRxu4T9udR7 a4YdZ6anQTOZRuhPDYhDJTsHVhiQct8gvPQBp3R8OXek9Qat/z0/blZZ2Wfwh5hjMb25 YWLnVIFgwnaWufnAUmWwRrt0EkpkVPCJzatgkFKRuu5Tx3cspolepBERo4k5KCe1Q1Rz 79bSH5yt3GweX7r2B+bTIzaExqGWimFaZbatf/8jIj/uvg1WPmCpuDMpRi7ZgP6mheCm IC1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=b+LW5hRuMvKOd4NiVwPngvtUjFU3uMFAD4m5HlAlevo=; b=sHDifHuy190NmxoGdeoILw8zCXqH6vuK8DhW8khQ7RoGoVB+TUWNMgH7H6hbnQKjVU fiRTrdnqL8cxJqugNNqWBmCMDSb8asX69rtlWD3m7WSXG5aafXZMS3aSe00v5dnDTfkD Tnlw3MXOxFeNOdkSNm1iQXVRIVyN9MFpCTy1FAs4F6GktBIHUX7ch8b91ldZ+MR1Mqmk rr0k/QGa9sl40t69dq2rLCoIRccXRRMyJqXqKgvVsV0r8IWEft732W8JlzMfUg1PDu1B 2+pyFpU5qdLSGUfOu/bpHnPGctgcVFoWR2oIRD6JFeicwyS6rCJWlzlD1EdakrtMPlli OAXA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b="VZnfZzs/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Co-developed-by: Praveenkumar I Signed-off-by: Praveenkumar I Signed-off-by: Devi Priya Reviewed-by: Konrad Dybcio --- Changes in V4: - Updated the comment as suggested by konrad s/Updating/Update s/725000uV/725mV arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts index 3ae38cf327ea..bdc1434fbe67 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts @@ -44,6 +44,25 @@ }; }; +&rpm_requests { + regulators { + compatible = "qcom,rpm-mp5496-regulators"; + + ipq9574_s1: s1 { + /* + * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders. + * During regulator registration, kernel not knowing the initial voltage, + * considers it as zero and brings up the regulators with minimum supported voltage. + * Update the regulator-min-microvolt with SVS voltage of 725mV so that + * the regulators are brought up with 725mV which is sufficient for all the + * corner parts to operate at 800MHz + */ + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1075000>; + }; + }; +}; + &pcie1_phy { status = "okay"; }; From patchwork Fri Apr 7 15:57:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Devi Priya X-Patchwork-Id: 80895 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp383122vqo; Fri, 7 Apr 2023 09:05:51 -0700 (PDT) X-Google-Smtp-Source: AKy350ZjnrsvcrUsXtHdZypQ3Fxnp3ckgHSZGSu/zy9IGtioZyujr25Ch57XBmylzGw1/7AjD8fF X-Received: by 2002:a05:6a20:be0a:b0:cc:d514:62cf with SMTP id ge10-20020a056a20be0a00b000ccd51462cfmr2581659pzb.43.1680883551171; Fri, 07 Apr 2023 09:05:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680883551; cv=none; d=google.com; s=arc-20160816; b=0NavfZeXYIiBf/175cEPt7saVZb5N0RbeZSx3anF+0SQuslnmVs6mPIdDCImFB15Bp 9w7WEjZxZeuj2u4RY0vIWpxaXQ/3oGGmrDJX9feqOztAhOMHfQtPlKzzeBg7C/5whPvy MSQjUUiFsfUgFtMFcOy4OwiIcEyVwG7QKZvI0y36DoCzB/6T0FEY0kXNIYzupLi2sd+D GH56k6wpEU8vwsU8FOepqIp3G/dnknhqYlTEC9zL2B1e5iiHd3U7KHr6yWPn8u0bpnZ7 SyBHpWEnu+LX4uLuUI4nWSuRgSGKRhvLukvUl+QkQ5ZNcxJftms2w2+usE/lii9ORG3d RfNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=ZLaW8DB/9vUmOO4NtVwP0HZhPklWTpAyTk7jxdCY6SM=; b=SZlgOydJ/KGygx5GsMNNJqobPUyfc7RxGeKcDFAwd5MPkHpYQarNj1WFYrK6ugnaHQ Bf2sgAt1+JAsUin0FnhsyNkLrKBDX86AwDvxltVBLQ6yyrH6f0SFZxZPy4zFX/+BREZ8 KXo2gi95UIPd89Ydo47zSkW1UysNBdW3Ulb162UyN00Ccsauhq5uiQjK9oLbrRKanhz6 aVnUNGKbKXSnFYbdhdgTxLI8yGpba2J3v0mzhTR+6gZRrW6KHmpa83xrPntvy3kK764J rbbZhaR7zTgaC5xMomYI+EDwFDLIm1hXePrlQK5qKUEG7hGYDvcaM3bENHSwTpnDs3Sf 2B1g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=ITWsPiSM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Reviewed-by: Konrad Dybcio Co-developed-by: Praveenkumar I Signed-off-by: Praveenkumar I Signed-off-by: Devi Priya --- Changes in V4: - Picked up the R-b tag arch/arm64/boot/dts/qcom/ipq9574.dtsi | 58 +++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 1f9b7529e7ed..cfef87b5fd22 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -6,6 +6,7 @@ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ +#include #include #include #include @@ -37,6 +38,10 @@ reg = <0x0>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq9574_s1>; }; CPU1: cpu@1 { @@ -45,6 +50,10 @@ reg = <0x1>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq9574_s1>; }; CPU2: cpu@2 { @@ -53,6 +62,10 @@ reg = <0x2>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq9574_s1>; }; CPU3: cpu@3 { @@ -61,6 +74,10 @@ reg = <0x3>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq9574_s1>; }; L2_0: l2-cache { @@ -75,6 +92,47 @@ reg = <0x0 0x40000000 0x0 0x0>; }; + cpu_opp_table: opp-table-cpu { + compatible = "operating-points-v2"; + opp-shared; + + opp-936000000 { + opp-hz = /bits/ 64 <936000000>; + opp-microvolt = <725000>; + clock-latency-ns = <200000>; + }; + + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <787500>; + clock-latency-ns = <200000>; + }; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <862500>; + clock-latency-ns = <200000>; + }; + + opp-1488000000 { + opp-hz = /bits/ 64 <1488000000>; + opp-microvolt = <925000>; + clock-latency-ns = <200000>; + }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <987500>; + clock-latency-ns = <200000>; + }; + + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <1062500>; + clock-latency-ns = <200000>; + }; + }; + firmware { scm { compatible = "qcom,scm-ipq9574", "qcom,scm";