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[8.43.85.97]) by mx.google.com with ESMTPS id du14-20020a17090772ce00b009394bed261dsi2354951ejc.107.2023.04.07.00.00.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 00:00:49 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=sGAWClNI; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 141AE3858C74 for ; Fri, 7 Apr 2023 07:00:48 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 141AE3858C74 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1680850848; bh=aLhHrePOwaQFi63mHUJrUksAItZLoGxhCqwYBLcb8Cw=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=sGAWClNITIZJfHeK2XLiqAglOKTqOpg8M6HD8I6iAaB5HozcfQeoiSGHcBjtM+nKd FP/Aek9+S+sXdlQ9ULs/wuWO3YQR9hpzD9Qmye8JvYpBrYksEGOlKp0AqyU6Jg7HEL nH7tanYMTVY87Dm9xN5wVMqwgBaLdvJLSV3QHPcM= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by sourceware.org (Postfix) with ESMTPS id 11A983858D28 for ; Fri, 7 Apr 2023 07:00:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 11A983858D28 X-IronPort-AV: E=McAfee;i="6600,9927,10672"; a="340429154" X-IronPort-AV: E=Sophos;i="5.98,326,1673942400"; d="scan'208";a="340429154" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2023 00:00:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10672"; a="776760551" X-IronPort-AV: E=Sophos;i="5.98,326,1673942400"; d="scan'208";a="776760551" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by FMSMGA003.fm.intel.com with ESMTP; 06 Apr 2023 23:59:59 -0700 Received: from yanzhang-dev.sh.intel.com (yanzhang-dev.sh.intel.com [10.239.82.176]) by shvmail02.sh.intel.com (Postfix) with ESMTP id A2078100725E; Fri, 7 Apr 2023 14:59:58 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, yanzhang.wang@intel.com Subject: [PATCH v2] RISC-V: Fix regression of -fzero-call-used-regs=all Date: Fri, 7 Apr 2023 14:59:40 +0800 Message-Id: <20230407065940.2331101-1-yanzhang.wang@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230406133441.1944365-1-yanzhang.wang@intel.com> References: <20230406133441.1944365-1-yanzhang.wang@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "yanzhang.wang--- via Gcc-patches" From: "Li, Pan2 via Gcc-patches" Reply-To: yanzhang.wang@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762434352748316862?= X-GMAIL-MSGID: =?utf-8?q?1762499859908115403?= From: Yanzhang Wang This patch registers a riscv specific function to TARGET_ZERO_CALL_USED_REGS instead of default in targhooks.cc. It will clean gpr and vector relevant registers. PR 109104 gcc/ChangeLog: * config/riscv/riscv-protos.h (GCC_RISCV_PROTOS_H): (emit_hard_vlmax_vsetvl): (vector_zero_call_used_regs): * config/riscv/riscv-v.cc (emit_hard_vlmax_vsetvl): (emit_vlmax_vsetvl): (vector_zero_call_used_regs): * config/riscv/riscv.cc (riscv_zero_call_used_regs): (TARGET_ZERO_CALL_USED_REGS): gcc/testsuite/ChangeLog: * gcc.target/riscv/zero-scratch-regs-1.c: New test. * gcc.target/riscv/zero-scratch-regs-2.c: New test. * gcc.target/riscv/zero-scratch-regs-3.c: New test. Signed-off-by: Yanzhang Wang Co-authored-by: Pan Li Co-authored-by: Ju-Zhe Zhong Co-authored-by: Kito Cheng --- gcc/config/riscv/riscv-protos.h | 5 ++ gcc/config/riscv/riscv-v.cc | 67 ++++++++++++++++++- gcc/config/riscv/riscv.cc | 21 ++++++ .../gcc.target/riscv/zero-scratch-regs-1.c | 9 +++ .../gcc.target/riscv/zero-scratch-regs-2.c | 24 +++++++ .../gcc.target/riscv/zero-scratch-regs-3.c | 57 ++++++++++++++++ 6 files changed, 180 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/zero-scratch-regs-3.c diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 4611447ddde..7ab0ec4b8be 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -22,6 +22,8 @@ along with GCC; see the file COPYING3. If not see #ifndef GCC_RISCV_PROTOS_H #define GCC_RISCV_PROTOS_H +#include "hard-reg-set.h" + /* Symbol types we understand. The order of this list must match that of the unspec enum in riscv.md, subsequent to UNSPEC_ADDRESS_FIRST. */ enum riscv_symbol_type { @@ -159,6 +161,7 @@ bool check_builtin_call (location_t, vec, unsigned int, bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT); bool legitimize_move (rtx, rtx, machine_mode); void emit_vlmax_vsetvl (machine_mode, rtx); +void emit_hard_vlmax_vsetvl (machine_mode, rtx); void emit_vlmax_op (unsigned, rtx, rtx, machine_mode); void emit_vlmax_op (unsigned, rtx, rtx, rtx, machine_mode); void emit_nonvlmax_op (unsigned, rtx, rtx, rtx, machine_mode); @@ -206,6 +209,8 @@ enum vlen_enum bool slide1_sew64_helper (int, machine_mode, machine_mode, machine_mode, rtx *); rtx gen_avl_for_scalar_move (rtx); + +HARD_REG_SET vector_zero_call_used_regs (HARD_REG_SET); } /* We classify builtin types into two classes: diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 2e91d019f6c..aad046240ee 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -43,6 +43,8 @@ #include "optabs.h" #include "tm-constrs.h" #include "rtx-vector-builder.h" +#include "diagnostic-core.h" +#include "targhooks.h" using namespace riscv_vector; @@ -118,6 +120,17 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT minval, && IN_RANGE (INTVAL (elt), minval, maxval)); } +/* Emit a vlmax vsetvl instruction with side effect, this should be only used + when optimization is tune off or emit after vsetvl insertion pass. */ +void +emit_hard_vlmax_vsetvl (machine_mode vmode, rtx vl) +{ + unsigned int sew = get_sew (vmode); + emit_insn (gen_vsetvl (Pmode, vl, RVV_VLMAX, gen_int_mode (sew, Pmode), + gen_int_mode (get_vlmul (vmode), Pmode), const0_rtx, + const0_rtx)); +} + void emit_vlmax_vsetvl (machine_mode vmode, rtx vl) { @@ -126,9 +139,7 @@ emit_vlmax_vsetvl (machine_mode vmode, rtx vl) unsigned int ratio = calculate_ratio (sew, vlmul); if (!optimize) - emit_insn (gen_vsetvl (Pmode, vl, RVV_VLMAX, gen_int_mode (sew, Pmode), - gen_int_mode (get_vlmul (vmode), Pmode), const0_rtx, - const0_rtx)); + emit_hard_vlmax_vsetvl (vmode, vl); else emit_insn (gen_vlmax_avl (Pmode, vl, gen_int_mode (ratio, Pmode))); } @@ -724,4 +735,54 @@ gen_avl_for_scalar_move (rtx avl) } } +HARD_REG_SET +vector_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) +{ + HARD_REG_SET zeroed_hardregs; + CLEAR_HARD_REG_SET (zeroed_hardregs); + + /* Find a register to hold vl. */ + unsigned vl_regno = INVALID_REGNUM; + /* Skip the first GPR, otherwise the existing vl is kept due to the same + between vl and avl. */ + for (unsigned regno = GP_REG_FIRST + 1; regno <= GP_REG_LAST; regno++) + { + if (TEST_HARD_REG_BIT (need_zeroed_hardregs, regno)) + { + vl_regno = regno; + break; + } + } + + if (vl_regno > GP_REG_LAST) + sorry ("can't allocate vl register for %qs on this target", + "-fzero-call-used-regs"); + + bool emitted_vlmax_vsetvl = false; + rtx vl = gen_rtx_REG (Pmode, vl_regno); /* vl is VLMAX. */ + for (unsigned regno = V_REG_FIRST; regno <= V_REG_LAST; ++regno) + { + if (TEST_HARD_REG_BIT (need_zeroed_hardregs, regno)) + { + rtx target = regno_reg_rtx[regno]; + machine_mode mode = GET_MODE (target); + poly_uint16 nunits = GET_MODE_NUNITS (mode); + machine_mode mask_mode = get_vector_mode (BImode, nunits).require (); + + if (!emitted_vlmax_vsetvl) + { + emit_hard_vlmax_vsetvl (mode, vl); + emitted_vlmax_vsetvl = true; + } + + emit_vlmax_op (code_for_pred_mov (mode), target, CONST0_RTX (mode), + vl, mask_mode); + + SET_HARD_REG_BIT (zeroed_hardregs, regno); + } + } + + return zeroed_hardregs; +} + } // namespace riscv_vector diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 5f542932d13..c3ae9571766 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7066,6 +7066,24 @@ riscv_shamt_matches_mask_p (int shamt, HOST_WIDE_INT mask) return shamt == ctz_hwi (mask); } +/* Generate a sequence of instructions that zero registers specified by + NEED_ZEROED_HARDREGS. Return the ZEROED_HARDREGS that are actually + zeroed. */ +HARD_REG_SET +riscv_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) +{ + HARD_REG_SET zeroed_hardregs; + CLEAR_HARD_REG_SET (zeroed_hardregs); + + if (TARGET_VECTOR) + zeroed_hardregs + |= riscv_vector::vector_zero_call_used_regs (need_zeroed_hardregs); + + return zeroed_hardregs | default_zero_call_used_regs (need_zeroed_hardregs + & ~zeroed_hardregs); +} + + /* Initialize the GCC target structure. */ #undef TARGET_ASM_ALIGNED_HI_OP #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" @@ -7317,6 +7335,9 @@ riscv_shamt_matches_mask_p (int shamt, HOST_WIDE_INT mask) #undef TARGET_DWARF_POLY_INDETERMINATE_VALUE #define TARGET_DWARF_POLY_INDETERMINATE_VALUE riscv_dwarf_poly_indeterminate_value +#undef TARGET_ZERO_CALL_USED_REGS +#define TARGET_ZERO_CALL_USED_REGS riscv_zero_call_used_regs + struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-riscv.h" diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c new file mode 100644 index 00000000000..41d94ab921a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64 -O2 -fzero-call-used-regs=used -fno-stack-protector -fno-PIC" } */ + +void +foo (void) +{ +} + +/* { dg-final { scan-assembler-not "li\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c new file mode 100644 index 00000000000..9161dd3d4ec --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64 -O2 -fzero-call-used-regs=all-gpr" } */ + +void +foo (void) +{ +} + +/* { dg-final { scan-assembler-not "vsetvli" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*t0,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*t1,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*t2,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*a0,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*a1,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*a2,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*a3,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*a4,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*a5,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*a6,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*a7,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*t3,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*t4,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*t5,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*t6,0" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-3.c b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-3.c new file mode 100644 index 00000000000..824fe9e548f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-3.c @@ -0,0 +1,57 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O2 -fzero-call-used-regs=all" } */ + +void +foo (void) +{ +} + +/* { dg-final { scan-assembler "vsetvli\[ \t\]*t0,zero,e32,m1,tu,mu" } } */ +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v0,0" } } */ +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v1,0" } } */ +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v2,0" } } */ +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v3,0" } } */ +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v4,0" } } */ +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v5,0" } } */ +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v6,0" } } */ +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v7,0" } } */ +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v8,0" } } */ +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v9,0" } } */ +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v10,0" } } */ +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v11,0" } } */ +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v12,0" } } */ +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v13,0" } } */ +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v14,0" } } */ +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v15,0" } } */ +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v16,0" } } */ +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v17,0" } } */ +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v18,0" } } */ +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v19,0" } } */ +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v20,0" } } */ +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v21,0" } } */ +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v22,0" } } */ +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v23,0" } } */ +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v24,0" } } */ +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v25,0" } } */ +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v26,0" } } */ +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v27,0" } } */ +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v28,0" } } */ +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v29,0" } } */ +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v30,0" } } */ +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v31,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*t0,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*t1,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*t2,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*a0,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*a1,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*a2,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*a3,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*a4,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*a5,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*a6,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*a7,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*t3,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*t4,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*t5,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*t6,0" } } */ +/* { dg-final { scan-assembler "fmv.d.x\[ \t\]*ft0,zero" } } */