From patchwork Fri Oct 21 06:46:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 6530 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4242:0:0:0:0:0 with SMTP id s2csp528566wrr; Thu, 20 Oct 2022 23:52:30 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6I8aMLj0SsryqlX1UhYTR7MP72/pAFcsC2QAujZgNVXKGjw8KapBIcwR+4IRBVl+4L4c71 X-Received: by 2002:a17:902:ced1:b0:184:ba6e:8c3b with SMTP id d17-20020a170902ced100b00184ba6e8c3bmr17992192plg.160.1666335149885; Thu, 20 Oct 2022 23:52:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666335149; cv=none; d=google.com; s=arc-20160816; b=Rsv95HO/gEDoZf7/QcXfRjykfrE5TENqHFKaXoaRUD847hKgwDg9/D0e10b/tCf13f zr9u5xRAOHrC9BOBcNplh3lL2Wt70az/E/UU68EoYG+JR/mT81bZ6S3PElZdlnsLTk1e TDAzi+Eg6aKlYITAZf3r8J+wiTOGzd3UY+pxB/gXAtSlf86QzWzEVzf73kE0iS0JffyH Gm28n5QN09teAD6A0dK24+VWEoK6mWTTFyX3VLHdXgfVaMMSy3iwpnAT5NaERbmVUQxf /ZaLJsj/WzCDsTkwyIg54PDQWieMExScSk2n4r5P+kIniso+drc0dNef1ycr53JMXedI d4tQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=XHwUfgwASZ3I5DHQkt0GUv1v6FcOnh/pVibtVcrU3Mo=; b=CrdaHgwVAbeGKS0PtyDBaf+6yd0hCP0YsBmk+lrYfWRYhGEBJU+4tpt/zipwz2cIuH UvK8gt7haMYjTdXumJb0/IEHuVzQcSIx8LTZTRo3zIfixRuv5276PRGj8/fvE/jRsyRb kEEM9S4bxfe65KfkECFt5gA9gfdwDng/Bo8aQezszWoSPROQbq76vFRLS+VFfBbh95UT hTXZMRt2NYRiwyqDmdeGsa2wpZt9u806D292KbVUZuH94VwEo1OcL0/tUG2JoZjXPq/i NwxgchJblItI5pmRHfR6eVOPkWOujkloDk3a8XNGVbLwvP9aUT8PWrQzlN6Jp/+d9WT4 6jSw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b="R9ROaxc/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id u1-20020a17090341c100b0017486813f81si27556122ple.528.2022.10.20.23.52.17; Thu, 20 Oct 2022 23:52:29 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b="R9ROaxc/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230186AbiJUGsC (ORCPT + 99 others); Fri, 21 Oct 2022 02:48:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59342 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230077AbiJUGrw (ORCPT ); Fri, 21 Oct 2022 02:47:52 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 384202413F4; Thu, 20 Oct 2022 23:47:49 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 8C40F61B39; Fri, 21 Oct 2022 06:47:48 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DE015C433D6; Fri, 21 Oct 2022 06:47:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666334867; bh=L2kl6xZZIoArZEtrdl2/F173ECwVvHETksPU21qwgRE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=R9ROaxc/KwLiIIiAAjv30f0ccyVD3IU4x6k9l5AzwnZ6eLV/ylJafIDqZp1SrBZrG 38yDMWOZNchG8nhG1Eu+moNdFWqX+iCN2FU/p8tHdB9VFGC65ICdsFdAEFizjDEh7n Zn8fQG8UFM/QtS3PngMFsGaPteqcc0sFOPBwHi4tDz+86kSbRJUwchP8zQFpxHGL1O jWpqhW5n+eve6zCxNYHYdKLYX28yXtB70ym3bFnh+ZKY7PFuK3hh/mC+2TIF/0hFLQ 6O47P9Te13+XISMhuGziVy6VUimDWAag2trAF+Yijtkd1sJx251xmQitpSANjTEP3R un1YWzKHdzlSg== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1olloc-0001fU-D5; Fri, 21 Oct 2022 08:47:34 +0200 From: Johan Hovold To: Stanimir Varbanov , Lorenzo Pieralisi Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , =?utf-8?q?Krzyszto?= =?utf-8?q?f_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Krishna chaitanya chundru , quic_vbadigan@quicinc.com, Brian Masney , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH v2 1/2] dt-bindings: PCI: qcom: Add SC8280XP/SA8540P interconnects Date: Fri, 21 Oct 2022 08:46:15 +0200 Message-Id: <20221021064616.6380-2-johan+linaro@kernel.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221021064616.6380-1-johan+linaro@kernel.org> References: <20221021064616.6380-1-johan+linaro@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747279046249426923?= X-GMAIL-MSGID: =?utf-8?q?1747279046249426923?= Add the missing SC8280XP/SA8540P "pcie-mem" and "cpu-pcie" interconnect paths to the bindings. Fixes: 76d777ae045e ("dt-bindings: PCI: qcom: Add SC8280XP to binding") Fixes: 76c4207f4085 ("dt-bindings: PCI: qcom: Add SA8540P to binding") Signed-off-by: Johan Hovold Reviewed-by: Rob Herring Acked-by: Manivannan Sadhasivam --- .../devicetree/bindings/pci/qcom,pcie.yaml | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 54f07852d279..2f851c804bb0 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -62,6 +62,14 @@ properties: minItems: 3 maxItems: 13 + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: pcie-mem + - const: cpu-pcie + resets: minItems: 1 maxItems: 12 @@ -631,6 +639,18 @@ allOf: items: - const: pci # PCIe core reset + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sa8540p + - qcom,pcie-sc8280xp + then: + required: + - interconnects + - interconnect-names + - if: not: properties: From patchwork Fri Oct 21 06:46:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 6529 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4242:0:0:0:0:0 with SMTP id s2csp527943wrr; Thu, 20 Oct 2022 23:50:51 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7dhwmUapB7emYFx9KmlHIIAbZfUNeeOKnMI8blJQ3RjZt8LJ1Ygosw+ERVkz10Msxb67Cf X-Received: by 2002:a17:90b:1c0a:b0:20a:7393:d8e9 with SMTP id oc10-20020a17090b1c0a00b0020a7393d8e9mr54522173pjb.188.1666335051444; Thu, 20 Oct 2022 23:50:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666335051; cv=none; d=google.com; s=arc-20160816; b=wAzEesakI8UdAWao9tBZYJFFjBJWVvoNHHU26OXiW1oLPXM3zO4NuNnYE7VOfyDgD7 QnwI4AxnlLGMyAcYZsIo6RanTzQZ2/5xKUA9JjtHticaHKhlTrqo4tJRL6PUw3NvRSAD BrjWWu40eOLvsi37pqhdywx4cZ+SWUYFpzQ/7r7/G2Tilr21iXJ4i10GEIGQ+1o0N70k Wy3YIg4Kjc6qNDCUHTLQRWi/KWxx6qh29fyWu9qr36h38audaKM7zlGQBOACTgpEBLdK siCjwUvhEfjLGDsbSO93caZXXTMe43U9bojp8z3b6DJUyudzRCutpLfHfUPrNMEGp5OH +NIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=UMAHGLyJ44N5WFGs1omS8guTszXDiWG1CClF7jYsBMk=; b=p0MCK/kyW9zWk9Ep01jHKSZnoAGh4c8XE3PMrPpEK5rPYELk8Lf3gDVUcIOuwxD3bm Onfwggnel3VpCHyj0gzNdKS9qZi8Ir9X8aTrqkLGk7Q9ydLc2py1AA1UXHKKws8ca6Yk bEF1yqMJSDcM9Hh5CMAn+JVifHu3A0La/ll4ChKWoiN522V6r/fZXyLoSQ2ovfNvGHrh AQKDbKB4vJFHBOKpJ6lnaOr74IZ6hYaKG4sD1daA89gvmF3fvZvxN3S+mLYD9ZYtGmVR IEt9KXn4h9HhLoytn0RCBE8oLi3Dk2SpMiKzOihw4QbjByxTRPVGXpJv8kQqVpIiLJr0 emgA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=rRPlIRnO; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id u8-20020a17090341c800b0016d5d09a43dsi29709917ple.331.2022.10.20.23.50.38; Thu, 20 Oct 2022 23:50:51 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=rRPlIRnO; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230180AbiJUGsA (ORCPT + 99 others); Fri, 21 Oct 2022 02:48:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59340 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230081AbiJUGrw (ORCPT ); Fri, 21 Oct 2022 02:47:52 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E2283242C9A; Thu, 20 Oct 2022 23:47:48 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 75E2D601D2; Fri, 21 Oct 2022 06:47:48 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D3732C433B5; Fri, 21 Oct 2022 06:47:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666334867; bh=eTZxC1jB3/0V0Rfdced1bkYKZ1MT7sUu1FOTOt8PolQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rRPlIRnOPhzMeB6r2V5WpRI38L/sUcuGWNXwbuxeqVmZJUJJGEDr8OwqSSrW9fkLG EHPqh79YREql28uu+U4qACvVhcUmShrYVch1nLLjMZnrGJvlwyToAOp2ChtnrfYy0T QjXqbD4rIHjAWC8V7pVCiELsG/RQC8ayfStX1k2tUuEy3VK86c3Ej1YtRESwyXXE1m 7pZU9zLSMqGtQk7fD1xQndAa9SiMkjZm7+0l8U8bMeofhe87iMzg4GkwzQ59XK5ANB YcWlJegft5yoUFUt2CoASsvH4DBybXMwtTkOH7A1eK6vGJyL+RLoVaqmqmW7+oFHeK AHx/XtL8g4Tjw== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1olloc-0001fW-GM; Fri, 21 Oct 2022 08:47:34 +0200 From: Johan Hovold To: Stanimir Varbanov , Lorenzo Pieralisi Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , =?utf-8?q?Krzyszto?= =?utf-8?q?f_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Krishna chaitanya chundru , quic_vbadigan@quicinc.com, Brian Masney , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH v2 2/2] PCI: qcom: Add basic interconnect support Date: Fri, 21 Oct 2022 08:46:16 +0200 Message-Id: <20221021064616.6380-3-johan+linaro@kernel.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221021064616.6380-1-johan+linaro@kernel.org> References: <20221021064616.6380-1-johan+linaro@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747278943003195285?= X-GMAIL-MSGID: =?utf-8?q?1747278943003195285?= On Qualcomm platforms like SC8280XP and SA8540P, interconnect bandwidth must be requested before enabling interconnect clocks. Add basic support for managing an optional "pcie-mem" interconnect path by setting a low constraint before enabling clocks and updating it after the link is up. Note that it is not possible for a controller driver to set anything but a maximum peak bandwidth as expected average bandwidth will vary with use case and actual use (and power policy?). This very much remains an unresolved problem with the interconnect framework. Also note that no constraint is set for the SC8280XP/SA8540P "cpu-pcie" path for now as it is not clear what an appropriate constraint would be (and the system does not crash when left unspecified). Fixes: 70574511f3fc ("PCI: qcom: Add support for SC8280XP") Reviewed-by: Brian Masney Signed-off-by: Johan Hovold Acked-by: Georgi Djakov --- drivers/pci/controller/dwc/pcie-qcom.c | 76 ++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 7db94a22238d..0c13f976626f 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -224,6 +225,7 @@ struct qcom_pcie { union qcom_pcie_resources res; struct phy *phy; struct gpio_desc *reset; + struct icc_path *icc_mem; const struct qcom_pcie_cfg *cfg; }; @@ -1644,6 +1646,74 @@ static const struct dw_pcie_ops dw_pcie_ops = { .start_link = qcom_pcie_start_link, }; +static int qcom_pcie_icc_init(struct qcom_pcie *pcie) +{ + struct dw_pcie *pci = pcie->pci; + int ret; + + pcie->icc_mem = devm_of_icc_get(pci->dev, "pcie-mem"); + if (IS_ERR(pcie->icc_mem)) { + ret = PTR_ERR(pcie->icc_mem); + return ret; + } + + /* + * Some Qualcomm platforms require interconnect bandwidth constraints + * to be set before enabling interconnect clocks. + * + * Set an initial peak bandwidth corresponding to single-lane Gen 1 + * for the pcie-mem path. + */ + ret = icc_set_bw(pcie->icc_mem, 0, MBps_to_icc(250)); + if (ret) { + dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", + ret); + return ret; + } + + return 0; +} + +static void qcom_pcie_icc_update(struct qcom_pcie *pcie) +{ + struct dw_pcie *pci = pcie->pci; + u32 offset, status, bw; + int speed, width; + int ret; + + if (!pcie->icc_mem) + return; + + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); + + /* Only update constraints if link is up. */ + if (!(status & PCI_EXP_LNKSTA_DLLLA)) + return; + + speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status); + width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status); + + switch (speed) { + case 1: + bw = MBps_to_icc(250); + break; + case 2: + bw = MBps_to_icc(500); + break; + default: + case 3: + bw = MBps_to_icc(985); + break; + } + + ret = icc_set_bw(pcie->icc_mem, 0, width * bw); + if (ret) { + dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", + ret); + } +} + static int qcom_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -1704,6 +1774,10 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_pm_runtime_put; } + ret = qcom_pcie_icc_init(pcie); + if (ret) + goto err_pm_runtime_put; + ret = pcie->cfg->ops->get_resources(pcie); if (ret) goto err_pm_runtime_put; @@ -1722,6 +1796,8 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_phy_exit; } + qcom_pcie_icc_update(pcie); + return 0; err_phy_exit: