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Signed-off-by: Dipen Patel Acked-by: Thierry Reding --- MAINTAINERS | 3 +++ 1 file changed, 3 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8d5bc223f305..65b58963f0d2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9425,6 +9425,9 @@ F: drivers/input/touchscreen/htcpen.c HTE SUBSYSTEM M: Dipen Patel +L: timestamp@lists.linux.dev +T: git git://git.kernel.org/pub/scm/linux/kernel/git/pateldipen1984/linux.git +Q: https://patchwork.kernel.org/project/timestamp/list/ S: Maintained F: Documentation/devicetree/bindings/timestamp/ F: Documentation/driver-api/hte/ From patchwork Thu Apr 6 17:18:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dipen Patel X-Patchwork-Id: 80367 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1192551vqo; Thu, 6 Apr 2023 10:34:06 -0700 (PDT) X-Google-Smtp-Source: AKy350YcjDSehp0GikeOPMrnE1/IPr33q34s0vbtRSgWkMQDiGPrnNauk16AKUZH/sIF88mtUI2Y X-Received: by 2002:a05:6a20:4987:b0:da:fa65:cd89 with SMTP id fs7-20020a056a20498700b000dafa65cd89mr380817pzb.9.1680802446114; Thu, 06 Apr 2023 10:34:06 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1680802446; cv=pass; d=google.com; s=arc-20160816; b=mvnJfJS6Os1rxnWVDZd4ogS3pGu3kgGKjx4Ez+LybVanljSjX1vVlkmNBujcmgTgea 9RDrvNgZZK1S6TwSqgFkDzOg/APq+5Fv5dsbydQl8HQwd84AJKoqWGPMqRdoZnJ9n6SS HZOhb9jyqHPVI0vZnvJSKZL4oc4fMkPNnKHIaGZ4sV7Dr3PFGvgz3C/cDVhvsr2l9D2Y pT2+k4Fr5ZoAzBfqIQsCp7LjEYzLrKMGIkFUPRXYItVNum05FJyKE35A0iZuGk7DabxY dNj4/SV+PWRDLrxDYtxgfSMNvTqgAtVsGqsq0r25xo1W4qKsGBrcvMve3vdeL1fKdKps 1GIA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=jq6UmJPHke1jcU1XfRhPlhhFfZbQYlbpC9SF83EL9xc=; b=RBBWIGiT8sYwb0Yu3FbUkfVtFl4k1SsSq9CcxJd/4+TUMAlB2Z9wJ1bCTR67TkyIsd DWusRGsyQxxIiGr7x+kdHQR1G3AKkySQAk9KBTbG3A/q8thkIlCLt3mfXr+lvff7TP2i z7XFH/UlvothBZQRHjyHG9/ZbHtkhQYYQIGPc14nLhz/NTjlAAvN5HvDDqiLqpb0+mGd KHasOY3/PBWSw2asbySbwwcweHte3Iuw8DCIUz+aah1sgypfa7oRPnDDTSiT/QtbUE2k T1XfoanN4C8lbUZzaTzLQ/SDkP06Wq2mPKY8Wz4A+NiHnjn+LRhoK4zMp1gb+gvFJNPC ga4Q== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=R+bSpCLV; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Dipen Patel Reviewed-by: Krzysztof Kozlowski --- v2: - Removed nvidia,slices property - Added nvidia,gpio-controller based on review comments from Thierry, this will help simplify the hte provider driver. v3: - Explained changes in detail in commit message - Added allOf section per review comment v4: - Logically divide the v3 patch as follows - Created Tegra234 support patch - Created depracate nvidia,slices property patch - Created addition of the nvidia,gpio-controller property patch .../timestamp/nvidia,tegra194-hte.yaml | 44 +++++++++++++++++-- 1 file changed, 40 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml b/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml index c31e207d1652..158dbe58c49f 100644 --- a/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml +++ b/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/timestamp/nvidia,tegra194-hte.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Tegra194 on chip generic hardware timestamping engine (HTE) +title: Tegra on chip generic hardware timestamping engine (HTE) provider maintainers: - Dipen Patel @@ -23,6 +23,8 @@ properties: enum: - nvidia,tegra194-gte-aon - nvidia,tegra194-gte-lic + - nvidia,tegra234-gte-aon + - nvidia,tegra234-gte-lic reg: maxItems: 1 @@ -43,9 +45,8 @@ properties: description: HTE lines are arranged in 32 bit slice where each bit represents different line/signal that it can enable/configure for the timestamp. It is u32 - property and depends on the HTE instance in the chip. The value 3 is for - GPIO GTE and 11 for IRQ GTE. - enum: [3, 11] + property and the value depends on the HTE instance in the chip. + enum: [3, 11, 17] '#timestamp-cells': description: @@ -55,6 +56,41 @@ properties: mentioned in the nvidia GPIO device tree binding document. const: 1 +allOf: + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra194-gte-aon + - nvidia,tegra234-gte-aon + then: + properties: + nvidia,slices: + const: 3 + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra194-gte-lic + then: + properties: + nvidia,slices: + const: 11 + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra234-gte-lic + then: + properties: + nvidia,slices: + const: 17 + required: - compatible - reg From patchwork Thu Apr 6 17:18:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dipen Patel X-Patchwork-Id: 80368 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1192574vqo; Thu, 6 Apr 2023 10:34:09 -0700 (PDT) X-Google-Smtp-Source: AKy350aQU5s6teaVj28uZQWmwTo/tloqbXsb5ZCTRgc0sW9V6ul46VqYGIRpwMv6uHGbWGCvHjo6 X-Received: by 2002:a17:903:22c9:b0:1a1:a0b7:7254 with SMTP id y9-20020a17090322c900b001a1a0b77254mr14097083plg.62.1680802448827; Thu, 06 Apr 2023 10:34:08 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1680802448; cv=pass; d=google.com; s=arc-20160816; b=LJNLzDMQgoRygB2jILUeGAeA1cMUSO4AqUgtVtwa/EfCcochfnnNt/UMw8XNo5QAfO 0OQHmey6g+CYlCsL73PbieNDxxh6q9I5R+/E72NjAZuCUXM0PxJvtMRJzBrH0ba+1s3r sSpmWrKih8hxjaH96NVOdRYAYMwE/NQzbhVU5pfOdDC1tnLowKkEVx5HGsUWLUBjVgKc 71/Gtz/vTC0MIfu6ZN5Ikl/ptQxLtlRnF159USH68B67SzvLNI6uq//dxuyQD+QAqBZn QCW2iBt2V9I9A6xGQpMR+aANCN6cu7I3Eem9Ol1/XtOQ1UiyifkPUisF6jH2wtXNjdHT 4Fhw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=03KGcNgzWZAGbU8MTWJAjF5hG5ie98vpsUZywcVmaJg=; b=iUvwNyaw92xEIHA6Jb+LQrAVVWg2j/siA8Zuh/5L4kE4jx6Q6KQiqTnKzyjYGK4vzF 85Jr9Ba/UdBMbfA9GyVjCylvt1cPT0DcFRVQ+YlcHT/0GLfDxcSM7GiRw9S449jigeUo R+ZHGF92JVuPRdjIam2psaAFLWWZ5e4wJG3PAjxtu6J7cgqNVKQayav045rIIbQf+RE2 PEiGKu+A6nWTlFQIS9r5UlhGwwmrX/kY/E29JF5rxynRAUB8UiFwqJXENSmFts01Km3F l5bvNff9F5X5TrUBQRd23TPQICaPXqZBfVkf0Hq1xQoxPeo1EHkgD4bpeZHZGjTybT6C 5emw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=tRz8PS4t; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Dipen Patel Reviewed-by: Linus Walleij Acked-by: Rob Herring --- .../bindings/timestamp/nvidia,tegra194-hte.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml b/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml index 158dbe58c49f..855dad3f2023 100644 --- a/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml +++ b/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml @@ -42,10 +42,13 @@ properties: nvidia,slices: $ref: /schemas/types.yaml#/definitions/uint32 + deprecated: true description: HTE lines are arranged in 32 bit slice where each bit represents different line/signal that it can enable/configure for the timestamp. It is u32 - property and the value depends on the HTE instance in the chip. + property and the value depends on the HTE instance in the chip. The AON + GTE instances for both Tegra194 and Tegra234 has 3 slices. The Tegra194 + LIC instance has 11 slices and Tegra234 LIC has 17 slices. enum: [3, 11, 17] '#timestamp-cells': @@ -95,7 +98,6 @@ required: - compatible - reg - interrupts - - nvidia,slices - "#timestamp-cells" additionalProperties: false @@ -107,7 +109,6 @@ examples: reg = <0xc1e0000 0x10000>; interrupts = <0 13 0x4>; nvidia,int-threshold = <1>; - nvidia,slices = <3>; #timestamp-cells = <1>; }; @@ -117,7 +118,6 @@ examples: reg = <0x3aa0000 0x10000>; interrupts = <0 11 0x4>; nvidia,int-threshold = <1>; - nvidia,slices = <11>; #timestamp-cells = <1>; }; From patchwork Thu Apr 6 17:18:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dipen Patel X-Patchwork-Id: 80364 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1192069vqo; Thu, 6 Apr 2023 10:33:11 -0700 (PDT) X-Google-Smtp-Source: AKy350bm7EXRCGb2WZuMhSAJmD5jtZN+i3d1JKrqyGlnSEjHSF7xgOoMHHisruMg/IlEEwqP0xjQ X-Received: by 2002:a17:90b:d87:b0:234:67ef:304b with SMTP id bg7-20020a17090b0d8700b0023467ef304bmr12424410pjb.37.1680802391645; Thu, 06 Apr 2023 10:33:11 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1680802391; cv=pass; d=google.com; s=arc-20160816; b=IumRAhZkfwKkMFG3D3n0ZUhZTGM9SwdZt0CHGstVs5D7ZfU7xIa8goMnMI8GO2+YDx UasJpGcvRYgJVTFG8yaFBly49+vR9MvKcNTLTFbQQ30KJtPlB/OSIC8ws2Ikpcl6D0uN OvjLXMhKz9D8uzx+UUoyjvd1oYXyyJMQaMKw5NXye2VCfBVBabapdIQOik1mLbGS2IZ0 Ff3EAT0L02RvaRPc91HrtCosc2qcchzsfLeW5xbP8rSObw26xYNDwazE1PVobX/DNHq1 vw51YhdNhH7Il1CpqmdKp144x+BJK1To0zFtdP9mhK1meTEqLMpq/gwR13WxhIgQGTc6 Pq3g== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=rpr7mmBjfnZDPZpotB3Ko5DC5NCtrzswAHRmVD+pezE=; b=Ko1e2Y8igwZ/Iyvs4Nw/qzUAiQHrQoH/BgwvhyBHkKfoh0epOqiENUuZ1VWIGzqdtz 8+XlXfX7hiHWyt5TYoZxWKmqamDBn72yop+mKD+/FsEA+N6yzJaqDulnqZSf9rfKFhQf pX5S2b90ZsZC6DDQOtI0Oz6oR+/8xUTQHrNjdfyu5a50A+B6fKvb0Vt0C2gCIZfq1nnC qB+yQH4JSXRS2bRi9o0gwOLCYyoDNs/LyW7NU+Ml6kMmRAAL7W0FqhmP6qxRM+SUMUWt oYCRsEC5loejMYN2zopBvZBVMIcV500P7BDVF3oLrt71PhTqbE+gEwLCxCXiPTYuFO+v 9X5g== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=kLj6MsE3; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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The patch introduces nvidia,gpio-controller property to represent that dependency. Signed-off-by: Dipen Patel Reviewed-by: Linus Walleij --- .../timestamp/nvidia,tegra194-hte.yaml | 36 ++++++++++++++++--- 1 file changed, 31 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml b/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml index 855dad3f2023..66eaa3fab8cc 100644 --- a/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml +++ b/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml @@ -51,6 +51,12 @@ properties: LIC instance has 11 slices and Tegra234 LIC has 17 slices. enum: [3, 11, 17] + nvidia,gpio-controller: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle to AON gpio controller instance. This is required to handle + namespace conversion between GPIO and GTE. + '#timestamp-cells': description: This represents number of line id arguments as specified by the @@ -59,6 +65,12 @@ properties: mentioned in the nvidia GPIO device tree binding document. const: 1 +required: + - compatible + - reg + - interrupts + - "#timestamp-cells" + allOf: - if: properties: @@ -94,11 +106,15 @@ allOf: nvidia,slices: const: 17 -required: - - compatible - - reg - - interrupts - - "#timestamp-cells" + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra234-gte-aon + then: + required: + - nvidia,gpio-controller additionalProperties: false @@ -112,6 +128,16 @@ examples: #timestamp-cells = <1>; }; + - | + tegra234_hte_aon: timestamp@c1e0000 { + compatible = "nvidia,tegra234-gte-aon"; + reg = <0xc1e0000 0x10000>; + interrupts = <0 13 0x4>; + nvidia,int-threshold = <1>; + nvidia,gpio-controller = <&gpio_aon>; + #timestamp-cells = <1>; + }; + - | tegra_hte_lic: timestamp@3aa0000 { compatible = "nvidia,tegra194-gte-lic"; From patchwork Thu Apr 6 17:18:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dipen Patel X-Patchwork-Id: 80360 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1185632vqo; Thu, 6 Apr 2023 10:21:43 -0700 (PDT) X-Google-Smtp-Source: AKy350brSy2t/NfcG9EFrCwZNIQ70vjGd4T5QVqmV0gog76WBBIm3/2iJF3DMh6P+C8HiWLoB9mn X-Received: by 2002:aa7:c457:0:b0:4a2:588f:b3c5 with SMTP id n23-20020aa7c457000000b004a2588fb3c5mr235061edr.21.1680801703565; Thu, 06 Apr 2023 10:21:43 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1680801703; cv=pass; d=google.com; s=arc-20160816; b=jnO4XQjZaQA2625t3hqAvEkDnUrC8uSxroblHQnAqFTJz8meif1RfnKRay4MoyTjsF eNtehKGV8ZNGZWWSbt0hyzMV/3AdxxqqftBm3slp2+zvOSt9xYnjBCyrVWvbZTsqOuEX SdwIYbHKW3h+ponzEzmCOWQ+YRNrksrH6o9y7GfhSYWZwsT/KVrLAad9ewImbPM8hgGu bweLGl3tir1E9ThQbuootNka9SAb8l0iCd0IvEN0dSa6rQ7VYID+6xQqRrlaW97LZ4IZ OeccSk3kXbJG6SeXpfkNqZ4dbWi4WmJ+byF8JtRf5lKEmqREb/IlaRBNpj4u33cwhX3t rG6w== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=Kx/kpYZ7ir9/y4hkhUOBaWiXie83l6Pngi0Gj/5GgOI=; b=Iu/rlHK89zH6rpQGDY04DioU5ldH2TkgvmztVjb6NzUBwtpNqJMNnhHSYUkZpQVm6X C3GAyz3bh+C64qVFEUlelcfOFozrrq2Uh9Pn1WlUMiDzuRZicS6lm688D9XTIIM4ll3p wIfUenkkBhEkxxTt3MjzLgcxIzIFB9fGUBADlGrRw+870idRmUKJpntzDBcWaeWJzPmn 2Mo332/jK2mKknQ0PHLgeDOgJdhJOsDE5cBbIqg/EjcfQpNXYwby6SYniIs+Pc8mQWKF F64FSdBLPIj/mEIVLxIalJzcgysa/6CDFGqN6jcQIG/f+f4ochkZzI1bER65zeHnZ3KN 10lA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=CVOl2nRq; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Dipen Patel --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 8fe8eda7654d..54790c6b6a2c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -1156,6 +1156,14 @@ clock-names = "fuse"; }; + hte_lic: hardware-timestamp@3aa0000 { + compatible = "nvidia,tegra234-gte-lic"; + reg = <0x0 0x3aa0000 0x0 0x10000>; + interrupts = ; + nvidia,int-threshold = <1>; + #timestamp-cells = <1>; + }; + hsp_top0: hsp@3c00000 { compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; reg = <0x0 0x03c00000 0x0 0xa0000>; @@ -1673,6 +1681,15 @@ #mbox-cells = <2>; }; + hte_aon: hardware-timestamp@c1e0000 { + compatible = "nvidia,tegra234-gte-aon"; + reg = <0x0 0xc1e0000 0x0 0x10000>; + interrupts = ; + nvidia,int-threshold = <1>; + nvidia,gpio-controller = <&gpio_aon>; + #timestamp-cells = <1>; + }; + gen2_i2c: i2c@c240000 { compatible = "nvidia,tegra194-i2c"; reg = <0x0 0xc240000 0x0 0x100>; From patchwork Thu Apr 6 17:18:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dipen Patel X-Patchwork-Id: 80361 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1185712vqo; Thu, 6 Apr 2023 10:21:52 -0700 (PDT) X-Google-Smtp-Source: AKy350bTbQZyBl+KVvz5zFfrsHdTu8cUSNZhgZAk36v7LaUWN0rY7T2EBAW9ufXcj8aI8cbe2oba X-Received: by 2002:a05:6a20:739a:b0:d7:3b62:3cf with SMTP id o26-20020a056a20739a00b000d73b6203cfmr178531pzd.54.1680801712422; Thu, 06 Apr 2023 10:21:52 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1680801712; cv=pass; d=google.com; s=arc-20160816; b=hY63kzYPYX/sSCh9ljaGaekCQtWiHdm+rDrb7V5PmrTTfJWGL4FMr6FkYnkTXghEhs h6ELqDO6Ts7qVvUG5fQ929hmT3VALcx3jEf4tbsY91ICkTjOwpcuMJ7iR+OwTSAF5JVh LK2DI2oT96fgpG/a0uEY+0d9nFG5LEpgET2ZyuKbacDd21ruSJq+pb+WM5ygPZLGiDHo srG+/IZaA65yk12Jbu4b3KkuOfNXnDfdFDjUhNBJbEc4MH+cUD7Xjan2Eki2N988joH5 HR0JfvuzlqGxJ/M9XIxlbZZJnDduiiOcXTFiBQ630ZMRqjE9ozNeKTAsafjfta/SQPSU c4jw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=dP5kJ/vC5AJs62jqKAJ+brtcGkn+r0lWkhnYvZGCnX4=; b=RVkqOs3NOszKgWLmaGc03rZ60gx+FP7Dw1fUt/qCbBeDVCKo5lEo6AuGLhHLjdPl2K kB2vrLRJIrS6d15OPScKUynAkrYYwwfVEeL2c2ArAzaYrMEUG/yN3l0uXwKW/lhoCl97 zewnJCCJq5KA+0kMTk2ePc61DwkLc9G499FXIL6Pz6IO77T7dDnPklX5u4Z5e2A4ZMs/ sydD6aOQ/xCcWWNlz7E0Tdsd56x2vtiepaWR1QwnUl7qr0dM/fgpQkqitGIfk+CBiJZv qbUivw8hUWyVhgNKdS+siMuaTtztIFr0NLTFeWRcZwZLwO+llRpMOywDNfmwUPIIfe64 0bEg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=YBXmH0Nw; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Dipen Patel Reviewed-by: Bagas Sanjaya --- v5: - rename tegra194-hte.rst to tegra-hte.rst Documentation/driver-api/hte/index.rst | 2 +- .../hte/{tegra194-hte.rst => tegra-hte.rst} | 33 +++++++++---------- 2 files changed, 17 insertions(+), 18 deletions(-) rename Documentation/driver-api/hte/{tegra194-hte.rst => tegra-hte.rst} (50%) diff --git a/Documentation/driver-api/hte/index.rst b/Documentation/driver-api/hte/index.rst index 9f43301c05dc..29011de9a4b8 100644 --- a/Documentation/driver-api/hte/index.rst +++ b/Documentation/driver-api/hte/index.rst @@ -18,5 +18,5 @@ HTE Tegra Provider .. toctree:: :maxdepth: 1 - tegra194-hte + tegra-hte diff --git a/Documentation/driver-api/hte/tegra194-hte.rst b/Documentation/driver-api/hte/tegra-hte.rst similarity index 50% rename from Documentation/driver-api/hte/tegra194-hte.rst rename to Documentation/driver-api/hte/tegra-hte.rst index f2d617265546..85e654772782 100644 --- a/Documentation/driver-api/hte/tegra194-hte.rst +++ b/Documentation/driver-api/hte/tegra-hte.rst @@ -5,25 +5,25 @@ HTE Kernel provider driver Description ----------- -The Nvidia tegra194 HTE provider driver implements two GTE -(Generic Timestamping Engine) instances: 1) GPIO GTE and 2) LIC -(Legacy Interrupt Controller) IRQ GTE. Both GTE instances get the -timestamp from the system counter TSC which has 31.25MHz clock rate, and the -driver converts clock tick rate to nanoseconds before storing it as timestamp -value. +The Nvidia tegra HTE provider also known as GTE (Generic Timestamping Engine) +driver implements two GTE instances: 1) GPIO GTE and 2) LIC +(Legacy Interrupt Controller) IRQ GTE. Both GTE instances get the timestamp +from the system counter TSC which has 31.25MHz clock rate, and the driver +converts clock tick rate to nanoseconds before storing it as timestamp value. GPIO GTE -------- This GTE instance timestamps GPIO in real time. For that to happen GPIO -needs to be configured as input. The always on (AON) GPIO controller instance -supports timestamping GPIOs in real time and it has 39 GPIO lines. The GPIO GTE -and AON GPIO controller are tightly coupled as it requires very specific bits -to be set in GPIO config register before GPIO GTE can be used, for that GPIOLIB -adds two optional APIs as below. The GPIO GTE code supports both kernel -and userspace consumers. The kernel space consumers can directly talk to HTE -subsystem while userspace consumers timestamp requests go through GPIOLIB CDEV -framework to HTE subsystem. +needs to be configured as input. Only the always on (AON) GPIO controller +instance supports timestamping GPIOs in real time as it is tightly coupled with +the GPIO GTE. To support this, GPIOLIB adds two optional APIs as mentioned +below. The GPIO GTE code supports both kernel and userspace consumers. The +kernel space consumers can directly talk to HTE subsystem while userspace +consumers timestamp requests go through GPIOLIB CDEV framework to HTE +subsystem. The hte devicetree binding described at +``Documentation/devicetree/bindings/timestamp`` provides an example of how a +consumer can request an GPIO line. See gpiod_enable_hw_timestamp_ns() and gpiod_disable_hw_timestamp_ns(). @@ -34,9 +34,8 @@ returns the timestamp in nanoseconds. LIC (Legacy Interrupt Controller) IRQ GTE ----------------------------------------- -This GTE instance timestamps LIC IRQ lines in real time. There are 352 IRQ -lines which this instance can add timestamps to in real time. The hte -devicetree binding described at ``Documentation/devicetree/bindings/timestamp`` +This GTE instance timestamps LIC IRQ lines in real time. The hte devicetree +binding described at ``Documentation/devicetree/bindings/timestamp`` provides an example of how a consumer can request an IRQ line. Since it is a one-to-one mapping with IRQ GTE provider, consumers can simply specify the IRQ number that they are interested in. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Apr 2023 17:18:57.4717 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a5c4536f-ee55-4636-0727-08db36c30195 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6446 X-Spam-Status: No, score=0.8 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762449203491350714?= X-GMAIL-MSGID: =?utf-8?q?1762449203491350714?= The Tegra234 AON GPIO instance and LIC IRQ support HTE. For the GPIO HTE support, it also requires to add mapping between GPIO and HTE framework same as it was done with Tegra194 SoC. Signed-off-by: Dipen Patel --- v2: - Changed how gpio_chip could be aquired for the mapping v3: - Renamed gpio_chip matching function - Used of_node to fwnode field in gpio_chip matching function as data as gpio_chip struct does not have of_node member anymore. v4: - Logically divide the original v3 patch as follows - Created this Tegra234 support patch - Created deprecated nvidia,slices patch - Created handle nvidia,gpio-controller patch drivers/hte/hte-tegra194-test.c | 2 +- drivers/hte/hte-tegra194.c | 124 ++++++++++++++++++++++++++++++-- 2 files changed, 121 insertions(+), 5 deletions(-) diff --git a/drivers/hte/hte-tegra194-test.c b/drivers/hte/hte-tegra194-test.c index 5d776a185bd6..d79c28a80517 100644 --- a/drivers/hte/hte-tegra194-test.c +++ b/drivers/hte/hte-tegra194-test.c @@ -16,7 +16,7 @@ #include /* - * This sample HTE GPIO test driver demonstrates HTE API usage by enabling + * This sample HTE test driver demonstrates HTE API usage by enabling * hardware timestamp on gpio_in and specified LIC IRQ lines. * * Note: gpio_out and gpio_in need to be shorted externally in order for this diff --git a/drivers/hte/hte-tegra194.c b/drivers/hte/hte-tegra194.c index 49a27af22742..5d1f947db0f6 100644 --- a/drivers/hte/hte-tegra194.c +++ b/drivers/hte/hte-tegra194.c @@ -62,6 +62,10 @@ #define NV_AON_HTE_SLICE2_IRQ_GPIO_25 25 #define NV_AON_HTE_SLICE2_IRQ_GPIO_26 26 #define NV_AON_HTE_SLICE2_IRQ_GPIO_27 27 +#define NV_AON_HTE_SLICE2_IRQ_GPIO_28 28 +#define NV_AON_HTE_SLICE2_IRQ_GPIO_29 29 +#define NV_AON_HTE_SLICE2_IRQ_GPIO_30 30 +#define NV_AON_HTE_SLICE2_IRQ_GPIO_31 31 #define HTE_TECTRL 0x0 #define HTE_TETSCH 0x4 @@ -220,7 +224,100 @@ static const struct tegra_hte_line_mapped tegra194_aon_gpio_sec_map[] = { [39] = {NV_AON_SLICE_INVALID, 0}, }; -static const struct tegra_hte_data aon_hte = { +static const struct tegra_hte_line_mapped tegra234_aon_gpio_map[] = { + /* gpio, slice, bit_index */ + /* AA port */ + [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, + [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, + [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, + [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, + [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, + [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, + [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, + [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, + /* BB port */ + [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, + [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, + [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, + [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, + /* CC port */ + [12] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, + [13] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, + [14] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, + [15] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, + [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, + [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, + [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, + [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, + /* DD port */ + [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, + [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, + [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, + /* EE port */ + [23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31}, + [24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30}, + [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29}, + [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28}, + [27] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, + [28] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, + [29] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, + [30] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, + /* GG port */ + [31] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, +}; + +static const struct tegra_hte_line_mapped tegra234_aon_gpio_sec_map[] = { + /* gpio, slice, bit_index */ + /* AA port */ + [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, + [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, + [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, + [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, + [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, + [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, + [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, + [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, + /* BB port */ + [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, + [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, + [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, + [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, + [12] = {NV_AON_SLICE_INVALID, 0}, + [13] = {NV_AON_SLICE_INVALID, 0}, + [14] = {NV_AON_SLICE_INVALID, 0}, + [15] = {NV_AON_SLICE_INVALID, 0}, + /* CC port */ + [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, + [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, + [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, + [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, + [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, + [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, + [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, + [23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, + /* DD port */ + [24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, + [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, + [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, + [27] = {NV_AON_SLICE_INVALID, 0}, + [28] = {NV_AON_SLICE_INVALID, 0}, + [29] = {NV_AON_SLICE_INVALID, 0}, + [30] = {NV_AON_SLICE_INVALID, 0}, + [31] = {NV_AON_SLICE_INVALID, 0}, + /* EE port */ + [32] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31}, + [33] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30}, + [34] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29}, + [35] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28}, + [36] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, + [37] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, + [38] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, + [39] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, + /* GG port */ + [40] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, +}; + +static const struct tegra_hte_data t194_aon_hte = { .map_sz = ARRAY_SIZE(tegra194_aon_gpio_map), .map = tegra194_aon_gpio_map, .sec_map_sz = ARRAY_SIZE(tegra194_aon_gpio_sec_map), @@ -228,6 +325,14 @@ static const struct tegra_hte_data aon_hte = { .type = HTE_TEGRA_TYPE_GPIO, }; +static const struct tegra_hte_data t234_aon_hte = { + .map_sz = ARRAY_SIZE(tegra234_aon_gpio_map), + .map = tegra234_aon_gpio_map, + .sec_map_sz = ARRAY_SIZE(tegra234_aon_gpio_sec_map), + .sec_map = tegra234_aon_gpio_sec_map, + .type = HTE_TEGRA_TYPE_GPIO, +}; + static const struct tegra_hte_data lic_hte = { .map_sz = 0, .map = NULL, @@ -535,7 +640,9 @@ static bool tegra_hte_match_from_linedata(const struct hte_chip *chip, static const struct of_device_id tegra_hte_of_match[] = { { .compatible = "nvidia,tegra194-gte-lic", .data = &lic_hte}, - { .compatible = "nvidia,tegra194-gte-aon", .data = &aon_hte}, + { .compatible = "nvidia,tegra194-gte-aon", .data = &t194_aon_hte}, + { .compatible = "nvidia,tegra234-gte-lic", .data = &lic_hte}, + { .compatible = "nvidia,tegra234-gte-aon", .data = &t234_aon_hte}, { } }; MODULE_DEVICE_TABLE(of, tegra_hte_of_match); @@ -635,8 +742,17 @@ static int tegra_hte_probe(struct platform_device *pdev) gc->match_from_linedata = tegra_hte_match_from_linedata; - hte_dev->c = gpiochip_find("tegra194-gpio-aon", - tegra_get_gpiochip_from_name); + if (of_device_is_compatible(dev->of_node, + "nvidia,tegra194-gte-aon")) + hte_dev->c = gpiochip_find("tegra194-gpio-aon", + tegra_get_gpiochip_from_name); + else if (of_device_is_compatible(dev->of_node, + "nvidia,tegra234-gte-aon")) + hte_dev->c = gpiochip_find("tegra234-gpio-aon", + tegra_get_gpiochip_from_name); + else + return -ENODEV; + if (!hte_dev->c) return dev_err_probe(dev, -EPROBE_DEFER, "wait for gpio controller\n"); From patchwork Thu Apr 6 17:18:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dipen Patel X-Patchwork-Id: 80362 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1187468vqo; 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Signed-off-by: Dipen Patel --- drivers/hte/hte-tegra194.c | 31 +++++++++++++++++++++---------- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/drivers/hte/hte-tegra194.c b/drivers/hte/hte-tegra194.c index 5d1f947db0f6..945c68c5e476 100644 --- a/drivers/hte/hte-tegra194.c +++ b/drivers/hte/hte-tegra194.c @@ -118,6 +118,7 @@ struct tegra_hte_line_data { struct tegra_hte_data { enum tegra_hte_type type; + u32 slices; u32 map_sz; u32 sec_map_sz; const struct tegra_hte_line_mapped *map; @@ -323,6 +324,7 @@ static const struct tegra_hte_data t194_aon_hte = { .sec_map_sz = ARRAY_SIZE(tegra194_aon_gpio_sec_map), .sec_map = tegra194_aon_gpio_sec_map, .type = HTE_TEGRA_TYPE_GPIO, + .slices = 3, }; static const struct tegra_hte_data t234_aon_hte = { @@ -331,12 +333,21 @@ static const struct tegra_hte_data t234_aon_hte = { .sec_map_sz = ARRAY_SIZE(tegra234_aon_gpio_sec_map), .sec_map = tegra234_aon_gpio_sec_map, .type = HTE_TEGRA_TYPE_GPIO, + .slices = 3, }; -static const struct tegra_hte_data lic_hte = { +static const struct tegra_hte_data t194_lic_hte = { .map_sz = 0, .map = NULL, .type = HTE_TEGRA_TYPE_LIC, + .slices = 11, +}; + +static const struct tegra_hte_data t234_lic_hte = { + .map_sz = 0, + .map = NULL, + .type = HTE_TEGRA_TYPE_LIC, + .slices = 17, }; static inline u32 tegra_hte_readl(struct tegra_hte_soc *hte, u32 reg) @@ -639,9 +650,9 @@ static bool tegra_hte_match_from_linedata(const struct hte_chip *chip, } static const struct of_device_id tegra_hte_of_match[] = { - { .compatible = "nvidia,tegra194-gte-lic", .data = &lic_hte}, + { .compatible = "nvidia,tegra194-gte-lic", .data = &t194_lic_hte}, { .compatible = "nvidia,tegra194-gte-aon", .data = &t194_aon_hte}, - { .compatible = "nvidia,tegra234-gte-lic", .data = &lic_hte}, + { .compatible = "nvidia,tegra234-gte-lic", .data = &t234_lic_hte}, { .compatible = "nvidia,tegra234-gte-aon", .data = &t234_aon_hte}, { } }; @@ -679,13 +690,6 @@ static int tegra_hte_probe(struct platform_device *pdev) dev = &pdev->dev; - ret = of_property_read_u32(dev->of_node, "nvidia,slices", &slices); - if (ret != 0) { - dev_err(dev, "Could not read slices\n"); - return -EINVAL; - } - nlines = slices << 5; - hte_dev = devm_kzalloc(dev, sizeof(*hte_dev), GFP_KERNEL); if (!hte_dev) return -ENOMEM; @@ -697,6 +701,13 @@ static int tegra_hte_probe(struct platform_device *pdev) dev_set_drvdata(&pdev->dev, hte_dev); hte_dev->prov_data = of_device_get_match_data(&pdev->dev); + ret = of_property_read_u32(dev->of_node, "nvidia,slices", &slices); + if (ret != 0) + slices = hte_dev->prov_data->slices; + + dev_dbg(dev, "slices:%d\n", slices); + nlines = slices << 5; + hte_dev->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(hte_dev->regs)) return PTR_ERR(hte_dev->regs); From patchwork Thu Apr 6 17:18:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dipen Patel X-Patchwork-Id: 80373 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1193344vqo; Thu, 6 Apr 2023 10:35:26 -0700 (PDT) X-Google-Smtp-Source: AKy350YT/PheKoUC47oESN1OO06m6wn6dNIglmyfS94WeLY64xjg+qIhgkWihiIsCQ5eKDuXj/g/ X-Received: by 2002:a17:902:fa0d:b0:1a1:d655:1ce4 with SMTP id la13-20020a170902fa0d00b001a1d6551ce4mr9365583plb.38.1680802525821; Thu, 06 Apr 2023 10:35:25 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1680802525; cv=pass; d=google.com; s=arc-20160816; b=XvMNQ3rTWKcu10sPbatUxk1FbQNHVrffSzNlwSy4Nxy+grxq3kHaoylT/hHCHkbp4B mmrcG+Qqd/B8RcWecITaaPxi8MgxUS7lwm3u+EuBDy6pHdVdW3j/HT7jGX2aQJfbeaHV Fc5GafSKCvdOA9Mkj0HrYJ731RgPR+jjy/epc38BOqoVT+oQeHY4ibwZhiCcoN8905t+ smhbrAo8vn3Avm9CN5l3+xHktLBZczfUFrLMTTdF2o001INuue/daeVg3KH/Yz3By2Ns o4p+fB0HvMNMZGINkgxq3g6IBBeMZwsUu02D3y8gP3+hJ3adycKuq8TEBSdx1F4MtHO2 EA5Q== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=8VuXydsVhYEwxRK1w0P8PtVMEifqFFyAoGYf+LUBVEg=; b=LWmLopR8A2wUVq7kf1GnPxV65N/u0tRJyKkBPe1bxK/40Vqua20YkTv5LEd/eYgIH2 tXK9y2pNpxJoasnNAPSniDTvuk+iWEM3FECHQmWty/JpzKN9fgVh1cACzNu8ij3i1Jjg 8uVxYcIM8+Lsyr69AFbQ6CLqRtfNF7mYNa1vMom36xdSBXXWoLvMZ3h9znASs9xp1q8C UQaRxSQUA8lQuSjy6VSa2wGaj+xFXa1ST5/ms3ShqYhyKF2p/hAh0+9Tij7sH5zGFi4U t64BSN0jer9o+9kZzeaZyOCI1N/h9a8Qbxa9D0vnSkKmM/GBph+gesk/me3MTNubXhy4 xVVg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=sIjtPB1v; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Apr 2023 17:18:58.3623 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3bda54bf-04b4-4772-4d45-08db36c3021f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR12MB5443 X-Spam-Status: No, score=0.8 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762449189598868560?= X-GMAIL-MSGID: =?utf-8?q?1762449189598868560?= The dt binding adds nvidia,gpio-controller property from Tegra234 SoC onwards to simplify code handling gpio chip search. The gpio chip search is needed for the AON GPIO GTE instances to map the hardware timestamp GPIO request (coming from the GPIO framework) to the tegra HTE providers. The patch also adds new gpio chip match function to match from the fwnode instead of the gpio controller label. The addition of the property does not break ABI for the existing Tegra194 code. Signed-off-by: Dipen Patel Reviewed-by: Linus Walleij --- drivers/hte/hte-tegra194.c | 28 +++++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/drivers/hte/hte-tegra194.c b/drivers/hte/hte-tegra194.c index 945c68c5e476..2c485ff5be22 100644 --- a/drivers/hte/hte-tegra194.c +++ b/drivers/hte/hte-tegra194.c @@ -679,6 +679,11 @@ static int tegra_get_gpiochip_from_name(struct gpio_chip *chip, void *data) return !strcmp(chip->label, data); } +static int tegra_gpiochip_match(struct gpio_chip *chip, void *data) +{ + return chip->fwnode == of_node_to_fwnode(data); +} + static int tegra_hte_probe(struct platform_device *pdev) { int ret; @@ -687,6 +692,7 @@ static int tegra_hte_probe(struct platform_device *pdev) struct device *dev; struct tegra_hte_soc *hte_dev; struct hte_chip *gc; + struct device_node *gpio_ctrl; dev = &pdev->dev; @@ -754,15 +760,23 @@ static int tegra_hte_probe(struct platform_device *pdev) gc->match_from_linedata = tegra_hte_match_from_linedata; if (of_device_is_compatible(dev->of_node, - "nvidia,tegra194-gte-aon")) + "nvidia,tegra194-gte-aon")) { hte_dev->c = gpiochip_find("tegra194-gpio-aon", tegra_get_gpiochip_from_name); - else if (of_device_is_compatible(dev->of_node, - "nvidia,tegra234-gte-aon")) - hte_dev->c = gpiochip_find("tegra234-gpio-aon", - tegra_get_gpiochip_from_name); - else - return -ENODEV; + } else { + gpio_ctrl = of_parse_phandle(dev->of_node, + "nvidia,gpio-controller", + 0); + if (!gpio_ctrl) { + dev_err(dev, + "gpio controller node not found\n"); + return -ENODEV; + } + + hte_dev->c = gpiochip_find(gpio_ctrl, + tegra_gpiochip_match); + of_node_put(gpio_ctrl); + } if (!hte_dev->c) return dev_err_probe(dev, -EPROBE_DEFER, From patchwork Thu Apr 6 17:18:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dipen Patel X-Patchwork-Id: 80366 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1192112vqo; Thu, 6 Apr 2023 10:33:15 -0700 (PDT) X-Google-Smtp-Source: AKy350bmdWh71uQkTHMfZDS5hbSenjagvNMbT33sZJ48yl5xbxLIp6g6Xe/8gELFxOzgkpw2WoWj X-Received: by 2002:a05:6a20:1b07:b0:d5:213a:476e with SMTP id ch7-20020a056a201b0700b000d5213a476emr202164pzb.51.1680802395631; Thu, 06 Apr 2023 10:33:15 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1680802395; cv=pass; d=google.com; s=arc-20160816; b=CrCLLqvCNjfd71pgCCzactRltvHizdiLG9Dbl4Lt02rk9UCY/5G0ZlmCmYwQzG4hs+ yfTchhSvDEDOoqIhLbBGsi881wKPfVWtedv5vw860GI/fqJmxcxOVL01sLzqlctxYa1A 1xVwnxtAJglrk2grE7PL9Ec/Fqq9SnssCqGRMH6mOL0BvVmUffpBA08kNEUEBAJxrLLA qDImlf2GrVOUmDhVMYAmls2hUjVMhBQXXwBZekrxnqt9eTVfkA0ES1bU37oMU6OAMeas 69I8FvIkmRKCATTBvK6ScPtdEnjH/tqyPGibFAhy5mJ1sNns+/OuVqTRg4UkzJs1RBME XdAA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=x0B4e4waDo/8ygYRfAUPi4j/yHBgi9ZU9AnjB6UuD5k=; b=X2RF577S28VxadUBLlLRIGVDysO2nWWfsy1YMoA3KSDphBDIri6AvqD6U1qUe0T4cH ZVmqaM8OfXLEgeujwL61Hk7qo0ozLuWimXKHubLrGNZW1X8vP7YZzrcrbR6aoxWHGKF+ 4qiRzrcqDtsnXb+qkSa4vLPMMKexdcZXPJKzj8sRqoEMfkqOTvbpuuswDqd8+gav0+Oo 26xO4s4NxQWyz/Bw59+TnF/8hxNkweJovTFNG5vXS9oFAAilgLhxIB4idjSaOyAKN2zc 4CCTLF47RcnEPUDtkeAzCBdtN5MEF6BXAoyNFLXNk0G/hu3WINwrrXczFwVTGqfdybx6 akLg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=LzzzeNkh; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Dipen Patel Acked-by: Thierry Reding Acked-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-tegra186.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c index 14c872b6ad05..b904de0b1784 100644 --- a/drivers/gpio/gpio-tegra186.c +++ b/drivers/gpio/gpio-tegra186.c @@ -1134,6 +1134,7 @@ static const struct tegra_gpio_soc tegra234_aon_soc = { .name = "tegra234-gpio-aon", .instance = 1, .num_irqs_per_bank = 8, + .has_gte = true, }; #define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \