From patchwork Thu Apr 6 15:36:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Earnshaw X-Patchwork-Id: 80324 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1118621vqo; Thu, 6 Apr 2023 08:37:28 -0700 (PDT) X-Google-Smtp-Source: AKy350ZYkOxfw3y3qiOeNWI8xUUCUUaivUBvs3Omv8MD05aCxdXhkurvw1Pz7DhI+JFV3fPIoBtg X-Received: by 2002:a17:906:a414:b0:905:a46b:a725 with SMTP id l20-20020a170906a41400b00905a46ba725mr5433655ejz.16.1680795448179; Thu, 06 Apr 2023 08:37:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680795448; cv=none; d=google.com; s=arc-20160816; b=XPbPcMnWc+7+4p/rvIL2PA9X6or8XFRBR9zpYKor0Mtgw0k8hBQG8m1jMKEkRa4K7Z 84cPdsSwXzYmRSQ6I1BjISoIoNgMin713O+LqXMbA1XHd/YM1+zrzC5/WKppOpQoT7PZ XHX4RwLapaKAuDUs01vIzNCkzg7BYl1afgIS2q83mI7ciCbrVgDqels9d9G/20z3S4Oz eZPBMB1r4zHatd91gCBKXHNJBenb4WJ/bqi6u5BgBhkwTKmvHrtZKfeCjfImzexPaYjy c4jEL1T5Tb6W63jEsVc5T4I60aq7JKqkQDTW9Z9wbwb3HRPPRC3D2KH8Q916BeCFXGfi xNaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:message-id:date:subject:cc :to:dmarc-filter:delivered-to:dkim-signature:dkim-filter; bh=c7bO01MNUdiS2i/gEnEx9UFQeew5bjbCyGmuRGZ0h2Q=; b=QE43xmtcG2vNXzCf4Y4mvwm4P7o4FAvYOhw/qTvx4KR2//I5lwQQF7DBbRX/v1Ktlb ium/GR8sYl5t4E44J9HehHL285yvY7Iig3El3eDCauMtYzz5Tcu0OUJgTXRPcZnIwfFl saWYZFsSx45U0nBS/c7AMud3nT8QfhTWBcwW8/LflHESRUmIWmYC2tv8JZ47tbp0qXTQ lSNjgAPoM44mkjctmS+UUI9d+LRvTWfL3OahFIpsp+96oD0oPsRGyVWv7Fvpfkxx3GMw 5VhYUJ5hMMlZG0Lvh4VeZ9FX06mSNRJBU3/noXpakxmD5y/QB4obHjCeC8VL+FZxk+hA jcMQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=K3PFusod; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id a2-20020a170906670200b0093cd9fa2838si1215126ejp.1009.2023.04.06.08.37.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Apr 2023 08:37:28 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=K3PFusod; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2B935385773F for ; Thu, 6 Apr 2023 15:37:20 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 2B935385773F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1680795440; bh=c7bO01MNUdiS2i/gEnEx9UFQeew5bjbCyGmuRGZ0h2Q=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=K3PFusodJdIBNZc5fSB4avue+iJhpPFTYarcShE2OGqYzL9y5XnMN/j7LGuRtX9Dv 4VSsq1TxZ85b/bwj+Y1jZra1slnQvAflJhRharEp3LcF8oS1njATIG51kPeUZkefjc sj2qMYgt7Hzd2/3eqFC5uCclgHtOyH+v1tJx3uCs= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 63DA23858D28 for ; Thu, 6 Apr 2023 15:36:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 63DA23858D28 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 157C9169E; Thu, 6 Apr 2023 08:37:19 -0700 (PDT) Received: from e126323.cambridge.arm.com (unknown [10.2.78.76]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6A5463F762; Thu, 6 Apr 2023 08:36:34 -0700 (PDT) To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw Subject: [committed] arm: mve: fix auto-inc generation [PR107674] Date: Thu, 6 Apr 2023 16:36:20 +0100 Message-Id: <20230406153620.931820-1-rearnsha@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-15.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Earnshaw via Gcc-patches From: Richard Earnshaw Reply-To: Richard Earnshaw Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762441767878662472?= X-GMAIL-MSGID: =?utf-8?q?1762441767878662472?= My change r13-416-g485a0ae0982abe caused the compiler to stop generating auto-inc operations on mve loads and stores. The fix is to check whether there is a replacement register available when in strict mode and the register is still a pseudo. gcc: PR target/107674 * config/arm/arm.cc (arm_effective_regno): New function. (mve_vector_mem_operand): Use it. --- gcc/config/arm/arm.cc | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc index a46627bc375..bf7ff9a9704 100644 --- a/gcc/config/arm/arm.cc +++ b/gcc/config/arm/arm.cc @@ -13639,6 +13639,19 @@ arm_coproc_mem_operand_no_writeback (rtx op) return arm_coproc_mem_operand_wb (op, 0); } +/* In non-STRICT mode, return the register number; in STRICT mode return + the hard regno or the replacement if it won't be a mem. Otherwise, return + the original pseudo number. */ +static int +arm_effective_regno (rtx op, bool strict) +{ + gcc_assert (REG_P (op)); + if (!strict || REGNO (op) < FIRST_PSEUDO_REGISTER + || !reg_renumber || reg_renumber[REGNO (op)] < 0) + return REGNO (op); + return reg_renumber[REGNO (op)]; +} + /* This function returns TRUE on matching mode and op. 1. For given modes, check for [Rn], return TRUE for Rn <= LO_REGS. 2. For other modes, check for [Rn], return TRUE for Rn < R15 (expect R13). */ @@ -13651,7 +13664,7 @@ mve_vector_mem_operand (machine_mode mode, rtx op, bool strict) /* Match: (mem (reg)). */ if (REG_P (op)) { - int reg_no = REGNO (op); + reg_no = arm_effective_regno (op, strict); return (((mode == E_V8QImode || mode == E_V4QImode || mode == E_V4HImode) ? reg_no <= LAST_LO_REGNUM : reg_no < LAST_ARM_REGNUM) @@ -13662,7 +13675,7 @@ mve_vector_mem_operand (machine_mode mode, rtx op, bool strict) if (code == POST_INC || code == PRE_DEC || code == PRE_INC || code == POST_DEC) { - reg_no = REGNO (XEXP (op, 0)); + reg_no = arm_effective_regno (XEXP (op, 0), strict); return (((mode == E_V8QImode || mode == E_V4QImode || mode == E_V4HImode) ? reg_no <= LAST_LO_REGNUM :(reg_no < LAST_ARM_REGNUM && reg_no != SP_REGNUM)) @@ -13678,7 +13691,7 @@ mve_vector_mem_operand (machine_mode mode, rtx op, bool strict) || (reload_completed && code == PLUS && REG_P (XEXP (op, 0)) && GET_CODE (XEXP (op, 1)) == CONST_INT)) { - reg_no = REGNO (XEXP (op, 0)); + reg_no = arm_effective_regno (XEXP (op, 0), strict); if (code == PLUS) val = INTVAL (XEXP (op, 1)); else