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Reviewed-by: Rob Herring Signed-off-by: Devi Priya --- Changes in V3: - Picked up the R-b tag .../devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml b/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml index 8c45f53212b1..a8ca8e0b27f8 100644 --- a/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml @@ -22,7 +22,7 @@ description: Each sub-node is identified using the node's name, with valid values listed for each of the pmics below. - For mp5496, s2 + For mp5496, s1, s2 For pm2250, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22 From patchwork Thu Apr 6 07:00:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Devi Priya X-Patchwork-Id: 80098 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp830895vqo; Thu, 6 Apr 2023 00:13:00 -0700 (PDT) X-Google-Smtp-Source: AKy350biVqD93ve6D/dLhMp0teTput2RSlGEVgh+xsrEqYNCKThNe/fIjNqtR9GSFVTLcYVgw8gL X-Received: by 2002:a17:906:f145:b0:8af:2a97:91d4 with SMTP id gw5-20020a170906f14500b008af2a9791d4mr5864353ejb.14.1680765179892; Thu, 06 Apr 2023 00:12:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680765179; cv=none; d=google.com; s=arc-20160816; b=Hjw3jpPPaUaLJ7Yhg1eYNbCqHeTMvCCKo6Q2AFw1uH+fFowSnXmQo9qpaMP3n59u7S j0otmurfHZ2Qr9MB13F/ubvC1DdVLGXn/W6QkZ7Tvr5AEt3jKmqPbhccnqtpyImp+i2F zA4EzPFJhbSCAhBvMOkuSaeT6gNiLeiPUAUaL1txj6aXNgfU1cWWOA9UK/JJng/W3H3L Ajcj0svfMAuKCzt5SZ1BoIql6hgIN+ai/4h+kPdj80ueHc9oaQUge9YDZ06KFIo7a5ZY ALxJ25ry79TqweGgPbyidhiT4ivbrBapNmivd54IQgBXmM2dzGTUtUQzs8MC8IVrLBpy /IvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=lZhz5ioxyUYicEKmzqXe20G9owP/70IZtLXMIwDa878=; b=stlxQEpF2vi653xbgFYvHkBQ+Zxv/B+Wy/aX/Pi8tW0o17uWsJk8EeBPYfCBic1ff9 sNOHLaKFOqJASsDD7V0qfPsf0dyAJzWFRbtKO8RwjW2J2BC8G3HtDeBAZcbPalu5/RjL pYztDIzNP4MGoi1KEBqyQrPaJ+CdZs9P/257O9SXAVITDe1B8KjwIMdCuZvw1IZXHBEE t8nT/HiwQrMm076ho5of+geVEn/Se5rE0RWdJwBIVejvfNZdlRSCn60Xtf0aI1rNdhg4 I9XmQYm7NfhnHgGGXTOodwq+QvewZeclgjEHN42f5rdXVkTSqzTTh0Z917j1ccf0M73k b9FA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=kfFHNuB5; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Co-developed-by: Praveenkumar I Signed-off-by: Praveenkumar I Signed-off-by: Devi Priya --- Changes in V3: - No change drivers/regulator/qcom_smd-regulator.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/regulator/qcom_smd-regulator.c b/drivers/regulator/qcom_smd-regulator.c index 6f722b2d682e..cb77b3bd1723 100644 --- a/drivers/regulator/qcom_smd-regulator.c +++ b/drivers/regulator/qcom_smd-regulator.c @@ -749,6 +749,15 @@ static const struct regulator_desc pms405_pldo600 = { .ops = &rpm_smps_ldo_ops, }; +static const struct regulator_desc mp5496_smpa1 = { + .linear_ranges = (struct linear_range[]) { + REGULATOR_LINEAR_RANGE(600000, 0, 127, 12500), + }, + .n_linear_ranges = 1, + .n_voltages = 128, + .ops = &rpm_mp5496_ops, +}; + static const struct regulator_desc mp5496_smpa2 = { .linear_ranges = (struct linear_range[]) { REGULATOR_LINEAR_RANGE(600000, 0, 127, 12500), @@ -794,6 +803,7 @@ struct rpm_regulator_data { }; static const struct rpm_regulator_data rpm_mp5496_regulators[] = { + { "s1", QCOM_SMD_RPM_SMPA, 1, &mp5496_smpa1, "s1" }, { "s2", QCOM_SMD_RPM_SMPA, 2, &mp5496_smpa2, "s2" }, { "l2", QCOM_SMD_RPM_LDOA, 2, &mp5496_ldoa2, "l2" }, {} From patchwork Thu Apr 6 07:00:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Devi Priya X-Patchwork-Id: 80094 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp826307vqo; Thu, 6 Apr 2023 00:05:04 -0700 (PDT) X-Google-Smtp-Source: AKy350a8MTBHjC/qIwESWXsZ9LzMzhJOlkYYVVB5rmNYCq0lquXUKkVeRlJBDOUPbE07MquDXJBP X-Received: by 2002:a17:90b:33cc:b0:237:40a5:7cb9 with SMTP id lk12-20020a17090b33cc00b0023740a57cb9mr10020737pjb.5.1680764704234; Thu, 06 Apr 2023 00:05:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680764704; cv=none; d=google.com; s=arc-20160816; b=O+F+hj8bSfpXD7UhRWm/fa3JxZtm+lkeIcw5lHyloxJlMSTHUV7X52V4hu40eiNnna pbtSyNGiGr3a4kovGSQzdFYyVMOz4nw3rtoLWuMVkjggFkH4/upNp99JGmpg3/XIC9ik rZ5hWI4jDGZRytct1xdi9bbVOfXFwxWmAHKPe7remqZtN+fAC6IdQi9TOR11gXBUSTCT O4MrPcVA5MYOE/D2Kix3g08RdRo74rvuX5JI412E/X148Ye0deKdYkow64iSrz5lGU9D 6ewLJCxIfMTV4UB8HKY30d9CkFJJ9JH2o5e0f6w8y/a8j9m3kKjG3OOKQ4J5/4kDINp5 vBeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=MJTnvT4dZT7GqFxblF5CDsTiIHcOdefKF4YqXGgrW7g=; b=bZC8/2/YtYKGjdoOZdgNiKqeSOhYspiBUrkFbnc2d2JUe/9SAwJIU9RgSziPyHLEzK 89lDk9hnDAI7XFE1+8Jm/8EZT8cLKEZ0xVRRC3qQMW+cXRUtuYKW60Z0ZGyOpIpk9S7k Qy6dnOH8DN3cubqVvn6KR/B53KyTfTnbM0tF9Z/u6Syuz3/0Wz5LjAM/Yzik4go7tlV7 w1ly9ZGIp0azqPAhuOg6zcD1XZmvgErRabvKu++UgNLeiCFI3xRfSIrXWhPIAzMz++r0 k9MV7QQ6oeGc/lzDN+ro1TBn1uki4eBbO2RYZrh1+FwNy1o0C7jCAMXAEHZyWQmCmjbM JKfA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=nQswFuCK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Co-developed-by: Praveenkumar I Signed-off-by: Praveenkumar I Signed-off-by: Devi Priya Reviewed-by: Konrad Dybcio --- Changes in V3: - Moved rpm_msg_ram node under /soc and updated the node name to sram@ - Moved rpm-glink node such that the nodes are sorted alphabetically arch/arm64/boot/dts/qcom/ipq9574.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 7c820463a79d..1f9b7529e7ed 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -110,12 +110,29 @@ }; }; + rpm-glink { + compatible = "qcom,glink-rpm"; + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-ipq9574"; + qcom,glink-channels = "rpm_requests"; + }; + }; + soc: soc@0 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + rpm_msg_ram: sram@60000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x00060000 0x6000>; + }; + pcie0_phy: phy@84000 { compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy"; reg = <0x00084000 0x1000>; From patchwork Thu Apr 6 07:00:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Devi Priya X-Patchwork-Id: 80105 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp832469vqo; Thu, 6 Apr 2023 00:16:38 -0700 (PDT) X-Google-Smtp-Source: AKy350YvFmxprUHO1PCFECpFQwg/PYCMlcSoBHVx4VD/TOyL+52ldSBh9Tvw2arw/axUuosEBAxA X-Received: by 2002:a17:907:da7:b0:933:422b:5f5d with SMTP id go39-20020a1709070da700b00933422b5f5dmr7396673ejc.18.1680765397902; Thu, 06 Apr 2023 00:16:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680765397; cv=none; d=google.com; s=arc-20160816; b=rYm1/A2XYpyuLdk6yTQFs4r3Hw6OcE6dZo2dXTYb+ckNPotNBx74+WEt3KY0xrTo3z 0NIYOf0VuOQmhOsZu/GST57GW8ZhAUU6Z9aWhY9yCew8h/Dde4zQLaKvO+VO6lqCi8Bc fvNxP6TC/uVNDzqF+qezoWYbPukI9jj6Qi7vBUADnGjVlAjRsPp20xl1E+Qx9HhKJjSO 0bkinZCKKDjX85EDQ1u3sLLwDU2FrBxZVQBf6PQZMoRIycbtzxKfpcKcvJPPUg8pkUU+ ofomBgDdm7DtvKc2Lw90J58QhaURIl0Xc+Q1GQApsqJ6MvBw7rcGHrCR/0SqGxVqge3t OVIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=t1I9rMZoWjCxLic+tlwDsH+JR1T/SjScAlj7YtP+Pqo=; b=w3KYL2qd18ZI4WMJ2jRnZaw6zwtqLA3vQHtOtLIMiOLP3AcUby39/0Go+4QES8/34l w+IpMJx+YtwFlbEqH2zKRCzPqZxc4MU2VIWpgnPs8pzHG6oWDxuOe92u2JXDoKAlx15R +ftsfRxoABnU9hBLcg65LtV0+Hzd0wqK5curvs4i2uNsuVGkfEKEwdQh1Pb5mgG8uiPO V9aU+lhsHKUu4XUBQRBznEF+1M7YyFhHSaidzhU30PgZlLTqW5ycy2v/0+suwzspILWP Fg+qaUgFNuPBSYT7z2SUjJMnamA+DkhDHJJ1yRQ3mg9OOX9V9oI0UxmjNB0Pnzi6zL7p e6kQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=ojIR187K; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Co-developed-by: Praveenkumar I Signed-off-by: Praveenkumar I Signed-off-by: Devi Priya --- Changes in V3: - Updated the regulator-min-microvolt with the SVS voltage 725000uV arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts index 3ae38cf327ea..06f579b1c590 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts @@ -44,6 +44,25 @@ }; }; +&rpm_requests { + regulators { + compatible = "qcom,rpm-mp5496-regulators"; + + ipq9574_s1: s1 { + /* + * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders. + * During regulator registration, kernel not knowing the initial voltage, + * considers it as zero and brings up the regulators with minimum supported voltage. + * Updating the regulator-min-microvolt with SVS voltage of 725000uV so that + * the regulators are brought up with 725000uV which is sufficient for all the + * corner parts to operate at 800MHz + */ + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1075000>; + }; + }; +}; + &pcie1_phy { status = "okay"; }; From patchwork Thu Apr 6 07:00:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Devi Priya X-Patchwork-Id: 80107 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp833728vqo; Thu, 6 Apr 2023 00:19:50 -0700 (PDT) X-Google-Smtp-Source: AKy350Z39u1vHEUjuIM7IHHG+nraH6FQ4nPVi2g3OUYGJ7Pfo+Fi2BSpV2Oh/pCX0pxb51Ae9nBd X-Received: by 2002:a05:6a20:b71b:b0:de:5c1a:d0e9 with SMTP id fg27-20020a056a20b71b00b000de5c1ad0e9mr2286327pzb.15.1680765589852; Thu, 06 Apr 2023 00:19:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680765589; cv=none; d=google.com; s=arc-20160816; b=t/hfkMHimmCw/LcnZ8axvikOS/gzavw/E/TkI1kIo7vurv9ljDcK/FOVh+9gB7AcV9 UP5+yaDr0cvG3R/o0uKk5LYMKq55hA1BaHsEIoVb8S3w4vVvquiUH/uWdlne7HLVJ+0N aTM/QeEz7P/05nTDsKKK+eULK3ZhGrumhqDhdezVFYAyg/7a/LFgpq+Sam8c5LqJ5c1C nfmVBIFMzgxRYP/xF3cfU4BUExYkzsrGzqzLpTomSbngM3eNDhReQulG7D8nTQO4yhqI /bvGPRIdRmMYPIm0IDxLogDg1lkfszvH6QgApaZqQFvxZHr/C6C8oMbSM3SFkI5lMBg9 xgIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=c5n0Io+nI3jAJhMEhIDADWL55PCDRw/hMJE8Y3nCFpg=; b=gvNvnk1D8nNzmzwI4q3ZXWDi2k0Up+y8cvUYBtBo6wYokWWQ8pjXXUjteMyEx2H0su aMFLl4KPhTrmnT8QariSKQy4MnJisBq3SaTwgeulBR8iDVLTphXReGYauiJdb/teXbjn j8RyAtfvTsZv1whWAMC6byzfp8i6JxiGs9id9ZiRXRKsWpQMlM3iCiK8ddlVRxl12LTc gzFthrz6AZLhh9JIukZClzYa/E6Q7PvAWiYzQZDYus3p/QvjfEUV5RL2p3XCq26wGQmp 2OfJOJNz3tK3nXgs9STddwyvdvtxxzlyMB5qsXqh71eHYGZJw/5U1IuivwE8YLhOwMT6 awAg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=DaDCCSJ4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Co-developed-by: Praveenkumar I Signed-off-by: Praveenkumar I Signed-off-by: Devi Priya Reviewed-by: Konrad Dybcio --- Changes in V3: - No change arch/arm64/boot/dts/qcom/ipq9574.dtsi | 58 +++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 1f9b7529e7ed..cfef87b5fd22 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -6,6 +6,7 @@ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ +#include #include #include #include @@ -37,6 +38,10 @@ reg = <0x0>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq9574_s1>; }; CPU1: cpu@1 { @@ -45,6 +50,10 @@ reg = <0x1>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq9574_s1>; }; CPU2: cpu@2 { @@ -53,6 +62,10 @@ reg = <0x2>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq9574_s1>; }; CPU3: cpu@3 { @@ -61,6 +74,10 @@ reg = <0x3>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq9574_s1>; }; L2_0: l2-cache { @@ -75,6 +92,47 @@ reg = <0x0 0x40000000 0x0 0x0>; }; + cpu_opp_table: opp-table-cpu { + compatible = "operating-points-v2"; + opp-shared; + + opp-936000000 { + opp-hz = /bits/ 64 <936000000>; + opp-microvolt = <725000>; + clock-latency-ns = <200000>; + }; + + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <787500>; + clock-latency-ns = <200000>; + }; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <862500>; + clock-latency-ns = <200000>; + }; + + opp-1488000000 { + opp-hz = /bits/ 64 <1488000000>; + opp-microvolt = <925000>; + clock-latency-ns = <200000>; + }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <987500>; + clock-latency-ns = <200000>; + }; + + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <1062500>; + clock-latency-ns = <200000>; + }; + }; + firmware { scm { compatible = "qcom,scm-ipq9574", "qcom,scm";