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Wed, 05 Apr 2023 14:02:59 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, jeffreyalaw@gmail.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, Patrick O'Neill Subject: [PATCH v2 1/8] RISCV: Eliminate SYNC memory models Date: Wed, 5 Apr 2023 14:01:11 -0700 Message-Id: <20230405210118.1969283-2-patrick@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230405210118.1969283-1-patrick@rivosinc.com> References: <20220407182918.294892-1-patrick@rivosinc.com> <20230405210118.1969283-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762371753488530894?= X-GMAIL-MSGID: =?utf-8?q?1762371753488530894?= Remove references to MEMMODEL_SYNC_* models by converting via memmodel_base(). 2023-04-05 Patrick O'Neill * atomic.c: Remove MEMMODEL_SYNC_* cases and sanitize memmodel input with memmodel_base Signed-off-by: Patrick O'Neill --- gcc/config/riscv/riscv.cc | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 76eee4a55e9..8f5636c93ed 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4288,14 +4288,11 @@ riscv_memmodel_needs_amo_acquire (enum memmodel model) { case MEMMODEL_ACQ_REL: case MEMMODEL_SEQ_CST: - case MEMMODEL_SYNC_SEQ_CST: case MEMMODEL_ACQUIRE: case MEMMODEL_CONSUME: - case MEMMODEL_SYNC_ACQUIRE: return true; case MEMMODEL_RELEASE: - case MEMMODEL_SYNC_RELEASE: case MEMMODEL_RELAXED: return false; @@ -4314,14 +4311,11 @@ riscv_memmodel_needs_release_fence (enum memmodel model) { case MEMMODEL_ACQ_REL: case MEMMODEL_SEQ_CST: - case MEMMODEL_SYNC_SEQ_CST: case MEMMODEL_RELEASE: - case MEMMODEL_SYNC_RELEASE: return true; case MEMMODEL_ACQUIRE: case MEMMODEL_CONSUME: - case MEMMODEL_SYNC_ACQUIRE: case MEMMODEL_RELAXED: return false; @@ -4360,6 +4354,7 @@ riscv_print_operand (FILE *file, rtx op, int letter) } machine_mode mode = GET_MODE (op); enum rtx_code code = GET_CODE (op); + const enum memmodel model = memmodel_base (INTVAL (op)); switch (letter) { @@ -4497,12 +4492,12 @@ riscv_print_operand (FILE *file, rtx op, int letter) break; case 'A': - if (riscv_memmodel_needs_amo_acquire ((enum memmodel) INTVAL (op))) + if (riscv_memmodel_needs_amo_acquire (model)) fputs (".aq", file); break; case 'F': - if (riscv_memmodel_needs_release_fence ((enum memmodel) INTVAL (op))) + if (riscv_memmodel_needs_release_fence (model)) fputs ("fence iorw,ow; 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Wed, 05 Apr 2023 14:03:01 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, jeffreyalaw@gmail.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, Patrick O'Neill Subject: [PATCH v2 2/8] RISCV: Enforce Libatomic LR/SC SEQ_CST Date: Wed, 5 Apr 2023 14:01:12 -0700 Message-Id: <20230405210118.1969283-3-patrick@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230405210118.1969283-1-patrick@rivosinc.com> References: <20220407182918.294892-1-patrick@rivosinc.com> <20230405210118.1969283-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762371993405256455?= X-GMAIL-MSGID: =?utf-8?q?1762371993405256455?= Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs recommended by table A.6 of the ISA manual. 2023-04-05 Patrick O'Neill * atomic.c: Change LR.aq/SC.rl pairs into sequentially consistent LR.aqrl/SC.rl pair. Signed-off-by: Patrick O'Neill --- libgcc/config/riscv/atomic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libgcc/config/riscv/atomic.c b/libgcc/config/riscv/atomic.c index 69f53623509..5f895939b0b 100644 --- a/libgcc/config/riscv/atomic.c +++ b/libgcc/config/riscv/atomic.c @@ -39,7 +39,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see unsigned old, tmp1, tmp2; \ \ asm volatile ("1:\n\t" \ - "lr.w.aq %[old], %[mem]\n\t" \ + "lr.w.aqrl %[old], %[mem]\n\t" \ #insn " %[tmp1], %[old], %[value]\n\t" \ invert \ "and %[tmp1], %[tmp1], %[mask]\n\t" \ @@ -73,7 +73,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see unsigned old, tmp1; \ \ asm volatile ("1:\n\t" \ - "lr.w.aq %[old], %[mem]\n\t" \ + "lr.w.aqrl %[old], %[mem]\n\t" \ "and %[tmp1], %[old], %[mask]\n\t" \ "bne %[tmp1], %[o], 1f\n\t" \ "and %[tmp1], %[old], %[not_mask]\n\t" \ From patchwork Wed Apr 5 21:01:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 79951 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6358:3d4a:b0:114:e959:cc0c with SMTP id b10csp621171rwc; Wed, 5 Apr 2023 14:09:56 -0700 (PDT) X-Google-Smtp-Source: AKy350ZwTHUeXBplvQnflJAB/wozrpd4E2HWJBNjoDz7RH2Wpc+zqp6/RIO8lzVfBfuPalcZgHXb X-Received: by 2002:a17:906:fa9b:b0:945:d94e:7054 with SMTP id lt27-20020a170906fa9b00b00945d94e7054mr5001581ejb.36.1680728995910; Wed, 05 Apr 2023 14:09:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680728995; cv=none; d=google.com; s=arc-20160816; b=JPDWg0IpmkPgffhf3Bq7/byjHsutQzVgSziGGIllMhQbCUfigjlQ4ReMDb+PbQqRec 00Nag3A3HS4iWZqgYPIv5uOpVz4lIYeY0JA5wIuk5Oe4o6kxpbiExzpXirEzftiO43tJ JaHCHFLc4VdCUbG3IZsw/dTZA2JE4aiLMLSU+jGY9bg2syYNo16Ddt5wMLMnQBKXJtuN ZnSPkVOKeLNuiFPGphb4Ytpev8lAF8g0oPoZ2SIid/JPilocP4/36bxdE9oFruy4gsVX kPDX9ns38ak6x60QndTIwIWudpemuIoKdcbOLDquDXmVs2TKOfv8cKnzW3nZhvuEE8jF PjcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=eRsKergMzYC6tajGopght9zcZxmMjs6Z05dcXlbHICg=; b=i8MxSynCzZVq036mbXkCOjWkFqd6k+r31c6Lcb9ijCFDrzrt31Ft/cA9C2fg1PqMEQ a6wNEDoZukMLp6MHl48uwiOfmeUVzSLFRnXw0IJh+YYUgAtxqAgvdaeEMJbsbkfYYwa8 WhiLOXlvcM1StN/Xjuyqu7Tsm1QVYUcjjssV/pHRjgWgJb+fe1mglebMFhWJJEW4UnhX hPMlaO2gqCOWS743aDt1uqwewUP7IuyqGBBGr5ZPvj4drXqlT6n5H2OTJYVfM/ZZOtBF IyjWvgxNfDrJgb1wzCus/JLvhU3lw+pvdjpSfkTwZnlRWTWU++qxqa2DDno2VL/mAG3M vbPg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20210112.gappssmtp.com header.s=20210112 header.b=wXxplG6f; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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Replace Fence/LR.aq/SC.aq pairs with strong SEQ_CST LR.aqrl/SC.rl pairs recommended by table A.6 of the ISA manual. 2023-04-05 Patrick O'Neill * sync.md: Change FENCE/LR.aq/SC.aq into sequentially consistent LR.aqrl/SC.rl pair. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/sync.md | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index c932ef87b9d..de42245981b 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -115,9 +115,16 @@ UNSPEC_COMPARE_AND_SWAP)) (clobber (match_scratch:GPR 6 "=&r"))] "TARGET_ATOMIC" - "%F5 1: lr.%A5 %0,%1; bne %0,%z2,1f; sc.%A4 %6,%z3,%1; bnez %6,1b; 1:" + { + return "1:\;" + "lr..aqrl\t%0,%1\;" + "bne\t%0,%z2,1f\;" + "sc..rl\t%6,%z3,%1\;" + "bnez\t%6,1b\;" + "1:"; + } [(set_attr "type" "atomic") - (set (attr "length") (const_int 20))]) + (set (attr "length") (const_int 16))]) (define_expand "atomic_compare_and_swap" [(match_operand:SI 0 "register_operand" "") ;; bool output From patchwork Wed Apr 5 21:01:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 79942 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp589238vqo; Wed, 5 Apr 2023 14:05:12 -0700 (PDT) X-Google-Smtp-Source: AKy350ZxoJUCYNhBi7NzvZUN/JeAEXitXpAkLlw6AQkXxJPGkaUFcqTIZLDZr3fS8+gZ0sdjDqZP X-Received: by 2002:a17:907:7ea9:b0:92b:e1ff:be30 with SMTP id qb41-20020a1709077ea900b0092be1ffbe30mr5611954ejc.4.1680728712631; Wed, 05 Apr 2023 14:05:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680728712; cv=none; d=google.com; s=arc-20160816; b=oEWzkSLDUoPv804SiLRUwZ9HX/eXQoRiyma0ri5ZN2mqzaij1zvPFxsVtJJwtslFIA kkxTaVy/rAsTL48pQY6K1OXTkQu2rg2B0Di6D4d3Upem0uh+cJiqdHgklHcUHAgzlCkk GyvXR0xx3kW4VGj641/nD1NH9KsSM1HdiG+kmSmiabHeHt2u5H6XbwsMiqOFeRNzMURI 4Nk5zLY9I9LASCmOHtioN0HOHfQkAfhzdZxlBSNW2hNj1HAKDy8hpR43jP3IP1fni4O4 zzbF2cE/ONwzCGa7nM0lGkF7m0OYF47ClVd0yizl6tGPJtKqksOR34ugqYmDsivhZoi5 Apkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=6ywSxDa6+bAZuEdeq9xREaPCG8lxpH/KGb1u4BvZgkw=; b=ltmbujK2V9faUkWxpkaTd2zF89kx34cCvEwlxdH4cJO0mP3AxkpwN7wVJo2uvjZ4Qk ls6QHzuqnanNEmYuWHwWqIwkVHA+OJjrWjHoUssZo9nBMivZdjOOjym1JxJ1ZC0SFxZL xzM5f+W+ALyPCyZoedkKTM8btMym/PaUUqzjocQLvlefmqX8SUZjP13mQds1Rfnde62V Aki3U919YixMJghkminxXj7gZ8oa+EkX4vWDQGO0QlTUtU3v76j2qTFX41GE0xjTl66y JJIci3sEQqq1D6p8b5rmPRePTtBNFjH0j4QLxkOPOlM+X8ZoR+O1LnD/GAtULwoFlewZ In7g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20210112.gappssmtp.com header.s=20210112 header.b=BLIcGxCm; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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Wed, 05 Apr 2023 14:03:03 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, jeffreyalaw@gmail.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, Patrick O'Neill Subject: [PATCH v2 4/8] RISCV: Add AMO release bits Date: Wed, 5 Apr 2023 14:01:14 -0700 Message-Id: <20230405210118.1969283-5-patrick@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230405210118.1969283-1-patrick@rivosinc.com> References: <20220407182918.294892-1-patrick@rivosinc.com> <20230405210118.1969283-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762371790427566438?= X-GMAIL-MSGID: =?utf-8?q?1762371790427566438?= This patch sets the relevant .rl bits on amo operations. 2023-04-05 Patrick O'Neill * riscv.cc (riscv_print_operand): change behavior of %A to include release bits. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/riscv.cc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 8f5636c93ed..8ffee494fbe 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4492,8 +4492,13 @@ riscv_print_operand (FILE *file, rtx op, int letter) break; case 'A': - if (riscv_memmodel_needs_amo_acquire (model)) + if (riscv_memmodel_needs_amo_acquire (model) && + riscv_memmodel_needs_release_fence (model)) + fputs (".aqrl", file); + else if (riscv_memmodel_needs_amo_acquire (model)) fputs (".aq", file); + else if (riscv_memmodel_needs_release_fence (model)) + fputs (".rl", file); break; case 'F': From patchwork Wed Apr 5 21:01:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 79944 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp590113vqo; Wed, 5 Apr 2023 14:06:40 -0700 (PDT) X-Google-Smtp-Source: AKy350ZsQzvX+0eGUX471bABgaa2dgPDLD9pgDEt4OMdmMuR7aAm3yli9JUJaCCIeO2srXO9EP2n X-Received: by 2002:a05:6402:3445:b0:4fa:7679:d44a with SMTP id l5-20020a056402344500b004fa7679d44amr2717767edc.11.1680728800378; Wed, 05 Apr 2023 14:06:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680728800; cv=none; d=google.com; s=arc-20160816; b=o6Tb1rZHfRu+ek4XNmWmRD0GRPDBJesiTuy2HDWJZSSPL6HgiVfDMzSK2HD0nm1Jxs I6T2NXVKNunOYBcTB2zDAlnIYtr4tYYHEjoA6dksbnJXPSMnmOzjudAF7NSrA9q2g7Gz NhDLraMm8WqYs59mkrzwS1KvN+XptUDclXlnpVkyiMIEslOtzvKphQnFp8r+bclPsiRu O9qeoi9/qnMOG+dSvdCvt9sWqG6VArpkE0CteGWsseyjB5Vy91PitK3NHnypiY0nyYby QGu0cPA62odEC0GOSJ4c/s1GcUcg6NbmQFvtenA1ARqI3sE3mbM8JW7nTMzTqwx9DLNW YqyQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=F2bBVJ77D9HA2dPUKZN1EC2GSdfzAA+eOkhFHj2yXzM=; b=m8ExqjvyeThTmSBjL+7Tn/ShYdiS+2ToGCEvQrwzzGSS0YAXhDWNfCbmP/sHb/glSv wcwlx4PU03pkqdPcLlAaCgmUiD+1ahWX2vx1Q7oefdoQv3gg5A3YTLYgql4ra001B8v+ gsIPA+guRvx0LRzPdFgPogBVPkMeJEUbCuk8abtv4PBjg5I6LXM0WdZEmN4+aKlSQjmO N/Qn3BYXX/eTutY36HzRPpeZ1G/BJyQZ+9jyvtCx224R1aK3bd7rObq7drtGVg29l+Gk Crw+775cmDqdhGZygdVNYMAwUFhhmx+vEXCtzqSGDgK0abxRbP19mSt5wV/9fEeG8Ti7 i3xA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20210112.gappssmtp.com header.s=20210112 header.b=jXH9fenn; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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Remove unnecessary release fences from atomic ops. This change brings AMO ops in line with table A.6 of the ISA manual. 2023-04-05 Patrick O'Neill * riscv.cc (riscv_memmodel_needs_amo_acquire): Change function name. * riscv.cc (riscv_print_operand): Remove unneeded %F case. * sync.md: Remove unneeded fences. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/riscv.cc | 16 +++++----------- gcc/config/riscv/sync.md | 16 ++++++++-------- 2 files changed, 13 insertions(+), 19 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 8ffee494fbe..6576e9ae524 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4301,11 +4301,11 @@ riscv_memmodel_needs_amo_acquire (enum memmodel model) } } -/* Return true if a FENCE should be emitted to before a memory access to - implement the release portion of memory model MODEL. */ +/* Return true if the .RL suffix should be added to an AMO to implement the + release portion of memory model MODEL. */ static bool -riscv_memmodel_needs_release_fence (enum memmodel model) +riscv_memmodel_needs_amo_release (enum memmodel model) { switch (model) { @@ -4331,7 +4331,6 @@ riscv_memmodel_needs_release_fence (enum memmodel model) 'R' Print the low-part relocation associated with OP. 'C' Print the integer branch condition for comparison OP. 'A' Print the atomic operation suffix for memory model OP. - 'F' Print a FENCE if the memory model requires a release. 'z' Print x0 if OP is zero, otherwise print OP normally. 'i' Print i if the operand is not a register. 'S' Print shift-index of single-bit mask OP. @@ -4493,19 +4492,14 @@ riscv_print_operand (FILE *file, rtx op, int letter) case 'A': if (riscv_memmodel_needs_amo_acquire (model) && - riscv_memmodel_needs_release_fence (model)) + riscv_memmodel_needs_amo_release (model)) fputs (".aqrl", file); else if (riscv_memmodel_needs_amo_acquire (model)) fputs (".aq", file); - else if (riscv_memmodel_needs_release_fence (model)) + else if (riscv_memmodel_needs_amo_release (model)) fputs (".rl", file); break; - case 'F': - if (riscv_memmodel_needs_release_fence (model)) - fputs ("fence iorw,ow; ", file); - break; - case 'i': if (code != REG) fputs ("i", file); diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index de42245981b..1aa9ac81cee 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -61,9 +61,9 @@ (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_ATOMIC_STORE))] "TARGET_ATOMIC" - "%F2amoswap.%A2 zero,%z1,%0" + "amoswap.%A2 zero,%z1,%0" [(set_attr "type" "atomic") - (set (attr "length") (const_int 8))]) + (set (attr "length") (const_int 4))]) (define_insn "atomic_" [(set (match_operand:GPR 0 "memory_operand" "+A") @@ -73,9 +73,9 @@ (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] "TARGET_ATOMIC" - "%F2amo.%A2 zero,%z1,%0" + "amo.%A2 zero,%z1,%0" [(set_attr "type" "atomic") - (set (attr "length") (const_int 8))]) + (set (attr "length") (const_int 4))]) (define_insn "atomic_fetch_" [(set (match_operand:GPR 0 "register_operand" "=&r") @@ -87,9 +87,9 @@ (match_operand:SI 3 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] "TARGET_ATOMIC" - "%F3amo.%A3 %0,%z2,%1" + "amo.%A3 %0,%z2,%1" [(set_attr "type" "atomic") - (set (attr "length") (const_int 8))]) + (set (attr "length") (const_int 4))]) (define_insn "atomic_exchange" [(set (match_operand:GPR 0 "register_operand" "=&r") @@ -100,9 +100,9 @@ (set (match_dup 1) (match_operand:GPR 2 "register_operand" "0"))] "TARGET_ATOMIC" - "%F3amoswap.%A3 %0,%z2,%1" + "amoswap.%A3 %0,%z2,%1" [(set_attr "type" "atomic") - (set (attr "length") (const_int 8))]) + (set (attr "length") (const_int 4))]) (define_insn "atomic_cas_value_strong" [(set (match_operand:GPR 0 "register_operand" "=&r") From patchwork Wed Apr 5 21:01:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 79945 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp590263vqo; Wed, 5 Apr 2023 14:06:57 -0700 (PDT) X-Google-Smtp-Source: AKy350Y5zsVriOIGIq/D4kyrXljh5GKhWLXXXCLEt3YCrpp+6kzGVMadnVxqUINsi2tUvCoZ22vw X-Received: by 2002:a17:906:4913:b0:93b:1cc5:4a1 with SMTP id b19-20020a170906491300b0093b1cc504a1mr4724320ejq.40.1680728817231; Wed, 05 Apr 2023 14:06:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680728817; cv=none; d=google.com; s=arc-20160816; b=sQPyhbAv3CJJnRBqNWGfYNe+6kg+INUDPC8KexSYjwj6FOxndj2F3BpE2lUjjjEB6Z 0FNuxnR6FtyY5DZqDnu+RSo4lw1OQQeZpgkA6p3oOrCc6Z+cP4NXGOklrGILcZDFf20L OQcikgFeUaQAIXlrK59dhQmNG7YdeEUIQhNdG/BuTYagbE7BQoDyfMSfQAmfr53tZPfG PTRLt9+bO/0OJlnxaWLRQw1UqJxjn/2Yb7+ciaJTkDVpk20ePhqIp68dLzkdCxMtuyHl R2etw1OZA7woN7sR4faSQB5tbD84BrEN/YfzboWTIK09it0Izy23hAP9sFIfScoqDBOi AdKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=I4Iv5OutDi8fQJpm4qflbaDO8Ma4+rSn9CJxchqX1Tk=; b=R/rgm7vm9R9wY8xMHdzfeHGt2rGpJ/d3nf4GlBtr59Rd6gWJBBUM6bafN/gRNI3j/l TwpOSxNHpFWLCA8kDioI6YJyac6gGmgwOqO9HCNldyXnpTKqphv1qf0h8C51LGgT/j6g +Zjpk7+m24F49eQmo1vK1Iri7m3EZz0Ff4eySHFjS5ide0UZ2mw1dKsyNLI+Wf+WJus1 Ll0T1pho+O7JNLXQDaW68OwNhvSI/9PfAgSBYSSyxccPsugCIzQ/R9gPebPcElPm972f SGOWxV+3sdYi7T9haWsdN8ubUSvBPRXJrOBFTTJfBLhmeIQPthzYjO8mqUJNNFWxpsRo ButQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20210112.gappssmtp.com header.s=20210112 header.b=vTLxFRCJ; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id zm9-20020a170906994900b00930943f134esi2733585ejb.8.2023.04.05.14.06.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Apr 2023 14:06:57 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@rivosinc-com.20210112.gappssmtp.com header.s=20210112 header.b=vTLxFRCJ; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 65E32385B530 for ; Wed, 5 Apr 2023 21:04:10 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pj1-x1041.google.com (mail-pj1-x1041.google.com [IPv6:2607:f8b0:4864:20::1041]) by sourceware.org (Postfix) with ESMTPS id 6F6743857716 for ; Wed, 5 Apr 2023 21:03:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6F6743857716 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pj1-x1041.google.com with SMTP id h12-20020a17090aea8c00b0023d1311fab3so38580506pjz.1 for ; Wed, 05 Apr 2023 14:03:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; t=1680728586; x=1683320586; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=I4Iv5OutDi8fQJpm4qflbaDO8Ma4+rSn9CJxchqX1Tk=; b=vTLxFRCJLmDAEQnq/7asQwzHn0K8RG2ouQWF9wUtfSsAlmQ4H8UGz7Srm6hWjEqxcZ BsFNfgdxo+fZrQxGLGX+wKPeSuSwDx37ebTPPGfsrA3crUt3oTsZHxqhGRFK3JRtUq/W uzeOG9P5l/o6d7AgP7T5CCeL/oEV9FdGNlAK2ffA6exCoq10fBl3wikkctovOu1KXJRz puwMECN5zLcz2YjJR1ANAWJE3IdELDtVC2GIwqBDn0vyBWwf7f7I5T2K8Asj6ADCUprK LcSF5PEU0LmmuhbPrHxFpTr+SH5VIt4pJw+LrZgaMRW4Q+YrLJTluID7M0mijo6xmjpp dSrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680728586; x=1683320586; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=I4Iv5OutDi8fQJpm4qflbaDO8Ma4+rSn9CJxchqX1Tk=; b=Te8euvy4t9LuFtn7dbOInWAmdMKo2CjPnoctQdq21HVH9sBWotVmv6YzZZGc5KBCOJ NMjV5sZwoskClILPfQEtKFSfCJT/9X1A9mXrKAUw9xHFeniNnIr3gRR4AqtegS0iObUC losP9tdyj+16umU4VMla6W/g2HqBaC8BA+rCD/DKp7lzq2u6R8fYhapnFCLawbxBmsyx JrkYvr+VF4F0R7h3WZD7+Cwyw8Hdh3OK2QK6ZfrwVzQRAZyoxSHWFOWelUXO0bzY37OQ BOOy0BsiocGvTR/gWgmfOb2h61GVdakY9L0RSAjSbSvhJ15Z8DE1uoQ6FKxu1zTuyN9g VTBQ== X-Gm-Message-State: AAQBX9d50n7F5JsTzLbVF7DDshvSPjZeBtNVWx1VO4wpmn2aitZIA9c8 XDnvQjodOoauafv9Rxzt0cuA1ZYxhTwU8go5H+k5leQcRHg= X-Received: by 2002:a17:90b:1c01:b0:23d:4b01:b27 with SMTP id oc1-20020a17090b1c0100b0023d4b010b27mr8440461pjb.10.1680728586132; Wed, 05 Apr 2023 14:03:06 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id e6-20020a17090a77c600b002342ccc8280sm1809477pjs.6.2023.04.05.14.03.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Apr 2023 14:03:05 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, jeffreyalaw@gmail.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, Patrick O'Neill Subject: [PATCH v2 6/8] RISCV: Weaken compare_exchange LR/SC pairs Date: Wed, 5 Apr 2023 14:01:16 -0700 Message-Id: <20230405210118.1969283-7-patrick@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230405210118.1969283-1-patrick@rivosinc.com> References: <20220407182918.294892-1-patrick@rivosinc.com> <20230405210118.1969283-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762371900223614578?= X-GMAIL-MSGID: =?utf-8?q?1762371900223614578?= Introduce the %I and %J flags for setting the .aqrl bits on LR/SC pairs as needed. Atomic compare and exchange ops provide success and failure memory models. C++17 and later place no restrictions on the relative strength of each model, so ensure we cover both by using a model that enforces the ordering of both given models. This change brings compare_exchange LR/SC ops in line with table A.6 of the ISA manual. 2023-04-05 Patrick O'Neill * riscv.cc: Add function to get the union of two memmodels in sync.md. * riscv-protos.h: Likewise. * sync.md (atomic_cas_value_strong): Remove static .aqrl bits on SC op/.rl bits on LR op and replace with optimized %I, %J flags. * compare-exchange-atomics-model-1.c: New test. * compare-exchange-atomics-model-2.c: Likewise. * compare-exchange-atomics-model-3.c: Likewise. * compare-exchange-atomics-model-4.c: Likewise. * compare-exchange-atomics-model-5.c: Likewise. * compare-exchange-atomics-model-6.c: Likewise. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/riscv-protos.h | 3 ++ gcc/config/riscv/riscv.cc | 44 +++++++++++++++++++ gcc/config/riscv/sync.md | 9 +++- .../riscv/compare-exchange-atomics-model-1.c | 12 +++++ .../riscv/compare-exchange-atomics-model-2.c | 12 +++++ .../riscv/compare-exchange-atomics-model-3.c | 12 +++++ .../riscv/compare-exchange-atomics-model-4.c | 12 +++++ .../riscv/compare-exchange-atomics-model-5.c | 12 +++++ 8 files changed, 114 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/compare-exchange-atomics-model-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/compare-exchange-atomics-model-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/compare-exchange-atomics-model-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/compare-exchange-atomics-model-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/compare-exchange-atomics-model-5.c diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 4611447ddde..b03edc3e8a5 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -22,6 +22,8 @@ along with GCC; see the file COPYING3. If not see #ifndef GCC_RISCV_PROTOS_H #define GCC_RISCV_PROTOS_H +#include "memmodel.h" + /* Symbol types we understand. The order of this list must match that of the unspec enum in riscv.md, subsequent to UNSPEC_ADDRESS_FIRST. */ enum riscv_symbol_type { @@ -79,6 +81,7 @@ extern void riscv_reinit (void); extern poly_uint64 riscv_regmode_natural_size (machine_mode); extern bool riscv_v_ext_vector_mode_p (machine_mode); extern bool riscv_shamt_matches_mask_p (int, HOST_WIDE_INT); +extern enum memmodel riscv_union_memmodels (enum memmodel, enum memmodel); /* Routines implemented in riscv-c.cc. */ void riscv_cpu_cpp_builtins (cpp_reader *); diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 6576e9ae524..061d2cf42b4 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4278,6 +4278,36 @@ riscv_print_operand_reloc (FILE *file, rtx op, bool hi_reloc) fputc (')', file); } +/* Return the memory model that encapuslates both given models. */ + +enum memmodel +riscv_union_memmodels (enum memmodel model1, enum memmodel model2) +{ + model1 = memmodel_base (model1); + model2 = memmodel_base (model2); + + enum memmodel weaker = model1 <= model2 ? model1: model2; + enum memmodel stronger = model1 > model2 ? model1: model2; + + switch (stronger) + { + case MEMMODEL_SEQ_CST: + case MEMMODEL_ACQ_REL: + return stronger; + case MEMMODEL_RELEASE: + if (weaker == MEMMODEL_ACQUIRE || weaker == MEMMODEL_CONSUME) + return MEMMODEL_ACQ_REL; + else + return stronger; + case MEMMODEL_ACQUIRE: + case MEMMODEL_CONSUME: + case MEMMODEL_RELAXED: + return stronger; + default: + gcc_unreachable (); + } +} + /* Return true if the .AQ suffix should be added to an AMO to implement the acquire portion of memory model MODEL. */ @@ -4331,6 +4361,8 @@ riscv_memmodel_needs_amo_release (enum memmodel model) 'R' Print the low-part relocation associated with OP. 'C' Print the integer branch condition for comparison OP. 'A' Print the atomic operation suffix for memory model OP. + 'I' Print the LR suffix for memory model OP. + 'J' Print the SC suffix for memory model OP. 'z' Print x0 if OP is zero, otherwise print OP normally. 'i' Print i if the operand is not a register. 'S' Print shift-index of single-bit mask OP. @@ -4500,6 +4532,18 @@ riscv_print_operand (FILE *file, rtx op, int letter) fputs (".rl", file); break; + case 'I': + if (model == MEMMODEL_SEQ_CST) + fputs (".aqrl", file); + else if (riscv_memmodel_needs_amo_acquire (model)) + fputs (".aq", file); + break; + + case 'J': + if (riscv_memmodel_needs_amo_release (model)) + fputs (".rl", file); + break; + case 'i': if (code != REG) fputs ("i", file); diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 1aa9ac81cee..b1a12545a19 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -116,10 +116,15 @@ (clobber (match_scratch:GPR 6 "=&r"))] "TARGET_ATOMIC" { + enum memmodel model_success = (enum memmodel) INTVAL(operands[4]); + enum memmodel model_failure = (enum memmodel) INTVAL(operands[5]); + /* Find the union of the two memory models so we can satisfy both success + and failure memory models. */ + operands[5] = GEN_INT(riscv_union_memmodels(model_success, model_failure)); return "1:\;" - "lr..aqrl\t%0,%1\;" + "lr.%I5\t%0,%1\;" "bne\t%0,%z2,1f\;" - "sc..rl\t%6,%z3,%1\;" + "sc.%J5\t%6,%z3,%1\;" "bnez\t%6,1b\;" "1:"; } diff --git a/gcc/testsuite/gcc.target/riscv/compare-exchange-atomics-model-1.c b/gcc/testsuite/gcc.target/riscv/compare-exchange-atomics-model-1.c new file mode 100644 index 00000000000..a2c3fc7a1b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/compare-exchange-atomics-model-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* Verify that appropriate bits are placed per memory model. */ +/* { dg-final { scan-assembler-not "lr.w.aq" } } */ +/* { dg-final { scan-assembler-not "lr.w.rl" } } */ +/* { dg-final { scan-assembler-not "sc.w.aq" } } */ +/* { dg-final { scan-assembler-not "sc.w.rl" } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_RELAXED, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/compare-exchange-atomics-model-2.c b/gcc/testsuite/gcc.target/riscv/compare-exchange-atomics-model-2.c new file mode 100644 index 00000000000..d23d4db945f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/compare-exchange-atomics-model-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* Verify that appropriate bits are placed per memory model. */ +/* { dg-final { scan-assembler "lr.w.aq" } } */ +/* { dg-final { scan-assembler-not "lr.w.rl" } } */ +/* { dg-final { scan-assembler-not "sc.w.aq" } } */ +/* { dg-final { scan-assembler-not "sc.w.rl" } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_CONSUME, __ATOMIC_CONSUME); +} diff --git a/gcc/testsuite/gcc.target/riscv/compare-exchange-atomics-model-3.c b/gcc/testsuite/gcc.target/riscv/compare-exchange-atomics-model-3.c new file mode 100644 index 00000000000..7379825c6f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/compare-exchange-atomics-model-3.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* Verify that appropriate bits are placed per memory model. */ +/* { dg-final { scan-assembler "lr.w.aq" } } */ +/* { dg-final { scan-assembler-not "lr.w.rl" } } */ +/* { dg-final { scan-assembler-not "sc.w.aq" } } */ +/* { dg-final { scan-assembler-not "sc.w.rl" } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/riscv/compare-exchange-atomics-model-4.c b/gcc/testsuite/gcc.target/riscv/compare-exchange-atomics-model-4.c new file mode 100644 index 00000000000..80ab9889288 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/compare-exchange-atomics-model-4.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* Verify that appropriate bits are placed per memory model. */ +/* { dg-final { scan-assembler "lr.w.aqrl" } } */ +/* { dg-final { scan-assembler "sc.w.rl" } } */ +/* { dg-final { scan-assembler-not "lr.w.rl" } } */ +/* { dg-final { scan-assembler-not "sc.w.aq" } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); +} diff --git a/gcc/testsuite/gcc.target/riscv/compare-exchange-atomics-model-5.c b/gcc/testsuite/gcc.target/riscv/compare-exchange-atomics-model-5.c new file mode 100644 index 00000000000..da905242317 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/compare-exchange-atomics-model-5.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* Verify that appropriate bits are placed per memory model. */ +/* { dg-final { scan-assembler "lr.w.aq" } } */ +/* { dg-final { scan-assembler "sc.w.rl" } } */ +/* { dg-final { scan-assembler-not "lr.w.rl" } } */ +/* { dg-final { scan-assembler-not "sc.w.aq" } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_RELEASE, __ATOMIC_ACQUIRE); +} From patchwork Wed Apr 5 21:01:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 79952 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6358:3d4a:b0:114:e959:cc0c with SMTP id b10csp621866rwc; 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Wed, 05 Apr 2023 14:03:07 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, jeffreyalaw@gmail.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, Patrick O'Neill Subject: [PATCH v2 7/8] RISCV: Weaken atomic stores Date: Wed, 5 Apr 2023 14:01:17 -0700 Message-Id: <20230405210118.1969283-8-patrick@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230405210118.1969283-1-patrick@rivosinc.com> References: <20220407182918.294892-1-patrick@rivosinc.com> <20230405210118.1969283-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762372181166795756?= X-GMAIL-MSGID: =?utf-8?q?1762372181166795756?= This change brings atomic stores in line with table A.6 of the ISA manual. 2023-04-05 Patrick O'Neill PR target/89835 * sync.md (atomic_store): Use simple store instruction in combination with a fence. * pr89835.c: New test. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/sync.md | 17 ++++++++++++----- gcc/testsuite/gcc.target/riscv/pr89835.c | 9 +++++++++ 2 files changed, 21 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/pr89835.c diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index b1a12545a19..cdd227721e1 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -53,17 +53,24 @@ ;; Atomic memory operations. -;; Implement atomic stores with amoswap. Fall back to fences for atomic loads. +;; Implement atomic stores with a leading fence. Fall back to fences for atomic loads. (define_insn "atomic_store" [(set (match_operand:GPR 0 "memory_operand" "=A") (unspec_volatile:GPR [(match_operand:GPR 1 "reg_or_0_operand" "rJ") (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_ATOMIC_STORE))] - "TARGET_ATOMIC" - "amoswap.%A2 zero,%z1,%0" - [(set_attr "type" "atomic") - (set (attr "length") (const_int 4))]) + "" + { + enum memmodel model = (enum memmodel) INTVAL (operands[2]); + model = memmodel_base (model); + if (model == MEMMODEL_SEQ_CST || model == MEMMODEL_RELEASE) + return "fence\tr,rw\;" + "s\t%z1,%0"; + else + return "s\t%z1,%0\;"; + } + [(set (attr "length") (const_int 8))]) (define_insn "atomic_" [(set (match_operand:GPR 0 "memory_operand" "+A") diff --git a/gcc/testsuite/gcc.target/riscv/pr89835.c b/gcc/testsuite/gcc.target/riscv/pr89835.c new file mode 100644 index 00000000000..ab190e11b60 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr89835.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* Verify that relaxed atomic stores use simple store instuctions. */ +/* { dg-final { scan-assembler-not "amoswap" } } */ + +void +foo(int bar, int baz) +{ + __atomic_store_n(&bar, baz, __ATOMIC_RELAXED); +} From patchwork Wed Apr 5 21:01:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 79953 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6358:3d4a:b0:114:e959:cc0c with SMTP id b10csp622486rwc; Wed, 5 Apr 2023 14:12:53 -0700 (PDT) X-Google-Smtp-Source: AKy350a2O8rqcnaaDPQjkfDe6UsinjxpQOwWy9MC42HwxtZNg2Cr6RquwEnfJvaeiMvhv5BQwgX0 X-Received: by 2002:aa7:d752:0:b0:502:aaca:a119 with SMTP id a18-20020aa7d752000000b00502aacaa119mr3164112eds.10.1680729173602; Wed, 05 Apr 2023 14:12:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680729173; cv=none; d=google.com; s=arc-20160816; b=IeB0drLLuhdpchut7zykar0opOdq8vuAqHs5JB0IAT79YZmbYtlChikN4jQZFdNlw4 uG6YPCJ7reJ32FB+YdEwKyzjU7x9nERQcLjaWSNMC4iKLSw/C3kR+lnQcLjbHoylpoUY wR2TZpPgoDEbcA7HFHcU2tY8md33Eo4oCcPr/ztrFR1nrCrIQS8r3087AC9C+Vohrrvx wwfUxT1wMbtLdyon55bEMo2/VutITywCJJikvdSkk/017WmnikH0IYEIi6VNYahUrjEU PDVaDgybYfBfiW7MbLRexpofUfoCVbQ5WEUvL1kVKnjrDDwIVh5+YswWfA5cBG92McG2 kRoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=pcNYn56UjLOYIUhjeLtRwQBit+o1zbjbdDRd9Ok0HAE=; b=ygNSTxqvlwBhdKGHnR0ewuwHZGSir6KaevkcS/NXkKecHfpzaG9EeuafE0z+kanUxF Urv3o+CHmkSU703XGSOwpy72XDvVufHquSAkRJODE8z9YKzK2OiM+iHxjb5cPVNNJNfF j0TjxesRSUdJjMzgYwuXK+J3RlnbnTq6BEOxeOv4jtKt/c/Wv2X7OtPx66WmMjMJWuQM 0LfHey/KUEFWwIc3qWmS8x7MeNYqowJXaHhdfwwtlfH1jo+gGy2ChosGNcCzyI6k/Rpi jLTz8kB6o5yNDZ+bP9nJBkjoCx0oZUsCPJCgws273toRgMJKQeLroTL8VKAzzvYOMd2Y WGgw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20210112.gappssmtp.com header.s=20210112 header.b=mRU7bHdb; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id b19-20020aa7dc13000000b005027766cac8si2477141edu.631.2023.04.05.14.12.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Apr 2023 14:12:53 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@rivosinc-com.20210112.gappssmtp.com header.s=20210112 header.b=mRU7bHdb; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3A3D138768A7 for ; Wed, 5 Apr 2023 21:06:18 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pl1-x644.google.com (mail-pl1-x644.google.com [IPv6:2607:f8b0:4864:20::644]) by sourceware.org (Postfix) with ESMTPS id B03C13857005 for ; Wed, 5 Apr 2023 21:03:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B03C13857005 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pl1-x644.google.com with SMTP id kq3so35573826plb.13 for ; Wed, 05 Apr 2023 14:03:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; t=1680728589; x=1683320589; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pcNYn56UjLOYIUhjeLtRwQBit+o1zbjbdDRd9Ok0HAE=; b=mRU7bHdbkN/ywjIDM6oGKkQAiXAw9nHW4Lai6j72fS3NiKpophaLHv5sMY10sH5NvS J4vBY1pZk1neXTRPedwX34udocsSViR7VmcuWh8OEWq7AB7wsER9vuZpg4e2gZrKAzA8 eCIXaK6sv/M44Q4fieAp7/Ykr1SBbSL5AdJdrh32wo0Poedd1ZuLjZkcD/T0yJBb0b3B bxWd502U/nNF7IUTFDkwBaIP9vrK4VzNs5cHwvgemcQJ96lki8qcapFRlJyDnnRt7AiX fkORjZi3Q9DXSAzzsA0k78hhSqFNJn2Lr7JmsYdwDdJ0Dvchx2DZ2Xe/71Y3QdUfHMm2 v71g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680728589; x=1683320589; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pcNYn56UjLOYIUhjeLtRwQBit+o1zbjbdDRd9Ok0HAE=; b=rZZCnJq2KeXiER+F0YPluqiYYTzRnuhyHcKzTcLnEF76eBpRxWGrDCQIGvkWAqO11q R/8GKK92HRrpN0Asp03xxWQHCAuEtxbPKP5QTPfTldjE+HbvajuqVK2dGCXGF+iv0msH c72a1k8SgiGnAUVFN7Rs4a/Gl5e78EyBswtx+5M23WfWMi4f+Qh+KY3ACxIIdAATqD4L l4bk2WePac0VsDJGF+qg2530baxb5Mupa3nHU5hIWQkMe3yIi7l+9aOmrWRy9LsJVntw PjyAyhXbb6XyZH8TP2z2DSKbULYIpLnHDNYubga0b1P3TJSuhPJvnvuYF5VcKRMD+h/l 9GlQ== X-Gm-Message-State: AAQBX9divau+7dbftHHd1yg9Mm7Ox4gIGzyelw0hSss+VRs2HzTM2pxG lQu5W8O3p4z12WxaUHl/+nFgVhQuhuQ2Pmkbo8u7pSMmMiM= X-Received: by 2002:a17:90b:4c92:b0:23f:635e:51e9 with SMTP id my18-20020a17090b4c9200b0023f635e51e9mr8432006pjb.8.1680728589402; Wed, 05 Apr 2023 14:03:09 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id e6-20020a17090a77c600b002342ccc8280sm1809477pjs.6.2023.04.05.14.03.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Apr 2023 14:03:08 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, jeffreyalaw@gmail.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, Patrick O'Neill Subject: [PATCH v2 8/8] RISCV: Weaken mem_thread_fence Date: Wed, 5 Apr 2023 14:01:18 -0700 Message-Id: <20230405210118.1969283-9-patrick@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230405210118.1969283-1-patrick@rivosinc.com> References: <20220407182918.294892-1-patrick@rivosinc.com> <20230405210118.1969283-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762372273929861892?= X-GMAIL-MSGID: =?utf-8?q?1762372273929861892?= This change brings atomic fences in line with table A.6 of the ISA manual. Relax mem_thread_fence according to the memmodel given. 2023-04-05 Patrick O'Neill * riscv.cc: Expose helper functions to sync.md. * riscv-protos.h: Likewise. * sync.md (mem_thread_fence_1): Change fence depending on aquire/release requirements. * amo-thread-fence-1: New test. * amo-thread-fence-2: Likewise. * amo-thread-fence-3: Likewise. * amo-thread-fence-4: Likewise. * amo-thread-fence-5: Likewise. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/riscv-protos.h | 2 ++ gcc/config/riscv/riscv.cc | 4 ++-- gcc/config/riscv/sync.md | 17 ++++++++++++++--- .../gcc.target/riscv/amo-thread-fence-1.c | 6 ++++++ .../gcc.target/riscv/amo-thread-fence-2.c | 6 ++++++ .../gcc.target/riscv/amo-thread-fence-3.c | 6 ++++++ .../gcc.target/riscv/amo-thread-fence-4.c | 6 ++++++ .../gcc.target/riscv/amo-thread-fence-5.c | 6 ++++++ 8 files changed, 48 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-5.c diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index b03edc3e8a5..233b8070047 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -81,6 +81,8 @@ extern void riscv_reinit (void); extern poly_uint64 riscv_regmode_natural_size (machine_mode); extern bool riscv_v_ext_vector_mode_p (machine_mode); extern bool riscv_shamt_matches_mask_p (int, HOST_WIDE_INT); +extern bool riscv_memmodel_needs_amo_acquire (enum memmodel); +extern bool riscv_memmodel_needs_amo_release (enum memmodel); extern enum memmodel riscv_union_memmodels (enum memmodel, enum memmodel); /* Routines implemented in riscv-c.cc. */ diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 061d2cf42b4..27d876ac44c 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4311,7 +4311,7 @@ riscv_union_memmodels (enum memmodel model1, enum memmodel model2) /* Return true if the .AQ suffix should be added to an AMO to implement the acquire portion of memory model MODEL. */ -static bool +bool riscv_memmodel_needs_amo_acquire (enum memmodel model) { switch (model) @@ -4334,7 +4334,7 @@ riscv_memmodel_needs_amo_acquire (enum memmodel model) /* Return true if the .RL suffix should be added to an AMO to implement the release portion of memory model MODEL. */ -static bool +bool riscv_memmodel_needs_amo_release (enum memmodel model) { switch (model) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index cdd227721e1..4204c956bd6 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -42,14 +42,25 @@ DONE; }) -;; Until the RISC-V memory model (hence its mapping from C++) is finalized, -;; conservatively emit a full FENCE. (define_insn "mem_thread_fence_1" [(set (match_operand:BLK 0 "" "") (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER)) (match_operand:SI 1 "const_int_operand" "")] ;; model "" - "fence\tiorw,iorw") + { + enum memmodel model = (enum memmodel) INTVAL (operands[1]); + model = memmodel_base (model); + if (model == MEMMODEL_ACQ_REL) + return "fence.tso"; + else if (riscv_memmodel_needs_amo_acquire (model) && + riscv_memmodel_needs_amo_release (model)) + return "fence\trw,rw"; + else if (riscv_memmodel_needs_amo_acquire (model)) + return "fence\tr,rw"; + else if (riscv_memmodel_needs_amo_release (model)) + return "fence\trw,w"; + } + [(set (attr "length") (const_int 4))]) ;; Atomic memory operations. diff --git a/gcc/testsuite/gcc.target/riscv/amo-thread-fence-1.c b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-1.c new file mode 100644 index 00000000000..833629bf2f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-1.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-final { scan-assembler-not "fence\t" } } */ + +int main() { + __atomic_thread_fence(__ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-thread-fence-2.c b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-2.c new file mode 100644 index 00000000000..3395ee41dbb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-final { scan-assembler "fence\tr,rw" } } */ + +int main() { + __atomic_thread_fence(__ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-thread-fence-3.c b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-3.c new file mode 100644 index 00000000000..59cc4e5d394 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-3.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-final { scan-assembler "fence\trw,w" } } */ + +int main() { + __atomic_thread_fence(__ATOMIC_RELEASE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-thread-fence-4.c b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-4.c new file mode 100644 index 00000000000..2afed9a9e38 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-4.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-final { scan-assembler "fence.tso" } } */ + +int main() { + __atomic_thread_fence(__ATOMIC_ACQ_REL); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-thread-fence-5.c b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-5.c new file mode 100644 index 00000000000..b8d56c0f066 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-5.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-final { scan-assembler "fence\trw,rw" } } */ + +int main() { + __atomic_thread_fence(__ATOMIC_SEQ_CST); +}