From patchwork Wed Apr 5 10:48:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 79558 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp208052vqo; Wed, 5 Apr 2023 03:56:11 -0700 (PDT) X-Google-Smtp-Source: AKy350Z481mGTynKiDiWZZBXFJTzwvfeNS/KLGd3sjlyhhfl5zKCLRw7AfzJkdehkHBT0sHICPfM X-Received: by 2002:a17:906:8492:b0:93e:5a85:ad3c with SMTP id m18-20020a170906849200b0093e5a85ad3cmr2366284ejx.57.1680692171292; Wed, 05 Apr 2023 03:56:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680692171; cv=none; d=google.com; s=arc-20160816; b=h1bonJFEb05QYuMtDjHAwAa88A/b50pFxYfgtoPqVg+iQ6teaOYXpzkqtJXodr5TZB ii7gQiTgCC3pS+Wfg0s+VRmm+Zti5E4AEsw0HP/O3vrfgO2GVO+v6HrrzxN0iJnyjtb8 FBfVv7mnYtmLgpT+6dnpaqA6AB+iQg9EjNTcwXNMVltwa4q70d/qMV+3WfQcwpQiXks7 292XUfU5hEGa2aR50NqOW6JCYtlFf4EqdhZG62x5Q6z7834M+khWa1enlbpsDuEBVP21 i26sj9K7AUBpSD74Am/2bqyR2BJftiyXgWs+2KK1GaVoyJR9VIbX47sKmog5hIJLs5wm B4cA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=PjlBvbh3eaYQdMUrEcW9s95jBLrDwV6kOykUeIJwqFU=; b=Z/gDt0DK+74805TuoQRAEqVjVa97DccDL2q/eV98M6ybo1VsjWLzfcLFWlPaBmr4iK eLk96uLErkKq0C1aolIWBc+WQR/zFtHPHg/Wy3hiySdZRVSk27U0kjLRpl+9wi2J0Hyg NnO7Vy9kdh+gp43U484BYRs0fhIDFoZeA/SSujJr/Nb6dOIB/QcZcW68pvMVfqjKl3dT DDMmAEan96De9upB45KsjozwNMhv9xcg8W2ZXLcqhuWsO4jc4wc9y/Ej2kvEUB4KrtiP RzdIPaDsv38a9bY0r0TtLRpi+v3qH1ZZ598FOr+nKCnSc9ocVhGNLUkxDVlCiqLbCSSO jYkg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=O0Un5q8x; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.1.37]) by smtp.gmail.com with ESMTPSA id u4-20020a2e9b04000000b00295a3a64816sm2777299lji.2.2023.04.05.03.48.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Apr 2023 03:48:37 -0700 (PDT) From: Konrad Dybcio Date: Wed, 05 Apr 2023 12:48:34 +0200 Subject: [PATCH v2 1/2] dt-bindings: interrupt-controller: mpm: Pass MSG RAM slice through phandle MIME-Version: 1.0 Message-Id: <20230328-topic-msgram_mpm-v2-1-e24a48e57f0d@linaro.org> References: <20230328-topic-msgram_mpm-v2-0-e24a48e57f0d@linaro.org> In-Reply-To: <20230328-topic-msgram_mpm-v2-0-e24a48e57f0d@linaro.org> To: Andy Gross , Bjorn Andersson , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Shawn Guo Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680691715; l=2113; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=R+nl9I6wuHXVSNu7ub0x4qWS9SfiNOhOzZJ7YrNBpgo=; b=nkKf8A9vZ3gv5c16oKZQlCBsfqwPAK9cloJD47Af9w4oLjF/q/kjJyT9Hl4zHElrEPnSKgSNhvrx izmgdvb9B9gxIw16BlNtjyjYEqwTaT7Nulq0JppAGtU2sjuLOcj/ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762333474191806401?= X-GMAIL-MSGID: =?utf-8?q?1762333474191806401?= Due to the wild nature of the Qualcomm RPM Message RAM, we can't really use 'reg' to point to the MPM's slice of Message RAM without cutting into an already-defined RPM MSG RAM node used for GLINK and SMEM. Document passing the register space as a slice of SRAM through the qcom,rpm-msg-ram property. This also makes 'reg' deprecated. Signed-off-by: Konrad Dybcio --- .../devicetree/bindings/interrupt-controller/qcom,mpm.yaml | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml index 509d20c091af..61fc5b1b74dc 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml @@ -29,6 +29,12 @@ properties: maxItems: 1 description: Specifies the base address and size of vMPM registers in RPM MSG RAM. + deprecated: true + + qcom,rpm-msg-ram: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the APSS MPM slice of the RPM Message RAM interrupts: maxItems: 1 @@ -64,23 +70,22 @@ properties: required: - compatible - - reg - interrupts - mboxes - interrupt-controller - '#interrupt-cells' - qcom,mpm-pin-count - qcom,mpm-pin-map + - qcom,rpm-msg-ram additionalProperties: false examples: - | #include - mpm: interrupt-controller@45f01b8 { + mpm: interrupt-controller { compatible = "qcom,mpm"; interrupts = ; - reg = <0x45f01b8 0x1000>; mboxes = <&apcs_glb 1>; interrupt-controller; #interrupt-cells = <2>; @@ -93,4 +98,5 @@ examples: <86 183>, <90 260>, <91 260>; + qcom,rpm-msg-ram = <&apss_mpm>; }; From patchwork Wed Apr 5 10:48:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 79557 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp208024vqo; Wed, 5 Apr 2023 03:56:07 -0700 (PDT) X-Google-Smtp-Source: AKy350YAL7Ahtf6mMYttbIDs/6PEyTN5E4NPA3LKpcEbth6lRgQyRR2RhLReuZo/PZ7B05JGw9kN X-Received: by 2002:a17:906:17c7:b0:944:5d34:2111 with SMTP id u7-20020a17090617c700b009445d342111mr2383296eje.66.1680692167200; Wed, 05 Apr 2023 03:56:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680692167; cv=none; d=google.com; s=arc-20160816; b=SpX0D4JByKJrd3uG5Hxr/dB4hNEx374BuKlLtzLSuoxlZJVVLhwAKUOgFSqIDS9V7l wzUhgmtLBRV8njh90M6Sm0a+LmilYaTO6aEWpMwc0Zn8WQPkzpTsjVr7oyEBEqvwV+PH X5BYMCYl6tiddacYdrI+gHMDVtajQVSJUgxapvrF2bGMPO3fTnTfG2sdIhGUpRbiYLGB mtteXesB8wLxegOH31S2xzvx3cCdNLRaWEg8ItvQElsA31/dMraR6mH996iVghG+lR6F r27yb6tHgmq7e+5FNkEX1KQ2d/VPMDdPWa+3S8rm9vtJL+Vf+BdkmKFUsUZq+hGVWEEI 4/4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=Bi/GSYXJQcjk80svXbFmJoU1UjMsZTTC+SEAdd/i1LY=; b=cxn8SsJPuc8qM5dlo3xqNEXmcPwZCFGpjD5WoXaWRspMmS240++P2iPXw/C5Q0aTts SnyLWzqFqP6p6cjDrOjtxDp4zqgbg7+1mvxtVP/9N5gMLFxEBXYeXJ5LEV0V1LCEtxzC /dNeeNjtp8xGMh7g7wvcyRqTOWaEWbU/CXFZwNyZKWfALTPDgin82I94AUBvTGCXBZdc Y0108XwQwu4gJ1aRWL1CD0EEwaU0AJnXiNPTRKgcOIvSLQ21qUPhgDxaWlGR4lZ7py5Y oMpaa3N0L80Nq9dSrHjaUcSkaILjem1Kx2t5wPewMa6+UxcGw3bCENr7+01fQNgkYWQE pUZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="lDpNpPU/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.1.37]) by smtp.gmail.com with ESMTPSA id u4-20020a2e9b04000000b00295a3a64816sm2777299lji.2.2023.04.05.03.48.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Apr 2023 03:48:38 -0700 (PDT) From: Konrad Dybcio Date: Wed, 05 Apr 2023 12:48:35 +0200 Subject: [PATCH v2 2/2] irqchip: irq-qcom-mpm: Support passing a slice of SRAM as reg space MIME-Version: 1.0 Message-Id: <20230328-topic-msgram_mpm-v2-2-e24a48e57f0d@linaro.org> References: <20230328-topic-msgram_mpm-v2-0-e24a48e57f0d@linaro.org> In-Reply-To: <20230328-topic-msgram_mpm-v2-0-e24a48e57f0d@linaro.org> To: Andy Gross , Bjorn Andersson , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Shawn Guo Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680691715; l=2707; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=xu+OxnOnfyyQMV5yk+DxmYZEKxx2j9CzQ4gEX4sggZE=; b=b5jBE4w42Kljvzt3wJ/kG4dpvf/EjVnoTaczlavfH3f0MIArqyLKYL45E1WPEzxoOJTZuEwwAJer dDrQD0elDtxV/bMNIElqW15WfoMD5c5TQnZ20Lr0cQgZhZ1JU6fF X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762333470245836113?= X-GMAIL-MSGID: =?utf-8?q?1762333470245836113?= The MPM hardware is accessible to us from the ARM CPUs through a shared memory region (RPM MSG RAM) that's also concurrently accessed by other kinds of cores on the system (like modem, ADSP etc.). Modeling this relation in a (somewhat) sane manner in the device tree basically requires us to either present the MPM as a child of said memory region (which makes little sense, as a mapped memory carveout is not a bus), define nodes which bleed their register spaces into one another, or passing their slice of the MSG RAM through some kind of a property. Go with the third option and add a way to map a region passed through the "qcom,rpm-msg-ram" property as our register space. The current way of using 'reg' is preserved for ABI reasons. Signed-off-by: Konrad Dybcio Acked-by: Shawn Guo --- drivers/irqchip/irq-qcom-mpm.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-qcom-mpm.c b/drivers/irqchip/irq-qcom-mpm.c index d30614661eea..ee5f39a4a42a 100644 --- a/drivers/irqchip/irq-qcom-mpm.c +++ b/drivers/irqchip/irq-qcom-mpm.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -322,8 +323,10 @@ static int qcom_mpm_init(struct device_node *np, struct device_node *parent) struct device *dev = &pdev->dev; struct irq_domain *parent_domain; struct generic_pm_domain *genpd; + struct device_node *msgram_np; struct qcom_mpm_priv *priv; unsigned int pin_cnt; + struct resource res; int i, irq; int ret; @@ -374,9 +377,21 @@ static int qcom_mpm_init(struct device_node *np, struct device_node *parent) raw_spin_lock_init(&priv->lock); - priv->base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); + /* If we have a handle to an RPM message ram partition, use it. */ + msgram_np = of_parse_phandle(np, "qcom,rpm-msg-ram", 0); + if (msgram_np) { + ret = of_address_to_resource(msgram_np, 0, &res); + /* Don't use devm_ioremap_resource, as we're accessing a shared region. */ + priv->base = devm_ioremap(dev, res.start, resource_size(&res)); + of_node_put(msgram_np); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + } else { + /* Otherwise, fall back to simple MMIO. */ + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + } for (i = 0; i < priv->reg_stride; i++) { qcom_mpm_write(priv, MPM_REG_ENABLE, i, 0);