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Wysocki" , "David S . Miller" , Jisheng Zhang , Anup Patel , Atish Patra Subject: [PATCH V4 01/23] riscv: move sbi_init() earlier before jump_label_init() Date: Tue, 4 Apr 2023 23:50:15 +0530 Message-Id: <20230404182037.863533-2-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404182037.863533-1-sunilvl@ventanamicro.com> References: <20230404182037.863533-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762271068416244508?= X-GMAIL-MSGID: =?utf-8?q?1762271068416244508?= From: Jisheng Zhang We call jump_label_init() in setup_arch() is to use static key mechanism earlier, but riscv jump label relies on the sbi functions, If we enable static key before sbi_init(), the code path looks like: static_branch_enable() .. arch_jump_label_transform() patch_text_nosync() flush_icache_range() flush_icache_all() sbi_remote_fence_i() for CONFIG_RISCV_SBI case __sbi_rfence() Since sbi isn't initialized, so NULL deference! Here is a typical panic log: [ 0.000000] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000000 [ 0.000000] Oops [#1] [ 0.000000] Modules linked in: [ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 5.18.0-rc7+ #79 [ 0.000000] Hardware name: riscv-virtio,qemu (DT) [ 0.000000] epc : 0x0 [ 0.000000] ra : sbi_remote_fence_i+0x1e/0x26 [ 0.000000] epc : 0000000000000000 ra : ffffffff80005826 sp : ffffffff80c03d50 [ 0.000000] gp : ffffffff80ca6178 tp : ffffffff80c0ad80 t0 : 6200000000000000 [ 0.000000] t1 : 0000000000000000 t2 : 62203a6b746e6972 s0 : ffffffff80c03d60 [ 0.000000] s1 : ffffffff80001af6 a0 : 0000000000000000 a1 : 0000000000000000 [ 0.000000] a2 : 0000000000000000 a3 : 0000000000000000 a4 : 0000000000000000 [ 0.000000] a5 : 0000000000000000 a6 : 0000000000000000 a7 : 0000000000080200 [ 0.000000] s2 : ffffffff808b3e48 s3 : ffffffff808bf698 s4 : ffffffff80cb2818 [ 0.000000] s5 : 0000000000000001 s6 : ffffffff80c9c345 s7 : ffffffff80895aa0 [ 0.000000] s8 : 0000000000000001 s9 : 000000000000007f s10: 0000000000000000 [ 0.000000] s11: 0000000000000000 t3 : ffffffff80824d08 t4 : 0000000000000022 [ 0.000000] t5 : 000000000000003d t6 : 0000000000000000 [ 0.000000] status: 0000000000000100 badaddr: 0000000000000000 cause: 000000000000000c [ 0.000000] ---[ end trace 0000000000000000 ]--- [ 0.000000] Kernel panic - not syncing: Attempted to kill the idle task! [ 0.000000] ---[ end Kernel panic - not syncing: Attempted to kill the idle task! ]--- Fix this issue by moving sbi_init() earlier before jump_label_init() Signed-off-by: Jisheng Zhang Reviewed-by: Anup Patel Reviewed-by: Atish Patra --- arch/riscv/kernel/setup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 376d2827e736..2d45a416d283 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -270,6 +270,7 @@ void __init setup_arch(char **cmdline_p) *cmdline_p = boot_command_line; early_ioremap_setup(); + sbi_init(); jump_label_init(); parse_early_param(); @@ -287,7 +288,6 @@ void __init setup_arch(char **cmdline_p) misc_mem_init(); init_resources(); - sbi_init(); #ifdef CONFIG_KASAN kasan_init(); From patchwork Tue Apr 4 18:20:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 79352 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp86872vqo; Tue, 4 Apr 2023 11:40:52 -0700 (PDT) X-Google-Smtp-Source: AKy350ZBfkhxagOtBVyZJ011JrkLX3Z6p7XVUmqIIysdnLRhlkxg63aSpz+HU72BREsLY3mbTSQi X-Received: by 2002:a17:907:8b95:b0:931:96c5:7646 with SMTP id tb21-20020a1709078b9500b0093196c57646mr561216ejc.57.1680633652243; Tue, 04 Apr 2023 11:40:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680633652; cv=none; d=google.com; s=arc-20160816; b=ILd4csyNdMquVAuOuAPht62WDAYyPgPEm3Aq9dhSWJw4P8e/HKDAu66BKSORmVN3LM 3i102TikMtO+H/n6A9LNSrs5siralNpdfFwOe2R5etwBuDuhqsc81hVIWWjHfXc97I6b XiE820XiBqj3YEr79VkriBIRaoiHIg1FsSCASsuIyq2tqoFQigxdZjfHnvgrxxm7L1xf 9ED/G6r8EUNfPioamaJs6vteHc++lChmCk1GG1GdqfxFzS49djQfMOSYipjYuy4yBYV7 WFikFIL2HVirssyMLSjopWujOTdNjIMoNqkKSTJLh7g0Buy7pKz9ny1TqKAP/7VdNFKh gAng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=DdBAV21+tEDurt/JvTaHJyUQ0LBM5nBDKYeMtin7GIs=; b=b/puj17B79gGN5A1Ejn3pNABuPf9zBMeO1MWACof+SFysy5eQBQNcbP4ECtnU1fVrs wSq6mLyrzWTbILOVKiOYmEJZrjAF5fUIItCA+UM5C7q447oVXVW+KdL40SG5VKx06+18 +2XK0rG38wPK+W6sLm2xT6vlzCvSue1n70MiKbM+y7xQc+tTOhAHD9VuBpK5MSCJO3ug /0hen/6u8yOxJLfl2wClRvbvGdcNzodnAuRhQqBl+wY69AvFTdHo6TBRJ1xH3ZcXlT2R fobRB9bK2JTVuUuS7z2eqyxc+KIZlZZbxxZ1QG01hhu2+rqHxJvU15PZMTDzlWZUiE1+ dCwg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=MX30zIpz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , "David S . Miller" , Sunil V L Subject: [PATCH V4 02/23] ACPICA: MADT: Add RISC-V INTC interrupt controller Date: Tue, 4 Apr 2023 23:50:16 +0530 Message-Id: <20230404182037.863533-3-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404182037.863533-1-sunilvl@ventanamicro.com> References: <20230404182037.863533-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762272113017777168?= X-GMAIL-MSGID: =?utf-8?q?1762272113017777168?= ACPICA commit bd6d1ae1e13abe78e149c8b61b4bc7bc7feab015 The ECR to add RISC-V INTC interrupt controller is approved by the UEFI forum and will be available in the next revision of the ACPI specification. Link: https://github.com/acpica/acpica/commit/bd6d1ae1 Reference: Mantis ID: 2348 Signed-off-by: Sunil V L --- include/acpi/actbl2.h | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h index b2973dbe37ee..c432fd15db65 100644 --- a/include/acpi/actbl2.h +++ b/include/acpi/actbl2.h @@ -891,7 +891,8 @@ enum acpi_madt_type { ACPI_MADT_TYPE_MSI_PIC = 21, ACPI_MADT_TYPE_BIO_PIC = 22, ACPI_MADT_TYPE_LPC_PIC = 23, - ACPI_MADT_TYPE_RESERVED = 24, /* 24 to 0x7F are reserved */ + ACPI_MADT_TYPE_RINTC = 24, + ACPI_MADT_TYPE_RESERVED = 25, /* 25 to 0x7F are reserved */ ACPI_MADT_TYPE_OEM_RESERVED = 0x80 /* 0x80 to 0xFF are reserved for OEM use */ }; @@ -1250,6 +1251,24 @@ enum acpi_madt_lpc_pic_version { ACPI_MADT_LPC_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */ }; +/* 24: RISC-V INTC */ +struct acpi_madt_rintc { + struct acpi_subtable_header header; + u8 version; + u8 reserved; + u32 flags; + u64 hart_id; + u32 uid; /* ACPI processor UID */ +}; + +/* Values for RISC-V INTC Version field above */ + +enum acpi_madt_rintc_version { + ACPI_MADT_RINTC_VERSION_NONE = 0, + ACPI_MADT_RINTC_VERSION_V1 = 1, + ACPI_MADT_RINTC_VERSION_RESERVED = 2 /* 2 and greater are reserved */ +}; + /* 80: OEM data */ struct acpi_madt_oem_data { From patchwork Tue Apr 4 18:20:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 79331 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp78307vqo; Tue, 4 Apr 2023 11:25:00 -0700 (PDT) X-Google-Smtp-Source: AKy350a746tgtNHvV04a2+nufz0URI/sHeG2vcMqktfKfxC6Pr5U1knswddxy8VQI+itijyEjfVM X-Received: by 2002:a17:903:1107:b0:1a2:58f1:5e1d with SMTP id n7-20020a170903110700b001a258f15e1dmr4533294plh.36.1680632700478; Tue, 04 Apr 2023 11:25:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680632700; cv=none; d=google.com; s=arc-20160816; b=Qsot3fEToUefR9xxGG6f8FUh1EQeGTRNhOC9hZLgPONQSfjP6bsgFnCV4axX9cr08o L+iVKA5bZOWELbSBahVIiTlkou8Zkboycck5HvgmimGahEdUVNzI64HlKTBobkye2vXB skf6PvCWb8HjsVM/hD3VDnm4b6RUhaT4SrzszEXKVaaX3joMkFd/UVyMPLC9cIjoAZ7q ckAROVogTr++h1dlH+KO2KX/9Bxtg3meMlYGbsQrxfoY39COnM8j5yTloqpE5truFHW3 2zUUOJnlCQrvaHx96tWoQ6m1KHxVR2dvwSPoWhKJexTlGtpqD3CBp+5rrodUpX7fhR/I g84Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=b3qZ67y38AFkmcquwwQ+jCEdL0KsuQFOs2StQrvk1r4=; b=kwKmKUratEsJNtZE1b4dmi8Pb09Eb/pscAfsgvpiYydgwdZZWZwOzQPZpPk2vaCcGc pp7rELyDcz5sHMv9rcvUXH0Dh+N2DHxadP//CuqCDTtiLBFqrgghTm7iMQWx3k4OuGOr qeUIqt8GZtQExQV6lv+kIejjIIzpjhjNebl8VDqoOZVcR+9ZV0DRaNtB2/6O4HtQGi0M q1705yD3qXQBjr4DGO5Ovp1yDx0hxMgmFcBaRTwXbgUJiJDiaJ/hvhpUDz2+5kC379r1 +kTLKH8RF0656qr0pVz00z/jxq0LNGLOq3K67znDlCJnlHf4Xn98Uv0dDs1oWNwR2ybG HMgA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=XNL5wXfo; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , "David S . Miller" , Sunil V L Subject: [PATCH V4 03/23] ACPICA: Add structure definitions for RISC-V RHCT Date: Tue, 4 Apr 2023 23:50:17 +0530 Message-Id: <20230404182037.863533-4-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404182037.863533-1-sunilvl@ventanamicro.com> References: <20230404182037.863533-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762271114805512225?= X-GMAIL-MSGID: =?utf-8?q?1762271114805512225?= ACPICA commit 82afd0434e79f74b96a6be88115ddc8343a1ba40 RISC-V Hart Capabilities Table (RHCT) is a new static table. The ECR to add RHCT is approved by the UEFI forum and will be available in the next version of the ACPI spec. Link: https://github.com/acpica/acpica/commit/82afd043 Reference: Mantis: 2349 Signed-off-by: Sunil V L --- include/acpi/actbl2.h | 48 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h index c432fd15db65..86bb79fdfa62 100644 --- a/include/acpi/actbl2.h +++ b/include/acpi/actbl2.h @@ -47,6 +47,7 @@ #define ACPI_SIG_PRMT "PRMT" /* Platform Runtime Mechanism Table */ #define ACPI_SIG_RASF "RASF" /* RAS Feature table */ #define ACPI_SIG_RGRT "RGRT" /* Regulatory Graphics Resource Table */ +#define ACPI_SIG_RHCT "RHCT" /* RISC-V Hart Capabilities Table */ #define ACPI_SIG_SBST "SBST" /* Smart Battery Specification Table */ #define ACPI_SIG_SDEI "SDEI" /* Software Delegated Exception Interface Table */ #define ACPI_SIG_SDEV "SDEV" /* Secure Devices table */ @@ -2604,6 +2605,53 @@ enum acpi_rgrt_image_type { ACPI_RGRT_TYPE_RESERVED = 2 /* 2 and greater are reserved */ }; +/******************************************************************************* + * + * RHCT - RISC-V Hart Capabilities Table + * Version 1 + * + ******************************************************************************/ + +struct acpi_table_rhct { + struct acpi_table_header header; /* Common ACPI table header */ + u32 reserved; + u64 time_base_freq; + u32 node_count; + u32 node_offset; +}; + +/* + * RHCT subtables + */ +struct acpi_rhct_node_header { + u16 type; + u16 length; + u16 revision; +}; + +/* Values for RHCT subtable Type above */ + +enum acpi_rhct_node_type { + ACPI_RHCT_NODE_TYPE_ISA_STRING = 0x0000, + ACPI_RHCT_NODE_TYPE_HART_INFO = 0xFFFF, +}; + +/* + * RHCT node specific subtables + */ + +/* ISA string node structure */ +struct acpi_rhct_isa_string { + u16 isa_length; + char isa[]; +}; + +/* Hart Info node structure */ +struct acpi_rhct_hart_info { + u16 num_offsets; + u32 uid; /* ACPI processor UID */ +}; + /******************************************************************************* * * SBST - Smart Battery Specification Table From patchwork Tue Apr 4 18:20:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 79346 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp85548vqo; Tue, 4 Apr 2023 11:38:19 -0700 (PDT) X-Google-Smtp-Source: AKy350aD+nWU2tgvAY1rxAJdn+itTud4zb/i6iToXLy6DGvcVn4VZNiI5apwBkSW+jqC1QRbthiv X-Received: by 2002:a62:1d01:0:b0:622:749a:b9de with SMTP id d1-20020a621d01000000b00622749ab9demr3116851pfd.27.1680633499477; Tue, 04 Apr 2023 11:38:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680633499; cv=none; d=google.com; s=arc-20160816; b=wWREt7eVBer1ZxNlmxmTIqkfeb7PZpZnXcbNSssbjLQsI2vBhlTzZ30tzLyfOZtdCB MJPuGf1qS/HD1BmxbnzeDhO8TZoAG/aAwcbySStViNEsvpigdL9XxTbOQVhaR7v9bq3Q ESegs7SxfJS89PU1CnFeLC06e793Qe704Abgx+IlOPJjqORQmFQwCmmrtpU3PVpQfRkD Df0voMHJcbhwuqLRFO/GO3eaTDQ83aDzzpBpioct3XdyENl1FCI4qhkKEScfbQDWz86C jTypbdt0iXzsIhgFWdodRZpz7ywwv9hXbIiLEM4YTk8sGHMrN1IG2MNcgWc5lf1qcbvI 5BSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=1wcGbfhUP5NrwGCYl7Q1yL0FMzRdJBr1PIlnUSkktJs=; b=YNwtjs1YBxUuG3u4E4ahwTCPKLIU8Sh2DD8l0nVGIJ+GyUmdKGe2ReHZZg2AGRyqcm I5Lu3ZjgduG3Plgg26QYhWrqwQm1M+i7AidY7TtwE81FGOtCgVWDmpwhqU2tBcOll/7b qeJvMi/QbGpor0XnoicyLCaH2I55QAj5vsAPoxE1squYehx5gDVVeQBKfEMUrm3CpJ89 KQ9/BO6nLDLFu6kZiYi+uqRnlmSlwf9O6xHz2g7zhAnZ3nq4hk5cE1X6j7nUdpfXef5U lnzqh1ZM1ZoEOmf67CLEKbNzPBMISmWdX120ju09TYNuDLPA0PGauSb50OuWPVHClSTJ 0qvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=aYnlk3Bg; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , "David S . Miller" , Sunil V L , "Rafael J . Wysocki" , Andrew Jones Subject: [PATCH V4 04/23] ACPI: tables: Print RINTC information when MADT is parsed Date: Tue, 4 Apr 2023 23:50:18 +0530 Message-Id: <20230404182037.863533-5-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404182037.863533-1-sunilvl@ventanamicro.com> References: <20230404182037.863533-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762271952106016667?= X-GMAIL-MSGID: =?utf-8?q?1762271952106016667?= When MADT is parsed, print RINTC information as below: ACPI: RISC-V INTC (acpi_uid[0x0000] hart_id[0x0] enabled) ACPI: RISC-V INTC (acpi_uid[0x0001] hart_id[0x1] enabled) ... ACPI: RISC-V INTC (acpi_uid[0x000f] hart_id[0xf] enabled) This debug information will be very helpful during bring up. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones --- drivers/acpi/tables.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/acpi/tables.c b/drivers/acpi/tables.c index 7b4680da57d7..8ab0a82b4da4 100644 --- a/drivers/acpi/tables.c +++ b/drivers/acpi/tables.c @@ -220,6 +220,16 @@ void acpi_table_print_madt_entry(struct acpi_subtable_header *header) } break; + case ACPI_MADT_TYPE_RINTC: + { + struct acpi_madt_rintc *p = (struct acpi_madt_rintc *)header; + + pr_debug("RISC-V INTC (acpi_uid[0x%04x] hart_id[0x%llx] %s)\n", + p->uid, p->hart_id, + (p->flags & ACPI_MADT_ENABLED) ? "enabled" : "disabled"); + } + break; + default: pr_warn("Found unsupported MADT entry (type = 0x%x)\n", header->type); From patchwork Tue Apr 4 18:20:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 79333 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp78483vqo; Tue, 4 Apr 2023 11:25:21 -0700 (PDT) X-Google-Smtp-Source: AKy350aH10SSpCYy7F8xYzWuRQ2+YEkfSXJSszRTzEzzz9JjiVa1lo0PrgIz8GRUb8gNiLRRcRnb X-Received: by 2002:a17:90b:4a50:b0:23b:4f2a:8016 with SMTP id lb16-20020a17090b4a5000b0023b4f2a8016mr3888302pjb.3.1680632721017; Tue, 04 Apr 2023 11:25:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680632720; cv=none; d=google.com; s=arc-20160816; b=zCfuqG1Byt3royn9uvSnN4Wh7g3EVpns++G+lBbs54Nbx+EZgI6xjXPjjjVncGsEfC QqrWfIVAGcHxS6A46bSHDHaQdladPPLqd/NdWqkMm2xqXVibbHj5PzwvNKsbHerYrR42 852z2LJLKAgenBb9ePWEGPF5Hbe11FkMEE4d5FYj94++4qtZkL7bNe8axG7YBjBjmmVW QPhxWDSjU5EnyBuYbZzV3gxIojWRYAQbEp6WQzYT4lnnSx57qxGCAoyDMNLZLAmWxyB/ oZCjC4mJshCdo4aCGdSmg/9s0qiHSrWXDvKfyRyHk02ekUOyL5G5NQWnxJtYjKcj0JxL 4RMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=g9sxg5LZ/1sJSiDItv56ESM72UWoohRRXZed1vK0StQ=; b=cuz+ui2aGDULX0y9Qrw8PelTEmf7/niISJjIHjw4rAqYKYWyTRlD8jcSXCmFfmjESZ sJTuC1VdijHWgpJrdfS21FpHG3QOLIDgS2XQVZ8IJhE+GkUhNOT322peM2Nc5EoFRyGP 31BOQy7JMEJRh4MXvDmGfUWqqUehEhv0kx+lCjrNdPf0rBFhytJ4myiDGyWwy4RSPqUW iPyS/hFEEFQjH0VIXFumfs9/Z2tsPhshDoaINGGzfRwjb+SQ0YJXomf9WyI7xpPdKaPS atwJDAN0LnjE6aDcw3ysMLjhckbWPRG9RmMWkEL84U4yMq0zjwmSsg2hOTwOS5GTgITY ruyg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=lS5ulDLp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , "David S . Miller" , Sunil V L , "Rafael J . Wysocki" Subject: [PATCH V4 05/23] ACPI: OSL: Make should_use_kmap() 0 for RISC-V Date: Tue, 4 Apr 2023 23:50:19 +0530 Message-Id: <20230404182037.863533-6-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404182037.863533-1-sunilvl@ventanamicro.com> References: <20230404182037.863533-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762271136018745152?= X-GMAIL-MSGID: =?utf-8?q?1762271136018745152?= Without this, if the tables are larger than 4K, acpi_map() will fail. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki --- drivers/acpi/osl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/acpi/osl.c b/drivers/acpi/osl.c index 3269a888fb7a..f725813d0cce 100644 --- a/drivers/acpi/osl.c +++ b/drivers/acpi/osl.c @@ -276,7 +276,7 @@ acpi_map_lookup_virt(void __iomem *virt, acpi_size size) return NULL; } -#if defined(CONFIG_IA64) || defined(CONFIG_ARM64) +#if defined(CONFIG_IA64) || defined(CONFIG_ARM64) || defined(CONFIG_RISCV) /* ioremap will take care of cache attributes */ #define should_use_kmap(pfn) 0 #else From patchwork Tue Apr 4 18:20:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 79347 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp86306vqo; Tue, 4 Apr 2023 11:39:44 -0700 (PDT) X-Google-Smtp-Source: AKy350b0lvb0m6h7qAsqaMi9oZjE0QEqmR5TB0fRnHnEyR/lFzvX1SP7vy3qQ90ClwHVn+jfQH7d X-Received: by 2002:a17:90b:1a86:b0:23f:7c82:2463 with SMTP id ng6-20020a17090b1a8600b0023f7c822463mr4275562pjb.9.1680633584097; Tue, 04 Apr 2023 11:39:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680633584; cv=none; d=google.com; s=arc-20160816; b=mW/Ed2ipojJ+v3cr1Rg8bcNIETaqclr3KQg7st49QecOCCpzn4IIn8oQr3oUZdjCWx +FECLBH3uigKAyElTWC92R/KYhddEuF/cmVNnw5yUN8OOn/vyh+1SuTrIt8/8eaJZfrP TMeWJxhpKNfv6Wd5tR/MJh8XL17/A4vemUQtSyy9imqjJzvrB2JzzAgdVbIvU/25KiZ/ TrXg7pK5pTNcK2ZL8klVpjxjcbCQAx3F+kJ/t2ginfbmBe+jmqHIenozb0wGGFpnIglf WnN2ISdjyl3dvyIQVJIDqyUIco3OSXO8uJ/Mlge+VEQa4X87vJ/3fUyB9taH+DzTyTGb Wv7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=uqq/+mqg8UwDMWxfTXWuuu6Kd1C3xGQm+w9MMHsOatM=; b=kj/ZhyjsQfI+FQi1Er7Tsfru7SrT1lFBAp7evFlyxpIht1XMlBBpiQjwHYWR3p4gJ8 UWwG7D2KmSNmmJAC+ahfpCvlJk2plcmotW0L0fZnzQtk4At2daoRTAonrKsvoo9gMoSa 32eQtpoPx2Nm5byKZ53CJBBCqSa4loy9L5FFdXLHcWZBHk8uFWj17Bc0Vlz9NJmkiyeT 08FSSxdIBsuMf4zAtu6g26q9oWvb69UOOs8wTiTnxNLiF9u13S4ylcNSGzvRXwEplmYg 6Bx+7cJlFsq/NJYX0W4gL9mSmsNL5ZKpVgIllbz2XNvX8i3VkyRfh5RuzWof0sbtFwjU Y+zw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=o78b340K; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , "David S . Miller" , Sunil V L , "Rafael J . Wysocki" , Andrew Jones , Conor Dooley Subject: [PATCH V4 06/23] RISC-V: Add support to build the ACPI core Date: Tue, 4 Apr 2023 23:50:20 +0530 Message-Id: <20230404182037.863533-7-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404182037.863533-1-sunilvl@ventanamicro.com> References: <20230404182037.863533-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762272040709079346?= X-GMAIL-MSGID: =?utf-8?q?1762272040709079346?= Enable ACPI core for RISC-V after adding architecture-specific interfaces and header files required to build the ACPI core. 1) Couple of header files are required unconditionally by the ACPI core. Add empty acenv.h and cpu.h header files. 2) If CONFIG_PCI is enabled, a few PCI related interfaces need to be provided by the architecture. Define dummy interfaces for now so that build succeeds. Actual implementation will be added when PCI support is added for ACPI along with external interrupt controller support. 3) A few globals and memory mapping related functions specific to the architecture need to be provided. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley Reviewed-by: Palmer Dabbelt --- arch/riscv/Kconfig | 5 +++ arch/riscv/include/asm/acenv.h | 11 +++++ arch/riscv/include/asm/acpi.h | 61 ++++++++++++++++++++++++++ arch/riscv/include/asm/cpu.h | 8 ++++ arch/riscv/kernel/Makefile | 2 + arch/riscv/kernel/acpi.c | 80 ++++++++++++++++++++++++++++++++++ 6 files changed, 167 insertions(+) create mode 100644 arch/riscv/include/asm/acenv.h create mode 100644 arch/riscv/include/asm/acpi.h create mode 100644 arch/riscv/include/asm/cpu.h create mode 100644 arch/riscv/kernel/acpi.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 139055bcfcae..710037f7ca0a 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -12,6 +12,8 @@ config 32BIT config RISCV def_bool y + select ACPI_GENERIC_GSI if ACPI + select ACPI_REDUCED_HARDWARE_ONLY if ACPI select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE @@ -639,6 +641,7 @@ config EFI depends on OF && !XIP_KERNEL depends on MMU default y + select ARCH_SUPPORTS_ACPI if 64BIT select EFI_GENERIC_STUB select EFI_PARAMS_FROM_FDT select EFI_RUNTIME_WRAPPERS @@ -742,3 +745,5 @@ source "drivers/cpufreq/Kconfig" endmenu # "CPU Power Management" source "arch/riscv/kvm/Kconfig" + +source "drivers/acpi/Kconfig" diff --git a/arch/riscv/include/asm/acenv.h b/arch/riscv/include/asm/acenv.h new file mode 100644 index 000000000000..43ae2e32c779 --- /dev/null +++ b/arch/riscv/include/asm/acenv.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * RISC-V specific ACPICA environments and implementation + */ + +#ifndef _ASM_ACENV_H +#define _ASM_ACENV_H + +/* This header is required unconditionally by the ACPI core */ + +#endif /* _ASM_ACENV_H */ diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h new file mode 100644 index 000000000000..bcade255bd6e --- /dev/null +++ b/arch/riscv/include/asm/acpi.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2013-2014, Linaro Ltd. + * Author: Al Stone + * Author: Graeme Gregory + * Author: Hanjun Guo + * + * Copyright (C) 2021-2023, Ventana Micro Systems Inc. + * Author: Sunil V L + */ + +#ifndef _ASM_ACPI_H +#define _ASM_ACPI_H + +/* Basic configuration for ACPI */ +#ifdef CONFIG_ACPI + +/* ACPI table mapping after acpi_permanent_mmap is set */ +void *acpi_os_ioremap(acpi_physical_address phys, acpi_size size); +#define acpi_os_ioremap acpi_os_ioremap + +#define acpi_strict 1 /* No out-of-spec workarounds on RISC-V */ +extern int acpi_disabled; +extern int acpi_noirq; +extern int acpi_pci_disabled; + +static inline void disable_acpi(void) +{ + acpi_disabled = 1; + acpi_pci_disabled = 1; + acpi_noirq = 1; +} + +static inline void enable_acpi(void) +{ + acpi_disabled = 0; + acpi_pci_disabled = 0; + acpi_noirq = 0; +} + +/* + * The ACPI processor driver for ACPI core code needs this macro + * to find out whether this cpu was already mapped (mapping from CPU hardware + * ID to CPU logical ID) or not. + */ +#define cpu_physical_id(cpu) cpuid_to_hartid_map(cpu) + +/* + * Since MADT must provide at least one RINTC structure, the + * CPU will be always available in MADT on RISC-V. + */ +static inline bool acpi_has_cpu_in_madt(void) +{ + return true; +} + +static inline void arch_fix_phys_package_id(int num, u32 slot) { } + +#endif /* CONFIG_ACPI */ + +#endif /*_ASM_ACPI_H*/ diff --git a/arch/riscv/include/asm/cpu.h b/arch/riscv/include/asm/cpu.h new file mode 100644 index 000000000000..28d45a6678ce --- /dev/null +++ b/arch/riscv/include/asm/cpu.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _ASM_CPU_H +#define _ASM_CPU_H + +/* This header is required unconditionally by the ACPI core */ + +#endif /* _ASM_CPU_H */ diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 67f542be1bea..8ce334f6932f 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -90,3 +90,5 @@ obj-$(CONFIG_EFI) += efi.o obj-$(CONFIG_COMPAT) += compat_syscall_table.o obj-$(CONFIG_COMPAT) += compat_signal.o obj-$(CONFIG_COMPAT) += compat_vdso/ + +obj-$(CONFIG_ACPI) += acpi.o diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c new file mode 100644 index 000000000000..81d448c41714 --- /dev/null +++ b/arch/riscv/kernel/acpi.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * RISC-V Specific Low-Level ACPI Boot Support + * + * Copyright (C) 2013-2014, Linaro Ltd. + * Author: Al Stone + * Author: Graeme Gregory + * Author: Hanjun Guo + * Author: Tomasz Nowicki + * Author: Naresh Bhat + * + * Copyright (C) 2021-2023, Ventana Micro Systems Inc. + * Author: Sunil V L + */ + +#include +#include +#include + +int acpi_noirq = 1; /* skip ACPI IRQ initialization */ +int acpi_disabled = 1; +EXPORT_SYMBOL(acpi_disabled); + +int acpi_pci_disabled = 1; /* skip ACPI PCI scan and IRQ initialization */ +EXPORT_SYMBOL(acpi_pci_disabled); + +/* + * __acpi_map_table() will be called before paging_init(), so early_ioremap() + * or early_memremap() should be called here to for ACPI table mapping. + */ +void __init __iomem *__acpi_map_table(unsigned long phys, unsigned long size) +{ + if (!size) + return NULL; + + return early_memremap(phys, size); +} + +void __init __acpi_unmap_table(void __iomem *map, unsigned long size) +{ + if (!map || !size) + return; + + early_memunmap(map, size); +} + +void *acpi_os_ioremap(acpi_physical_address phys, acpi_size size) +{ + return memremap(phys, size, MEMREMAP_WB); +} + +#ifdef CONFIG_PCI + +/* + * These interfaces are defined just to enable building ACPI core. + * TODO: Update it with actual implementation when external interrupt + * controller support is added in RISC-V ACPI. + */ +int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, + int reg, int len, u32 *val) +{ + return PCIBIOS_DEVICE_NOT_FOUND; +} + +int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, + int reg, int len, u32 val) +{ + return PCIBIOS_DEVICE_NOT_FOUND; +} + +int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) +{ + return -1; +} + +struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) +{ + return NULL; +} +#endif /* CONFIG_PCI */ From patchwork Tue Apr 4 18:20:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 79330 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp78282vqo; Tue, 4 Apr 2023 11:24:57 -0700 (PDT) X-Google-Smtp-Source: AKy350ZZBOM9hPgkVsMj81ISwYPB67hBgQgOzDc77s00EbAP9NqCD3IZSIXXaA58VYXPXibyvKSE X-Received: by 2002:a05:6a20:bca9:b0:da:2d16:db8c with SMTP id fx41-20020a056a20bca900b000da2d16db8cmr3027331pzb.35.1680632696953; Tue, 04 Apr 2023 11:24:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680632696; cv=none; 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Wysocki" , "David S . Miller" , Sunil V L , "Rafael J . Wysocki" , Andrew Jones Subject: [PATCH V4 07/23] ACPI: processor_core: RISC-V: Enable mapping processor to the hartid Date: Tue, 4 Apr 2023 23:50:21 +0530 Message-Id: <20230404182037.863533-8-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404182037.863533-1-sunilvl@ventanamicro.com> References: <20230404182037.863533-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762271110862768504?= X-GMAIL-MSGID: =?utf-8?q?1762271110862768504?= processor_core needs arch-specific functions to map the ACPI ID to the physical ID. In RISC-V platforms, hartid is the physical id and RINTC structure in MADT provides this mapping. Add arch-specific function to get this mapping from RINTC. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones --- arch/riscv/include/asm/acpi.h | 3 +++ drivers/acpi/processor_core.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index bcade255bd6e..9be52b6ffae1 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -15,6 +15,9 @@ /* Basic configuration for ACPI */ #ifdef CONFIG_ACPI +typedef u64 phys_cpuid_t; +#define PHYS_CPUID_INVALID INVALID_HARTID + /* ACPI table mapping after acpi_permanent_mmap is set */ void *acpi_os_ioremap(acpi_physical_address phys, acpi_size size); #define acpi_os_ioremap acpi_os_ioremap diff --git a/drivers/acpi/processor_core.c b/drivers/acpi/processor_core.c index 2ac48cda5b20..d6606a9f2da6 100644 --- a/drivers/acpi/processor_core.c +++ b/drivers/acpi/processor_core.c @@ -106,6 +106,32 @@ static int map_gicc_mpidr(struct acpi_subtable_header *entry, return -EINVAL; } +/* + * Retrieve the RISC-V hartid for the processor + */ +static int map_rintc_hartid(struct acpi_subtable_header *entry, + int device_declaration, u32 acpi_id, + phys_cpuid_t *hartid) +{ + struct acpi_madt_rintc *rintc = + container_of(entry, struct acpi_madt_rintc, header); + + if (!(rintc->flags & ACPI_MADT_ENABLED)) + return -ENODEV; + + /* device_declaration means Device object in DSDT, in the + * RISC-V, logical processors are required to + * have a Processor Device object in the DSDT, so we should + * check device_declaration here + */ + if (device_declaration && rintc->uid == acpi_id) { + *hartid = rintc->hart_id; + return 0; + } + + return -EINVAL; +} + static phys_cpuid_t map_madt_entry(struct acpi_table_madt *madt, int type, u32 acpi_id) { @@ -136,6 +162,9 @@ static phys_cpuid_t map_madt_entry(struct acpi_table_madt *madt, } else if (header->type == ACPI_MADT_TYPE_GENERIC_INTERRUPT) { if (!map_gicc_mpidr(header, type, acpi_id, &phys_id)) break; + } else if (header->type == ACPI_MADT_TYPE_RINTC) { + if (!map_rintc_hartid(header, type, acpi_id, &phys_id)) + break; } entry += header->length; } From patchwork Tue Apr 4 18:20:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 79334 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp78508vqo; Tue, 4 Apr 2023 11:25:24 -0700 (PDT) X-Google-Smtp-Source: AKy350aCnuBmyzw+hyNF5SGBFnrwAp7HMkp63cfj5dC6itHo7O1rZuAzu7ERIG9G9z3YdbruFQfW X-Received: by 2002:a17:90b:4a4b:b0:23d:1fc0:dd1f with SMTP id lb11-20020a17090b4a4b00b0023d1fc0dd1fmr3559127pjb.38.1680632724368; Tue, 04 Apr 2023 11:25:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680632724; cv=none; d=google.com; s=arc-20160816; b=SiuHvgz3wVTDay0iEWtAtQzhPxMwT3qVhVRgCaHIrWUExVUbRjzCfWBxs6vMYvzEXG FXwNf6wVS7uwHk0rzXERyAbFr0OBtijHyCcp4eB55eSL+Qb8a1+Zhsc2pq9QQLHJ2Y5a n72bKvXOZ3PVozUe/aHqtV7xkLYHyAdhF23SIA8YPHcMMPupdMZVCCkbi3gjvIWnAslY EK1TsA9F8cZSl34ZPa9ygyVo5lThpfpZixUvpMV5T9QKfuB9TAyJhnX1kHjBl25Pl4BM yjMYgexajqcF1RiO9LdXmGvjMgA6a0WpnNFyvqBn0ZNkRW9g57cW+mDKZyxJPRoFu9lu zlKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=sK3yofAaBPCm3lmjxfNqOeEWtEi7+pbDB/M30NYTLb4=; b=0mAOHbf6B9Lbmb47rikvwAiYfuc9cPqCj41MExIVfQbssIN2grUhaFbNPd7sxTnJfT i8fu7lPqmVDBVW4TbPvDXAd25mFe1LSjeAxruyRt01j0WFBeP82rFXSf0mm1bL6upQv6 XUeHSzEfrM0ZVQ621McBBK5t0XqVHs7ZQ7C/LXTpIadBOBmmH2l+gkbnoiStklLucUM8 phSmn/k66Koj8bSO6uXr86D+U529YYfVgRZ4XCQE2iwPEyWsdibShl9hR/dOS5wVwLxy /yz45AEUlwT3LrDScaYAtlCRBN1AWkmRlBriO6mzSr2/4ODQS8s4Af2ahWNm2McuzOZs 1q+A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=JtyGYEmj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , "David S . Miller" , Sunil V L , "Rafael J . Wysocki" Subject: [PATCH V4 08/23] RISC-V: ACPI: Cache and retrieve the RINTC structure Date: Tue, 4 Apr 2023 23:50:22 +0530 Message-Id: <20230404182037.863533-9-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404182037.863533-1-sunilvl@ventanamicro.com> References: <20230404182037.863533-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762271139292771558?= X-GMAIL-MSGID: =?utf-8?q?1762271139292771558?= RINTC structures in the MADT provide mapping between the hartid and the CPU. This is required many times even at run time like cpuinfo. So, instead of parsing the ACPI table every time, cache the RINTC structures and provide a function to get the correct RINTC structure for a given cpu. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones --- arch/riscv/include/asm/acpi.h | 2 ++ arch/riscv/kernel/acpi.c | 60 +++++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+) diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index 9be52b6ffae1..1606dce8992e 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -59,6 +59,8 @@ static inline bool acpi_has_cpu_in_madt(void) static inline void arch_fix_phys_package_id(int num, u32 slot) { } +struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu); +u32 get_acpi_id_for_cpu(int cpu); #endif /* CONFIG_ACPI */ #endif /*_ASM_ACPI_H*/ diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c index 81d448c41714..40ab55309c70 100644 --- a/arch/riscv/kernel/acpi.c +++ b/arch/riscv/kernel/acpi.c @@ -24,6 +24,66 @@ EXPORT_SYMBOL(acpi_disabled); int acpi_pci_disabled = 1; /* skip ACPI PCI scan and IRQ initialization */ EXPORT_SYMBOL(acpi_pci_disabled); +static struct acpi_madt_rintc cpu_madt_rintc[NR_CPUS]; + +static int acpi_parse_madt_rintc(union acpi_subtable_headers *header, const unsigned long end) +{ + struct acpi_madt_rintc *rintc = (struct acpi_madt_rintc *)header; + int cpuid; + + if (!(rintc->flags & ACPI_MADT_ENABLED)) + return 0; + + cpuid = riscv_hartid_to_cpuid(rintc->hart_id); + /* + * When CONFIG_SMP is disabled, mapping won't be created for + * all cpus. + * CPUs more than NR_CPUS, will be ignored. + */ + if (cpuid >= 0 && cpuid < NR_CPUS) + cpu_madt_rintc[cpuid] = *rintc; + + return 0; +} + +static int acpi_init_rintc_array(void) +{ + if (acpi_table_parse_madt(ACPI_MADT_TYPE_RINTC, acpi_parse_madt_rintc, 0) > 0) + return 0; + + return -ENODEV; +} + +/* + * Instead of parsing (and freeing) the ACPI table, cache + * the RINTC structures since they are frequently used + * like in cpuinfo. + */ +struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu) +{ + static bool rintc_init_done; + + if (!rintc_init_done) { + if (acpi_init_rintc_array()) { + pr_err("No valid RINTC entries exist\n"); + return NULL; + } + + rintc_init_done = true; + } + + return &cpu_madt_rintc[cpu]; +} + +u32 get_acpi_id_for_cpu(int cpu) +{ + struct acpi_madt_rintc *rintc = acpi_cpu_get_madt_rintc(cpu); + + BUG_ON(!rintc); + + return rintc->uid; +} + /* * __acpi_map_table() will be called before paging_init(), so early_ioremap() * or early_memremap() should be called here to for ACPI table mapping. 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Wysocki" , "David S . Miller" , Sunil V L , "Rafael J . Wysocki" , Andrew Jones Subject: [PATCH V4 09/23] drivers/acpi: RISC-V: Add RHCT related code Date: Tue, 4 Apr 2023 23:50:23 +0530 Message-Id: <20230404182037.863533-10-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404182037.863533-1-sunilvl@ventanamicro.com> References: <20230404182037.863533-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762271130793870385?= X-GMAIL-MSGID: =?utf-8?q?1762271130793870385?= RHCT is a new table defined for RISC-V to communicate the features of the CPU to the OS. Create a new architecture folder in drivers/acpi and add RHCT parsing code. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Reviewed-by: Palmer Dabbelt --- arch/riscv/include/asm/acpi.h | 9 ++++ drivers/acpi/Makefile | 2 + drivers/acpi/riscv/Makefile | 2 + drivers/acpi/riscv/rhct.c | 83 +++++++++++++++++++++++++++++++++++ 4 files changed, 96 insertions(+) create mode 100644 drivers/acpi/riscv/Makefile create mode 100644 drivers/acpi/riscv/rhct.c diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index 1606dce8992e..2b3e78d5a13b 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -61,6 +61,15 @@ static inline void arch_fix_phys_package_id(int num, u32 slot) { } struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu); u32 get_acpi_id_for_cpu(int cpu); +int acpi_get_riscv_isa(struct acpi_table_header *table, + unsigned int cpu, const char **isa); +#else +static inline int acpi_get_riscv_isa(struct acpi_table_header *table, + unsigned int cpu, const char **isa) +{ + return -EINVAL; +} + #endif /* CONFIG_ACPI */ #endif /*_ASM_ACPI_H*/ diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile index feb36c0b9446..3fc5a0d54f6e 100644 --- a/drivers/acpi/Makefile +++ b/drivers/acpi/Makefile @@ -131,3 +131,5 @@ obj-y += dptf/ obj-$(CONFIG_ARM64) += arm64/ obj-$(CONFIG_ACPI_VIOT) += viot.o + +obj-$(CONFIG_RISCV) += riscv/ diff --git a/drivers/acpi/riscv/Makefile b/drivers/acpi/riscv/Makefile new file mode 100644 index 000000000000..8b3b126e0b94 --- /dev/null +++ b/drivers/acpi/riscv/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-y += rhct.o diff --git a/drivers/acpi/riscv/rhct.c b/drivers/acpi/riscv/rhct.c new file mode 100644 index 000000000000..ea78d906a0fe --- /dev/null +++ b/drivers/acpi/riscv/rhct.c @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022-2023, Ventana Micro Systems Inc + * Author: Sunil V L + * + */ + +#define pr_fmt(fmt) "ACPI: RHCT: " fmt + +#include + +static struct acpi_table_header *acpi_get_rhct(void) +{ + static struct acpi_table_header *rhct; + acpi_status status; + + /* + * RHCT will be used at runtime on every CPU, so we + * don't need to call acpi_put_table() to release the table mapping. + */ + if (!rhct) { + status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct); + if (ACPI_FAILURE(status)) { + pr_warn_once("No RHCT table found\n"); + return NULL; + } + } + + return rhct; +} + +/* + * During early boot, the caller should call acpi_get_table() and pass its pointer to + * these functions(and free up later). At run time, since this table can be used + * multiple times, NULL may be passed in order to use the cached table. + */ +int acpi_get_riscv_isa(struct acpi_table_header *table, unsigned int cpu, const char **isa) +{ + struct acpi_rhct_node_header *node, *ref_node, *end; + u32 size_hdr = sizeof(struct acpi_rhct_node_header); + u32 size_hartinfo = sizeof(struct acpi_rhct_hart_info); + struct acpi_rhct_hart_info *hart_info; + struct acpi_rhct_isa_string *isa_node; + struct acpi_table_rhct *rhct; + u32 *hart_info_node_offset; + u32 acpi_cpu_id = get_acpi_id_for_cpu(cpu); + + BUG_ON(acpi_disabled); + + if (!table) { + rhct = (struct acpi_table_rhct *)acpi_get_rhct(); + if (!rhct) + return -ENOENT; + } else { + rhct = (struct acpi_table_rhct *)table; + } + + end = ACPI_ADD_PTR(struct acpi_rhct_node_header, rhct, rhct->header.length); + + for (node = ACPI_ADD_PTR(struct acpi_rhct_node_header, rhct, rhct->node_offset); + node < end; + node = ACPI_ADD_PTR(struct acpi_rhct_node_header, node, node->length)) { + if (node->type == ACPI_RHCT_NODE_TYPE_HART_INFO) { + hart_info = ACPI_ADD_PTR(struct acpi_rhct_hart_info, node, size_hdr); + hart_info_node_offset = ACPI_ADD_PTR(u32, hart_info, size_hartinfo); + if (acpi_cpu_id != hart_info->uid) + continue; + + for (int i = 0; i < hart_info->num_offsets; i++) { + ref_node = ACPI_ADD_PTR(struct acpi_rhct_node_header, + rhct, hart_info_node_offset[i]); + if (ref_node->type == ACPI_RHCT_NODE_TYPE_ISA_STRING) { + isa_node = ACPI_ADD_PTR(struct acpi_rhct_isa_string, + ref_node, size_hdr); + *isa = isa_node->isa; + return 0; + } + } + } + } + + return -1; +} From patchwork Tue Apr 4 18:20:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 79335 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp78674vqo; Tue, 4 Apr 2023 11:25:43 -0700 (PDT) X-Google-Smtp-Source: AKy350bfOJBFJIuVNez0OaqOW9yekpUfL2U68oyeXyFsqdMGqAs1f2lrC2ih3f3LWuEa37RnN3nD X-Received: by 2002:a17:902:da92:b0:1a2:1a5b:cc6a with SMTP id j18-20020a170902da9200b001a21a5bcc6amr4529080plx.40.1680632742894; Tue, 04 Apr 2023 11:25:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680632742; cv=none; d=google.com; s=arc-20160816; b=zgT9Lgvdt/9ZoaZfyV6FJNbBX/jMuKReF+toqRqEd+m+ILuUgzj/FXr9cZrzI6vD4x vqlK5n3p/uw2wC+YxqRLfcpPsup+cCBPa0D0vTD29DrZjqP6KCoyHf+YVEVyf3Fbj0Oj iv8nQ3Qg8/NYuRw6gk/cJjr4H7yzVyni68cwXUkgTLtWAxw0zZv9578ICL6g2W2rJEnn Jga2BfQuqPQP+QG/jHYciWkjj/nvl4i/MGQAHco3NKkZAbU0pNMWal3/v5Da2dbvu00m RniyKG5PtZaDd6IndInSXF79paVQ6YTCOLX+QZL35Ji7bmvkq6dMkU9a28V8Z10FHz6E SaUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=5pi8xH0IxXrFGj4CxsC9boyEOiTx1Qa4CmKA7c/Mr88=; b=cbTy/OMVLCkyp+nwo4rZqr7xsbbmeuha8IjW4JTYKcGUIa0OGyewIaziejrNEKm6aj rbGI3EIOyUDWVWEuf2xEUtSuV980TyRDQZ8Pc4KBPTtJ2R8VOclnBRhSSLIdQIGtunn9 MMy1pchEJJSTgT1TCjYLB6+bN3l2ezYqS6o/kMJkV5XnyH+L70qCUg8h1zklqvSXfHzc spvYTD5y3HP/Nbj31q6CofQj4ch6O8mDeemDXl6rZDjbXVoRsp4acFvl1eDBSkKslSFd TKQvTL8d+xWNf01YnkM6aRsYs+0ARLr2os2C2ZtzN2jzw4y7t17Z/AO/ABtF7sn3sL3b Nf6Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=NrI6ACm7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , "David S . Miller" , Sunil V L , "Rafael J . Wysocki" , Conor Dooley , Andrew Jones Subject: [PATCH V4 10/23] RISC-V: smpboot: Create wrapper smp_setup() Date: Tue, 4 Apr 2023 23:50:24 +0530 Message-Id: <20230404182037.863533-11-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404182037.863533-1-sunilvl@ventanamicro.com> References: <20230404182037.863533-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762271158831009239?= X-GMAIL-MSGID: =?utf-8?q?1762271158831009239?= smp_setup() currently assumes DT-based platforms. To enable ACPI, first make this a wrapper function and move existing code to a separate DT-specific function. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Conor Dooley Reviewed-by: Andrew Jones Reviewed-by: Palmer Dabbelt --- arch/riscv/kernel/smpboot.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 00b53913d4c6..26214ddefaa4 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -70,7 +70,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus) } } -void __init setup_smp(void) +static void __init of_parse_and_init_cpus(void) { struct device_node *dn; unsigned long hart; @@ -116,6 +116,11 @@ void __init setup_smp(void) } } +void __init setup_smp(void) +{ + of_parse_and_init_cpus(); +} + static int start_secondary_cpu(int cpu, struct task_struct *tidle) { if (cpu_ops[cpu]->cpu_start) From patchwork Tue Apr 4 18:20:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 79340 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp79073vqo; Tue, 4 Apr 2023 11:26:33 -0700 (PDT) X-Google-Smtp-Source: AKy350bgdI3sfM5mcymKuNpZY5vva0t51fpXREAeD/KFJMYbaZfrrxExxXqEnvOu01DA/2SpAoAF X-Received: by 2002:a05:6a00:1948:b0:627:de16:889c with SMTP id s8-20020a056a00194800b00627de16889cmr84276pfk.4.1680632793597; Tue, 04 Apr 2023 11:26:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680632793; cv=none; d=google.com; s=arc-20160816; b=O90edNepOmY54gH+2HXbdMk9hwc+TDOVYtJRmqN0ejoNxdoAMZZG1e3Z3I2paD/hPw r9Oqp/OpBZKIf2FAM+dIZAhrD2pzpZ41e5181NjvgjNjW4GoQF3mLZEDyWRY5VEIoyx3 8noi7tbmttBksuyweCRUfMJck9w3v0sxNSY1jWnairTxxxoS3UKaPfpTy6gpWot43Jmx Rxtllpg/ooaZQl6uN2w4/nk1Uc2kfx8wiegERma3AYK0i3KOp7QJjjokdQxgB79KoscK dQPhceio03a/xIad+X2iWJevOUEnxtYR/hEt7vbVGnGRuDX8zuToZmaF7DHycYqe0hnK nUVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=XGonri/T19XQF2naGXJvqqLnbSM1YN1GWyJxGmsm0G8=; b=j5VJb3CiBhV/us6jJ7ouCX9sJpQJiL5OqMiFSPFD52iA5ZOWpDvsltu7c72CS8RsUE EgkO5Nvu+cDVp4OMeGcvemMRKOHp0tphPUHiyM9FwhH2AzZm4hsw/CcZGZr9RCchGMs9 ZCP+iQEQyRV5jMcBljOPCZ8o9x5kLl+N3NpbmrvykDTTzdSsWdp+8FI0/09MZEIwYESa KtIKaFwMs4TUz5cIzCbiryYFv5c6EyS41ICkl4HNsvT7TnyXFZ68dzdONrivxkeEgS5W 4E61zejSvasrYEhR2siXieXFjPe6ELAO4ki6DsFIbwrICXikhMmXLOUbDG6ane8McL13 zsgg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=jlU6cVDR; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , "David S . Miller" , Sunil V L , "Rafael J . Wysocki" , Conor Dooley Subject: [PATCH V4 11/23] RISC-V: smpboot: Add ACPI support in smp_setup() Date: Tue, 4 Apr 2023 23:50:25 +0530 Message-Id: <20230404182037.863533-12-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404182037.863533-1-sunilvl@ventanamicro.com> References: <20230404182037.863533-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762271211738657201?= X-GMAIL-MSGID: =?utf-8?q?1762271211738657201?= Enable SMP boot on ACPI based platforms by using the RINTC structures in the MADT table. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Conor Dooley Reviewed-by: Andrew Jones --- arch/riscv/include/asm/acpi.h | 2 + arch/riscv/kernel/smpboot.c | 72 ++++++++++++++++++++++++++++++++++- 2 files changed, 73 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index 2b3e78d5a13b..b26ba911f0a9 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -63,6 +63,8 @@ struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu); u32 get_acpi_id_for_cpu(int cpu); int acpi_get_riscv_isa(struct acpi_table_header *table, unsigned int cpu, const char **isa); + +static inline int acpi_numa_get_nid(unsigned int cpu) { return NUMA_NO_NODE; } #else static inline int acpi_get_riscv_isa(struct acpi_table_header *table, unsigned int cpu, const char **isa) diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 26214ddefaa4..6a854b200b72 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -8,6 +8,7 @@ * Copyright (C) 2017 SiFive */ +#include #include #include #include @@ -70,6 +71,72 @@ void __init smp_prepare_cpus(unsigned int max_cpus) } } +#ifdef CONFIG_ACPI +static unsigned int cpu_count = 1; + +static int __init acpi_parse_rintc(union acpi_subtable_headers *header, const unsigned long end) +{ + unsigned long hart; + static bool found_boot_cpu; + struct acpi_madt_rintc *processor = (struct acpi_madt_rintc *)header; + + /* + * Each RINTC structure in MADT will have a flag. If ACPI_MADT_ENABLED + * bit in the flag is not enabled, it means OS should not try to enable + * the cpu to which RINTC belongs. + */ + if (!(processor->flags & ACPI_MADT_ENABLED)) + return 0; + + if (BAD_MADT_ENTRY(processor, end)) + return -EINVAL; + + acpi_table_print_madt_entry(&header->common); + + hart = processor->hart_id; + if (hart == INVALID_HARTID) { + pr_warn("Invalid hartid\n"); + return 0; + } + + if (hart == cpuid_to_hartid_map(0)) { + BUG_ON(found_boot_cpu); + found_boot_cpu = true; + early_map_cpu_to_node(0, acpi_numa_get_nid(cpu_count)); + return 0; + } + + if (cpu_count >= NR_CPUS) { + pr_warn("NR_CPUS is too small for the number of ACPI tables.\n"); + return 0; + } + + cpuid_to_hartid_map(cpu_count) = hart; + early_map_cpu_to_node(cpu_count, acpi_numa_get_nid(cpu_count)); + cpu_count++; + + return 0; +} + +static void __init acpi_parse_and_init_cpus(void) +{ + int cpuid; + + cpu_set_ops(0); + + acpi_table_parse_madt(ACPI_MADT_TYPE_RINTC, acpi_parse_rintc, 0); + + for (cpuid = 1; cpuid < nr_cpu_ids; cpuid++) { + if (cpuid_to_hartid_map(cpuid) != INVALID_HARTID) { + cpu_set_ops(cpuid); + set_cpu_possible(cpuid, true); + } + } +} +#else +#define acpi_parse_and_init_cpus(...) do { } while (0) +#endif + static void __init of_parse_and_init_cpus(void) { struct device_node *dn; @@ -118,7 +185,10 @@ static void __init of_parse_and_init_cpus(void) void __init setup_smp(void) { - of_parse_and_init_cpus(); + if (acpi_disabled) + of_parse_and_init_cpus(); + else + acpi_parse_and_init_cpus(); } static int start_secondary_cpu(int cpu, struct task_struct *tidle) From patchwork Tue Apr 4 18:20:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 79339 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp79056vqo; Tue, 4 Apr 2023 11:26:32 -0700 (PDT) X-Google-Smtp-Source: AKy350YvKVEhjIk+v7mZ0fylFBZbbSuRjZXHRDFJmdhFx++Dced4TVR35psCf6gPGa1xLXYm8TEe X-Received: by 2002:a17:902:cec5:b0:1a1:e364:3452 with SMTP id d5-20020a170902cec500b001a1e3643452mr4582191plg.29.1680632791957; Tue, 04 Apr 2023 11:26:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680632791; cv=none; d=google.com; s=arc-20160816; b=iVMONKG/zOTjs1ypzSs/AwbPUOqyZNflbUsMgP2VsF9YD+nw+ksANEnduCaJPayB7T 7//+2fLc6bRNxHAnJPjHjrSMNtWKKO0StK+PGNN2I4SQU/TlzEvy6HVT8Ke3ZZnt/DV2 IJDVoAFBAer3kuUu1zAJfgZscQXNT4XsRaAmXNKP094Gsn7VIFme8rROF44rrdYL4G/i z/TIjudlJmH49lfF29LHmmB5oP6d4UINltSWbs6/9QOjD/JsWbTequMmHOrmN2MM/MkX bEe31Pw6aQboJiK4WXQ52uo9rEwt8Og3vJHPAyYMvS7co8/1MaJNDqS+Z5ZYTmk9uXyQ 2ybg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=vOfAYG3XRnm+elp9Rz4INSxNTdbKknHW/6eObzO7hi8=; b=LPgW8NLXVW0S5Z4Fz6coOpStl3jNXmWyZhlgSYpp+pcDKgDAJVcdQDSf85q97VbQld sOur9QODiuBgTaTcKHzCiuJwj/I2UcfJ95ipyFueeVDytvAI2KJ/Wnv7OoAxgvISQiID REEJ7MtVRSOEZToTvZixw5XlcwOqX/Yi6zOSY4rdVBoV74oA50HYQaU8vQj7VFOIMQYI 6hpEVHJhg7PXfT1UBBkOVh6yeHrA13yaCCXSVN6snCdNTGJBkdMuPdqjQQIZ0BlLSt6r SF5fZCA5cvEZQExiqp0TX8zOtWD7v/ySqyPbLuF4YZyrWrZ7leGCwDrkFreTSMsh8b5r 1EhQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=L8YECRNq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , "David S . Miller" , Sunil V L Subject: [PATCH V4 12/23] RISC-V: cpufeature: Avoid calling riscv_of_processor_hartid() Date: Tue, 4 Apr 2023 23:50:26 +0530 Message-Id: <20230404182037.863533-13-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404182037.863533-1-sunilvl@ventanamicro.com> References: <20230404182037.863533-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762271210077939539?= X-GMAIL-MSGID: =?utf-8?q?1762271210077939539?= riscv_fill_hwcap() finds hartid of each cpu but never really uses it. So, remove this unnecessary call. Signed-off-by: Sunil V L --- arch/riscv/kernel/cpufeature.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 59d58ee0f68d..63e56ce04162 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -91,7 +91,6 @@ void __init riscv_fill_hwcap(void) char print_str[NUM_ALPHA_EXTS + 1]; int i, j, rc; unsigned long isa2hwcap[26] = {0}; - unsigned long hartid; isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I; isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M; @@ -109,10 +108,6 @@ void __init riscv_fill_hwcap(void) DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); const char *temp; - rc = riscv_of_processor_hartid(node, &hartid); - if (rc < 0) - continue; - if (of_property_read_string(node, "riscv,isa", &isa)) { pr_warn("Unable to find \"riscv,isa\" devicetree entry\n"); continue; From patchwork Tue Apr 4 18:20:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 79341 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp79133vqo; Tue, 4 Apr 2023 11:26:41 -0700 (PDT) X-Google-Smtp-Source: AKy350YoQeLZ25fobU8x/caf8hwmpZ65kpgFqvVICeIh2UNNdaoyEuSaSpBzq2E1mL6J5DI+H2Xh X-Received: by 2002:a17:902:e843:b0:1a1:8860:70e5 with SMTP id t3-20020a170902e84300b001a1886070e5mr4527131plg.57.1680632801517; Tue, 04 Apr 2023 11:26:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680632801; cv=none; d=google.com; s=arc-20160816; b=Ijyz5sUIIynUtDPtC8aUajH/TszDmHS202U5d+tftCmaeaBxeZuaUiApsyaS45UUK6 RAzLIZf8CYcOnk1r1yohXX6ubdqb+PVeGuIzHmxIkUw9THITK3b/+kSkHCCoLpYhfhwS 0Gj3yT1D4EFZT/08cGtISYs9UjUFvEbFJrzDq4Nhn+cFpEDpOJX+7HiOCc36JFPmD4fA NfD/LkSsI7tOzaTgOZNjbGLCJCyMNE1xYFWGhWM16HRmdHzXZXr3E53XxWvlDgpRW/0w 9LDiYFvvH2IgWIdxkn8IgF84KFfsGVn9o3BMG/+Rm7RcoUcWByH91pIEhHXUNDpOQ54A aKkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=A0yVz+rx5mJyuV/igvCpVezJBLvGHPHOHFjhwqh4528=; b=OGjs7/1HzkPukeQgxZemdzQVgKwzIEa2uo43kkIK0E9KtLfLtJNoKb5N+r2UqtDsKd 0sPTyn7meO7xL31JBxGL70FevjhBmPdSrQVS9gU+t4KTlNb2DMJwybZHDjDNSnCKS9G9 zKXfdsfR9Lem3ckX+I8KMpMBHlZEv3XJpc/E7tHH7pFj3ok7Lw6hlk8IkSnuCmVCV+pO UzvnQddnA3E/huCsA94AUbpVzKOH4K/LteuWonmmOmxDs0kUH90JOtvg92jDXUp/aquH U28v6bKgU/EDDYLYyxYjwRiUSVjKwhBTDYRM4cNdclm1/FormrUBZOXMhL482VwZqjbd p6Wg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b="oEps0B7/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , "David S . Miller" , Sunil V L , "Rafael J . Wysocki" , Andrew Jones Subject: [PATCH V4 13/23] RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap() Date: Tue, 4 Apr 2023 23:50:27 +0530 Message-Id: <20230404182037.863533-14-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404182037.863533-1-sunilvl@ventanamicro.com> References: <20230404182037.863533-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762271220704345159?= X-GMAIL-MSGID: =?utf-8?q?1762271220704345159?= On ACPI based systems, the information about the hart like ISA is provided by the RISC-V Hart Capabilities Table (RHCT). Enable filling up hwcap structure based on the information in RHCT. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- arch/riscv/kernel/cpufeature.c | 39 ++++++++++++++++++++++++++++++---- 1 file changed, 35 insertions(+), 4 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 63e56ce04162..5d2065b937e5 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -6,6 +6,7 @@ * Copyright (C) 2017 SiFive */ +#include #include #include #include @@ -13,6 +14,8 @@ #include #include #include +#include +#include #include #include #include @@ -91,6 +94,9 @@ void __init riscv_fill_hwcap(void) char print_str[NUM_ALPHA_EXTS + 1]; int i, j, rc; unsigned long isa2hwcap[26] = {0}; + struct acpi_table_header *rhct; + acpi_status status; + unsigned int cpu; isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I; isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M; @@ -103,14 +109,36 @@ void __init riscv_fill_hwcap(void) bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX); - for_each_of_cpu_node(node) { + if (!acpi_disabled) { + status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct); + if (ACPI_FAILURE(status)) + return; + } + + for_each_possible_cpu(cpu) { unsigned long this_hwcap = 0; DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); const char *temp; - if (of_property_read_string(node, "riscv,isa", &isa)) { - pr_warn("Unable to find \"riscv,isa\" devicetree entry\n"); - continue; + if (acpi_disabled) { + node = of_cpu_device_node_get(cpu); + if (node) { + rc = of_property_read_string(node, "riscv,isa", &isa); + of_node_put(node); + if (rc) { + pr_warn("Unable to find \"riscv,isa\" devicetree entry\n"); + continue; + } + } else { + pr_warn("Unable to find cpu node\n"); + continue; + } + } else { + rc = acpi_get_riscv_isa(rhct, cpu, &isa); + if (rc < 0) { + pr_warn("Unable to get ISA for the hart - %d\n", cpu); + continue; + } } temp = isa; @@ -243,6 +271,9 @@ void __init riscv_fill_hwcap(void) bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX); } + if (!acpi_disabled && rhct) + acpi_put_table((struct acpi_table_header *)rhct); + /* We don't support systems with F but without D, so mask those out * here. */ if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) { From patchwork Tue Apr 4 18:20:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 79336 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp78730vqo; Tue, 4 Apr 2023 11:25:51 -0700 (PDT) X-Google-Smtp-Source: AKy350ZWxQBF07Bmqy7td1wYfxEGgIMVetE823q3O7zs/kOTH/qxqnm3L17pWmJlQEP5gFNk/7oq X-Received: by 2002:a05:6a20:8e19:b0:d9:6660:8746 with SMTP id y25-20020a056a208e1900b000d966608746mr40324pzj.18.1680632750886; Tue, 04 Apr 2023 11:25:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680632750; cv=none; d=google.com; s=arc-20160816; b=LngG5nHH2GNyaM2XoSo3IzuywhSnOOpi/44KN5+k5zKizb6AORHlRMcipHaciFfDxs 6BGw1PWs84Q3Od98fXXINljCBci1BUGEtp61Ux0HEFpgkrZ2UmimZe8uIR2nhk1vWmr1 jrk3sLczitUUnVju9wPGgO3JU22es7nCf2xkzGI5+57F0/0DabuiExnq2iPyD2Dv7y7T M+8Z7dtlmkETSzrxUtB5nzca11Kz5S67KZbPQW3RgtzT8DFLqAY2D9Pq5lFnkIqqvWaM Hy8C5UUfiyE+3E3zYkQp8G1vCdNFG6AztHE8Ik3f+zCD3vTALl4X5DltuAj3yAH3mf4c Ctuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=xu/Iz4Gys9b28icQ+yc3gYklUvfwHJ9XRG8B+aoThpM=; b=ssfRBVYcUSaCCLDbcV1HQpkQoBFBzs6JwMrDyA52Moq0vAU959nnyRtoSfvq5n2FeW B5L04y+5ZCB0DWTfvRM3hswoC90W4VsKhaPDrARExGd6dJOyNO9PHFTkMuyThel3tBam q1cyZ9F8Uioq8mapfVsXW2sUdP7GNFkqVtMuSLyf5RaJ0oCF7KO9WlEe0/dT1q88j45K /Qgoq9vo0iotE7WuQGMAsqwmYZmsGBcQYHqehjHk/VAhGfpQxfQ3EM9WwJ7AaXhZFNhz 5wHGbpqIU8pftOI2DTSkz4gevjqaUaxFvpK4aYHtiiBiUCUo3toh9oWDrHSBxGrioXU8 GlQw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=JAHpEivL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , "David S . Miller" , Sunil V L , "Rafael J . Wysocki" , Andrew Jones Subject: [PATCH V4 14/23] RISC-V: cpu: Enable cpuinfo for ACPI systems Date: Tue, 4 Apr 2023 23:50:28 +0530 Message-Id: <20230404182037.863533-15-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404182037.863533-1-sunilvl@ventanamicro.com> References: <20230404182037.863533-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762271167416684663?= X-GMAIL-MSGID: =?utf-8?q?1762271167416684663?= On ACPI based platforms, few details like ISA need to be read from the ACPI table. Enable cpuinfo on ACPI based systems. ACPI has nothing similar to DT compatible property for each CPU. SBI calls must be used to get vendor/arch/imp ID for any errata. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- arch/riscv/kernel/cpu.c | 30 ++++++++++++++++++++++-------- 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 8400f0cc9704..ace4752516d8 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -3,10 +3,12 @@ * Copyright (C) 2012 Regents of the University of California */ +#include #include #include #include #include +#include #include #include #include @@ -283,23 +285,35 @@ static void c_stop(struct seq_file *m, void *v) static int c_show(struct seq_file *m, void *v) { unsigned long cpu_id = (unsigned long)v - 1; - struct device_node *node = of_get_cpu_node(cpu_id, NULL); struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id); + struct device_node *node; const char *compat, *isa; seq_printf(m, "processor\t: %lu\n", cpu_id); seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id)); - if (!of_property_read_string(node, "riscv,isa", &isa)) - print_isa(m, isa); - print_mmu(m); - if (!of_property_read_string(node, "compatible", &compat) - && strcmp(compat, "riscv")) - seq_printf(m, "uarch\t\t: %s\n", compat); + + if (acpi_disabled) { + node = of_get_cpu_node(cpu_id, NULL); + if (!of_property_read_string(node, "riscv,isa", &isa)) + print_isa(m, isa); + + print_mmu(m); + if (!of_property_read_string(node, "compatible", &compat) && + strcmp(compat, "riscv")) + seq_printf(m, "uarch\t\t: %s\n", compat); + + of_node_put(node); + } else { + if (!acpi_get_riscv_isa(NULL, cpu_id, &isa)) + print_isa(m, isa); + + print_mmu(m); + } + seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid); seq_printf(m, "marchid\t\t: 0x%lx\n", ci->marchid); seq_printf(m, "mimpid\t\t: 0x%lx\n", ci->mimpid); seq_puts(m, "\n"); - of_node_put(node); return 0; } From patchwork Tue Apr 4 18:20:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 79342 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp79304vqo; Tue, 4 Apr 2023 11:27:07 -0700 (PDT) X-Google-Smtp-Source: AKy350Y2YTiZbvKrFmQmlu1sk5Cmnt7pLcet3x8TB1hdBauH6yGIzyhUHzj0SHSKI6axs7rSjQTc X-Received: by 2002:a17:90b:4b10:b0:23b:49ad:a350 with SMTP id lx16-20020a17090b4b1000b0023b49ada350mr4166089pjb.9.1680632826887; Tue, 04 Apr 2023 11:27:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680632826; cv=none; d=google.com; s=arc-20160816; b=s+8PHdu45qk/QJtTtCLzETReX1wH7JBJPpfynZcRFOHITVflvUWfsLWzTEy3QztNOh 1lI6kKTn6ktgOzGK0GUwNUJ+H9ipeb9FqrM6kD89jMiUOQ1BanJRBppGThKlBS/ildNi QR4RuhAdVfDMIDVmdwGf4LX8bh/m4ztAE4zXvKCS2rFO2wmRBl4uUIrb7J0pHUEIsPgT UwpbHYRy/rtycVf6LMlDVadW+2lrFPC4WEKTr3R+zcNmXaGsQW2IPVhh4bSccAjCNkhA 10K1DHO9CeGKVWSbATgNKHbzkVu6JTCMXcYM0w7kzeo8rgXydI5yNT8+mOYfB8BThfuZ uw1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=FnYfF/i1bPfcv2iwCG3R0sVVOpyG4WRD2DXFzz9wWW8=; b=WfHErwzjkIMeND8leow+hrJ2KYk8xww1JNT66VHhbGVff9WKeiXoMR+wKDbOJbyg1g N4NiKjz1Mo7WUGKAu9KYVninKe1KAF5CB8bp6jjZ2sRCuE+rF2ZQw0sm9uahJve4LPWH NYJDyvfymIhHDMa4ArX278ygo9IZUD+Jc57KeG1sFqZNyUyQNFHTaEhjn8LyFWx3Q3HQ yt8RYsOTPfYdJil5m+ajxDgfPFEaTx+X1uN1D0q2c24K0ZDbZWjMYA1yCf62/02pJivE r5Gizreg7zIRxAyerLOsFsW/fntpGbDPozpcAmAmrn7d6I/q/762gA60bjimMQs4Oxut 2XQg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=lNBUKMHS; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , "David S . Miller" , Sunil V L , "Rafael J . Wysocki" , Andrew Jones , Conor Dooley Subject: [PATCH V4 15/23] irqchip/riscv-intc: Add ACPI support Date: Tue, 4 Apr 2023 23:50:29 +0530 Message-Id: <20230404182037.863533-16-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404182037.863533-1-sunilvl@ventanamicro.com> References: <20230404182037.863533-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762271246890597035?= X-GMAIL-MSGID: =?utf-8?q?1762271246890597035?= Add support for initializing the RISC-V INTC driver on ACPI platforms. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- drivers/irqchip/irq-riscv-intc.c | 74 ++++++++++++++++++++++++++------ 1 file changed, 61 insertions(+), 13 deletions(-) diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index f229e3e66387..6b476fa356c0 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -6,6 +6,7 @@ */ #define pr_fmt(fmt) "riscv-intc: " fmt +#include #include #include #include @@ -112,6 +113,30 @@ static struct fwnode_handle *riscv_intc_hwnode(void) return intc_domain->fwnode; } +static int __init riscv_intc_init_common(struct fwnode_handle *fn) +{ + int rc; + + intc_domain = irq_domain_create_linear(fn, BITS_PER_LONG, + &riscv_intc_domain_ops, NULL); + if (!intc_domain) { + pr_err("unable to add IRQ domain\n"); + return -ENXIO; + } + + rc = set_handle_irq(&riscv_intc_irq); + if (rc) { + pr_err("failed to set irq handler\n"); + return rc; + } + + riscv_set_intc_hwnode_fn(riscv_intc_hwnode); + + pr_info("%d local interrupts mapped\n", BITS_PER_LONG); + + return 0; +} + static int __init riscv_intc_init(struct device_node *node, struct device_node *parent) { @@ -133,24 +158,47 @@ static int __init riscv_intc_init(struct device_node *node, if (riscv_hartid_to_cpuid(hartid) != smp_processor_id()) return 0; - intc_domain = irq_domain_add_linear(node, BITS_PER_LONG, - &riscv_intc_domain_ops, NULL); - if (!intc_domain) { - pr_err("unable to add IRQ domain\n"); - return -ENXIO; - } - - rc = set_handle_irq(&riscv_intc_irq); + rc = riscv_intc_init_common(of_node_to_fwnode(node)); if (rc) { - pr_err("failed to set irq handler\n"); + pr_err("failed to initialize INTC\n"); return rc; } - riscv_set_intc_hwnode_fn(riscv_intc_hwnode); - - pr_info("%d local interrupts mapped\n", BITS_PER_LONG); - return 0; } IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init); + +#ifdef CONFIG_ACPI + +static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header, + const unsigned long end) +{ + int rc; + struct fwnode_handle *fn; + struct acpi_madt_rintc *rintc; + + rintc = (struct acpi_madt_rintc *)header; + + /* + * The ACPI MADT will have one INTC for each CPU (or HART) + * so riscv_intc_acpi_init() function will be called once + * for each INTC. We only do INTC initialization + * for the INTC belonging to the boot CPU (or boot HART). + */ + if (riscv_hartid_to_cpuid(rintc->hart_id) != smp_processor_id()) + return 0; + + fn = irq_domain_alloc_named_fwnode("RISCV-INTC"); + if (!fn) { + pr_err("unable to allocate INTC FW node\n"); + return -ENOMEM; + } + + rc = riscv_intc_init_common(fn); + return rc; +} + +IRQCHIP_ACPI_DECLARE(riscv_intc, ACPI_MADT_TYPE_RINTC, NULL, + ACPI_MADT_RINTC_VERSION_V1, riscv_intc_acpi_init); +#endif From patchwork Tue Apr 4 18:20:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 79337 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp78916vqo; Tue, 4 Apr 2023 11:26:15 -0700 (PDT) X-Google-Smtp-Source: AKy350Y9C4VMh2r8aTvobQOed0yHpyrQNj/4DTZSS5KKhlCcT9u5k7a8UOtALrCGMtseiOSgk/ba X-Received: by 2002:a17:902:ced2:b0:199:1160:956c with SMTP id d18-20020a170902ced200b001991160956cmr122553plg.31.1680632775007; Tue, 04 Apr 2023 11:26:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680632774; cv=none; d=google.com; s=arc-20160816; b=plQABTflIfnj/EcsEd/RuLZqg0+zo1n9KC4dN29uDwAUGVFv7R3SX90MBkNJxbIwbz Pzet/xIo11sgFhlgu0sUBvIqUAdTcVsyFktQ83t9qt9+KG2WtOXc2TPCz/UbrpDMOKNz NhVBsA8ic/4XF9iiaquKwZoIPEU61CDo6LS6xFCid8AGJgYGH5cHxGYtYqfqigvW+ViL gUweWmU2B+avtitV+v7Fq/aVLtEiW7JzFT4i3z/MsuRWoP5JKbUL+8Wlmx18W7N8ItOq tYrA1mroWAu03i01njMLdbn/b/17i3WAO6lMlU2WJcAVdR/FshLgffz6WRtlijchFe2X Wlzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=7z6bEMhbWIxvIOeCxyJDoCOcsyBkr0Sn2VEh+xkIGVw=; b=xzlM3v5YW4TgjfWEp50p4CzN+ogJB9sdgBDyd7YDSUzlQWMkUTdbTGZ0VrZmEhqpp6 Ey2kKgzhvrK/bwrFZVKzu+iwAMxQWYuzYVGCYo3hPaXjPVcxZRgLU2VUtmHglKOgW+0A q//gM2HD3jUV230h/8GizmJD1oo0hoLgqe+/ddFr+thTbVujnxwACoC6t5SFbWeL7isq c3Yr748PddcZKWZLRmHKm1Ti97W/Xe9L7vsSlphpytSOIWyUza3jjAKYiZvnrJkGkHSK SGzZjFKounqVqosQjR6pAVNNgwm6atqxWkI9zMPA9g1hwLFqZoQEnss0yFtZLhDdNutO XqYA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=i9p1p7aC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , "David S . Miller" , Sunil V L , Anup Patel , "Rafael J . Wysocki" , Andrew Jones Subject: [PATCH V4 16/23] clocksource/timer-riscv: Refactor riscv_timer_init_dt() Date: Tue, 4 Apr 2023 23:50:30 +0530 Message-Id: <20230404182037.863533-17-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404182037.863533-1-sunilvl@ventanamicro.com> References: <20230404182037.863533-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762271192471574743?= X-GMAIL-MSGID: =?utf-8?q?1762271192471574743?= Refactor the timer init function such that few things can be shared by both DT and ACPI based platforms. Co-developed-by: Anup Patel Signed-off-by: Anup Patel Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- drivers/clocksource/timer-riscv.c | 81 +++++++++++++++---------------- 1 file changed, 40 insertions(+), 41 deletions(-) diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index 5f0f10c7e222..cecc4662293b 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -124,61 +124,28 @@ static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -static int __init riscv_timer_init_dt(struct device_node *n) +static int __init riscv_timer_init_common(void) { - int cpuid, error; - unsigned long hartid; - struct device_node *child; + int error; struct irq_domain *domain; + struct fwnode_handle *intc_fwnode = riscv_get_intc_hwnode(); - error = riscv_of_processor_hartid(n, &hartid); - if (error < 0) { - pr_warn("Not valid hartid for node [%pOF] error = [%lu]\n", - n, hartid); - return error; - } - - cpuid = riscv_hartid_to_cpuid(hartid); - if (cpuid < 0) { - pr_warn("Invalid cpuid for hartid [%lu]\n", hartid); - return cpuid; - } - - if (cpuid != smp_processor_id()) - return 0; - - child = of_find_compatible_node(NULL, NULL, "riscv,timer"); - if (child) { - riscv_timer_cannot_wake_cpu = of_property_read_bool(child, - "riscv,timer-cannot-wake-cpu"); - of_node_put(child); - } - - domain = NULL; - child = of_get_compatible_child(n, "riscv,cpu-intc"); - if (!child) { - pr_err("Failed to find INTC node [%pOF]\n", n); - return -ENODEV; - } - domain = irq_find_host(child); - of_node_put(child); + domain = irq_find_matching_fwnode(intc_fwnode, DOMAIN_BUS_ANY); if (!domain) { - pr_err("Failed to find IRQ domain for node [%pOF]\n", n); + pr_err("Failed to find irq_domain for INTC node [%pfwP]\n", + intc_fwnode); return -ENODEV; } riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER); if (!riscv_clock_event_irq) { - pr_err("Failed to map timer interrupt for node [%pOF]\n", n); + pr_err("Failed to map timer interrupt for node [%pfwP]\n", intc_fwnode); return -ENODEV; } - pr_info("%s: Registering clocksource cpuid [%d] hartid [%lu]\n", - __func__, cpuid, hartid); error = clocksource_register_hz(&riscv_clocksource, riscv_timebase); if (error) { - pr_err("RISCV timer register failed [%d] for cpu = [%d]\n", - error, cpuid); + pr_err("RISCV timer registration failed [%d]\n", error); return error; } @@ -207,4 +174,36 @@ static int __init riscv_timer_init_dt(struct device_node *n) return error; } +static int __init riscv_timer_init_dt(struct device_node *n) +{ + int cpuid, error; + unsigned long hartid; + struct device_node *child; + + error = riscv_of_processor_hartid(n, &hartid); + if (error < 0) { + pr_warn("Invalid hartid for node [%pOF] error = [%lu]\n", + n, hartid); + return error; + } + + cpuid = riscv_hartid_to_cpuid(hartid); + if (cpuid < 0) { + pr_warn("Invalid cpuid for hartid [%lu]\n", hartid); + return cpuid; + } + + if (cpuid != smp_processor_id()) + return 0; + + child = of_find_compatible_node(NULL, NULL, "riscv,timer"); + if (child) { + riscv_timer_cannot_wake_cpu = of_property_read_bool(child, + "riscv,timer-cannot-wake-cpu"); + of_node_put(child); + } + + return riscv_timer_init_common(); +} + TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt); From patchwork Tue Apr 4 18:20:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 79338 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp78976vqo; Tue, 4 Apr 2023 11:26:21 -0700 (PDT) X-Google-Smtp-Source: AKy350Y7pHy3yI5EaYuNm2AXUeA62AOTOJCkAiZaU2ewz782Ibppzbh3LXGttw5o1T6mv/P1QH0n X-Received: by 2002:a17:903:2890:b0:1a1:b65c:dea7 with SMTP id ku16-20020a170903289000b001a1b65cdea7mr3537087plb.47.1680632781559; Tue, 04 Apr 2023 11:26:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680632781; cv=none; d=google.com; s=arc-20160816; b=SugJU5TPRUbi4lBuBH+g2j6lJwiNdlrNcFPvRgj+otd8NSTMouDAYsc0X5ho7DAlKt e5d/hrDV0XW6MPyb7TpavFdet1+aTNg3AroCqvWzq/s+Qu3KjjZbdFrdorThZpmoyM4Y 1YpW0UHrywzeRGOTMTwRSLuMoC0whitwl6Ak4wboINKuIFDukq6haQTuS6KIDgSwyyvR ktgJDiP/13TjHAET9Gq1ClC20cR8fonJVRmjYpqJleaTbuxamHX69b1VS3uHTsuNLblA KQMF+2QqXrSaAG0MMmc53aZS2uBYgMn0I3cPLvy3QIpIGpmS//K+u9+2Q0B6iwetqHGH nkGw== ARC-Message-Signature: i=1; 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Wysocki" , "David S . Miller" , Sunil V L , "Rafael J . Wysocki" , Andrew Jones Subject: [PATCH V4 17/23] clocksource/timer-riscv: Add ACPI support Date: Tue, 4 Apr 2023 23:50:31 +0530 Message-Id: <20230404182037.863533-18-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404182037.863533-1-sunilvl@ventanamicro.com> References: <20230404182037.863533-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762271199475754234?= X-GMAIL-MSGID: =?utf-8?q?1762271199475754234?= Initialize the timer driver based on RHCT table on ACPI based platforms. Currently, ACPI doesn't support a flag to indicate that the timer interrupt can wake up the cpu irrespective of its power state. It will be added in future update. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- drivers/clocksource/timer-riscv.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index cecc4662293b..da3071b387eb 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -10,6 +10,7 @@ #define pr_fmt(fmt) "riscv-timer: " fmt +#include #include #include #include @@ -207,3 +208,13 @@ static int __init riscv_timer_init_dt(struct device_node *n) } TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt); + +#ifdef CONFIG_ACPI +static int __init riscv_timer_acpi_init(struct acpi_table_header *table) +{ + return riscv_timer_init_common(); +} + +TIMER_ACPI_DECLARE(aclint_mtimer, ACPI_SIG_RHCT, riscv_timer_acpi_init); + +#endif From patchwork Tue Apr 4 18:20:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 79343 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp83254vqo; Tue, 4 Apr 2023 11:34:16 -0700 (PDT) X-Google-Smtp-Source: AKy350Y2XlSLd9TdA66Z4wsBFj51+jYJztL16nn/usG2VtmP6x7wTQIqRfzjpYy4Y65hWHueJ52h X-Received: by 2002:a05:6a20:2a08:b0:da:35d1:c46f with SMTP id e8-20020a056a202a0800b000da35d1c46fmr2844086pzh.43.1680633256165; Tue, 04 Apr 2023 11:34:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680633256; cv=none; d=google.com; s=arc-20160816; b=mRTvKedKPuFvw/cNCnK8cIeoYQyALk011CseQz0upLHbPqqoLbQ8LRlUL+PDDwHwJR iBQ1zOFJOFAMOSjvm8dUY2xs4x144FMpt3jSvZUqtXTMwXHUFUV64GS3Yy0LiwknIkvo OZTj3U3fFCcFHwKx3Xg7nMFMBuzgl+y7ejPkTtyT6wWD25utzPpV1RM+CvfuKd12jaN6 tZmTeu+M9bXG+iulQ7ihNAjDWZrLljyoI7Z10hTFAg7RdcNE9uxpSiBgP8Q9pDB+Id2y rA8i13cn2cNMQnjUiNvYqEXk9fMIaqOTDDequndxlIEBta9YGQ/yXri2ibpOMtBvO1p0 rnFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=yRIRI8aArNgE1fextAvbnFu2fBTu5X0gP4d56RcrLtU=; b=wvqQJVmwBHdPyZ3TSD5oD3CJ+Qh3ZbXulpDPr7+kdTC4dydSUleztNpxWSn9RaeuiD aZHxVGoYt7EoArxZxHRcotqj35km0XyeDNlD3l9Csy983WGQU6wglh5Qoy0YmoiXlDR/ yai2FrcsESuuAgdadrJEMUf9wlqH+fD0rzkkdnc+7vEsnhiSxIctMyryLDcfOLctDc6z DVdzQKvqdyo2hR2+QVgr4rHyMNfXp/e52n/lRNhEviVwQOSaP+RDbSwp75PKrNF8K9X5 RsX7FGBw5FoiYrmFFZqRgGB8pfahNzgKsiVSghbVkwlx9FxqWkrESXp87icyJztWH7wH uppw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b="kR+s/3Cy"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , "David S . Miller" , Sunil V L , "Rafael J . Wysocki" , Andrew Jones , Conor Dooley Subject: [PATCH V4 18/23] RISC-V: time.c: Add ACPI support for time_init() Date: Tue, 4 Apr 2023 23:50:32 +0530 Message-Id: <20230404182037.863533-19-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404182037.863533-1-sunilvl@ventanamicro.com> References: <20230404182037.863533-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762271697401596835?= X-GMAIL-MSGID: =?utf-8?q?1762271697401596835?= On ACPI based platforms, timer related information is available in RHCT. Add ACPI based probe support to the timer initialization. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- arch/riscv/kernel/time.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/arch/riscv/kernel/time.c b/arch/riscv/kernel/time.c index babaf3b48ba8..23641e82a9df 100644 --- a/arch/riscv/kernel/time.c +++ b/arch/riscv/kernel/time.c @@ -4,6 +4,7 @@ * Copyright (C) 2017 SiFive */ +#include #include #include #include @@ -18,17 +19,29 @@ EXPORT_SYMBOL_GPL(riscv_timebase); void __init time_init(void) { struct device_node *cpu; + struct acpi_table_rhct *rhct; + acpi_status status; u32 prop; - cpu = of_find_node_by_path("/cpus"); - if (!cpu || of_property_read_u32(cpu, "timebase-frequency", &prop)) - panic(KERN_WARNING "RISC-V system with no 'timebase-frequency' in DTS\n"); - of_node_put(cpu); - riscv_timebase = prop; + if (acpi_disabled) { + cpu = of_find_node_by_path("/cpus"); + if (!cpu || of_property_read_u32(cpu, "timebase-frequency", &prop)) + panic("RISC-V system with no 'timebase-frequency' in DTS\n"); + + of_node_put(cpu); + riscv_timebase = prop; + of_clk_init(NULL); + } else { + status = acpi_get_table(ACPI_SIG_RHCT, 0, (struct acpi_table_header **)&rhct); + if (ACPI_FAILURE(status)) + panic("RISC-V ACPI system with no RHCT table\n"); + + riscv_timebase = rhct->time_base_freq; + acpi_put_table((struct acpi_table_header *)rhct); + } lpj_fine = riscv_timebase / HZ; - of_clk_init(NULL); timer_probe(); tick_setup_hrtimer_broadcast(); From patchwork Tue Apr 4 18:20:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 79345 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp84051vqo; Tue, 4 Apr 2023 11:35:47 -0700 (PDT) X-Google-Smtp-Source: AKy350Zhfe8kvQS2aAIMgnZHELZOY22EntKYcptORmlUyQQs5roN8vL5qquNVd7K+5dNyhjfqbls X-Received: by 2002:a05:6a20:6687:b0:db:6a5a:3ce7 with SMTP id o7-20020a056a20668700b000db6a5a3ce7mr2821713pzh.12.1680633347588; Tue, 04 Apr 2023 11:35:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680633347; cv=none; d=google.com; s=arc-20160816; b=X+u3tanArueucTjadp6Z94hx+RCWP4wi5G6/8NFdHIDv1BhZ4I2FwLrLfEYzQ2FJBU 9pnNXECE5I2w/mXG5bfVIcfnqdM2qyPxFwW1R1vFyt0xqV3+jKWKbGw1bu12Cf8HT0jG T+g1rQXMNqGe0/bBJsl9icrZOLDx3DWy6x8Xpegg+iTITUnnLEfloujWqIEYESAijWag PyDEzgBFayQqSZ7DqPgBKvSN8bgxcQFve3O6J26iYmiBUkPKlI7gLgbjnsus6x8oQEGo BugU5UrHR3l+PqCHwmVhMmJZlS8xLl2wfRe+Iy1SKloOZZM+GfH2zxgki8l9P/GDgJ38 wO3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=aP7AggSRQOT5peR8zwTrsLFo6vHa1hKXa4wOp9AUSiM=; b=GtnRbEQJYXMVO+/AxIxdHMIArKfMX+SK/9H1GdcLVN0CDiO4INnrFElmQz98wjCymr 7orG00JdXUF4aI3Te7d0TycbrOKqy6aRLE+yFVHplQCSqUsp5P7p/BOpPC/12YaFsoLz 9TuNcIoWxiQqolV9zQJfTgcaAMBe/s1m8LSP5YddtlQg0nxZCLSEiW7rMk4ClsBnC1zB CaJ+Hw0MIAg6+oUkI7S8s99BPEIHsJjhLOJf9lElh8OP5sIz2lAbFMClkRyokrcrWmiw nUDvk4z1ZjfO9r29a9KVbKzTe6+4VlhdP3Bty3iQxMGmpJ7/Snett8HKDXLbqcf8bEzp c6JA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=Yn6r9xFO; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , "David S . Miller" , Sunil V L , "Rafael J . Wysocki" , Andrew Jones , Conor Dooley Subject: [PATCH V4 19/23] RISC-V: Add ACPI initialization in setup_arch() Date: Tue, 4 Apr 2023 23:50:33 +0530 Message-Id: <20230404182037.863533-20-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404182037.863533-1-sunilvl@ventanamicro.com> References: <20230404182037.863533-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762271792996248103?= X-GMAIL-MSGID: =?utf-8?q?1762271792996248103?= Initialize the ACPI core for RISC-V during boot. ACPI tables and interpreter are initialized based on the information passed from the firmware and the value of the kernel parameter 'acpi'. With ACPI support added for RISC-V, the kernel parameter 'acpi' is also supported on RISC-V. Hence, update the documentation. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Acked-by: Conor Dooley --- .../admin-guide/kernel-parameters.txt | 8 +- arch/riscv/kernel/acpi.c | 126 ++++++++++++++++++ arch/riscv/kernel/setup.c | 25 ++-- 3 files changed, 147 insertions(+), 12 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 6221a1d057dd..047679554453 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1,17 +1,17 @@ - acpi= [HW,ACPI,X86,ARM64] + acpi= [HW,ACPI,X86,ARM64,RISCV64] Advanced Configuration and Power Interface Format: { force | on | off | strict | noirq | rsdt | copy_dsdt } force -- enable ACPI if default was off - on -- enable ACPI but allow fallback to DT [arm64] + on -- enable ACPI but allow fallback to DT [arm64,riscv64] off -- disable ACPI if default was on noirq -- do not use ACPI for IRQ routing strict -- Be less tolerant of platforms that are not strictly ACPI specification compliant. rsdt -- prefer RSDT over (default) XSDT copy_dsdt -- copy DSDT to memory - For ARM64, ONLY "acpi=off", "acpi=on" or "acpi=force" - are available + For ARM64 and RISCV64, ONLY "acpi=off", "acpi=on" or + "acpi=force" are available See also Documentation/power/runtime_pm.rst, pci=noacpi diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c index 40ab55309c70..890c30fb3dbe 100644 --- a/arch/riscv/kernel/acpi.c +++ b/arch/riscv/kernel/acpi.c @@ -16,6 +16,7 @@ #include #include #include +#include int acpi_noirq = 1; /* skip ACPI IRQ initialization */ int acpi_disabled = 1; @@ -25,6 +26,131 @@ int acpi_pci_disabled = 1; /* skip ACPI PCI scan and IRQ initialization */ EXPORT_SYMBOL(acpi_pci_disabled); static struct acpi_madt_rintc cpu_madt_rintc[NR_CPUS]; +static bool param_acpi_off __initdata; +static bool param_acpi_on __initdata; +static bool param_acpi_force __initdata; + +static int __init parse_acpi(char *arg) +{ + if (!arg) + return -EINVAL; + + /* "acpi=off" disables both ACPI table parsing and interpreter */ + if (strcmp(arg, "off") == 0) + param_acpi_off = true; + else if (strcmp(arg, "on") == 0) /* prefer ACPI over DT */ + param_acpi_on = true; + else if (strcmp(arg, "force") == 0) /* force ACPI to be enabled */ + param_acpi_force = true; + else + return -EINVAL; /* Core will print when we return error */ + + return 0; +} +early_param("acpi", parse_acpi); + +/* + * acpi_fadt_sanity_check() - Check FADT presence and carry out sanity + * checks on it + * + * Return 0 on success, <0 on failure + */ +static int __init acpi_fadt_sanity_check(void) +{ + struct acpi_table_header *table; + struct acpi_table_fadt *fadt; + acpi_status status; + int ret = 0; + + /* + * FADT is required on riscv; retrieve it to check its presence + * and carry out revision and ACPI HW reduced compliancy tests + */ + status = acpi_get_table(ACPI_SIG_FADT, 0, &table); + if (ACPI_FAILURE(status)) { + const char *msg = acpi_format_exception(status); + + pr_err("Failed to get FADT table, %s\n", msg); + return -ENODEV; + } + + fadt = (struct acpi_table_fadt *)table; + + /* + * The revision in the table header is the FADT's Major revision. The + * FADT also has a minor revision, which is stored in the FADT itself. + * + * TODO: Currently, we check for 6.5 as the minimum version to check + * for HW_REDUCED flag. However, once RISC-V updates are released in + * the ACPI spec, we need to update this check for exact minor revision + */ + if (table->revision < 6 || (table->revision == 6 && fadt->minor_revision < 5)) { + pr_err(FW_BUG "Unsupported FADT revision %d.%d, should be 6.5+\n", + table->revision, fadt->minor_revision); + } + + if (!(fadt->flags & ACPI_FADT_HW_REDUCED)) { + pr_err("FADT not ACPI hardware reduced compliant\n"); + ret = -EINVAL; + } + + /* + * acpi_get_table() creates FADT table mapping that + * should be released after parsing and before resuming boot + */ + acpi_put_table(table); + return ret; +} + +/* + * acpi_boot_table_init() called from setup_arch(), always. + * 1. find RSDP and get its address, and then find XSDT + * 2. extract all tables and checksums them all + * 3. check ACPI FADT HW reduced flag + * + * We can parse ACPI boot-time tables such as MADT after + * this function is called. + * + * On return ACPI is enabled if either: + * + * - ACPI tables are initialized and sanity checks passed + * - acpi=force was passed in the command line and ACPI was not disabled + * explicitly through acpi=off command line parameter + * + * ACPI is disabled on function return otherwise + */ +void __init acpi_boot_table_init(void) +{ + /* + * Enable ACPI instead of device tree unless + * - ACPI has been disabled explicitly (acpi=off), or + * - firmware has not populated ACPI ptr in EFI system table + * and ACPI has not been [force] enabled (acpi=on|force) + */ + if (param_acpi_off || + (!param_acpi_on && !param_acpi_force && + efi.acpi20 == EFI_INVALID_TABLE_ADDR)) + return; + + /* + * ACPI is disabled at this point. Enable it in order to parse + * the ACPI tables and carry out sanity checks + */ + enable_acpi(); + + /* + * If ACPI tables are initialized and FADT sanity checks passed, + * leave ACPI enabled and carry on booting; otherwise disable ACPI + * on initialization error. + * If acpi=force was passed on the command line it forces ACPI + * to be enabled even if its initialization failed. + */ + if (acpi_table_init() || acpi_fadt_sanity_check()) { + pr_err("Failed to init ACPI tables\n"); + if (!param_acpi_force) + disable_acpi(); + } +} static int acpi_parse_madt_rintc(union acpi_subtable_headers *header, const unsigned long end) { diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 2d45a416d283..7b2b065a9f70 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -8,6 +8,7 @@ * Nick Kossifidis */ +#include #include #include #include @@ -276,14 +277,22 @@ void __init setup_arch(char **cmdline_p) efi_init(); paging_init(); -#if IS_ENABLED(CONFIG_BUILTIN_DTB) - unflatten_and_copy_device_tree(); -#else - if (early_init_dt_verify(__va(XIP_FIXUP(dtb_early_pa)))) - unflatten_device_tree(); - else - pr_err("No DTB found in kernel mappings\n"); -#endif + + /* Parse the ACPI tables for possible boot-time configuration */ + acpi_boot_table_init(); + if (acpi_disabled) { + if (IS_ENABLED(CONFIG_BUILTIN_DTB)) { + unflatten_and_copy_device_tree(); + } else { + if (early_init_dt_verify(__va(XIP_FIXUP(dtb_early_pa)))) + unflatten_device_tree(); + else + pr_err("No DTB found in kernel mappings\n"); + } + } else { + early_init_dt_verify(__va(XIP_FIXUP(dtb_early_pa))); + } + early_init_fdt_scan_reserved_mem(); misc_mem_init(); From patchwork Tue Apr 4 18:20:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 79344 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp83464vqo; Tue, 4 Apr 2023 11:34:40 -0700 (PDT) X-Google-Smtp-Source: AKy350aYHmy6oEcTlbko5Xgh+dUxGbmnc3u/YwNSMYrp0ueKrOYtDC/mnBK4TDG5LrEOTSfZdbW6 X-Received: by 2002:a17:90b:4ac7:b0:237:8417:d9e3 with SMTP id mh7-20020a17090b4ac700b002378417d9e3mr3853530pjb.15.1680633279754; Tue, 04 Apr 2023 11:34:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680633279; cv=none; d=google.com; s=arc-20160816; b=FF5JPm/04Vj4arxTymhS4QaZ/Uh9mzjbeOU6ij7EzNSjW/xEYp5IEFouMeB4KRtG+R iHAKVUgEHWkcZS4xItpZN/RSeqjH9aSPMWttde0sjlhtPfP2l/AuAeckFp8go4ftaZNL KzhRFmzLoolqeO+b2kWzikKW/g+mQOeNhfALqUB/RgjmJMMgrMpJTMdZO+cYvJXwQ0Cj 8q8kCuV5krFOKEjZKt/1YG34/kG5j48ZVSFvTwTGY3ZPAqyUvfbA6HCHQVIk4qmMU+WW FrZT80g3EgnAAMogeMFpO+rXeM4sBqRCDocNx4nlCNXJJNykAXGGy49MN33yq3jxaS00 5Zxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=O8jniZVFM5VdIC7zEQqZON+ttcH4hGM09Ty8jho7PtM=; b=nybYuIMe6qKJ818Cbu+RLKbrOOxg3+HrZ3OfnzqPoG19ZsrWWcpxpbNlg6mKfGAR0Y TsBlFvjkr4ufF0RVmZjdPdoSSe/R+LdHgVmPiZ8q/GDXHsOI3DqLVdSy/9zsH+pu/OaT B8rRkFTzQxDNvc2HyjAgYrRUGN1Xc/CWV6JcKmYeJ63y1LWuwnZmEleE2wa3SmA6De/S iGIMyI+sza1cm0rnc5nRTjG5v+NJhgkmjXqYBiEoTouyhC6GC9H/F6Wq0CypVm6r2O+c vR3rzaHYmyuYXz6N8QBbQc2tqN3BPGBexucb+ikpOWgwuSqLtV6KBTrKRET7fE5P3f7d eRBA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=l4Jw1Rq2; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , "David S . Miller" , Sunil V L , "Rafael J . Wysocki" , Andrew Jones Subject: [PATCH V4 20/23] RISC-V: Enable ACPI in defconfig Date: Tue, 4 Apr 2023 23:50:34 +0530 Message-Id: <20230404182037.863533-21-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404182037.863533-1-sunilvl@ventanamicro.com> References: <20230404182037.863533-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762271721981497384?= X-GMAIL-MSGID: =?utf-8?q?1762271721981497384?= Add support to build ACPI subsystem in defconfig. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index d98d6e90b2b8..8822b49ddb59 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -238,3 +238,4 @@ CONFIG_RCU_EQS_DEBUG=y # CONFIG_FTRACE is not set # CONFIG_RUNTIME_TESTING_MENU is not set CONFIG_MEMTEST=y +CONFIG_ACPI=y From patchwork Tue Apr 4 18:20:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 79348 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp86371vqo; Tue, 4 Apr 2023 11:39:52 -0700 (PDT) X-Google-Smtp-Source: AKy350bndYNpA1XsL1fUx5CZj08cp3QxWX46VxSuSBfzTC/NPM1wsRcA2+Os2s04bWjG+1uN0HRl X-Received: by 2002:a17:906:f2c1:b0:930:9385:ce51 with SMTP id gz1-20020a170906f2c100b009309385ce51mr439594ejb.68.1680633592075; Tue, 04 Apr 2023 11:39:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680633592; cv=none; d=google.com; s=arc-20160816; b=i1ieCYGMQoKJtLysYPybmx64BJrbgP95mA7ScjGD8swzCK/S9Tvp+HKarF2E1EwPpa sWfnhECcGskaQTwHfZKAinHj6c5SSjlFh6wHjjvyDJ79mn7ir5Z9ocfPAtbFBEhoYSCk 2wiB3sxQmxaseJMmlCQRw6t0HcFasxWu7shcwGIX4p1me8ZB12kcRnbcb62Krq9DmFmD TS1aWLjZGSZWJd7gGoE93hEzyOfVcD0joOT0nalAuHe8itB+/GprvvcCv5Ff35+arWo8 MNAAFo1ldC7Mk3VD7TEaDe26L7QOkb9tTshKDBB8DWdq7pLfQ+Gjmdc+xnDQkiUHfPCQ Nnsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=bxjRnY50ljGzDkjFJKwpbgFpDq6dD9KEN8bTRX7WND0=; b=d2ni1Z8HltIAd7CWSkXc9BxGsmzdUsVMjDIGHYDSH5iupdd4UehQPfV6PgDoIFQgqi s9KNZztEzvGzdSmOaB7F3wjjaz3XJZR5TBZVNo43ZBoIhKYspM1eL1lQ/98Ak2hfecmT zo4/Cb2N5Pt5isp4UHuDD903DaQ4Q6guiZ++bNNRXGkTFs8vkbfYkHj6QiM4XgwSxVr+ 0X2uBKj9/LViqSsT8wufuNLIchWdchXCVW7VyQ+AdyMHAENrtz67+0wVLDqNqT3W5LP/ mKdswFyp3HljVWRy5GJjSUkHTKCTCy9Vnz7k58zCzmWQwWUpiuCXyKS3EG68A2EfXzzy u+Tg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=DUjOausd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , "David S . Miller" , Sunil V L , "Rafael J . Wysocki" Subject: [PATCH V4 21/23] MAINTAINERS: Add entry for drivers/acpi/riscv Date: Tue, 4 Apr 2023 23:50:35 +0530 Message-Id: <20230404182037.863533-22-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404182037.863533-1-sunilvl@ventanamicro.com> References: <20230404182037.863533-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762272049358974922?= X-GMAIL-MSGID: =?utf-8?q?1762272049358974922?= ACPI defines few RISC-V specific tables which need parsing code added in drivers/acpi/riscv. Add maintainer entries for this newly created folder. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 90abe83c02f3..903a52027309 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -406,6 +406,14 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: drivers/acpi/arm64 +ACPI FOR RISC-V (ACPI/riscv) +M: Sunil V L +L: linux-acpi@vger.kernel.org +L: linux-riscv@lists.infradead.org +S: Maintained +F: arch/riscv/kernel/acpi.c +F: drivers/acpi/riscv + ACPI SERIAL MULTI INSTANTIATE DRIVER M: Hans de Goede L: platform-driver-x86@vger.kernel.org From patchwork Tue Apr 4 18:20:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 79349 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp86673vqo; Tue, 4 Apr 2023 11:40:25 -0700 (PDT) X-Google-Smtp-Source: AKy350ZZQ9LnSMTuyxIFj+TVjewj1QJfecGzeB4DJ8+B5SdsPvQYpIvA+N0pgBY+LTCk6ks9/jm8 X-Received: by 2002:a05:6402:8d7:b0:4fd:2675:3783 with SMTP id d23-20020a05640208d700b004fd26753783mr516028edz.1.1680633625742; Tue, 04 Apr 2023 11:40:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680633625; cv=none; d=google.com; s=arc-20160816; b=bK/V14ctcJnHhiG5QJuLOtekKb7buw4h8AP/dmXx4X4N1CzmheQPXWZe90HHeED7Bg KQudlXkF1JoOo1TiHny3fmAQRL70tGixzE+Ck9GlXqVuZibz5BkB7ZFAtESjJK412wPR TaCqlgbensKFcQuBnyAiGiuuNoLvvwO8JdG6ia0rErR5F06lCjVV7RDtCxg5U7Mojnt1 S0dkRBFzunYtzZ+bBn4TpypojbJTLI+91NHMtbhmTqxafVLiJ/+p3mqP4U4KREefOkTG mN0z5rX/B2pOdBdhmlr7NMSxn+iGl/ZexTmjlpFAS7p79KfWLxvor2MsPgFL7ox82RE3 IcOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=bQY7IsXlYzYdPvbtAuGQhW+vz7kmikxb6Hsl9qnqiJo=; b=JlrfJozv4//E1+g+ViaXaSaUnn29gLKUMIMo+1LyChhZJ20z4l0uUoYx2j36mkQpiC 1pfOp5X2Oc1BINQdVZnhOkt02TGZR9DpHLP4JMzVgIBCbiwJ/flSrKpboHkJQPcMErFw JnFF2MD5qG+lQd47/QVDeH8pxG9rAwRNWtlD64m3ZSgXZ3gyAnVi2ubdMUtumE6S+cp6 eMGqdFPTEFVYxp67DiUprALMcLdDMxSZ/TlwqcUvVjptohjouxvp3fjCeN4UpdHUE/Ff Q0jWZzrDss7+QxJ9VC44wOzn2bREEoD4zSOtIiRhiVnHrOBFaaK1FvxycS8KLzCeDAQw x7hA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=SIAlskAB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , "David S . Miller" , Sunil V L Subject: [PATCH V4 22/23] platform/surface: Disable for RISC-V Date: Tue, 4 Apr 2023 23:50:36 +0530 Message-Id: <20230404182037.863533-23-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404182037.863533-1-sunilvl@ventanamicro.com> References: <20230404182037.863533-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762272085046891555?= X-GMAIL-MSGID: =?utf-8?q?1762272085046891555?= With CONFIG_ACPI enabled for RISC-V, this driver gets enabled in allmodconfig build. However, RISC-V doesn't support sub-word atomics which is used by this driver. Due to this, the build fails with below error. In function ‘ssh_seq_next’, inlined from ‘ssam_request_write_data’ at drivers/platform/surface/aggregator/controller.c:1483:8: ././include/linux/compiler_types.h:399:45: error: call to ‘__compiletime_assert_335’ declared with attribute error: BUILD_BUG failed 399 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) | ^ ./include/linux/compiler.h:78:45: note: in definition of macro ‘unlikely’ 78 | # define unlikely(x) __builtin_expect(!!(x), 0) | ^ ././include/linux/compiler_types.h:387:9: note: in expansion of macro ‘__compiletime_assert’ 387 | __compiletime_assert(condition, msg, prefix, suffix) | ^~~~~~~~~~~~~~~~~~~~ ././include/linux/compiler_types.h:399:9: note: in expansion of macro ‘_compiletime_assert’ 399 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) | ^~~~~~~~~~~~~~~~~~~ ./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’ 39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg) | ^~~~~~~~~~~~~~~~~~ ./include/linux/build_bug.h:59:21: note: in expansion of macro ‘BUILD_BUG_ON_MSG’ 59 | #define BUILD_BUG() BUILD_BUG_ON_MSG(1, "BUILD_BUG failed") | ^~~~~~~~~~~~~~~~ ./arch/riscv/include/asm/cmpxchg.h:335:17: note: in expansion of macro ‘BUILD_BUG’ 335 | BUILD_BUG(); \ | ^~~~~~~~~ ./arch/riscv/include/asm/cmpxchg.h:344:30: note: in expansion of macro ‘__cmpxchg’ 344 | (__typeof__(*(ptr))) __cmpxchg((ptr), \ | ^~~~~~~~~ ./include/linux/atomic/atomic-instrumented.h:1916:9: note: in expansion of macro ‘arch_cmpxchg’ 1916 | arch_cmpxchg(__ai_ptr, __VA_ARGS__); \ | ^~~~~~~~~~~~ drivers/platform/surface/aggregator/controller.c:61:32: note: in expansion of macro ‘cmpxchg’ 61 | while (unlikely((ret = cmpxchg(&c->value, old, new)) != old)) { | ^~~~~~~ So, disable this driver for RISC-V even when ACPI is enabled for now. Signed-off-by: Sunil V L Acked-by: Maximilian Luz --- drivers/platform/surface/aggregator/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/platform/surface/aggregator/Kconfig b/drivers/platform/surface/aggregator/Kconfig index c114f9dd5fe1..88afc38ffdc5 100644 --- a/drivers/platform/surface/aggregator/Kconfig +++ b/drivers/platform/surface/aggregator/Kconfig @@ -4,7 +4,7 @@ menuconfig SURFACE_AGGREGATOR tristate "Microsoft Surface System Aggregator Module Subsystem and Drivers" depends on SERIAL_DEV_BUS - depends on ACPI + depends on ACPI && !RISCV select CRC_CCITT help The Surface System Aggregator Module (Surface SAM or SSAM) is an From patchwork Tue Apr 4 18:20:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 79350 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp86800vqo; Tue, 4 Apr 2023 11:40:43 -0700 (PDT) X-Google-Smtp-Source: AKy350YgJmmAR5yQB6ynl2w5p6m+7ck+zdx5p+6yUk7RTxKpWDoqFZ6moqVeUnKk8XZ9zMZLgLlt X-Received: by 2002:a17:902:da8f:b0:19c:da7f:a234 with SMTP id j15-20020a170902da8f00b0019cda7fa234mr3719283plx.67.1680633643464; Tue, 04 Apr 2023 11:40:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680633643; cv=none; d=google.com; s=arc-20160816; b=nspMKhgwB1hEYL5/nrBgqiawKwctcaYUECB2g4/g9r2gLENjD8VQqhUtMEhvq/J+g2 54NXskW0X6tOpNvVmSljC+h2tDZtKwX8nVp6enQ9FabvFcMrauQExnjAIdd3Qw9uW/FL f5fUOQJ85EbtZLqvuT9Zw8vt+90jOn8Hfx2uKbiGVBLmSOweKncj93PfGxAlyoLAG5Sb XPeYRyL7u8gTyor0AjKwdgk7kGa3PJga30IgScQidHNUz0U2+/ktKyv4MkZ4kPP7h5C1 j/Q8IlO7wdpc+CtSc2Wqvxnegxu0J45CIw5U3QZHDKsyGB+Ct3tvh1+OibdjPPrenAus fNJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Gqxa4spepTnsUwVbNTwSWIuFxwC658E+AuuPxXktYUk=; b=w45mjklUm36uHKAI9bh23se0TVQCc1FysJVazVqM0Dn/dKnkpD8dr84H7WWSRaCNO5 Xxg/3mhCpfeJYP8iaqEaEOPYZ3dNCn8s1KzEHaeTD95jVzV0cCmFF2w9CtCotcxzf411 LDp8M/hT2siLpSmHcWjHK4w9XAxngq5bbUPx9lxkfEIcVjx1/GvVZw5ac4V4kCjs7MTa vvnbzid08wJR9g+kyAbb3DA06ZbTHx8WYMb9e1EGambTFfCINl3eeAy/MZJz8w0c3u64 w1Lfhyyrs8LRlcT3V+bwr69vDoWMxf0oDdvGC8l3s5u5N7oDLZCKwD+Bmypllyf1JRXy Pfyg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=kAvoNYqd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , "David S . Miller" , Sunil V L Subject: [PATCH V4 23/23] crypto: hisilicon/qm: Workaround to enable build with RISC-V clang Date: Tue, 4 Apr 2023 23:50:37 +0530 Message-Id: <20230404182037.863533-24-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404182037.863533-1-sunilvl@ventanamicro.com> References: <20230404182037.863533-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762272103100313100?= X-GMAIL-MSGID: =?utf-8?q?1762272103100313100?= With CONFIG_ACPI enabled for RISC-V, this driver gets enabled in allmodconfig build. The gcc tool chain builds this driver removing the inline arm64 assembly code. However, clang for RISC-V tries to build the arm64 assembly and below error is seen. drivers/crypto/hisilicon/qm.c:627:10: error: invalid output constraint '+Q' in asm "+Q" (*((char __iomem *)fun_base)) ^ It appears that RISC-V clang is not smart enough to detect IS_ENABLED(CONFIG_ARM64) and remove the dead code. As a workaround, move this check to preprocessing stage which works with the RISC-V clang tool chain. Signed-off-by: Sunil V L Reviewed-by: Conor Dooley --- drivers/crypto/hisilicon/qm.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c index e4c84433a88a..a5f521529ab2 100644 --- a/drivers/crypto/hisilicon/qm.c +++ b/drivers/crypto/hisilicon/qm.c @@ -611,13 +611,9 @@ EXPORT_SYMBOL_GPL(hisi_qm_wait_mb_ready); static void qm_mb_write(struct hisi_qm *qm, const void *src) { void __iomem *fun_base = qm->io_base + QM_MB_CMD_SEND_BASE; - unsigned long tmp0 = 0, tmp1 = 0; - if (!IS_ENABLED(CONFIG_ARM64)) { - memcpy_toio(fun_base, src, 16); - dma_wmb(); - return; - } +#if IS_ENABLED(CONFIG_ARM64) + unsigned long tmp0 = 0, tmp1 = 0; asm volatile("ldp %0, %1, %3\n" "stp %0, %1, %2\n" @@ -627,6 +623,11 @@ static void qm_mb_write(struct hisi_qm *qm, const void *src) "+Q" (*((char __iomem *)fun_base)) : "Q" (*((char *)src)) : "memory"); +#else + memcpy_toio(fun_base, src, 16); + dma_wmb(); +#endif + } static int qm_mb_nolock(struct hisi_qm *qm, struct qm_mailbox *mailbox)