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([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:52:59 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 01/33] x86/traps: let common_interrupt() handle IRQ_MOVE_CLEANUP_VECTOR Date: Tue, 4 Apr 2023 03:26:44 -0700 Message-Id: <20230404102716.1795-2-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762245336535446260?= X-GMAIL-MSGID: =?utf-8?q?1762245336535446260?= From: "H. Peter Anvin (Intel)" IRQ_MOVE_CLEANUP_VECTOR is the only one of the system IRQ vectors that is *below* FIRST_SYSTEM_VECTOR. It is a slow path, so just push it into common_interrupt() just before the spurious interrupt handling. Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/kernel/irq.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c index 766ffe3ba313..7e125fff45ab 100644 --- a/arch/x86/kernel/irq.c +++ b/arch/x86/kernel/irq.c @@ -248,6 +248,10 @@ DEFINE_IDTENTRY_IRQ(common_interrupt) desc = __this_cpu_read(vector_irq[vector]); if (likely(!IS_ERR_OR_NULL(desc))) { handle_irq(desc, regs); +#ifdef CONFIG_SMP + } else if (vector == IRQ_MOVE_CLEANUP_VECTOR) { + sysvec_irq_move_cleanup(regs); +#endif } else { ack_APIC_irq(); From patchwork Tue Apr 4 10:26:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 79020 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2952098vqo; Tue, 4 Apr 2023 04:32:25 -0700 (PDT) X-Google-Smtp-Source: AKy350bNdW1MQ+YrsEkG8lZ5Tn13i7IwalWx+VpD0+WhQOKD97fUV6tsGTz3WiUvmrnHWvdsVHl+ X-Received: by 2002:a17:903:1245:b0:1a0:75fe:cd66 with SMTP id u5-20020a170903124500b001a075fecd66mr2711141plh.50.1680607945183; Tue, 04 Apr 2023 04:32:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680607945; cv=none; d=google.com; s=arc-20160816; b=eLGpQUN407UzA6+0PfLxrTzXP5GpgX787LfWz2lXyn9jmserfDPskKIrUsk3vdBKAC 0IMABEP66hSAz8Nkbh05Q/Q4d21bZG8fqoWm4xHLiPGzAxBP6GnQ2zUu6sGJNAsrMgAZ EePh/W0r8W97qhffmXyZRj945jCSYjtYa37/S34iuu9/zUd/726JtwUDd84C0zaNH9dm Omjxr0cyY/usAU/OXZFEg4q5U4XHe/PP11rVt8+nTrrQvv+RwOtt2eT3XDkh70CFsHvD 70/18pnpZBWONEJXL6HDUriZLNtR7zEkooXe0u+vg1Xx4BtRcvfgnQptJwDwhM6CRxiI knoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=69uZgB5syZguYJi9iT6gO8XISz/gXRjkiGmbEgB4SD0=; b=L4OASy7vP0UVwzdVA4MCvJx/JmPs4CXXIDwtIio0iX+e6oblq7AgSXOgzPxSbSbisZ RxEmbscyR8OSICIpghh0GBDQK+POcNx1N3IXLgZur5VYle/yF1MkK6M/KUTQLe4b++bL B5EDSvcqPTaEhcPHbwmu6Y9mnLYR15asMD1fvEXR78Mi7eWWDa8ORJfvLB2t5gq+av+R rdEjBGgRq2opiWA2r4cxJtvvy0qymF7QoeJ16hTVkUx8SMo4av7b2lNuaycujJLz16C5 B3e6THzQrZuQ4AFhmDdKKqvC7vfhyy3xMdyVokH7hw4CQVVhsEqIEvXKh4QRgS3v8gKk x7og== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=bwyuGNPL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:52:59 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 02/33] x86/fred: make unions for the cs and ss fields in struct pt_regs Date: Tue, 4 Apr 2023 03:26:45 -0700 Message-Id: <20230404102716.1795-3-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762245156614505036?= X-GMAIL-MSGID: =?utf-8?q?1762245156614505036?= From: "H. Peter Anvin (Intel)" Make the cs and ss fields in struct pt_regs unions between the actual selector and the unsigned long stack slot. FRED uses this space to store additional flags. The printk changes are simply due to the cs and ss fields changed to unsigned short from unsigned long. Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- Changes since v3: * Rename csl/ssl of the pt_regs structure to csx/ssx (x for extended) (Andrew Cooper). --- arch/x86/entry/vsyscall/vsyscall_64.c | 2 +- arch/x86/include/asm/ptrace.h | 34 ++++++++++++++++++++++++--- arch/x86/kernel/process_64.c | 2 +- 3 files changed, 33 insertions(+), 5 deletions(-) diff --git a/arch/x86/entry/vsyscall/vsyscall_64.c b/arch/x86/entry/vsyscall/vsyscall_64.c index d234ca797e4a..2429ad0df068 100644 --- a/arch/x86/entry/vsyscall/vsyscall_64.c +++ b/arch/x86/entry/vsyscall/vsyscall_64.c @@ -76,7 +76,7 @@ static void warn_bad_vsyscall(const char *level, struct pt_regs *regs, if (!show_unhandled_signals) return; - printk_ratelimited("%s%s[%d] %s ip:%lx cs:%lx sp:%lx ax:%lx si:%lx di:%lx\n", + printk_ratelimited("%s%s[%d] %s ip:%lx cs:%x sp:%lx ax:%lx si:%lx di:%lx\n", level, current->comm, task_pid_nr(current), message, regs->ip, regs->cs, regs->sp, regs->ax, regs->si, regs->di); diff --git a/arch/x86/include/asm/ptrace.h b/arch/x86/include/asm/ptrace.h index f4db78b09c8f..2abb23e6c1e2 100644 --- a/arch/x86/include/asm/ptrace.h +++ b/arch/x86/include/asm/ptrace.h @@ -82,12 +82,40 @@ struct pt_regs { * On hw interrupt, it's IRQ number: */ unsigned long orig_ax; -/* Return frame for iretq */ +/* Return frame for iretq/eretu/erets */ unsigned long ip; - unsigned long cs; + union { + unsigned long csx; /* cs extended: CS + any fields above it */ + struct __attribute__((__packed__)) { + unsigned short cs; /* CS selector proper */ + unsigned int current_stack_level: 2; + unsigned int __csx_resv1 : 6; + unsigned int interrupt_shadowed : 1; + unsigned int software_initiated : 1; + unsigned int __csx_resv2 : 2; + unsigned int nmi : 1; + unsigned int __csx_resv3 : 3; + unsigned int __csx_resv4 : 32; + }; + }; unsigned long flags; unsigned long sp; - unsigned long ss; + union { + unsigned long ssx; /* ss extended: SS + any fields above it */ + struct __attribute__((__packed__)) { + unsigned short ss; /* SS selector proper */ + unsigned int __ssx_resv1 : 16; + unsigned int vector : 8; + unsigned int __ssx_resv2 : 8; + unsigned int type : 4; + unsigned int __ssx_resv3 : 4; + unsigned int enclv : 1; + unsigned int long_mode : 1; + unsigned int nested : 1; + unsigned int __ssx_resv4 : 1; + unsigned int instr_len : 4; + }; + }; /* top of stack page */ }; diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index bb65a68b4b49..a1aa74864c8b 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -116,7 +116,7 @@ void __show_regs(struct pt_regs *regs, enum show_regs_mode mode, printk("%sFS: %016lx(%04x) GS:%016lx(%04x) knlGS:%016lx\n", log_lvl, fs, fsindex, gs, gsindex, shadowgs); - printk("%sCS: %04lx DS: %04x ES: %04x CR0: %016lx\n", + printk("%sCS: %04x DS: %04x ES: %04x CR0: %016lx\n", log_lvl, regs->cs, ds, es, cr0); printk("%sCR2: %016lx CR3: %016lx CR4: %016lx\n", log_lvl, cr2, cr3, cr4); From patchwork Tue Apr 4 10:26:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 79009 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2943238vqo; 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([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:53:00 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 03/33] x86/traps: add a system interrupt table for system interrupt dispatch Date: Tue, 4 Apr 2023 03:26:46 -0700 Message-Id: <20230404102716.1795-4-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762244240841278913?= X-GMAIL-MSGID: =?utf-8?q?1762244240841278913?= From: "H. Peter Anvin (Intel)" On x86, external interrupts are divided into the following two groups 1) system interrupts 2) external device interrupts External device interrupts are all routed to common_interrupt(), which dispatches external device interrupts through a per-CPU external interrupt dispatch table vector_irq. For system interrupts, add a system interrupt handler table for dispatching a system interrupt to its corresponding handler directly. Thus a software based dispatch function will be: void external_interrupt(struct pt_regs *regs) { u8 vector = regs->vector; if (is_system_interrupt(vector)) system_interrupt_handlers[vector_to_sysvec(vector)](regs); else /* external device interrupt */ common_interrupt(regs); } Signed-off-by: H. Peter Anvin (Intel) Co-developed-by: Xin Li Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/asm/idtentry.h | 64 +++++++++++++++++++++++++++------ arch/x86/include/asm/traps.h | 7 ++++ arch/x86/kernel/traps.c | 62 ++++++++++++++++++++++++++++++++ 3 files changed, 122 insertions(+), 11 deletions(-) diff --git a/arch/x86/include/asm/idtentry.h b/arch/x86/include/asm/idtentry.h index b241af4ce9b4..2876ddae02bc 100644 --- a/arch/x86/include/asm/idtentry.h +++ b/arch/x86/include/asm/idtentry.h @@ -167,17 +167,22 @@ __visible noinstr void func(struct pt_regs *regs, unsigned long error_code) /** * DECLARE_IDTENTRY_IRQ - Declare functions for device interrupt IDT entry - * points (common/spurious) + * points (common/spurious) and their corresponding + * software based dispatch handlers in the non-noinstr + * text section * @vector: Vector number (ignored for C) * @func: Function name of the entry point * - * Maps to DECLARE_IDTENTRY_ERRORCODE() + * Maps to DECLARE_IDTENTRY_ERRORCODE(), plus a dispatch function prototype */ #define DECLARE_IDTENTRY_IRQ(vector, func) \ - DECLARE_IDTENTRY_ERRORCODE(vector, func) + DECLARE_IDTENTRY_ERRORCODE(vector, func); \ + void dispatch_##func(struct pt_regs *regs, unsigned long error_code) /** * DEFINE_IDTENTRY_IRQ - Emit code for device interrupt IDT entry points + * and their corresponding software based dispatch + * handlers in the non-noinstr text section * @func: Function name of the entry point * * The vector number is pushed by the low level entry stub and handed @@ -187,6 +192,9 @@ __visible noinstr void func(struct pt_regs *regs, unsigned long error_code) * irq_enter/exit_rcu() are invoked before the function body and the * KVM L1D flush request is set. Stack switching to the interrupt stack * has to be done in the function body if necessary. + * + * dispatch_func() is a software based dispatch handler in the non-noinstr + * text section. */ #define DEFINE_IDTENTRY_IRQ(func) \ static void __##func(struct pt_regs *regs, u32 vector); \ @@ -204,31 +212,48 @@ __visible noinstr void func(struct pt_regs *regs, \ irqentry_exit(regs, state); \ } \ \ +void dispatch_##func(struct pt_regs *regs, unsigned long error_code) \ +{ \ + u32 vector = (u32)(u8)error_code; \ + \ + kvm_set_cpu_l1tf_flush_l1d(); \ + run_irq_on_irqstack_cond(__##func, regs, vector); \ +} \ + \ static noinline void __##func(struct pt_regs *regs, u32 vector) /** * DECLARE_IDTENTRY_SYSVEC - Declare functions for system vector entry points + * and their corresponding software based dispatch + * handlers in the non-noinstr text section * @vector: Vector number (ignored for C) * @func: Function name of the entry point * - * Declares three functions: + * Declares four functions: * - The ASM entry point: asm_##func * - The XEN PV trap entry point: xen_##func (maybe unused) * - The C handler called from the ASM entry point + * - The C handler used in the system interrupt handler table * - * Maps to DECLARE_IDTENTRY(). + * Maps to DECLARE_IDTENTRY(), plus a dispatch table function prototype */ #define DECLARE_IDTENTRY_SYSVEC(vector, func) \ - DECLARE_IDTENTRY(vector, func) + DECLARE_IDTENTRY(vector, func); \ + void dispatch_table_##func(struct pt_regs *regs) /** * DEFINE_IDTENTRY_SYSVEC - Emit code for system vector IDT entry points + * and their corresponding software based dispatch + * handlers in the non-noinstr text section * @func: Function name of the entry point * * irqentry_enter/exit() and irq_enter/exit_rcu() are invoked before the * function body. KVM L1D flush request is set. * - * Runs the function on the interrupt stack if the entry hit kernel mode + * Runs the function on the interrupt stack if the entry hit kernel mode. + * + * dispatch_table_func() is used in the system interrupt handler table for + * system interrupts dispatching. */ #define DEFINE_IDTENTRY_SYSVEC(func) \ static void __##func(struct pt_regs *regs); \ @@ -244,11 +269,19 @@ __visible noinstr void func(struct pt_regs *regs) \ irqentry_exit(regs, state); \ } \ \ +void dispatch_table_##func(struct pt_regs *regs) \ +{ \ + kvm_set_cpu_l1tf_flush_l1d(); \ + run_sysvec_on_irqstack_cond(__##func, regs); \ +} \ + \ static noinline void __##func(struct pt_regs *regs) /** * DEFINE_IDTENTRY_SYSVEC_SIMPLE - Emit code for simple system vector IDT - * entry points + * entry points and their corresponding + * software based dispatch handlers in + * the non-noinstr text section * @func: Function name of the entry point * * Runs the function on the interrupted stack. No switch to IRQ stack and @@ -256,6 +289,9 @@ static noinline void __##func(struct pt_regs *regs) * * Only use for 'empty' vectors like reschedule IPI and KVM posted * interrupt vectors. + * + * dispatch_table_func() is used in the system interrupt handler table for + * system interrupts dispatching. */ #define DEFINE_IDTENTRY_SYSVEC_SIMPLE(func) \ static __always_inline void __##func(struct pt_regs *regs); \ @@ -273,6 +309,14 @@ __visible noinstr void func(struct pt_regs *regs) \ irqentry_exit(regs, state); \ } \ \ +void dispatch_table_##func(struct pt_regs *regs) \ +{ \ + __irq_enter_raw(); \ + kvm_set_cpu_l1tf_flush_l1d(); \ + __##func (regs); \ + __irq_exit_raw(); \ +} \ + \ static __always_inline void __##func(struct pt_regs *regs) /** @@ -634,9 +678,7 @@ DECLARE_IDTENTRY(X86_TRAP_VE, exc_virtualization_exception); /* Device interrupts common/spurious */ DECLARE_IDTENTRY_IRQ(X86_TRAP_OTHER, common_interrupt); -#ifdef CONFIG_X86_LOCAL_APIC DECLARE_IDTENTRY_IRQ(X86_TRAP_OTHER, spurious_interrupt); -#endif /* System vector entry points */ #ifdef CONFIG_X86_LOCAL_APIC @@ -647,7 +689,7 @@ DECLARE_IDTENTRY_SYSVEC(X86_PLATFORM_IPI_VECTOR, sysvec_x86_platform_ipi); #endif #ifdef CONFIG_SMP -DECLARE_IDTENTRY(RESCHEDULE_VECTOR, sysvec_reschedule_ipi); +DECLARE_IDTENTRY_SYSVEC(RESCHEDULE_VECTOR, sysvec_reschedule_ipi); DECLARE_IDTENTRY_SYSVEC(IRQ_MOVE_CLEANUP_VECTOR, sysvec_irq_move_cleanup); DECLARE_IDTENTRY_SYSVEC(REBOOT_VECTOR, sysvec_reboot); DECLARE_IDTENTRY_SYSVEC(CALL_FUNCTION_SINGLE_VECTOR, sysvec_call_function_single); diff --git a/arch/x86/include/asm/traps.h b/arch/x86/include/asm/traps.h index 47ecfff2c83d..28c8ba5fd81c 100644 --- a/arch/x86/include/asm/traps.h +++ b/arch/x86/include/asm/traps.h @@ -47,4 +47,11 @@ void __noreturn handle_stack_overflow(struct pt_regs *regs, struct stack_info *info); #endif +/* + * How system interrupt handlers are called. + */ +#define DECLARE_SYSTEM_INTERRUPT_HANDLER(f) \ + void f (struct pt_regs *regs) +typedef DECLARE_SYSTEM_INTERRUPT_HANDLER((*system_interrupt_handler)); + #endif /* _ASM_X86_TRAPS_H */ diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index d317dc3d06a3..2cbe7e7e8b96 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -1451,6 +1451,68 @@ DEFINE_IDTENTRY_SW(iret_error) } #endif +#ifdef CONFIG_X86_64 + +#ifndef CONFIG_X86_LOCAL_APIC +/* + * Used when local APIC is not configured to build into the kernel, but + * dispatch_table_spurious_interrupt() needs dispatch_spurious_interrupt(). + */ +DEFINE_IDTENTRY_IRQ(spurious_interrupt) +{ + pr_info("Spurious interrupt (vector 0x%x) on CPU#%d, should never happen.\n", + vector, smp_processor_id()); +} +#endif + +static void dispatch_table_spurious_interrupt(struct pt_regs *regs) +{ + dispatch_spurious_interrupt(regs, regs->vector); +} + +#define SYSV(x,y) [(x) - FIRST_SYSTEM_VECTOR] = y + +static system_interrupt_handler system_interrupt_handlers[NR_SYSTEM_VECTORS] = { + [0 ... NR_SYSTEM_VECTORS-1] = dispatch_table_spurious_interrupt, +#ifdef CONFIG_SMP + SYSV(RESCHEDULE_VECTOR, dispatch_table_sysvec_reschedule_ipi), + SYSV(CALL_FUNCTION_VECTOR, dispatch_table_sysvec_call_function), + SYSV(CALL_FUNCTION_SINGLE_VECTOR, dispatch_table_sysvec_call_function_single), + SYSV(REBOOT_VECTOR, dispatch_table_sysvec_reboot), +#endif + +#ifdef CONFIG_X86_THERMAL_VECTOR + SYSV(THERMAL_APIC_VECTOR, dispatch_table_sysvec_thermal), +#endif + +#ifdef CONFIG_X86_MCE_THRESHOLD + SYSV(THRESHOLD_APIC_VECTOR, dispatch_table_sysvec_threshold), +#endif + +#ifdef CONFIG_X86_MCE_AMD + SYSV(DEFERRED_ERROR_VECTOR, dispatch_table_sysvec_deferred_error), +#endif + +#ifdef CONFIG_X86_LOCAL_APIC + SYSV(LOCAL_TIMER_VECTOR, dispatch_table_sysvec_apic_timer_interrupt), + SYSV(X86_PLATFORM_IPI_VECTOR, dispatch_table_sysvec_x86_platform_ipi), +# ifdef CONFIG_HAVE_KVM + SYSV(POSTED_INTR_VECTOR, dispatch_table_sysvec_kvm_posted_intr_ipi), + SYSV(POSTED_INTR_WAKEUP_VECTOR, dispatch_table_sysvec_kvm_posted_intr_wakeup_ipi), + SYSV(POSTED_INTR_NESTED_VECTOR, dispatch_table_sysvec_kvm_posted_intr_nested_ipi), +# endif +# ifdef CONFIG_IRQ_WORK + SYSV(IRQ_WORK_VECTOR, dispatch_table_sysvec_irq_work), +# endif + SYSV(SPURIOUS_APIC_VECTOR, dispatch_table_sysvec_spurious_apic_interrupt), + SYSV(ERROR_APIC_VECTOR, dispatch_table_sysvec_error_interrupt), +#endif +}; + +#undef SYSV + +#endif /* CONFIG_X86_64 */ + void __init trap_init(void) { /* Init cpu_entry_area before IST entries are set up */ From patchwork Tue Apr 4 10:26:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 78995 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2930624vqo; Tue, 4 Apr 2023 03:56:32 -0700 (PDT) X-Google-Smtp-Source: AKy350akWq8AO5+sue4mlgK/LRubSCuNqUNKkVViDdHWgKjnSVthCqzG6M7fNr++wnkQsw6Bebs0 X-Received: by 2002:a17:906:9c96:b0:92f:b290:78c with SMTP id fj22-20020a1709069c9600b0092fb290078cmr1919556ejc.21.1680605792426; Tue, 04 Apr 2023 03:56:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680605792; cv=none; d=google.com; s=arc-20160816; b=rqZzMr/uXjW4Ih8NLaRaww2PVjOOzTu3gjvCIicI9XO5f3APuVIqDDLy9MFNhk5F6S 97tZ6fegUC4lc1uKtzRWigiVEZqW7kzpcyBakH+Rjm4gyB9dUEx2ZdZIFv6UnQ1G/Moq 5CAGujBjH7ApBjHwWV09myVepogL29Jdqlx2bCfm73EfSE/sOU6QjBtlamdcoTTxQZ6Y 0itEktpgUOhk7GxaWAofKkdp4Rj5D9ae8VZp4srZEOTVKKxMrEkxfwOdJpNTjNvQBw8P CTrHykPty/k4HeQ6Rxsf+dHf/n2oGp7/JAZcxT6Y5OGEr+V1tDtBlAPoMifHEX8Hks4+ RYTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=WqEsudKPtU/48zeiRN+6GQBbNzGrNsHFqQ78iXIZMtA=; b=UIF3weCbEC2Xf6CP0XVn/dpud+F0o+ui4exkZ9i+WJXskwR70RgRrEpVEB78BF/149 q7FBC9b+7lAwIGiZwtivIKbFS9ttym0gbVT0s4ad2LRNlZQU7rzScjnxykDoTBVHqPfq HJ8qsEbTvlVEaJK3DyfZKcbkXmqOJZQ33BjlaODczIWuVn4DoXLqKATkaqEhMnc+z7WK qBLja+3PxS3CgyGa3gRNIIuFO1w0oovo1VMgrtxMaRWNG/gPnkCo4IOZ7p7JPVwNY+Po GladIZS6SXwtlkNIM2CXdukAqmEsYigsWw3jDo0G0h51ARsouZe9MImtaQIVdJ7mnDYV 1pSQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=DOIUiUS3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:53:00 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 04/33] x86/traps: add install_system_interrupt_handler() Date: Tue, 4 Apr 2023 03:26:47 -0700 Message-Id: <20230404102716.1795-5-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762242899418021310?= X-GMAIL-MSGID: =?utf-8?q?1762242899418021310?= Some kernel components install system interrupt handlers into the IDT, and we need to do the same for system_interrupt_handlers. A new function install_system_interrupt_handler() is added to install a system interrupt handler into both the IDT and system_interrupt_handlers. Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/asm/traps.h | 2 ++ arch/x86/kernel/cpu/acrn.c | 7 +++++-- arch/x86/kernel/cpu/mshyperv.c | 22 ++++++++++++++-------- arch/x86/kernel/kvm.c | 4 +++- arch/x86/kernel/traps.c | 10 ++++++++++ drivers/xen/events/events_base.c | 5 ++++- 6 files changed, 38 insertions(+), 12 deletions(-) diff --git a/arch/x86/include/asm/traps.h b/arch/x86/include/asm/traps.h index 28c8ba5fd81c..46f5e4e2a346 100644 --- a/arch/x86/include/asm/traps.h +++ b/arch/x86/include/asm/traps.h @@ -41,6 +41,8 @@ void math_emulate(struct math_emu_info *); bool fault_in_kernel_space(unsigned long address); +void install_system_interrupt_handler(unsigned int n, const void *asm_addr, const void *addr); + #ifdef CONFIG_VMAP_STACK void __noreturn handle_stack_overflow(struct pt_regs *regs, unsigned long fault_address, diff --git a/arch/x86/kernel/cpu/acrn.c b/arch/x86/kernel/cpu/acrn.c index 485441b7f030..9351bf183a9e 100644 --- a/arch/x86/kernel/cpu/acrn.c +++ b/arch/x86/kernel/cpu/acrn.c @@ -18,6 +18,7 @@ #include #include #include +#include static u32 __init acrn_detect(void) { @@ -26,8 +27,10 @@ static u32 __init acrn_detect(void) static void __init acrn_init_platform(void) { - /* Setup the IDT for ACRN hypervisor callback */ - alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR, asm_sysvec_acrn_hv_callback); + /* Install system interrupt handler for ACRN hypervisor callback */ + install_system_interrupt_handler(HYPERVISOR_CALLBACK_VECTOR, + asm_sysvec_acrn_hv_callback, + sysvec_acrn_hv_callback); x86_platform.calibrate_tsc = acrn_get_tsc_khz; x86_platform.calibrate_cpu = acrn_get_tsc_khz; diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c index f1197366a97d..c102c9192cbb 100644 --- a/arch/x86/kernel/cpu/mshyperv.c +++ b/arch/x86/kernel/cpu/mshyperv.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -491,19 +492,24 @@ static void __init ms_hyperv_init_platform(void) */ x86_platform.apic_post_init = hyperv_init; hyperv_setup_mmu_ops(); - /* Setup the IDT for hypervisor callback */ - alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR, asm_sysvec_hyperv_callback); - /* Setup the IDT for reenlightenment notifications */ + /* Install system interrupt handler for hypervisor callback */ + install_system_interrupt_handler(HYPERVISOR_CALLBACK_VECTOR, + asm_sysvec_hyperv_callback, + sysvec_hyperv_callback); + + /* Install system interrupt handler for reenlightenment notifications */ if (ms_hyperv.features & HV_ACCESS_REENLIGHTENMENT) { - alloc_intr_gate(HYPERV_REENLIGHTENMENT_VECTOR, - asm_sysvec_hyperv_reenlightenment); + install_system_interrupt_handler(HYPERV_REENLIGHTENMENT_VECTOR, + asm_sysvec_hyperv_reenlightenment, + sysvec_hyperv_reenlightenment); } - /* Setup the IDT for stimer0 */ + /* Install system interrupt handler for stimer0 */ if (ms_hyperv.misc_features & HV_STIMER_DIRECT_MODE_AVAILABLE) { - alloc_intr_gate(HYPERV_STIMER0_VECTOR, - asm_sysvec_hyperv_stimer0); + install_system_interrupt_handler(HYPERV_STIMER0_VECTOR, + asm_sysvec_hyperv_stimer0, + sysvec_hyperv_stimer0); } # ifdef CONFIG_SMP diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c index 1cceac5984da..5c684df6de7a 100644 --- a/arch/x86/kernel/kvm.c +++ b/arch/x86/kernel/kvm.c @@ -829,7 +829,9 @@ static void __init kvm_guest_init(void) if (kvm_para_has_feature(KVM_FEATURE_ASYNC_PF_INT) && kvmapf) { static_branch_enable(&kvm_async_pf_enabled); - alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR, asm_sysvec_kvm_asyncpf_interrupt); + install_system_interrupt_handler(HYPERVISOR_CALLBACK_VECTOR, + asm_sysvec_kvm_asyncpf_interrupt, + sysvec_kvm_asyncpf_interrupt); } #ifdef CONFIG_SMP diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index 2cbe7e7e8b96..12072e2af4a6 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -1513,6 +1513,16 @@ static system_interrupt_handler system_interrupt_handlers[NR_SYSTEM_VECTORS] = { #endif /* CONFIG_X86_64 */ +void __init install_system_interrupt_handler(unsigned int n, const void *asm_addr, const void *addr) +{ + BUG_ON(n < FIRST_SYSTEM_VECTOR); + +#ifdef CONFIG_X86_64 + system_interrupt_handlers[n - FIRST_SYSTEM_VECTOR] = (system_interrupt_handler)addr; +#endif + alloc_intr_gate(n, asm_addr); +} + void __init trap_init(void) { /* Init cpu_entry_area before IST entries are set up */ diff --git a/drivers/xen/events/events_base.c b/drivers/xen/events/events_base.c index c7715f8bd452..cf1a5ca3bf62 100644 --- a/drivers/xen/events/events_base.c +++ b/drivers/xen/events/events_base.c @@ -45,6 +45,7 @@ #include #include #include +#include #include #include #endif @@ -2249,7 +2250,9 @@ static __init void xen_alloc_callback_vector(void) return; pr_info("Xen HVM callback vector for event delivery is enabled\n"); - alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR, asm_sysvec_xen_hvm_callback); + install_system_interrupt_handler(HYPERVISOR_CALLBACK_VECTOR, + asm_sysvec_xen_hvm_callback, + sysvec_xen_hvm_callback); } #else void xen_setup_callback_vector(void) {} From patchwork Tue Apr 4 10:26:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 79015 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2949933vqo; Tue, 4 Apr 2023 04:29:08 -0700 (PDT) X-Google-Smtp-Source: AKy350Zu6sduaEQlweg3yxtDZFZNipnb/wbDs9xZyrvBUXJD2GaAOKXb5KZk6fH3YULiPW6HL+Vm X-Received: by 2002:a17:906:2897:b0:932:4990:2563 with SMTP id o23-20020a170906289700b0093249902563mr1873282ejd.24.1680607748256; Tue, 04 Apr 2023 04:29:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680607748; cv=none; d=google.com; s=arc-20160816; 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([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:53:00 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 05/33] x86/traps: add external_interrupt() to dispatch external interrupts Date: Tue, 4 Apr 2023 03:26:48 -0700 Message-Id: <20230404102716.1795-6-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762244950068451948?= X-GMAIL-MSGID: =?utf-8?q?1762244950068451948?= From: "H. Peter Anvin (Intel)" Add external_interrupt() to dispatch external interrupts to their handlers. If an external interrupt is a system interrupt, dipatch it through system_interrupt_handlers table, otherwise to dispatch_common_interrupt(). Signed-off-by: H. Peter Anvin (Intel) Co-developed-by: Xin Li Tested-by: Shan Kang Signed-off-by: Xin Li --- Changes since v5: * Initialize system_interrupt_handlers with dispatch_table_spurious_interrupt() instead of NULL to get rid of a branch (Peter Zijlstra). --- arch/x86/kernel/traps.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index 12072e2af4a6..f86cd233b00b 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -1511,6 +1511,32 @@ static system_interrupt_handler system_interrupt_handlers[NR_SYSTEM_VECTORS] = { #undef SYSV +/* + * External interrupt dispatch function. + * + * Until/unless dispatch_common_interrupt() can be taught to deal with the + * special system vectors, split the dispatch. + * + * Note: dispatch_common_interrupt() already deals with IRQ_MOVE_CLEANUP_VECTOR. + */ +int external_interrupt(struct pt_regs *regs) +{ + unsigned int vector = regs->vector; + unsigned int sysvec = vector - FIRST_SYSTEM_VECTOR; + + if (vector < FIRST_EXTERNAL_VECTOR) { + pr_err("invalid external interrupt vector %d\n", vector); + return -EINVAL; + } + + if (sysvec < NR_SYSTEM_VECTORS) + system_interrupt_handlers[sysvec](regs); + else + dispatch_common_interrupt(regs, vector); + + return 0; +} + #endif /* CONFIG_X86_64 */ void __init install_system_interrupt_handler(unsigned int n, const void *asm_addr, const void *addr) From patchwork Tue Apr 4 10:26:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 79022 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2952950vqo; Tue, 4 Apr 2023 04:33:58 -0700 (PDT) X-Google-Smtp-Source: AKy350Yi7Bw32KKb3wZ0/3nyVSHHRjms3qEd9B2LJ/TyuhznLWh3okNVfO/8Z9/WMF2LWMYtZdV1 X-Received: by 2002:a17:906:3a93:b0:933:9f43:5c3b with SMTP id y19-20020a1709063a9300b009339f435c3bmr1981444ejd.59.1680608037916; Tue, 04 Apr 2023 04:33:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680608037; cv=none; d=google.com; s=arc-20160816; b=eV7pIVsoYkVrV0YxHW1a+BtPPWildXZ7RMWU8NYJIqnpeZG8U6UJZuI9URxLoI1OZG Bd/93Daql2lc0pq7998D72ddkOWgXoeabA9zDePujBtySvYxtxcXoWrsW7G7dMCy5epc EXixF83A0gfm+Ek0SK9yqk0AitYdsqN+nhoPHHuXBUnmQqmlTs5GX+lg1i+BTWbKnymB IC6mGKWR5tRcFv2tx5Jy4X6qnFTHHA8ajAJ6X16hJFMHlE1eXdihpH2lCQd/V2iTyogT MqxGAn98S7tCKCRU9/YA6KhQ01XKaWb/BqPKWG2cF152mG/iGySW83g6Kj9+CAA8bLbR YDaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=s1TnurdU9eI1YRCwil5WMrFTmYZQx9ZLxqgiOpLcQhQ=; b=0yDBdrvab3Y7mPzILJu8iOE7t84bZmOEDBEqG2SXqdEkt7vhjAWyNKkuu3d46AQN43 egvzuN7HPjnrcJOAplbiJE2c5aOlU61S3nbUQiDdTV2JSD7Fkw8YhvOKxDUbvmoYsGeM 1gjHCIYMAkz2q6YA7cbOWvuzbP3jqPB65GXboe6sObw3nfYu9aCR+/+ejMAknEZj7GRh a00aqmPnidinSuDeO0FZRzIncNgihgjNf9BbJicAb/f9nm6cJxsjoY+ZL2O1kOh0rcbh Usp4VW6pZGGNDZ87AoSOty3ojoVyerndeQzIcROvTxJ3QA6bJiYr27aoGWwFEIFmncd7 lpQw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="PzWQ/BE2"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:53:01 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 06/33] x86/cpufeature: add the cpu feature bit for FRED Date: Tue, 4 Apr 2023 03:26:49 -0700 Message-Id: <20230404102716.1795-7-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762245253991322106?= X-GMAIL-MSGID: =?utf-8?q?1762245253991322106?= From: "H. Peter Anvin (Intel)" Add the CPU feature bit for FRED (Flexible Return and Event Delivery). The Intel flexible return and event delivery (FRED) architecture defines simple new transitions that change privilege level (ring transitions). The FRED architecture was designed with the following goals: 1) Improve overall performance and response time by replacing event delivery through the interrupt descriptor table (IDT event delivery) and event return by the IRET instruction with lower latency transitions. 2) Improve software robustness by ensuring that event delivery establishes the full supervisor context and that event return establishes the full user context. The new transitions defined by the FRED architecture are FRED event delivery and, for returning from events, two FRED return instructions. FRED event delivery can effect a transition from ring 3 to ring 0, but it is used also to deliver events incident to ring 0. One FRED instruction (ERETU) effects a return from ring 0 to ring 3, while the other (ERETS) returns while remaining in ring 0. Search for the latest FRED spec in most search engines with this search pattern: site:intel.com FRED (flexible return and event delivery) specification Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/asm/cpufeatures.h | 1 + tools/arch/x86/include/asm/cpufeatures.h | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 73c9672c123b..1fa444478d33 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -318,6 +318,7 @@ #define X86_FEATURE_FZRM (12*32+10) /* "" Fast zero-length REP MOVSB */ #define X86_FEATURE_FSRS (12*32+11) /* "" Fast short REP STOSB */ #define X86_FEATURE_FSRC (12*32+12) /* "" Fast short REP {CMPSB,SCASB} */ +#define X86_FEATURE_FRED (12*32+17) /* Flexible Return and Event Delivery */ #define X86_FEATURE_LKGS (12*32+18) /* "" Load "kernel" (userspace) GS */ #define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */ #define X86_FEATURE_AVX_IFMA (12*32+23) /* "" Support for VPMADD52[H,L]UQ */ diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h index b89005819cd5..e9064f4a011a 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -312,6 +312,7 @@ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */ #define X86_FEATURE_CMPCCXADD (12*32+ 7) /* "" CMPccXADD instructions */ +#define X86_FEATURE_FRED (12*32+17) /* Flexible Return and Event Delivery */ #define X86_FEATURE_LKGS (12*32+18) /* "" Load "kernel" (userspace) GS */ #define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */ #define X86_FEATURE_AVX_IFMA (12*32+23) /* "" Support for VPMADD52[H,L]UQ */ From patchwork Tue Apr 4 10:26:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 79016 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2951478vqo; Tue, 4 Apr 2023 04:31:34 -0700 (PDT) X-Google-Smtp-Source: AKy350Y++99UPjRYDpT05IGgmYXQTXMRzNKSguSLJQC/YVcyoycgvjGG6G3f8PUoZv8QjG74ReMO X-Received: by 2002:a17:906:9513:b0:947:3d04:61dc with SMTP id u19-20020a170906951300b009473d0461dcmr2046155ejx.77.1680607894371; Tue, 04 Apr 2023 04:31:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680607894; cv=none; d=google.com; s=arc-20160816; b=x+AAtl8tPPgqtZwZBU5fqZ4A+2RlyTwhi5NmPzfhQ2msf+SXdIyzIcCZeFWJMLVBvB kdEWEM/bm30WjWn1ljTrRzvwARPZAmBRe41jYLgrFvv9Y5fJYRGmQRtH2ERmgQVjdWZy WgwQjZJLBsw98Te0NT4khqvdX6yXssqg70NHiyb5R/zMh8FNXb+4fqF7HilgLPjPM17K OhCeaT8Qa9CZIEhFHxh1PN0aO3MNQIJizf94Q1gi0hvjlhStUxd7QDjXhwYAR9jnOGTL GDZb2B4FSqZcZ/hbxw0BDEj7NDVcPEJ6m4NjZTQi1f17VtIrmoS5GMMGUDvA7wqrSE6Y FcYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=OnPWU3zKvAFN5zCINdgJhSm8PRbtANkhAuSAcv2ya+Y=; b=uh4Cgpifir+XOrrxbBtFJeJgG3jMujKR/NY6rd29o1bdEEgKb+lvX2VXtp/TfJ3b1D mAKMVVCYbnlwRSFP62ynGPdbzNiivLMNaS0YC3IkZ5pXfK2rHpLqwJsTPOn4KTSfSGab 8ttNLFzQHRSz/Bw30zKCrMPgH+jf/EXEZJvPW6J3M4WPQ3A6IqSC3OVZm9yIjiLEJnxj gzbz62Dbj5MOeFwhvZgoEB/hBG+19AI0Gfv4tmdXgt6zf6a6nWspipIk+ZXu41pPZsvl BGAjpSYNLuvbs3nZYQwT/o5pXbVmkHv5aR3VzITcQxXKNoClbLouUPMUu9jppri6vdSb puyg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=EYD1Pjnd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:53:01 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 07/33] x86/opcode: add ERETU, ERETS instructions to x86-opcode-map Date: Tue, 4 Apr 2023 03:26:50 -0700 Message-Id: <20230404102716.1795-8-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762245103352192247?= X-GMAIL-MSGID: =?utf-8?q?1762245103352192247?= From: "H. Peter Anvin (Intel)" Add the instruction opcodes used by FRED: ERETU, ERETS. Opcode number is per public FRED draft spec v3.0. Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/lib/x86-opcode-map.txt | 2 +- tools/arch/x86/lib/x86-opcode-map.txt | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt index 5168ee0360b2..7a269e269dc0 100644 --- a/arch/x86/lib/x86-opcode-map.txt +++ b/arch/x86/lib/x86-opcode-map.txt @@ -1052,7 +1052,7 @@ EndTable GrpTable: Grp7 0: SGDT Ms | VMCALL (001),(11B) | VMLAUNCH (010),(11B) | VMRESUME (011),(11B) | VMXOFF (100),(11B) | PCONFIG (101),(11B) | ENCLV (000),(11B) -1: SIDT Ms | MONITOR (000),(11B) | MWAIT (001),(11B) | CLAC (010),(11B) | STAC (011),(11B) | ENCLS (111),(11B) +1: SIDT Ms | MONITOR (000),(11B) | MWAIT (001),(11B) | CLAC (010),(11B) | STAC (011),(11B) | ENCLS (111),(11B) | ERETU (F3),(010),(11B) | ERETS (F2),(010),(11B) 2: LGDT Ms | XGETBV (000),(11B) | XSETBV (001),(11B) | VMFUNC (100),(11B) | XEND (101)(11B) | XTEST (110)(11B) | ENCLU (111),(11B) 3: LIDT Ms 4: SMSW Mw/Rv diff --git a/tools/arch/x86/lib/x86-opcode-map.txt b/tools/arch/x86/lib/x86-opcode-map.txt index 5168ee0360b2..7a269e269dc0 100644 --- a/tools/arch/x86/lib/x86-opcode-map.txt +++ b/tools/arch/x86/lib/x86-opcode-map.txt @@ -1052,7 +1052,7 @@ EndTable GrpTable: Grp7 0: SGDT Ms | VMCALL (001),(11B) | VMLAUNCH (010),(11B) | VMRESUME (011),(11B) | VMXOFF (100),(11B) | PCONFIG (101),(11B) | ENCLV (000),(11B) -1: SIDT Ms | MONITOR (000),(11B) | MWAIT (001),(11B) | CLAC (010),(11B) | STAC (011),(11B) | ENCLS (111),(11B) +1: SIDT Ms | MONITOR (000),(11B) | MWAIT (001),(11B) | CLAC (010),(11B) | STAC (011),(11B) | ENCLS (111),(11B) | ERETU (F3),(010),(11B) | ERETS (F2),(010),(11B) 2: LGDT Ms | XGETBV (000),(11B) | XSETBV (001),(11B) | VMFUNC (100),(11B) | XEND (101)(11B) | XTEST (110)(11B) | ENCLU (111),(11B) 3: LIDT Ms 4: SMSW Mw/Rv From patchwork Tue Apr 4 10:26:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 79024 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2953714vqo; Tue, 4 Apr 2023 04:35:03 -0700 (PDT) X-Google-Smtp-Source: AKy350YiECX8RZ29ECB/7QAliKfupXRUC6SaYjvqYdknkvBjR6uIaC1fE+FM/bhCcWJioRWMH7/z X-Received: by 2002:aa7:8bdb:0:b0:62a:1267:2036 with SMTP id s27-20020aa78bdb000000b0062a12672036mr1708126pfd.34.1680608102928; Tue, 04 Apr 2023 04:35:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680608102; cv=none; d=google.com; s=arc-20160816; b=MBe/MTayw1fHoKcoSJUxBuWlbZzFYnWI6oauodBM/leEQ6J0nl97kszEmozJAD9KsK +gJi4zZtzcjbeVFIbBxsqQSZCSqBzLLiWvPYHjOvVaoFJlfRjyLhoJNApPYsbS6LQQaI qOR+n4JMpKU/tVukNQYPzzMFAeEJou+3owcb12lCqtix9QKNlS9Pb+YRuinprbvZCNJs W7qr/xROvBsvc30c/170BcMbTri8K9MuBf9+hsRnGXqD/m1u6Hyn43qg4s4gYYmtWQwY O5rHwR/drqLkLp27LLHZDxqjKuHMWDv2F0QzNB7ttRXTJ4u6EwzrC8q8aEkzFeLNxkvd Etcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tkDfrOl/uVtgxQ9PHVt8tndLfQaqM7/GlymaVGt9Xqw=; b=vNv4K7v5J3lR8S7pMtXVAsbbKUyWV4K3ZNYe72tggFAsCdf1QnP7EWxIWpF5nNvEHL d+fdSN+UEvyV1gaha1RxoL/kbH6NZ6D4de1hxNiAjr0/jXN7wDUKBA1oplSk0pffwChI MFJw5oNfdCCmyhESUriR415KRlxytAO7DMdC4q8GfhGmzprBGZU9qT31+o5ep3qUI0n+ 4CyKuHQ12ROwIG/ywuYS2vOwFHwqB9uOHb/zfRuvczh/+GPKyAySOHyo+PhjaXn1MZ+w zkPOFZmV+NfEpdKpjbas/o2rZDP2F3Jwyjp72M78B5eCNqNsn+DdCcGNCQVRrlmoKO8/ XCqQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Ucmit8aQ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:53:01 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 08/33] x86/objtool: teach objtool about ERETU and ERETS Date: Tue, 4 Apr 2023 03:26:51 -0700 Message-Id: <20230404102716.1795-9-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762245321921118317?= X-GMAIL-MSGID: =?utf-8?q?1762245321921118317?= From: "H. Peter Anvin (Intel)" Update the objtool decoder to know about the ERETU and ERETS instructions (type INSN_CONTEXT_SWITCH.) Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- tools/objtool/arch/x86/decode.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/tools/objtool/arch/x86/decode.c b/tools/objtool/arch/x86/decode.c index 9ef024fd648c..8e9c802f78ec 100644 --- a/tools/objtool/arch/x86/decode.c +++ b/tools/objtool/arch/x86/decode.c @@ -509,11 +509,20 @@ int arch_decode_instruction(struct objtool_file *file, const struct section *sec if (op2 == 0x01) { - if (modrm == 0xca) - insn->type = INSN_CLAC; - else if (modrm == 0xcb) - insn->type = INSN_STAC; - + switch (insn_last_prefix_id(&ins)) { + case INAT_PFX_REPE: + case INAT_PFX_REPNE: + if (modrm == 0xca) + /* eretu/erets */ + insn->type = INSN_CONTEXT_SWITCH; + break; + default: + if (modrm == 0xca) + insn->type = INSN_CLAC; + else if (modrm == 0xcb) + insn->type = INSN_STAC; + break; + } } else if (op2 >= 0x80 && op2 <= 0x8f) { insn->type = INSN_JUMP_CONDITIONAL; From patchwork Tue Apr 4 10:26:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 79006 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2941649vqo; Tue, 4 Apr 2023 04:15:15 -0700 (PDT) X-Google-Smtp-Source: AKy350Zmkv6SMxohoUILdPl1gMf0Sd8UFKjQF7oSJNfO0lIegp3d2EyCnv6Q7Em6zbOS/fF31NE6 X-Received: by 2002:a17:90b:4b01:b0:23f:7625:49b6 with SMTP id lx1-20020a17090b4b0100b0023f762549b6mr2427513pjb.37.1680606915518; Tue, 04 Apr 2023 04:15:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680606915; cv=none; d=google.com; s=arc-20160816; b=s8Ylu/cUzthntFm7U/C1U0VQ9jpORL7PtMk9ymEZRcvPitPtv5fe4Df6QC+eDMewIT okGY9XU64226kQm2EQuSnVgWHJf9x6NVRPrvJMcNkU9w+ekJRgZxx6mdF+M3VkiZARey l2jev9r36hJYmSyUDMNdueA9rrWwmQz3BGWYtP24DPgk6zgwJYqBgAcbDyuJtVhQNTsc ba8tF1tXnIotyS5j9jf2QNV6uM2agL22/317h2fiLLU1KsPCpEDxVF6GbDF/0S7YSyuD iExjSc4eBEEip7aVqV136ysJYg0IdNH/p6AjPX2AEqif6VvHlYW5r+CBSoWSdHWqY3gC pV2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=xiBkMNop4zUxT+iIfOnmWuMSopGG/t7/1Amns2i3v5k=; b=UEWvCSowiEU8Fd8SssNh1Z5jOpgCZ6DdzW8SPEO+cuDcC1OEEyjFY3C9x7ocvdJVmy xSp+tUSYPAbpvPCmpMTDx86NHAwBu2DjOWCbxwIFuiFIHbv7l4g5MWi3h1VVpPWuvv7N A2qhb/qBh6WdompmLEFlpKwzMt6p1SZ9JupJ16lmfQsOQCMbK3HDh6p2F/gYOxHLGceH JGNibZMKMovdPlvHx79teJI4v3DhV1aaiBqnUaBc+6geXg7IDpJjdPFJqk9Ex0xjok9b PKVVGg6N4awWqk1D+KdDI6RnHGE4Gyd+T7vszUlA7Ayz47HFCqkLVDD4m4nh5h/WIh/t 0L1Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=nZH5g8eD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:53:01 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 09/33] x86/cpu: add X86_CR4_FRED macro Date: Tue, 4 Apr 2023 03:26:52 -0700 Message-Id: <20230404102716.1795-10-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762244077004334411?= X-GMAIL-MSGID: =?utf-8?q?1762244077004334411?= From: "H. Peter Anvin (Intel)" Add X86_CR4_FRED macro for the FRED bit in %cr4. This bit should be a pinned bit, not to be changed after initialization. Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/uapi/asm/processor-flags.h | 2 ++ arch/x86/kernel/cpu/common.c | 11 ++++++++--- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/uapi/asm/processor-flags.h b/arch/x86/include/uapi/asm/processor-flags.h index c47cc7f2feeb..a90933f1ff41 100644 --- a/arch/x86/include/uapi/asm/processor-flags.h +++ b/arch/x86/include/uapi/asm/processor-flags.h @@ -132,6 +132,8 @@ #define X86_CR4_PKE _BITUL(X86_CR4_PKE_BIT) #define X86_CR4_CET_BIT 23 /* enable Control-flow Enforcement Technology */ #define X86_CR4_CET _BITUL(X86_CR4_CET_BIT) +#define X86_CR4_FRED_BIT 32 /* enable FRED kernel entry */ +#define X86_CR4_FRED _BITULL(X86_CR4_FRED_BIT) /* * x86-64 Task Priority Register, CR8 diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 8cd4126d8253..e8cf6f4cfb52 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -412,10 +412,15 @@ static __always_inline void setup_umip(struct cpuinfo_x86 *c) cr4_clear_bits(X86_CR4_UMIP); } -/* These bits should not change their value after CPU init is finished. */ +/* + * These bits should not change their value after CPU init is finished. + * The explicit cast to unsigned long suppresses a warning on i386 for + * x86-64 only feature bits >= 32. + */ static const unsigned long cr4_pinned_mask = - X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | - X86_CR4_FSGSBASE | X86_CR4_CET; + (unsigned long) + (X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | + X86_CR4_FSGSBASE | X86_CR4_CET | X86_CR4_FRED); static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); static unsigned long cr4_pinned_bits __ro_after_init; From patchwork Tue Apr 4 10:26:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 79012 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2947281vqo; Tue, 4 Apr 2023 04:25:09 -0700 (PDT) X-Google-Smtp-Source: AKy350b+P03Ye86dnJZBbcGhHborxuzLkl2eojUU5nqigjZFjBNpLMW/XmaW525U4rP25Yngh8ZK X-Received: by 2002:a05:6a20:c426:b0:de:9f78:f677 with SMTP id en38-20020a056a20c42600b000de9f78f677mr1670982pzb.23.1680607509389; Tue, 04 Apr 2023 04:25:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680607509; cv=none; d=google.com; s=arc-20160816; b=A9u8NxLb8ER1IociMn4gHWv8LDr2RAm1KB9C4X+gOx076gl8PHUOQAc+96YodcnprT bMSeHbuAGOReu0fxH+0qsTRjUNNj9heN40oBMTR1KgbVPibDOal3RX/AkiyCycqAvHIc 06Tgh+AMyrqIqdGig6Zn4A/0Z/pbsC/yCx3AW6RjHiVZjCewXXP8twuPjMfBz9zEdFHT VpkEg6ISsqsTVGytekKtAyJWDM1RFEQkFicDUtabQjdZIdk/FRZw4oWiE3IIeWU5BKuD +E3iJfKa37ckniZwbgzjLsbDeS9QhcnoaTtTvlPnYcOYtkhOzBnJduMYODdABNkq3am4 hYjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=P6HtFL7+PoyEnNsypW2XPKGndzZapARWh2X/00BDeqI=; b=kBR0xsqb0x33h8D0qQH66C1KiK/Ueue8ukD46pLshC9CpbUP6aQ0BT5BbpRB8waLF8 0mF9zLUhG+6Xw6E2d61ryToTqFMz4CXkGLyRtd2aEbiedazxQyoYdqJd66RA4DuqO9II F4yF973sGhzHmFZ5Szg+tQPsbRaZJSqt7/0TeJqnlZCPha0Q9kG7opfnNTTaqCQ5ZodX mbgYQeFf6NQqZzX3efyRSdo9v2Q4ufpFfXP2X7g84EVVCqLne3ZQzu//ml2+VLs6qY2Q 7fFpnCWmYp60vmhhMn1Ki95djflRfeg24ZTvALgCPdMLV0LJG3+VDS3oUky6DjEMWn0y w3Dg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=GkHf5rh3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:53:02 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 10/33] x86/fred: add Kconfig option for FRED (CONFIG_X86_FRED) Date: Tue, 4 Apr 2023 03:26:53 -0700 Message-Id: <20230404102716.1795-11-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762244699695932114?= X-GMAIL-MSGID: =?utf-8?q?1762244699695932114?= From: "H. Peter Anvin (Intel)" Add the configuration option CONFIG_X86_FRED to enable FRED. Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/Kconfig | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index a825bf031f49..da62178bb246 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -500,6 +500,15 @@ config X86_CPU_RESCTRL Say N if unsure. +config X86_FRED + bool "Flexible Return and Event Delivery" + depends on X86_64 + help + When enabled, try to use Flexible Return and Event Delivery + instead of the legacy SYSCALL/SYSENTER/IDT architecture for + ring transitions and exception/interrupt handling if the + system supports. + if X86_32 config X86_BIGSMP bool "Support for big SMP systems with more than 8 CPUs" From patchwork Tue Apr 4 10:26:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 79030 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2955281vqo; Tue, 4 Apr 2023 04:37:44 -0700 (PDT) X-Google-Smtp-Source: AKy350ZNmbVkyDk/LzrdZV8XiQzv4z3ylXjI+LwVwENvk0/iL0KYWhIWrx85nfpikvVRpcKTapAo X-Received: by 2002:a17:906:b04f:b0:92e:d6e6:f3ad with SMTP id bj15-20020a170906b04f00b0092ed6e6f3admr1810477ejb.6.1680608264398; Tue, 04 Apr 2023 04:37:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680608264; cv=none; d=google.com; s=arc-20160816; b=gIsImxO7fcPDL05tR99FnIlAt+kUEH7LjwSCwcoUzFHa8avn+w/WA8EizWA4ysdA88 pAuOrf/nXDEil2GgxAG+aGt6OP3XN5zDwmfKjsO3LQs5Gu1ylCbIg1N13TChPLRk8o3G 7HEBk6r7CVQC0wp7BiDvMhtU6S5yNJyrV6232TvXSwLLRkIIQ0oIEZdgJnpV6+Qq8Y8/ 2c2J+heJRcEgE7Gj/EoXOaki92ko00ZPZ6XiyI45xLQ9sjICJJK2xRpkcO7xiZ5vLOkr TtZZHhmgTIZLgoNwz5kN591nQ6MraRIhWruJ9PBeXFRGk6WeAYzMJZf2M9XqkRPPCKIT CKIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=UNRomGZrJ3xieh7lf30jl8hFXPb8gU2nVpw4p5i9r5Y=; b=U2QCfG+xfQAM8mOk2DzHH17zlqz/tdCxZFDwe+G4j+mUFfG/Q7be8PXWdppCvkM1x4 KHqn1RPD4GSmGpdkT/iOOfV+q4SQ8W312BcUgdxteajgHr6zF6WIdlcwUz4ZGeK9bNke 9JBuc15YIy9KG/yZJIJfMOmJXzS9vQNzO2JpnCeocuadkCtYP3aSiK1tOvUQvM+TwyRH 0dviQjuASIONlGugdLCXrCWWCtCJULgAU2Yf27WWC/aQsM1T5ifeQCsN76/zYM6bJ8vq wFRyWB3ekEXDzYRKx4xldSSSPByhTyKv+G+gj0kZi8qqD4x48HFYGPzECVo0Gk3l1SKp Hzbg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="G4DV/Jj2"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:53:02 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 11/33] x86/fred: if CONFIG_X86_FRED is disabled, disable FRED support Date: Tue, 4 Apr 2023 03:26:54 -0700 Message-Id: <20230404102716.1795-12-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762245491278618475?= X-GMAIL-MSGID: =?utf-8?q?1762245491278618475?= From: "H. Peter Anvin (Intel)" Add CONFIG_X86_FRED to to make cpu_feature_enabled() work correctly with FRED. Originally-by: Megha Dey Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/asm/disabled-features.h | 8 +++++++- tools/arch/x86/include/asm/disabled-features.h | 8 +++++++- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h index 5dfa4fb76f4b..56838de9cb23 100644 --- a/arch/x86/include/asm/disabled-features.h +++ b/arch/x86/include/asm/disabled-features.h @@ -99,6 +99,12 @@ # define DISABLE_TDX_GUEST (1 << (X86_FEATURE_TDX_GUEST & 31)) #endif +#ifdef CONFIG_X86_FRED +# define DISABLE_FRED 0 +#else +# define DISABLE_FRED (1 << (X86_FEATURE_FRED & 31)) +#endif + /* * Make sure to add features to the correct mask */ @@ -115,7 +121,7 @@ #define DISABLED_MASK10 0 #define DISABLED_MASK11 (DISABLE_RETPOLINE|DISABLE_RETHUNK|DISABLE_UNRET| \ DISABLE_CALL_DEPTH_TRACKING) -#define DISABLED_MASK12 0 +#define DISABLED_MASK12 (DISABLE_FRED) #define DISABLED_MASK13 0 #define DISABLED_MASK14 0 #define DISABLED_MASK15 0 diff --git a/tools/arch/x86/include/asm/disabled-features.h b/tools/arch/x86/include/asm/disabled-features.h index 5dfa4fb76f4b..56838de9cb23 100644 --- a/tools/arch/x86/include/asm/disabled-features.h +++ b/tools/arch/x86/include/asm/disabled-features.h @@ -99,6 +99,12 @@ # define DISABLE_TDX_GUEST (1 << (X86_FEATURE_TDX_GUEST & 31)) #endif +#ifdef CONFIG_X86_FRED +# define DISABLE_FRED 0 +#else +# define DISABLE_FRED (1 << (X86_FEATURE_FRED & 31)) +#endif + /* * Make sure to add features to the correct mask */ @@ -115,7 +121,7 @@ #define DISABLED_MASK10 0 #define DISABLED_MASK11 (DISABLE_RETPOLINE|DISABLE_RETHUNK|DISABLE_UNRET| \ DISABLE_CALL_DEPTH_TRACKING) -#define DISABLED_MASK12 0 +#define DISABLED_MASK12 (DISABLE_FRED) #define DISABLED_MASK13 0 #define DISABLED_MASK14 0 #define DISABLED_MASK15 0 From patchwork Tue Apr 4 10:26:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 78996 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2930844vqo; Tue, 4 Apr 2023 03:57:04 -0700 (PDT) X-Google-Smtp-Source: AKy350axJQlP/eKHF7jcs54T3TwByHLOYgOR2AaeBlPxrVUxSiUYLMQvo5cMXVs3xccd9hSI4lDv X-Received: by 2002:a17:906:14d5:b0:931:59f:d42 with SMTP id y21-20020a17090614d500b00931059f0d42mr1753964ejc.29.1680605823688; Tue, 04 Apr 2023 03:57:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680605823; cv=none; d=google.com; s=arc-20160816; b=f5CI68nwohll5RkrYb1JTuhM9QMdCEG3MVzF2jdpaUSGMNoQsQWArqv1CmFAoVYnLM SV9xbL5wUEBjMjhjlaixYU59xd3R6h/G72M1hO6AnpCTu3daTi189AN4GconARQ7H7BB VJzc5eM8n91bBJqtm/u+tUN+ujyfnDSZ/P1rtpw5VVbmOUm9cXKVTaTfsrr7V5wlZttx q6zT+DD4iGrXN16rCJ3K46HSWdZNOhOy1WhWpgCzSU+N26xSkGgEsX93M/IXl+8Xzaqu z7ipuNOWTm6pDNSspp3L8wS5oxNHcu33WR3VJsq8V2R6Z8EsvF/CfIV3hcUlBtWaneVF c8ug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=bxlRTsP9VdEoqzfLEjO6uA1EB+3I6TDY2eyMrxjMlAY=; b=GRIt8saI7YXp/szAavFIGoDgxSUkY4ohafftxhrp8ivnlP5ElZivs7nozIqlPnFWYh 4NF8WVVg1IbYff3o0DobbRU3TsHLw11y0UUKiqxWfzCtRy7rCGLjq3Kc1E7W4CnNfxZY xOS2G5czrf+Ws6qv2rJeJPPaaSpdul+RgwJYRVO5BEtMq3Jtzv3VHCQWNZdjGTLw/5lf Gt+101bXykIVV3RUZRatsPpztuCWKJ48UZLK6VsIklXbCQiQRT4eQG5WkQ/iZQI94vXZ KacRAi/5Q3GT1G0cNO09db52SUsQ2JLOmxBnb1wJMM71ezeK4A2QQhuN1OGNkVLpTmUo sgOQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Oj+6Cnne; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:53:02 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 12/33] x86/cpu: add MSR numbers for FRED configuration Date: Tue, 4 Apr 2023 03:26:55 -0700 Message-Id: <20230404102716.1795-13-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762242932322211624?= X-GMAIL-MSGID: =?utf-8?q?1762242932322211624?= From: "H. Peter Anvin (Intel)" Add MSR numbers for the FRED configuration registers. Originally-by: Megha Dey Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/asm/msr-index.h | 13 ++++++++++++- tools/arch/x86/include/asm/msr-index.h | 13 ++++++++++++- 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index ad35355ee43e..87db728f8bbc 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -36,8 +36,19 @@ #define EFER_FFXSR (1<<_EFER_FFXSR) #define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS) -/* Intel MSRs. Some also available on other CPUs */ +/* FRED MSRs */ +#define MSR_IA32_FRED_RSP0 0x1cc /* Level 0 stack pointer */ +#define MSR_IA32_FRED_RSP1 0x1cd /* Level 1 stack pointer */ +#define MSR_IA32_FRED_RSP2 0x1ce /* Level 2 stack pointer */ +#define MSR_IA32_FRED_RSP3 0x1cf /* Level 3 stack pointer */ +#define MSR_IA32_FRED_STKLVLS 0x1d0 /* Exception stack levels */ +#define MSR_IA32_FRED_SSP0 MSR_IA32_PL0_SSP /* Level 0 shadow stack pointer */ +#define MSR_IA32_FRED_SSP1 0x1d1 /* Level 1 shadow stack pointer */ +#define MSR_IA32_FRED_SSP2 0x1d2 /* Level 2 shadow stack pointer */ +#define MSR_IA32_FRED_SSP3 0x1d3 /* Level 3 shadow stack pointer */ +#define MSR_IA32_FRED_CONFIG 0x1d4 /* Entrypoint and interrupt stack level */ +/* Intel MSRs. Some also available on other CPUs */ #define MSR_TEST_CTRL 0x00000033 #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29 #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT) diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h index ad35355ee43e..87db728f8bbc 100644 --- a/tools/arch/x86/include/asm/msr-index.h +++ b/tools/arch/x86/include/asm/msr-index.h @@ -36,8 +36,19 @@ #define EFER_FFXSR (1<<_EFER_FFXSR) #define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS) -/* Intel MSRs. Some also available on other CPUs */ +/* FRED MSRs */ +#define MSR_IA32_FRED_RSP0 0x1cc /* Level 0 stack pointer */ +#define MSR_IA32_FRED_RSP1 0x1cd /* Level 1 stack pointer */ +#define MSR_IA32_FRED_RSP2 0x1ce /* Level 2 stack pointer */ +#define MSR_IA32_FRED_RSP3 0x1cf /* Level 3 stack pointer */ +#define MSR_IA32_FRED_STKLVLS 0x1d0 /* Exception stack levels */ +#define MSR_IA32_FRED_SSP0 MSR_IA32_PL0_SSP /* Level 0 shadow stack pointer */ +#define MSR_IA32_FRED_SSP1 0x1d1 /* Level 1 shadow stack pointer */ +#define MSR_IA32_FRED_SSP2 0x1d2 /* Level 2 shadow stack pointer */ +#define MSR_IA32_FRED_SSP3 0x1d3 /* Level 3 shadow stack pointer */ +#define MSR_IA32_FRED_CONFIG 0x1d4 /* Entrypoint and interrupt stack level */ +/* Intel MSRs. Some also available on other CPUs */ #define MSR_TEST_CTRL 0x00000033 #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29 #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT) From patchwork Tue Apr 4 10:26:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 79027 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2954986vqo; Tue, 4 Apr 2023 04:37:12 -0700 (PDT) X-Google-Smtp-Source: AKy350bdLahOTUpeRl1nEhamcEx5/H3Vqej1bo/OrcN9nhxuXNwUUMA8snbV+deEvdy7NVytIl7M X-Received: by 2002:a17:906:58d6:b0:947:792d:bf7e with SMTP id e22-20020a17090658d600b00947792dbf7emr2275976ejs.58.1680608232418; Tue, 04 Apr 2023 04:37:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680608232; cv=none; d=google.com; s=arc-20160816; b=FTJdQBjU/FTCHjBgQpzBUNNREH/PnT8QLoIHr5CvenmwYnHrzCoLzXkP496nqb3Dc5 8//Xxr0S+1bUr6RGIdxeKZRP0HarFbOuCZrtZDopGPLWtETIR0fpAmEeRbo45AnulHZH YjkATH975HR1ydgtg9eDlckRolBailzJYhnSzYXggocC0Ib+oFJrSyzOCh0mI2Dd6Fof VNF7Hig3ZK8nB8R/k+L6LWkpjygI6KL/Qq8QvIRQmj32LExpEF4w3zLYI6jbxmqRg03L D8NpfT1AwZxLQM+zhwrgLnwbUrCBpczlHOwDQeYhomyJZ00HCawG0CwbHqJMsydAIzwX jsuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=+VaUPr04RvGnPD9G9LEI7rZpFLR5XlVkh+7KmqRc0j4=; b=FEBf3XGLDpTY/+myqX0SqlOWs9GhHmKmn6D/PQ/U643fdD50yBpngqiwyuDW8VuSEc vkbwpc8zTZIo+/4FysuJoCKo9wbHVZfRxhgqUgxZVL03mbe1Qwbm8sO70wKtjA4Bfw4m tTxWwHbfXWcAMtnBXkb26xtznC8rBefW6ZQN1sNAM64VcmUce7Qf1/sajfrzO5w3t9Ep 7zsiAn5WPQUSxoMhSajspWWU5M43a1dI5LkZP/OiZWxGhv1OLQB3n5DW0f15e4TuUrKW ViJP7SGpHgeXShA1IkVXmjSpmybQeEeNd9v8TGK2Wbftu0zo0jb09ZK9DYdxb9TlNwfj CgiA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=BGuYly58; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:53:02 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 13/33] x86/fred: header file for event types Date: Tue, 4 Apr 2023 03:26:56 -0700 Message-Id: <20230404102716.1795-14-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762245457657705550?= X-GMAIL-MSGID: =?utf-8?q?1762245457657705550?= FRED inherits the Intel VT-x enhancement of classified events with a two-level event dispatch logic. The first-level dispatch is on the event type, not the event vector as used in the IDT architecture. This also means that vectors in different event types are orthogonal, e.g., vectors 0x10-0x1f become available as hardware interrupts. Add a header file for event types, and also use it in . Suggested-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/asm/event-type.h | 17 +++++++++++++++++ arch/x86/include/asm/vmx.h | 17 +++++++++-------- 2 files changed, 26 insertions(+), 8 deletions(-) create mode 100644 arch/x86/include/asm/event-type.h diff --git a/arch/x86/include/asm/event-type.h b/arch/x86/include/asm/event-type.h new file mode 100644 index 000000000000..fedaa0e492c5 --- /dev/null +++ b/arch/x86/include/asm/event-type.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_X86_EVENT_TYPE_H +#define _ASM_X86_EVENT_TYPE_H + +/* + * Event type codes: these are the same that are used by VTx. + */ +#define EVENT_TYPE_HWINT 0 /* Maskable external interrupt */ +#define EVENT_TYPE_RESERVED 1 +#define EVENT_TYPE_NMI 2 /* Non-maskable interrupt */ +#define EVENT_TYPE_HWFAULT 3 /* Hardware exceptions (e.g., page fault) */ +#define EVENT_TYPE_SWINT 4 /* Software interrupt (INT n) */ +#define EVENT_TYPE_PRIVSW 5 /* INT1 (ICEBP) */ +#define EVENT_TYPE_SWFAULT 6 /* Software exception (INT3 or INTO) */ +#define EVENT_TYPE_OTHER 7 /* FRED: SYSCALL/SYSENTER */ + +#endif diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h index 498dc600bd5c..8d9b8b0d8e56 100644 --- a/arch/x86/include/asm/vmx.h +++ b/arch/x86/include/asm/vmx.h @@ -15,6 +15,7 @@ #include #include #include +#include #include #define VMCS_CONTROL_BIT(x) BIT(VMX_FEATURE_##x & 0x1f) @@ -372,14 +373,14 @@ enum vmcs_field { #define VECTORING_INFO_DELIVER_CODE_MASK INTR_INFO_DELIVER_CODE_MASK #define VECTORING_INFO_VALID_MASK INTR_INFO_VALID_MASK -#define INTR_TYPE_EXT_INTR (0 << 8) /* external interrupt */ -#define INTR_TYPE_RESERVED (1 << 8) /* reserved */ -#define INTR_TYPE_NMI_INTR (2 << 8) /* NMI */ -#define INTR_TYPE_HARD_EXCEPTION (3 << 8) /* processor exception */ -#define INTR_TYPE_SOFT_INTR (4 << 8) /* software interrupt */ -#define INTR_TYPE_PRIV_SW_EXCEPTION (5 << 8) /* ICE breakpoint - undocumented */ -#define INTR_TYPE_SOFT_EXCEPTION (6 << 8) /* software exception */ -#define INTR_TYPE_OTHER_EVENT (7 << 8) /* other event */ +#define INTR_TYPE_EXT_INTR (EVENT_TYPE_HWINT << 8) /* external interrupt */ +#define INTR_TYPE_RESERVED (EVENT_TYPE_RESERVED << 8) /* reserved */ +#define INTR_TYPE_NMI_INTR (EVENT_TYPE_NMI << 8) /* NMI */ +#define INTR_TYPE_HARD_EXCEPTION (EVENT_TYPE_HWFAULT << 8) /* processor exception */ +#define INTR_TYPE_SOFT_INTR (EVENT_TYPE_SWINT << 8) /* software interrupt */ +#define INTR_TYPE_PRIV_SW_EXCEPTION (EVENT_TYPE_PRIVSW << 8) /* ICE breakpoint - undocumented */ +#define INTR_TYPE_SOFT_EXCEPTION (EVENT_TYPE_SWFAULT << 8) /* software exception */ +#define INTR_TYPE_OTHER_EVENT (EVENT_TYPE_OTHER << 8) /* other event */ /* GUEST_INTERRUPTIBILITY_INFO flags. */ #define GUEST_INTR_STATE_STI 0x00000001 From patchwork Tue Apr 4 10:26:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 79029 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2955207vqo; Tue, 4 Apr 2023 04:37:35 -0700 (PDT) X-Google-Smtp-Source: AKy350aXiPMk+mD6yoyroWvgTZ8OxsBQL5jI1B5/UIfoQDad3Er10K9TAs5iWPtADM3w+pm9PQG+ X-Received: by 2002:aa7:d148:0:b0:502:62:78 with SMTP id r8-20020aa7d148000000b0050200620078mr2089003edo.28.1680608255608; Tue, 04 Apr 2023 04:37:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680608255; cv=none; d=google.com; s=arc-20160816; b=W2xah7LlgDJfoG52xqGEvwzP7QZl9iW3xRl2LvEVlUOBd1ZyelzswIswbm7cqANCIx tNBXdbx4zrqpMUeKchKnUsZfvQun0M+jut/C7OlkYbYER7aKgstqI6bNQTnbEDFowvJb o794QiGQgh0aYYiy38tOx14x+Sfj3iNU2Yno6PLph8y4H+FH9iiEQG1h+BRQADKMie42 UnVhUe4DqpslqDlfwiQiRs/183E2vNykWiPjSOJK6bkTIXAo+CiUHmNsxKqxD75t1mOJ wVLzTjibswR3AffF5ph4JuZ5Sn//mFIAX+SiWfKV6FW2C+ufr38okmNfz/TwrfdjcNVs NXMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=RRd0UBdwKjamp5FLwk0MN5YETEbG7sJ4jhrhEPxF8Ss=; b=tdJ8b+Qxxx3Mjz+XNTceoaZfITzj8cwTgrF1qyGpjKdhSxC7P9m5F9L32o21ZvLERN O8shs5qX0Yih3k4Tbs9Ac1nGFN1p/qelAqv92SEDuj7PO+3fH/g+CcvqtzfOGkGCxmQS GfVtCmt5wbad3DVwNi8pkKAWGJhNFy7xipPUDF1er26Z3cT5RMxAulAnf/xVVGlSR277 pTt8cneKF3y14Uyh/qIrZ62yet5A33lzv9Rs3kIX8cqhN7YXbIHqKZjwqOHAVhuw5raC GaJKQBSOThaREzWjEjsYr5EyRFnmdF8oiI6htjDJACQevQvAxNax2aWyKJ4/ngLqsNep 6FJw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=QT0korpH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:53:03 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 14/33] x86/fred: header file with FRED definitions Date: Tue, 4 Apr 2023 03:26:57 -0700 Message-Id: <20230404102716.1795-15-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762245482478468564?= X-GMAIL-MSGID: =?utf-8?q?1762245482478468564?= From: "H. Peter Anvin (Intel)" Add a header file for FRED prototypes and definitions. Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- Changes since v6: * Replace pt_regs csx flags prefix FRED_CSL_ with FRED_CSX_. --- arch/x86/include/asm/fred.h | 106 ++++++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) create mode 100644 arch/x86/include/asm/fred.h diff --git a/arch/x86/include/asm/fred.h b/arch/x86/include/asm/fred.h new file mode 100644 index 000000000000..b59397411ab9 --- /dev/null +++ b/arch/x86/include/asm/fred.h @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * arch/x86/include/asm/fred.h + * + * Macros for Flexible Return and Event Delivery (FRED) + */ + +#ifndef ASM_X86_FRED_H +#define ASM_X86_FRED_H + +#ifdef CONFIG_X86_FRED + +#include +#include + +/* + * FRED return instructions + * + * Replace with "ERETS"/"ERETU" once binutils support FRED return instructions. + * The binutils version supporting FRED instructions is still TBD, and will + * update once we have it. + */ +#define ERETS _ASM_BYTES(0xf2,0x0f,0x01,0xca) +#define ERETU _ASM_BYTES(0xf3,0x0f,0x01,0xca) + +/* + * RSP is aligned to a 64-byte boundary before used to push a new stack frame + */ +#define FRED_STACK_FRAME_RSP_MASK _AT(unsigned long, (~0x3f)) + +/* + * Event stack level macro for the FRED_STKLVLS MSR. + * Usage example: FRED_STKLVL(X86_TRAP_DF, 3) + * Multiple values can be ORd together. + */ +#define FRED_STKLVL(v,l) (_AT(unsigned long, l) << (2*(v))) + +/* FRED_CONFIG MSR */ +#define FRED_CONFIG_CSL_MASK 0x3 +#define FRED_CONFIG_REDZONE_AMOUNT 1 /* measured in 64-byte cache lines */ +#define FRED_CONFIG_REDZONE (_AT(unsigned long, FRED_CONFIG_REDZONE_AMOUNT) << 6) +#define FRED_CONFIG_INT_STKLVL(l) (_AT(unsigned long, l) << 9) +#define FRED_CONFIG_ENTRYPOINT(p) _AT(unsigned long, (p)) + +/* FRED event type and vector bit width and counts */ +#define FRED_EVENT_TYPE_BITS 3 /* only 3 bits used in FRED 3.0 */ +#define FRED_EVENT_TYPE_COUNT _BITUL(FRED_EVENT_TYPE_BITS) +#define FRED_EVENT_VECTOR_BITS 8 +#define FRED_EVENT_VECTOR_COUNT _BITUL(FRED_EVENT_VECTOR_BITS) + +/* FRED EVENT_TYPE_OTHER vector numbers */ +#define FRED_SYSCALL 1 +#define FRED_SYSENTER 2 + +/* Flags above the CS selector (regs->csx) */ +#define FRED_CSX_ENABLE_NMI _BITUL(28) +#define FRED_CSX_ALLOW_SINGLE_STEP _BITUL(25) +#define FRED_CSX_INTERRUPT_SHADOW _BITUL(24) + +#ifndef __ASSEMBLY__ + +#include +#include + +/* FRED stack frame information */ +struct fred_info { + unsigned long edata; /* Event data: CR2, DR6, ... */ + unsigned long resv; +}; + +/* Full format of the FRED stack frame */ +struct fred_frame { + struct pt_regs regs; + struct fred_info info; +}; + +/* Getting the FRED frame information from a pt_regs pointer */ +static __always_inline struct fred_info *fred_info(struct pt_regs *regs) +{ + return &container_of(regs, struct fred_frame, regs)->info; +} + +static __always_inline unsigned long fred_event_data(struct pt_regs *regs) +{ + return fred_info(regs)->edata; +} + +/* + * How FRED event handlers are called. + * + * FRED event delivery establishes the full supervisor context + * by pushing everything related to the event being delivered + * to the FRED stack frame, e.g., the faulting linear address + * of a #PF is pushed as event data of the FRED #PF stack frame. + * Thus a struct pt_regs has everything needed and it's the only + * input parameter required for a FRED event handler. + */ +#define DECLARE_FRED_HANDLER(f) void f (struct pt_regs *regs) +#define DEFINE_FRED_HANDLER(f) noinstr DECLARE_FRED_HANDLER(f) +typedef DECLARE_FRED_HANDLER((*fred_handler)); + +#endif /* __ASSEMBLY__ */ + +#endif /* CONFIG_X86_FRED */ + +#endif /* ASM_X86_FRED_H */ From patchwork Tue Apr 4 10:26:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 79028 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2955123vqo; Tue, 4 Apr 2023 04:37:28 -0700 (PDT) X-Google-Smtp-Source: AKy350ZDKGHYdI5L1If3qbBeXkLP0OlHuwnV+9Xzlro2swAp/LsWCNhjwTg6K8cfcd+gJ8vc1eCQ X-Received: by 2002:a17:906:b0da:b0:92e:efa:b9b4 with SMTP id bk26-20020a170906b0da00b0092e0efab9b4mr1888567ejb.22.1680608248429; Tue, 04 Apr 2023 04:37:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680608248; cv=none; d=google.com; s=arc-20160816; b=y9+PRJlojUWmtAFJYG19MPnSUHHspCcyZzTcDq2tm2XdGx8UPIGtB4wRFW9OIhuTM5 O1a9YyuFC2RevvJLveFgLbejBJ05HBtgkmULLD5IaJ4ohuAQDExUfYyTLUB5uoLpL1bF +qznWyt6G6i77q1B8pYbO6XTgqCdtZhCO/Ga46TutImMvJZXL7ksv3l5CrGy6khHZGnF NmJwbypL4HABZ1CRiZhZoiR0u8g1ij4J1z1558ARU9jH5IyFYZM49QOWiY1+nh8cZSez IJ2X/NP97otQQeEdTmJUaK5Kge52pRRPYNyM5z/aM0xx1koH6Op48jMwg0Kkxq5QgBC9 rKdw== ARC-Message-Signature: i=1; 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([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:53:03 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 15/33] x86/fred: reserve space for the FRED stack frame Date: Tue, 4 Apr 2023 03:26:58 -0700 Message-Id: <20230404102716.1795-16-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762245474890118078?= X-GMAIL-MSGID: =?utf-8?q?1762245474890118078?= From: "H. Peter Anvin (Intel)" When using FRED, reserve space at the top of the stack frame, just like i386 does. A future version of FRED might have dynamic frame sizes, though, in which case it might be necessary to make TOP_OF_KERNEL_STACK_PADDING a variable instead of a constant. Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/asm/thread_info.h | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h index f1cccba52eb9..998483078d5f 100644 --- a/arch/x86/include/asm/thread_info.h +++ b/arch/x86/include/asm/thread_info.h @@ -31,7 +31,9 @@ * In vm86 mode, the hardware frame is much longer still, so add 16 * bytes to make room for the real-mode segments. * - * x86_64 has a fixed-length stack frame. + * x86-64 has a fixed-length stack frame, but it depends on whether + * or not FRED is enabled. Future versions of FRED might make this + * dynamic, but for now it is always 2 words longer. */ #ifdef CONFIG_X86_32 # ifdef CONFIG_VM86 @@ -39,8 +41,12 @@ # else # define TOP_OF_KERNEL_STACK_PADDING 8 # endif -#else -# define TOP_OF_KERNEL_STACK_PADDING 0 +#else /* x86-64 */ +# ifdef CONFIG_X86_FRED +# define TOP_OF_KERNEL_STACK_PADDING (2*8) +# else +# define TOP_OF_KERNEL_STACK_PADDING 0 +# endif #endif /* From patchwork Tue Apr 4 10:26:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 79013 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2947382vqo; Tue, 4 Apr 2023 04:25:19 -0700 (PDT) X-Google-Smtp-Source: AKy350Yv5Cxoir6QHKX393cf71S/jzDTWnFni5DCgF1opWivq0hmgUJLq7xCupy2PeAaH5f5Oter X-Received: by 2002:a17:90b:4a52:b0:23f:6830:568e with SMTP id lb18-20020a17090b4a5200b0023f6830568emr2610373pjb.8.1680607519311; Tue, 04 Apr 2023 04:25:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680607519; cv=none; d=google.com; s=arc-20160816; b=W3ZVmzlRnMRpUNSIoI1HRb2i+jS1vrLIR+8nMbgzJhD5FGaM0NODQcnApjG6TpN+yq kj7NNZQ3fMWUUB0H4k0bgk63fzxBo59M93yGwr+KPdkVtTIF2t7V2zdjbW+ne+7TbvnS K1M8nBGmNelGa42mOasR3RznUrVIRRlloJNZAGY2uoORQXckEv6F7qeKCIoVbmqxW8x3 fCc0Brvq7Ux/8ezfCBDGkM9hjq4z2G8S1gKPV7ac673YjeWz1NzQ66S9Fmdx7vBaQyRM 1etRPl4H4wT8hsjTpNQW5XpVd+EPITuGsGjRoi23dArg3pZJuj6ELyoF6Eco6yu2FcIk YnOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=M5bV6szz0XuXm6oCNHc4S7Y0o7foTuWrMoJq3PC0c4s=; b=hQjit6QTaqEJ2uZ38ArLYLKbhxMnT2cnX0bfcpvZKHL3GjKDJ8BHleupTWXkj/1ost chzPS4TrrVfczuAcp9gN8WRW4yzgzOpBzdaLobFOaPfLhZhjsP+tvNEgzYsHBrkEGVvM AcbdxEyALqNmW48CEGcPXQjJXMAE+8DMf27fH584NqX0hJ/dEwwTI12R1duMGQzWaxJp n6mOlwfsL7+S86a+xlpcrVWROGQtvnx84TgRPCtmlqjPgvxb68kidOExlIQ9TjAf9EcQ ZRO/LZ7T3u6wzoltp7FC1Ds5EjKM1pwH82xinIvUx+udVuXnaVfTwcldQ4r0F5zayU/l yzJA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=kZ+J7VPZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:53:03 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 16/33] x86/fred: add a page fault entry stub for FRED Date: Tue, 4 Apr 2023 03:26:59 -0700 Message-Id: <20230404102716.1795-17-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762244710372023764?= X-GMAIL-MSGID: =?utf-8?q?1762244710372023764?= From: "H. Peter Anvin (Intel)" Add a page fault entry stub for FRED. On a FRED system, the faulting address (CR2) is passed on the stack, to avoid the problem of transient state. Thus we get the page fault address from the stack instead of CR2. Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/asm/fred.h | 2 ++ arch/x86/mm/fault.c | 20 ++++++++++++++++++-- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/fred.h b/arch/x86/include/asm/fred.h index b59397411ab9..4ff05d350066 100644 --- a/arch/x86/include/asm/fred.h +++ b/arch/x86/include/asm/fred.h @@ -99,6 +99,8 @@ static __always_inline unsigned long fred_event_data(struct pt_regs *regs) #define DEFINE_FRED_HANDLER(f) noinstr DECLARE_FRED_HANDLER(f) typedef DECLARE_FRED_HANDLER((*fred_handler)); +DECLARE_FRED_HANDLER(fred_exc_page_fault); + #endif /* __ASSEMBLY__ */ #endif /* CONFIG_X86_FRED */ diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c index a498ae1fbe66..0f946121de14 100644 --- a/arch/x86/mm/fault.c +++ b/arch/x86/mm/fault.c @@ -33,6 +33,7 @@ #include /* kvm_handle_async_pf */ #include /* fixup_vdso_exception() */ #include +#include /* fred_event_data() */ #define CREATE_TRACE_POINTS #include @@ -1507,9 +1508,10 @@ handle_page_fault(struct pt_regs *regs, unsigned long error_code, } } -DEFINE_IDTENTRY_RAW_ERRORCODE(exc_page_fault) +static __always_inline void page_fault_common(struct pt_regs *regs, + unsigned int error_code, + unsigned long address) { - unsigned long address = read_cr2(); irqentry_state_t state; prefetchw(¤t->mm->mmap_lock); @@ -1556,3 +1558,17 @@ DEFINE_IDTENTRY_RAW_ERRORCODE(exc_page_fault) irqentry_exit(regs, state); } + +DEFINE_IDTENTRY_RAW_ERRORCODE(exc_page_fault) +{ + page_fault_common(regs, error_code, read_cr2()); +} + +#ifdef CONFIG_X86_FRED + +DEFINE_FRED_HANDLER(fred_exc_page_fault) +{ + page_fault_common(regs, regs->orig_ax, fred_event_data(regs)); +} + +#endif /* CONFIG_X86_FRED */ From patchwork Tue Apr 4 10:27:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 79031 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2955414vqo; Tue, 4 Apr 2023 04:37:58 -0700 (PDT) X-Google-Smtp-Source: AKy350b1yuAohYoi/XyXpGjGrSbnSj4u4lmJiNxqEi5owgr9HqaDKSvP2uKHSd3lO7bc7CmeMQ3V X-Received: by 2002:aa7:9ad3:0:b0:625:e3c0:8a58 with SMTP id x19-20020aa79ad3000000b00625e3c08a58mr1886420pfp.4.1680608278180; Tue, 04 Apr 2023 04:37:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680608278; cv=none; d=google.com; s=arc-20160816; b=DN5SINb9YcbI97If+B1Zi9egvVsa32ywm4CqB1nj5fYNrVyzDmBxpaUD1GKQ+ynchD HY6Eg5R+0GtDbiWwZCnLfzt3CKyecZfQd70wJO3qovtWY8NyZmAWvQj/F7KTIIKhpr+O CjrwnfMCT6MxRppO1zgRiqIVChPHpLGh44AD2OMISiXAcHeZCi9x6jFexEHTa8TsBr5N ck4ksDR8uCcv4J7WeYGrAQ1BxxGWZ8IyoqskqQ7OOygUD0xRQmh6YMW/HolhanavtWDg UkkyRBDzeEDCPo0v8LSN1m0xA+wFy4uquqG3L8pApgcR7soOweWXlfBZ5E9rBYdUfjUm 9RSg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=6Z0IE2XqP9vwd8ByVTpsUWrJgdNXimuX8wyggK0V93I=; b=rP5T7Z5kAE6+fUr4ioOe7YwwoGbHTjZRbzpBN97C8J5oMsYpkITcyhGdjsvJKfDnP1 30CUxwVksIV7YhcymxONQo4c9vqKFhIv3c4khLu8pfSN7ML8fAPpz4TbdmOSpmgBLuQ1 lYJIiJxWDiyYClNdmaonVsnRDymMvHG3XwXxi+/mMfDfqUvVMMABtvwQ+/ZzpmlAW6Gd fUU/NYjNVO5RPE9d+Nz40Yx/blLlilBw+tu6mxmH9JCEjqpiSFQ5a4+wxdj6WdN2jTLN E0zd2/Rd1D1p+oYqcrQKAuZVoes1k44my/shJ1cqsonU5jCXfHmRmmZ2hvOd+YhsiMOE iESA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=bieQ+DI9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:53:03 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 17/33] x86/fred: add a debug fault entry stub for FRED Date: Tue, 4 Apr 2023 03:27:00 -0700 Message-Id: <20230404102716.1795-18-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762245505761067273?= X-GMAIL-MSGID: =?utf-8?q?1762245505761067273?= From: "H. Peter Anvin (Intel)" Add a debug fault entry stub for FRED. On a FRED system, the debug trap status information (DR6) is passed on the stack, to avoid the problem of transient state. Furthermore, FRED transitions avoid a lot of ugly corner cases the handling of which can, and should be, skipped. The FRED debug trap status information saved on the stack differs from DR6 in both stickiness and polarity; it is exactly what debug_read_clear_dr6() returns, and exc_debug_user()/exc_debug_kernel() expect. Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- Changes since v1: * call irqentry_nmi_{enter,exit}() in both IDT and FRED debug fault kernel handler (Peter Zijlstra). --- arch/x86/include/asm/fred.h | 1 + arch/x86/kernel/traps.c | 56 +++++++++++++++++++++++++++---------- 2 files changed, 42 insertions(+), 15 deletions(-) diff --git a/arch/x86/include/asm/fred.h b/arch/x86/include/asm/fred.h index 4ff05d350066..f670430aaa54 100644 --- a/arch/x86/include/asm/fred.h +++ b/arch/x86/include/asm/fred.h @@ -99,6 +99,7 @@ static __always_inline unsigned long fred_event_data(struct pt_regs *regs) #define DEFINE_FRED_HANDLER(f) noinstr DECLARE_FRED_HANDLER(f) typedef DECLARE_FRED_HANDLER((*fred_handler)); +DECLARE_FRED_HANDLER(fred_exc_debug); DECLARE_FRED_HANDLER(fred_exc_page_fault); #endif /* __ASSEMBLY__ */ diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index f86cd233b00b..549f7f962f8f 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -47,6 +47,7 @@ #include #include #include +#include #include #include #include @@ -1020,21 +1021,9 @@ static bool notify_debug(struct pt_regs *regs, unsigned long *dr6) return false; } -static __always_inline void exc_debug_kernel(struct pt_regs *regs, - unsigned long dr6) +static __always_inline void debug_kernel_common(struct pt_regs *regs, + unsigned long dr6) { - /* - * Disable breakpoints during exception handling; recursive exceptions - * are exceedingly 'fun'. - * - * Since this function is NOKPROBE, and that also applies to - * HW_BREAKPOINT_X, we can't hit a breakpoint before this (XXX except a - * HW_BREAKPOINT_W on our stack) - * - * Entry text is excluded for HW_BP_X and cpu_entry_area, which - * includes the entry stack is excluded for everything. - */ - unsigned long dr7 = local_db_save(); irqentry_state_t irq_state = irqentry_nmi_enter(regs); instrumentation_begin(); @@ -1062,7 +1051,8 @@ static __always_inline void exc_debug_kernel(struct pt_regs *regs, * Catch SYSENTER with TF set and clear DR_STEP. If this hit a * watchpoint at the same time then that will still be handled. */ - if ((dr6 & DR_STEP) && is_sysenter_singlestep(regs)) + if (!cpu_feature_enabled(X86_FEATURE_FRED) && + (dr6 & DR_STEP) && is_sysenter_singlestep(regs)) dr6 &= ~DR_STEP; /* @@ -1090,7 +1080,25 @@ static __always_inline void exc_debug_kernel(struct pt_regs *regs, out: instrumentation_end(); irqentry_nmi_exit(regs, irq_state); +} +static __always_inline void exc_debug_kernel(struct pt_regs *regs, + unsigned long dr6) +{ + /* + * Disable breakpoints during exception handling; recursive exceptions + * are exceedingly 'fun'. + * + * Since this function is NOKPROBE, and that also applies to + * HW_BREAKPOINT_X, we can't hit a breakpoint before this (XXX except a + * HW_BREAKPOINT_W on our stack) + * + * Entry text is excluded for HW_BP_X and cpu_entry_area, which + * includes the entry stack is excluded for everything. + */ + unsigned long dr7 = local_db_save(); + + debug_kernel_common(regs, dr6); local_db_restore(dr7); } @@ -1179,6 +1187,24 @@ DEFINE_IDTENTRY_DEBUG_USER(exc_debug) { exc_debug_user(regs, debug_read_clear_dr6()); } + +# ifdef CONFIG_X86_FRED +DEFINE_FRED_HANDLER(fred_exc_debug) +{ + /* + * The FRED debug information saved onto stack differs from + * DR6 in both stickiness and polarity; it is exactly what + * debug_read_clear_dr6() returns. + */ + unsigned long dr6 = fred_event_data(regs); + + if (user_mode(regs)) + exc_debug_user(regs, dr6); + else + debug_kernel_common(regs, dr6); +} +# endif /* CONFIG_X86_FRED */ + #else /* 32 bit does not have separate entry points. */ DEFINE_IDTENTRY_RAW(exc_debug) From patchwork Tue Apr 4 10:27:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 79014 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2949716vqo; Tue, 4 Apr 2023 04:28:48 -0700 (PDT) X-Google-Smtp-Source: AKy350bGUz/kXx3yVVufgOn2MxN3/ydYcft4Tm2TEtClIv58VRenwF0+ZuyKNei2JbdHhJW/IGhx X-Received: by 2002:a05:6a20:29a0:b0:d8:f061:abab with SMTP id f32-20020a056a2029a000b000d8f061ababmr2014192pzh.5.1680607728658; Tue, 04 Apr 2023 04:28:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680607728; cv=none; d=google.com; s=arc-20160816; b=TSlLCA9CIC23jCHNaYLIv6B00M6NwvyJP8F4TgMX6PDUrbD8rVZGlGfyT3PIznq7UP /VSIn5y9z0lXliakjUxwQrMvpB/PlsIW44Lungd89Ymu8n/VSavM5OcyYkKFRtt1+ftk cNdxRVLRuiJQuc6sM0JIf1doR/m2jEu0OZC58rvipeAiwleNe5hth8v8fZImGTl6D4Nw A9gP7DxdpqBNhbhewuKr7xV5w4930IRwUlokokzLRMwKPzaYw4R1SupSD6cyuTZ+348Y rfrUjIEIxGrVjxhfamEz0BW+5qurMawQmQOxevo2j8jWdFbj71C+7Rv37Beabp/im+3K BU1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=FujSQUqHBZl8iLTALotlYQnjAeVJMmty12OH3VL/Yzw=; b=IpHD+C3TInB4Ky7l3tLsNdeToLjqsZ+g+YsJtEGvu1eF0JPx4dgdJUYMkdnEzIXspX wbVc0IRoviqU8r67eijRr6j2Mlk2tMq1L9AcmZEodWPrX1fHC0/viKZdAmRGJSM3LfKg yF/fOnGNjqwzFtQszOVnndEF1XmAUMCWtKYuuQMrWXdbhfkiBQOkuUUhMXeeUdF48EL3 HqO1YjGLZf7cVFyzqUJGUROLGO/Tkc8j4wuDjMYBbMiGovyW2ilLksF+UT6IfDKJL00H 86bnk1TjaadWUUPPlzzw8TW5SLOw/V3rKJjG6SzoJB04FqK+rhzKjY2fsJjSrXQBD2jc EhxA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=cPMrKTd6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:53:04 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 18/33] x86/fred: add a NMI entry stub for FRED Date: Tue, 4 Apr 2023 03:27:01 -0700 Message-Id: <20230404102716.1795-19-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762244929598838783?= X-GMAIL-MSGID: =?utf-8?q?1762244929598838783?= From: "H. Peter Anvin (Intel)" On a FRED system, NMIs nest both with themselves and faults, transient information is saved into the stack frame, and NMI unblocking only happens when the stack frame indicates that so should happen. Thus, the NMI entry stub for FRED is really quite small... Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/asm/fred.h | 1 + arch/x86/kernel/nmi.c | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/arch/x86/include/asm/fred.h b/arch/x86/include/asm/fred.h index f670430aaa54..9ce2a6439091 100644 --- a/arch/x86/include/asm/fred.h +++ b/arch/x86/include/asm/fred.h @@ -99,6 +99,7 @@ static __always_inline unsigned long fred_event_data(struct pt_regs *regs) #define DEFINE_FRED_HANDLER(f) noinstr DECLARE_FRED_HANDLER(f) typedef DECLARE_FRED_HANDLER((*fred_handler)); +DECLARE_FRED_HANDLER(fred_exc_nmi); DECLARE_FRED_HANDLER(fred_exc_debug); DECLARE_FRED_HANDLER(fred_exc_page_fault); diff --git a/arch/x86/kernel/nmi.c b/arch/x86/kernel/nmi.c index 776f4b1e395b..e7b2abe42583 100644 --- a/arch/x86/kernel/nmi.c +++ b/arch/x86/kernel/nmi.c @@ -34,6 +34,7 @@ #include #include #include +#include #define CREATE_TRACE_POINTS #include @@ -643,6 +644,24 @@ void nmi_backtrace_stall_check(const struct cpumask *btp) #endif +#ifdef CONFIG_X86_FRED +DEFINE_FRED_HANDLER(fred_exc_nmi) +{ + /* + * With FRED, CR2 and DR6 are pushed atomically on faults, + * so we don't have to worry about saving and restoring them. + * Breakpoint faults nest, so assume it is OK to leave DR7 + * enabled. + */ + irqentry_state_t irq_state = irqentry_nmi_enter(regs); + + inc_irq_stat(__nmi_count); + default_do_nmi(regs); + + irqentry_nmi_exit(regs, irq_state); +} +#endif + void stop_nmi(void) { ignore_nmis++; From patchwork Tue Apr 4 10:27:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 78997 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2931395vqo; Tue, 4 Apr 2023 03:58:27 -0700 (PDT) X-Google-Smtp-Source: AKy350ZocMOIN3pM0ymsnVCYfeUSNo2+w7JP0AckSTQBKUfCYgnWBImMKpItiKiveqZ2K5hAZ8fc X-Received: by 2002:a17:90b:78b:b0:237:ae98:a47f with SMTP id l11-20020a17090b078b00b00237ae98a47fmr22688207pjz.1.1680605906726; Tue, 04 Apr 2023 03:58:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680605906; cv=none; d=google.com; s=arc-20160816; b=FcSkWR5miVTy7vaQkBHCKdxCCclgygYAAv0/PEyGXBX6NplQYiqzpOX/ysOnDuDvR6 T6q7f4SrTIvN+bgGX/VxjnJUJOtcUPM8UKLSXQicEASo/IF8F3mB8NFjSVWrvFm8mTjH cy8cccr92pw+f19fVzAfHTE/ruryTqFfK34Prl5v2Zt0mNii3Dc2krLrxXK2905fuhAj rwZRfeGGMBSoK8E9EyW1+jIFjjRhAV0dBGRghe2ogTB0W84kQUixOSm5GvrjuY+Zaepi whIKMzSy8NzglyuR11A/4/Iy/XYZZMW0Z2SwmQtvdc+XxbvIy88ettz1J922aVLVvfMi 1AXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=noHnDU6HVdIEvG2vFbd/tjfbHM4UcQUOqh8bLYYP0WE=; b=B4c/g2ohmwvFIHijAqjEkBeFLnjEYc19byJvBu1Ik/b+cC1LWgtTYQ0u3dqK6xff8i WSiYLkV6ZYgRI79SsudFRJ2FaDZ9TnXTjtld8jQdg723XXzHGefc3g3QvCIUoG9VXi8/ K6+x7G6pa2GEDdT2/gbeGB1pejNiSCWos/GOLbK1RWm3979CDcQDeDUo6KRmMabLwpSO feAS8RJPSn0IE+WDXPfc4V3IMDYZ/X4gX3XCdC6SGrOXGJmdomkc8PbatsauR+rf2M2a v2w7fGq7knKhqq2wVGcecthTDwFmxKOre8/duuhLHGCnIJba3fV7wYnE9DvpzKS6dLCh 0w1g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=NYuiDZfK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:53:04 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 19/33] x86/fred: add a machine check entry stub for FRED Date: Tue, 4 Apr 2023 03:27:02 -0700 Message-Id: <20230404102716.1795-20-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762243019013921794?= X-GMAIL-MSGID: =?utf-8?q?1762243019013921794?= Add a machine check entry stub for FRED. Tested-by: Shan Kang Signed-off-by: Xin Li --- Changes since v5: * Disallow #DB inside #MCE for robustness sake (Peter Zijlstra). --- arch/x86/include/asm/fred.h | 1 + arch/x86/kernel/cpu/mce/core.c | 15 +++++++++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/x86/include/asm/fred.h b/arch/x86/include/asm/fred.h index 9ce2a6439091..61048aa4e01d 100644 --- a/arch/x86/include/asm/fred.h +++ b/arch/x86/include/asm/fred.h @@ -102,6 +102,7 @@ typedef DECLARE_FRED_HANDLER((*fred_handler)); DECLARE_FRED_HANDLER(fred_exc_nmi); DECLARE_FRED_HANDLER(fred_exc_debug); DECLARE_FRED_HANDLER(fred_exc_page_fault); +DECLARE_FRED_HANDLER(fred_exc_machine_check); #endif /* __ASSEMBLY__ */ diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 2eec60f50057..859331a6a7ad 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -52,6 +52,7 @@ #include #include #include +#include #include "internal.h" @@ -2111,6 +2112,20 @@ DEFINE_IDTENTRY_MCE_USER(exc_machine_check) exc_machine_check_user(regs); local_db_restore(dr7); } + +#ifdef CONFIG_X86_FRED +DEFINE_FRED_HANDLER(fred_exc_machine_check) +{ + unsigned long dr7; + + dr7 = local_db_save(); + if (user_mode(regs)) + exc_machine_check_user(regs); + else + exc_machine_check_kernel(regs); + local_db_restore(dr7); +} +#endif #else /* 32bit unified entry point */ DEFINE_IDTENTRY_RAW(exc_machine_check) From patchwork Tue Apr 4 10:27:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 79017 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2951649vqo; Tue, 4 Apr 2023 04:31:47 -0700 (PDT) X-Google-Smtp-Source: AKy350aSC5e3H0eDQ3zD3lpw+Ie3oyVlXw+MyneUmMxuPQdN6w2t1u8pKo7H1/7rLJo8lXBcXa9I X-Received: by 2002:a17:902:f54d:b0:19f:27fe:95c3 with SMTP id h13-20020a170902f54d00b0019f27fe95c3mr2896757plf.41.1680607907493; Tue, 04 Apr 2023 04:31:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680607907; cv=none; d=google.com; s=arc-20160816; b=okHm/aHZ2YNE1lD7Tpr8NJnjPbAaMQD1NgXMPDxAKyVZWSarXIj/TNgH7wnSaPykv1 M9FCe5RLDvBaty2LZUYAl2gkzxqv4S07hhsxc2yjUuGTUbQpEPLjJKFeVODc515NsdsX xH+9XnZho8tTIRbZBqtqIn4tryEyTObhuya7oMVdyqiuYPdzE1C5rtVBoQyZ34JB8vqh 8rSv5kHaHScf8Nu6blueI/+dwu9mFak4mF7vfoLBcs/q8m825jfqGUD0ZOLnEe78dfgl hkxs3ATPA1y13AK09aWhE6KyC3Fzhm3dyISmYThzOIX9Q77sa8N4lgGeyFFpHKEqnYrr SOzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=vXN/9P6+Xojvdb9LZm3JSykFOa6yS/vI18dScvJDQbM=; b=E714tcq+ol06zSg1Vnx/9RNL79j7XyG5BESNoQRVEaQBAF30PR4LvxFeBYLB16GLca 97d09bHN6giNo6cbD/z0YrJRT9oKWeCCaih7ajbKzt+HEm2ETHvjtSHU1fjJgH2RGIxy IklYJkZxx3lTC1fhqpXWowNHCrlzZPmbFi0+/4zc/iaNtutum814OvfBjJY02OGKoWR9 hXXqUHDvU0gFT9/3erVZ2AnK64YZX7fI9Uj7EKHJ5MSqdV0LV0Lo1+V5Ws6u3iu9fGoH r4ATXP56mVKpJgmJr+kPm5gRE4s/IygHy+fkCBckQ+bTSBUH2ir2/2zIY0e+fHMljs48 xA1w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="lFnD7/0y"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:53:04 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 20/33] x86/fred: FRED entry/exit and dispatch code Date: Tue, 4 Apr 2023 03:27:03 -0700 Message-Id: <20230404102716.1795-21-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762245117217439273?= X-GMAIL-MSGID: =?utf-8?q?1762245117217439273?= From: "H. Peter Anvin (Intel)" The code to actually handle kernel and event entry/exit using FRED. It is split up into two files thus: - entry_64_fred.S contains the actual entrypoints and exit code, and saves and restores registers. - entry_fred.c contains the two-level event dispatch code for FRED. The first-level dispatch is on the event type, and the second-level is on the event vector. Originally-by: Megha Dey Signed-off-by: H. Peter Anvin (Intel) Co-developed-by: Xin Li Tested-by: Shan Kang Signed-off-by: Xin Li --- Changes since v1: * Initialize a FRED exception handler to fred_bad_event() instead of NULL if no FRED handler defined for an exception vector (Peter Zijlstra). * Push calling irqentry_{enter,exit}() and instrumentation_{begin,end}() down into individual FRED exception handlers, instead of in the dispatch framework (Peter Zijlstra). --- arch/x86/entry/Makefile | 5 +- arch/x86/entry/entry_64_fred.S | 57 +++++++++ arch/x86/entry/entry_fred.c | 220 ++++++++++++++++++++++++++++++++ arch/x86/include/asm/idtentry.h | 8 ++ 4 files changed, 289 insertions(+), 1 deletion(-) create mode 100644 arch/x86/entry/entry_64_fred.S create mode 100644 arch/x86/entry/entry_fred.c diff --git a/arch/x86/entry/Makefile b/arch/x86/entry/Makefile index ca2fe186994b..c93e7f5c2a06 100644 --- a/arch/x86/entry/Makefile +++ b/arch/x86/entry/Makefile @@ -18,6 +18,9 @@ obj-y += vdso/ obj-y += vsyscall/ obj-$(CONFIG_PREEMPTION) += thunk_$(BITS).o +CFLAGS_entry_fred.o += -fno-stack-protector +CFLAGS_REMOVE_entry_fred.o += -pg $(CC_FLAGS_FTRACE) +obj-$(CONFIG_X86_FRED) += entry_64_fred.o entry_fred.o + obj-$(CONFIG_IA32_EMULATION) += entry_64_compat.o syscall_32.o obj-$(CONFIG_X86_X32_ABI) += syscall_x32.o - diff --git a/arch/x86/entry/entry_64_fred.S b/arch/x86/entry/entry_64_fred.S new file mode 100644 index 000000000000..d975cacd060f --- /dev/null +++ b/arch/x86/entry/entry_64_fred.S @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * arch/x86/entry/entry_64_fred.S + * + * The actual FRED entry points. + */ +#include +#include +#include +#include + +#include "calling.h" + + .code64 + .section ".noinstr.text", "ax" + +.macro FRED_ENTER + UNWIND_HINT_EMPTY + PUSH_AND_CLEAR_REGS + movq %rsp, %rdi /* %rdi -> pt_regs */ +.endm + +.macro FRED_EXIT + UNWIND_HINT_REGS + POP_REGS + addq $8,%rsp /* Drop error code */ +.endm + +/* + * The new RIP value that FRED event delivery establishes is + * IA32_FRED_CONFIG & ~FFFH for events that occur in ring 3. + * Thus the FRED ring 3 entry point must be 4K page aligned. + */ + .align 4096 + +SYM_CODE_START_NOALIGN(fred_entrypoint_user) + FRED_ENTER + call fred_entry_from_user +SYM_INNER_LABEL(fred_exit_user, SYM_L_GLOBAL) + FRED_EXIT + ERETU +SYM_CODE_END(fred_entrypoint_user) + +.fill fred_entrypoint_kernel - ., 1, 0xcc + +/* + * The new RIP value that FRED event delivery establishes is + * (IA32_FRED_CONFIG & ~FFFH) + 256 for events that occur in + * ring 0, i.e., fred_entrypoint_user + 256. + */ + .org fred_entrypoint_user+256 +SYM_CODE_START_NOALIGN(fred_entrypoint_kernel) + FRED_ENTER + call fred_entry_from_kernel + FRED_EXIT + ERETS +SYM_CODE_END(fred_entrypoint_kernel) diff --git a/arch/x86/entry/entry_fred.c b/arch/x86/entry/entry_fred.c new file mode 100644 index 000000000000..0bff1db913b8 --- /dev/null +++ b/arch/x86/entry/entry_fred.c @@ -0,0 +1,220 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * arch/x86/entry/entry_fred.c + * + * This contains the dispatch functions called from the entry point + * assembly. + */ + +#include +#include /* oops_begin/end, ... */ +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Badness... + */ +static DEFINE_FRED_HANDLER(fred_bad_event) +{ + irqentry_state_t irq_state = irqentry_nmi_enter(regs); + + instrumentation_begin(); + + /* Panic on events from a high stack level */ + if (regs->current_stack_level > 0) { + pr_emerg("PANIC: invalid or fatal FRED event; event type %u " + "vector %u error 0x%lx aux 0x%lx at %04x:%016lx\n", + regs->type, regs->vector, regs->orig_ax, + fred_event_data(regs), regs->cs, regs->ip); + die("invalid or fatal FRED event", regs, regs->orig_ax); + panic("invalid or fatal FRED event"); + } else { + unsigned long flags = oops_begin(); + int sig = SIGKILL; + + pr_alert("BUG: invalid or fatal FRED event; event type %u " + "vector %u error 0x%lx aux 0x%lx at %04x:%016lx\n", + regs->type, regs->vector, regs->orig_ax, + fred_event_data(regs), regs->cs, regs->ip); + + if (__die("Invalid or fatal FRED event", regs, regs->orig_ax)) + sig = 0; + + oops_end(flags, regs, sig); + } + + instrumentation_end(); + irqentry_nmi_exit(regs, irq_state); +} + +noinstr void fred_exc_double_fault(struct pt_regs *regs) +{ + exc_double_fault(regs, regs->orig_ax); +} + +/* + * Exception entry + */ +static DEFINE_FRED_HANDLER(fred_exception) +{ + /* + * Exceptions that cannot happen on FRED h/w are set to fred_bad_event(). + */ + static const fred_handler exception_handlers[NUM_EXCEPTION_VECTORS] = { + [X86_TRAP_DE] = exc_divide_error, + [X86_TRAP_DB] = fred_exc_debug, + [X86_TRAP_NMI] = fred_bad_event, /* A separate event type, not handled here */ + [X86_TRAP_BP] = exc_int3, + [X86_TRAP_OF] = exc_overflow, + [X86_TRAP_BR] = exc_bounds, + [X86_TRAP_UD] = exc_invalid_op, + [X86_TRAP_NM] = exc_device_not_available, + [X86_TRAP_DF] = fred_exc_double_fault, + [X86_TRAP_OLD_MF] = fred_bad_event, /* 387 only! */ + [X86_TRAP_TS] = fred_exc_invalid_tss, + [X86_TRAP_NP] = fred_exc_segment_not_present, + [X86_TRAP_SS] = fred_exc_stack_segment, + [X86_TRAP_GP] = fred_exc_general_protection, + [X86_TRAP_PF] = fred_exc_page_fault, + [X86_TRAP_SPURIOUS] = fred_bad_event, /* Interrupts are their own event type */ + [X86_TRAP_MF] = exc_coprocessor_error, + [X86_TRAP_AC] = fred_exc_alignment_check, + [X86_TRAP_MC] = fred_exc_machine_check, + [X86_TRAP_XF] = exc_simd_coprocessor_error, + [X86_TRAP_VE...NUM_EXCEPTION_VECTORS-1] = fred_bad_event + }; + u8 vector = array_index_nospec((u8)regs->vector, NUM_EXCEPTION_VECTORS); + + exception_handlers[vector](regs); +} + +static __always_inline void fred_emulate_trap(struct pt_regs *regs) +{ + regs->type = EVENT_TYPE_SWFAULT; + regs->orig_ax = 0; + fred_exception(regs); +} + +static __always_inline void fred_emulate_fault(struct pt_regs *regs) +{ + regs->ip -= regs->instr_len; + fred_emulate_trap(regs); +} + +/* + * Emulate SYSENTER if applicable. This is not the preferred system + * call in 32-bit mode under FRED, rather int $0x80 is preferred and + * exported in the vdso. SYSCALL proper has a hard-coded early out in + * fred_entry_from_user(). + */ +static DEFINE_FRED_HANDLER(fred_syscall_slow) +{ + if (IS_ENABLED(CONFIG_IA32_EMULATION) && + likely(regs->vector == FRED_SYSENTER)) { + /* Convert frame to a syscall frame */ + regs->orig_ax = regs->ax; + regs->ax = -ENOSYS; + do_fast_syscall_32(regs); + } else { + regs->vector = X86_TRAP_UD; + fred_emulate_fault(regs); + } +} + +/* + * Some software exceptions can also be triggered as int instructions, + * for historical reasons. Implement those here. The performance-critical + * int $0x80 (32-bit system call) has a hard-coded early out. + */ +static DEFINE_FRED_HANDLER(fred_sw_interrupt_user) +{ + if (IS_ENABLED(CONFIG_IA32_EMULATION) && + likely(regs->vector == IA32_SYSCALL_VECTOR)) { + /* Convert frame to a syscall frame */ + regs->orig_ax = regs->ax; + regs->ax = -ENOSYS; + return do_int80_syscall_32(regs); + } + + switch (regs->vector) { + case X86_TRAP_BP: + case X86_TRAP_OF: + fred_emulate_trap(regs); + break; + default: + regs->vector = X86_TRAP_GP; + fred_emulate_fault(regs); + break; + } +} + +static DEFINE_FRED_HANDLER(fred_hw_interrupt) +{ + irqentry_state_t state = irqentry_enter(regs); + + instrumentation_begin(); + external_interrupt(regs); + instrumentation_end(); + irqentry_exit(regs, state); +} + +__visible noinstr void fred_entry_from_user(struct pt_regs *regs) +{ + static const fred_handler user_handlers[FRED_EVENT_TYPE_COUNT] = + { + [EVENT_TYPE_HWINT] = fred_hw_interrupt, + [EVENT_TYPE_RESERVED] = fred_bad_event, + [EVENT_TYPE_NMI] = fred_exc_nmi, + [EVENT_TYPE_SWINT] = fred_sw_interrupt_user, + [EVENT_TYPE_HWFAULT] = fred_exception, + [EVENT_TYPE_SWFAULT] = fred_exception, + [EVENT_TYPE_PRIVSW] = fred_exception, + [EVENT_TYPE_OTHER] = fred_syscall_slow + }; + + /* + * FRED employs a two-level event dispatch mechanism, with + * the first-level on the type of an event and the second-level + * on its vector. Thus a dispatch typically induces 2 calls. + * We optimize it by using early outs for the most frequent + * events, and syscalls are the first. We may also need early + * outs for page faults. + */ + if (likely(regs->type == EVENT_TYPE_OTHER && + regs->vector == FRED_SYSCALL)) { + /* Convert frame to a syscall frame */ + regs->orig_ax = regs->ax; + regs->ax = -ENOSYS; + do_syscall_64(regs, regs->orig_ax); + } else { + /* Not a system call */ + u8 type = array_index_nospec((u8)regs->type, FRED_EVENT_TYPE_COUNT); + + user_handlers[type](regs); + } +} + +__visible noinstr void fred_entry_from_kernel(struct pt_regs *regs) +{ + static const fred_handler kernel_handlers[FRED_EVENT_TYPE_COUNT] = + { + [EVENT_TYPE_HWINT] = fred_hw_interrupt, + [EVENT_TYPE_RESERVED] = fred_bad_event, + [EVENT_TYPE_NMI] = fred_exc_nmi, + [EVENT_TYPE_SWINT] = fred_bad_event, + [EVENT_TYPE_HWFAULT] = fred_exception, + [EVENT_TYPE_SWFAULT] = fred_exception, + [EVENT_TYPE_PRIVSW] = fred_exception, + [EVENT_TYPE_OTHER] = fred_bad_event + }; + u8 type = array_index_nospec((u8)regs->type, FRED_EVENT_TYPE_COUNT); + + /* The pt_regs frame on entry here is an exception frame */ + kernel_handlers[type](regs); +} diff --git a/arch/x86/include/asm/idtentry.h b/arch/x86/include/asm/idtentry.h index 2876ddae02bc..bd43866f9c3e 100644 --- a/arch/x86/include/asm/idtentry.h +++ b/arch/x86/include/asm/idtentry.h @@ -82,6 +82,7 @@ static __always_inline void __##func(struct pt_regs *regs) #define DECLARE_IDTENTRY_ERRORCODE(vector, func) \ asmlinkage void asm_##func(void); \ asmlinkage void xen_asm_##func(void); \ + __visible void fred_##func(struct pt_regs *regs); \ __visible void func(struct pt_regs *regs, unsigned long error_code) /** @@ -106,6 +107,11 @@ __visible noinstr void func(struct pt_regs *regs, \ irqentry_exit(regs, state); \ } \ \ +__visible noinstr void fred_##func(struct pt_regs *regs) \ +{ \ + func (regs, regs->orig_ax); \ +} \ + \ static __always_inline void __##func(struct pt_regs *regs, \ unsigned long error_code) @@ -622,6 +628,8 @@ DECLARE_IDTENTRY_RAW(X86_TRAP_MC, exc_machine_check); #ifdef CONFIG_XEN_PV DECLARE_IDTENTRY_RAW(X86_TRAP_MC, xenpv_exc_machine_check); #endif +#else +#define fred_exc_machine_check fred_bad_event #endif /* NMI */ From patchwork Tue Apr 4 10:27:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 78998 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2931495vqo; Tue, 4 Apr 2023 03:58:40 -0700 (PDT) X-Google-Smtp-Source: AKy350bbXYtyJ5mdjYRlDyexCLEts7TPl2IWKBV6Jyy3lvLfucPH69RAfQtJ74HSuqvOlNheqRsA X-Received: by 2002:a17:903:120e:b0:1a0:67fb:444b with SMTP id l14-20020a170903120e00b001a067fb444bmr22189442plh.2.1680605920114; Tue, 04 Apr 2023 03:58:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680605920; cv=none; d=google.com; s=arc-20160816; b=fMRBX6r9e1Y0Z4vmcTG1GooSimGdC/5dCGZsbwSF6hhK8zvadbySe584RvGEuSEq5K m+0uOUqru02bIl73GfGYmzbl6w7UNQ+5FDJUCy58sUXd63+LNxupRHigNIjBK663s3Ek b+UiMlpLULJ2CxpGvd3wwboaIQrcTIzNfaUjSCYBdAVV5fouigJgHQhyrmLYpzDJscPa GWUmT1I966WWkjZrigfcKa3Sl2TgHAyyF/ghNvQ+j8TZ4ZJHH66ivlV+FWvW1vAwQ9s1 UCsHvVKgK8K+2BPJ2DhmDJUtGiSraxlGF5oJb0eoA5gJ2QiJsuuZmEltr/CfDlDIjzIN cJ9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=LjyUJodvslqOHVIlJtjG7C7aG8ztN5TsdljforHvp40=; b=Zxed0BzAvwQg1vO6akyltVz7csTi14u/yI996FgZhg9h4qiALDC7tstvjctSItrlXh xqWpTq2Elanv4DVm4vJWMWC48sKuvUKNVhVhsmgCY155uZlCnAchO/r4c+jxTz4ZnVoY M4YtQ1RaI8cJdtdzIkWFtZzu1lvEfJBX9sHyZ4rn99+u3pZ2iL2Td8oSI3ke8rMsl6ai +FSq005fWJtHhr7lnz+wngH1PTdb8CeaW3vWAbsD8qo1gqYdYUVpmYqmlaHODmb30Qhd glsAgD9xR5FKGFgjasqNSxavzApsJ1sCnkuP9fP88amyHmmF+pZKTiVxfaAf/xJaLEa/ 1FLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=YDSzPsT6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:53:04 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 21/33] x86/fred: FRED initialization code Date: Tue, 4 Apr 2023 03:27:04 -0700 Message-Id: <20230404102716.1795-22-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762243033388920948?= X-GMAIL-MSGID: =?utf-8?q?1762243033388920948?= From: "H. Peter Anvin (Intel)" The code to initialize FRED when it's available and _not_ disabled. cpu_init_fred_exceptions() is the core function to initialize FRED, which 1. Sets up FRED entrypoints for events happening in ring 0 and 3. 2. Sets up a default stack for event handling. 3. Sets up dedicated event stacks for DB/NMI/MC/DF, equivalent to the IDT IST stacks. 4. Forces 32-bit system calls to use "int $0x80" only. 5. Enables FRED and invalidtes IDT. When the FRED is used, cpu_init_exception_handling() initializes FRED through calling cpu_init_fred_exceptions(), otherwise it sets up TSS IST and loads IDT. As FRED uses the ring 3 FRED entrypoint for SYSCALL and SYSENTER, it skips setting up SYSCALL/SYSENTER related MSRs, e.g., MSR_LSTAR. Signed-off-by: H. Peter Anvin (Intel) Co-developed-by: Xin Li Tested-by: Shan Kang Signed-off-by: Xin Li --- Changes since v5: * Add a comment for FRED stack level settings (Lai Jiangshan). * Define #DB/NMI/#MC/#DF stack levels using macros. --- arch/x86/include/asm/fred.h | 27 +++++++++++++ arch/x86/include/asm/traps.h | 2 + arch/x86/kernel/Makefile | 1 + arch/x86/kernel/cpu/common.c | 74 +++++++++++++++++++++------------- arch/x86/kernel/fred.c | 78 ++++++++++++++++++++++++++++++++++++ arch/x86/kernel/irqinit.c | 7 +++- arch/x86/kernel/traps.c | 16 +++++++- 7 files changed, 175 insertions(+), 30 deletions(-) create mode 100644 arch/x86/kernel/fred.c diff --git a/arch/x86/include/asm/fred.h b/arch/x86/include/asm/fred.h index 61048aa4e01d..c5fbc4f18059 100644 --- a/arch/x86/include/asm/fred.h +++ b/arch/x86/include/asm/fred.h @@ -57,6 +57,19 @@ #define FRED_CSX_ALLOW_SINGLE_STEP _BITUL(25) #define FRED_CSX_INTERRUPT_SHADOW _BITUL(24) +/* #DB in the kernel would imply the use of a kernel debugger. */ +#define FRED_DB_STACK_LEVEL 1 +#define FRED_NMI_STACK_LEVEL 2 +#define FRED_MC_STACK_LEVEL 2 +/* + * #DF is the highest level because a #DF means "something went wrong + * *while delivering an exception*." The number of cases for which that + * can happen with FRED is drastically reduced and basically amounts to + * "the stack you pointed me to is broken." Thus, always change stacks + * on #DF, which means it should be at the highest level. + */ +#define FRED_DF_STACK_LEVEL 3 + #ifndef __ASSEMBLY__ #include @@ -104,8 +117,22 @@ DECLARE_FRED_HANDLER(fred_exc_debug); DECLARE_FRED_HANDLER(fred_exc_page_fault); DECLARE_FRED_HANDLER(fred_exc_machine_check); +/* + * The actual assembly entry and exit points + */ +extern __visible void fred_entrypoint_user(void); + +/* + * Initialization + */ +void cpu_init_fred_exceptions(void); +void fred_setup_apic(void); + #endif /* __ASSEMBLY__ */ +#else +#define cpu_init_fred_exceptions() BUG() +#define fred_setup_apic() BUG() #endif /* CONFIG_X86_FRED */ #endif /* ASM_X86_FRED_H */ diff --git a/arch/x86/include/asm/traps.h b/arch/x86/include/asm/traps.h index 46f5e4e2a346..612b3d6fec53 100644 --- a/arch/x86/include/asm/traps.h +++ b/arch/x86/include/asm/traps.h @@ -56,4 +56,6 @@ void __noreturn handle_stack_overflow(struct pt_regs *regs, void f (struct pt_regs *regs) typedef DECLARE_SYSTEM_INTERRUPT_HANDLER((*system_interrupt_handler)); +system_interrupt_handler get_system_interrupt_handler(unsigned int i); + #endif /* _ASM_X86_TRAPS_H */ diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile index dd61752f4c96..08d9c0a0bfbe 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -47,6 +47,7 @@ obj-y += platform-quirks.o obj-y += process_$(BITS).o signal.o signal_$(BITS).o obj-y += traps.o idt.o irq.o irq_$(BITS).o dumpstack_$(BITS).o obj-y += time.o ioport.o dumpstack.o nmi.o +obj-$(CONFIG_X86_FRED) += fred.o obj-$(CONFIG_MODIFY_LDT_SYSCALL) += ldt.o obj-y += setup.o x86_init.o i8259.o irqinit.o obj-$(CONFIG_JUMP_LABEL) += jump_label.o diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index e8cf6f4cfb52..eea41cb8722e 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -58,6 +58,7 @@ #include #include #include +#include #include #include #include @@ -2054,28 +2055,6 @@ static void wrmsrl_cstar(unsigned long val) /* May not be marked __init: used by software suspend */ void syscall_init(void) { - wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); - wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); - -#ifdef CONFIG_IA32_EMULATION - wrmsrl_cstar((unsigned long)entry_SYSCALL_compat); - /* - * This only works on Intel CPUs. - * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. - * This does not cause SYSENTER to jump to the wrong location, because - * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). - */ - wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); - wrmsrl_safe(MSR_IA32_SYSENTER_ESP, - (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); - wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); -#else - wrmsrl_cstar((unsigned long)ignore_sysret); - wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); - wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); - wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); -#endif - /* * Flags to clear on syscall; clear as much as possible * to minimize user space-kernel interference. @@ -2086,6 +2065,41 @@ void syscall_init(void) X86_EFLAGS_IF|X86_EFLAGS_DF|X86_EFLAGS_OF| X86_EFLAGS_IOPL|X86_EFLAGS_NT|X86_EFLAGS_RF| X86_EFLAGS_AC|X86_EFLAGS_ID); + + /* + * The default user and kernel segments + */ + wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); + + if (cpu_feature_enabled(X86_FEATURE_FRED)) { + /* Both sysexit and sysret cause #UD when FRED is enabled */ + wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); + wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); + wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); + } else { + wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); + +#ifdef CONFIG_IA32_EMULATION + wrmsrl_cstar((unsigned long)entry_SYSCALL_compat); + /* + * This only works on Intel CPUs. + * On AMD CPUs these MSRs are 32-bit, CPU truncates + * MSR_IA32_SYSENTER_EIP. + * This does not cause SYSENTER to jump to the wrong + * location, because AMD doesn't allow SYSENTER in + * long mode (either 32- or 64-bit). + */ + wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); + wrmsrl_safe(MSR_IA32_SYSENTER_ESP, + (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); + wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); +#else + wrmsrl_cstar((unsigned long)ignore_sysret); + wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); + wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); + wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); +#endif + } } #else /* CONFIG_X86_64 */ @@ -2218,18 +2232,24 @@ void cpu_init_exception_handling(void) /* paranoid_entry() gets the CPU number from the GDT */ setup_getcpu(cpu); - /* IST vectors need TSS to be set up. */ - tss_setup_ist(tss); + /* Set up the TSS */ tss_setup_io_bitmap(tss); set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); - load_TR_desc(); /* GHCB needs to be setup to handle #VC. */ setup_ghcb(); - /* Finally load the IDT */ - load_current_idt(); + if (cpu_feature_enabled(X86_FEATURE_FRED)) { + /* Set up FRED exception handling */ + cpu_init_fred_exceptions(); + } else { + /* IST vectors need TSS to be set up. */ + tss_setup_ist(tss); + + /* Finally load the IDT */ + load_current_idt(); + } } /* diff --git a/arch/x86/kernel/fred.c b/arch/x86/kernel/fred.c new file mode 100644 index 000000000000..907abfd69f3f --- /dev/null +++ b/arch/x86/kernel/fred.c @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include +#include +#include +#include /* For cr4_set_bits() */ +#include + +/* + * Initialize FRED on this CPU. This cannot be __init as it is called + * during CPU hotplug. + */ +void cpu_init_fred_exceptions(void) +{ + wrmsrl(MSR_IA32_FRED_CONFIG, + FRED_CONFIG_REDZONE | /* Reserve for CALL emulation */ + FRED_CONFIG_INT_STKLVL(0) | + FRED_CONFIG_ENTRYPOINT(fred_entrypoint_user)); + + /* + * The purpose of separate stacks for NMI, #DB and #MC *in the kernel* + * (remember that user space faults are always taken on stack level 0) + * is to avoid overflowing the kernel stack. + */ + wrmsrl(MSR_IA32_FRED_STKLVLS, + FRED_STKLVL(X86_TRAP_DB, FRED_DB_STACK_LEVEL) | + FRED_STKLVL(X86_TRAP_NMI, FRED_NMI_STACK_LEVEL) | + FRED_STKLVL(X86_TRAP_MC, FRED_MC_STACK_LEVEL) | + FRED_STKLVL(X86_TRAP_DF, FRED_DF_STACK_LEVEL)); + + /* The FRED equivalents to IST stacks... */ + wrmsrl(MSR_IA32_FRED_RSP1, __this_cpu_ist_top_va(DB)); + wrmsrl(MSR_IA32_FRED_RSP2, __this_cpu_ist_top_va(NMI)); + wrmsrl(MSR_IA32_FRED_RSP3, __this_cpu_ist_top_va(DF)); + + /* Not used with FRED */ + wrmsrl(MSR_LSTAR, 0ULL); + wrmsrl(MSR_CSTAR, 0ULL); + wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); + wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); + wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); + + /* Enable FRED */ + cr4_set_bits(X86_CR4_FRED); + idt_invalidate(); /* Any further IDT use is a bug */ + + /* Use int $0x80 for 32-bit system calls in FRED mode */ + setup_clear_cpu_cap(X86_FEATURE_SYSENTER32); + setup_clear_cpu_cap(X86_FEATURE_SYSCALL32); +} + +/* + * Initialize system vectors from a FRED perspective, so + * lapic_assign_system_vectors() can do its job. + */ +void __init fred_setup_apic(void) +{ + int i; + + for (i = 0; i < FIRST_EXTERNAL_VECTOR; i++) + set_bit(i, system_vectors); + + /* + * Don't set the non assigned system vectors in the + * system_vectors bitmap. Otherwise they show up in + * /proc/interrupts. + */ +#ifdef CONFIG_SMP + set_bit(IRQ_MOVE_CLEANUP_VECTOR, system_vectors); +#endif + + for (i = 0; i < NR_SYSTEM_VECTORS; i++) { + if (get_system_interrupt_handler(i) != NULL) { + set_bit(i + FIRST_SYSTEM_VECTOR, system_vectors); + } + } + + /* The rest are fair game... */ +} diff --git a/arch/x86/kernel/irqinit.c b/arch/x86/kernel/irqinit.c index c683666876f1..2a510f72dd11 100644 --- a/arch/x86/kernel/irqinit.c +++ b/arch/x86/kernel/irqinit.c @@ -28,6 +28,7 @@ #include #include #include +#include #include /* @@ -96,7 +97,11 @@ void __init native_init_IRQ(void) /* Execute any quirks before the call gates are initialised: */ x86_init.irqs.pre_vector_init(); - idt_setup_apic_and_irq_gates(); + if (cpu_feature_enabled(X86_FEATURE_FRED)) + fred_setup_apic(); + else + idt_setup_apic_and_irq_gates(); + lapic_assign_system_vectors(); if (!acpi_ioapic && !of_ioapic && nr_legacy_irqs()) { diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index 549f7f962f8f..ecfaf4d647bb 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -1537,6 +1537,14 @@ static system_interrupt_handler system_interrupt_handlers[NR_SYSTEM_VECTORS] = { #undef SYSV +system_interrupt_handler get_system_interrupt_handler(unsigned int i) +{ + if (i >= NR_SYSTEM_VECTORS) + return NULL; + + return system_interrupt_handlers[i]; +} + /* * External interrupt dispatch function. * @@ -1572,7 +1580,8 @@ void __init install_system_interrupt_handler(unsigned int n, const void *asm_add #ifdef CONFIG_X86_64 system_interrupt_handlers[n - FIRST_SYSTEM_VECTOR] = (system_interrupt_handler)addr; #endif - alloc_intr_gate(n, asm_addr); + if (!cpu_feature_enabled(X86_FEATURE_FRED)) + alloc_intr_gate(n, asm_addr); } void __init trap_init(void) @@ -1585,7 +1594,10 @@ void __init trap_init(void) /* Initialize TSS before setting up traps so ISTs work */ cpu_init_exception_handling(); + /* Setup traps as cpu_init() might #GP */ - idt_setup_traps(); + if (!cpu_feature_enabled(X86_FEATURE_FRED)) + idt_setup_traps(); + cpu_init(); } From patchwork Tue Apr 4 10:27:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 78999 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2931531vqo; Tue, 4 Apr 2023 03:58:44 -0700 (PDT) X-Google-Smtp-Source: AKy350ZCbVFvFTkFMhqvUhdk9jJLBcK5aKEocSvFemPRyVMJGZI01KhYrrOo8WBhMIpqXccWjDdb X-Received: by 2002:a17:903:1246:b0:1a2:9ce6:6483 with SMTP id u6-20020a170903124600b001a29ce66483mr2393647plh.64.1680605923991; Tue, 04 Apr 2023 03:58:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680605923; cv=none; d=google.com; s=arc-20160816; b=zuswN0dU07N1qIhZ8nnkJocF8A1xPo30b7+shtY2DmZVaaVQX/sy+ROmNXDJW3jogc M7/gHF+GHCx+1Ip3qDLDUxsAJjrN+B6ZJXg1JQ29SA9iztW40R6cKdgU2JuQIhnBoU/E Kj7BNXdgj1EHCckaGZg4YoQ+4LwKcmeVg6NwhUj5uGoh6G07Y4IUfx2ENA0DLQQxmJBM eFd4IXpT5ld5t+Lrfl6Pxzsv8/JmOp2Ec5SUQ5eTWL6ZYlNWyU+H6RF8QbYcvbvhDHzB Y92bCjfRGbJEMwYaqzvTUhrdC0druqSiTHBp4sEjhdavOLhMqxLDoj2gekFni8n/DWF6 Pb4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=o/s4OgoBvlYE/i/ueeuD809hBfxz0iI2J7KU1Tu8hr0=; b=VZJXgszNAVG9DgZcKHDjh9QP/n6clmZ+0B9kTijs90nk0FAO4WejPqAbTyehx4xVgy mUX1vwiWuPkiXoGAKUN9YbCFEB1yKnrQE21nqRJrvAcaxaHeuVOoykiuuRE5JVlUssQg A3SljKnegIREXQrq1bW9Pq3jvQouSHd2C9Hxw7/NEZrGsPmRlqAjbEtvsMXS4A67yRSa PY+0zt07nDlQ9OFYXf0EOEsFl8tvG9eWJVYjDOuiHItP6yZwpqY5Y8aT1mFE/ROrKD5R LNbuJbrUduQnfcoEmqwDOw2agC/U43TCJfptJ3kH/I9lRjHOtsAOUZRMDL7PCxBZGh76 l0iA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=CcbJ1Ctq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:53:04 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 22/33] x86/fred: update MSR_IA32_FRED_RSP0 during task switch Date: Tue, 4 Apr 2023 03:27:05 -0700 Message-Id: <20230404102716.1795-23-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762243037700479772?= X-GMAIL-MSGID: =?utf-8?q?1762243037700479772?= From: "H. Peter Anvin (Intel)" MSR_IA32_FRED_RSP0 is used during ring 3 event delivery, and needs to be updated to point to the top of next task stack during task switch. Update MSR_IA32_FRED_RSP0 with WRMSR instruction for now, and will use WRMSRNS/WRMSRLIST for performance once it gets upstreamed. Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/asm/switch_to.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/switch_to.h b/arch/x86/include/asm/switch_to.h index 5c91305d09d2..00fd85abc1d2 100644 --- a/arch/x86/include/asm/switch_to.h +++ b/arch/x86/include/asm/switch_to.h @@ -68,9 +68,16 @@ static inline void update_task_stack(struct task_struct *task) #ifdef CONFIG_X86_32 this_cpu_write(cpu_tss_rw.x86_tss.sp1, task->thread.sp0); #else - /* Xen PV enters the kernel on the thread stack. */ - if (cpu_feature_enabled(X86_FEATURE_XENPV)) + if (cpu_feature_enabled(X86_FEATURE_FRED)) { + /* + * Will use WRMSRNS/WRMSRLIST for performance once it's upstreamed. + */ + wrmsrl(MSR_IA32_FRED_RSP0, + task_top_of_stack(task) + TOP_OF_KERNEL_STACK_PADDING); + } else if (cpu_feature_enabled(X86_FEATURE_XENPV)) { + /* Xen PV enters the kernel on the thread stack. */ load_sp0(task_top_of_stack(task)); + } #endif } From patchwork Tue Apr 4 10:27:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 79011 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2947279vqo; Tue, 4 Apr 2023 04:25:09 -0700 (PDT) X-Google-Smtp-Source: AKy350ZI7Y8rRGJhJ1XkMVZYne0Etsz1LjM0Z37Rf4YyeLbKKTZG/OXM8Iv6uV7Jv8f0r77lQxSl X-Received: by 2002:a17:90b:4f42:b0:23f:84b9:d7a9 with SMTP id pj2-20020a17090b4f4200b0023f84b9d7a9mr2253988pjb.18.1680607509271; Tue, 04 Apr 2023 04:25:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680607509; cv=none; d=google.com; s=arc-20160816; b=h2M+uCXDnCeSDJ1bGINIrVsIlp1D2KFzbxzG84M9o7tmZGQ9EMxIONMAuGS1WqGjZU EdMEbL1DKcEcZHsbVd3dylHrgTYipEo/J585E4v2k8xlj/Cist+O14DDJ0SNF7NJoGrF 4cg3MFj6bAEWaRuGxRhEkDinN/M2wVNYCwhcyH+mqR2S1d+KhBaEf2SkFuJJXdCzxCDB NpF3jDjRtgDWr+JQ2nNkB9hZpKy8ga+0AzZmuaX1WPnCHgWAs/7le7S3kI746gROnba0 r49XeL60MnO0Nfg3il3AK05SwaQWJF+AqETxBRDVcjhDzXb2HZt5BqYPSyTPJlSEfY9Q 8Eqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=KIufXiS22ukm4bYjosPpn6jOKXWPfemJH11Ed6G9b7k=; b=ML+RP7xPPSzDRBfPXhi0vgyA9uG+AtAMqzzCw0l78oxZwLlSP/qn7LzgD8WM+A9QtS lcepOxkucix+9QI1mOOPezrM3UsYpg0UVl3VmHYLgOg7pIu6rKs81eBONuauE1Jj4nSK pugvBbLR2Dcq7SRgPNbB906L4c984ykosiYagQHUa05MY1pH18vB4pC2Mtr436tbqvzk krvmtHSNlH5z8l6ixjez+vKu1F9dn8/5fNXpLkYqhbhOp5ZJL+f4PCFE1/wQtMmo/fOV jfeF3AIuQ+bmKk1lqph6BBxC0b7WzLLrKB7Mf+ltMWMob/bsP8GP/1yQhRBhJmEqU2tE kitg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=OxLFL1EG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:53:05 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 23/33] x86/fred: let ret_from_fork() jmp to fred_exit_user when FRED is enabled Date: Tue, 4 Apr 2023 03:27:06 -0700 Message-Id: <20230404102716.1795-24-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762244699819797274?= X-GMAIL-MSGID: =?utf-8?q?1762244699819797274?= From: "H. Peter Anvin (Intel)" Let ret_from_fork() jmp to fred_exit_user when FRED is enabled, otherwise the existing IDT code is chosen. Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/entry/entry_64.S | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index eccc3431e515..5b595a9b2ffb 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -299,7 +299,12 @@ SYM_CODE_START_NOALIGN(ret_from_fork) UNWIND_HINT_REGS movq %rsp, %rdi call syscall_exit_to_user_mode /* returns with IRQs disabled */ +#ifdef CONFIG_X86_FRED + ALTERNATIVE "jmp swapgs_restore_regs_and_return_to_usermode", \ + "jmp fred_exit_user", X86_FEATURE_FRED +#else jmp swapgs_restore_regs_and_return_to_usermode +#endif 1: /* kernel thread */ From patchwork Tue Apr 4 10:27:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 79026 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2954498vqo; Tue, 4 Apr 2023 04:36:21 -0700 (PDT) X-Google-Smtp-Source: AKy350bkfs2IPr2vjSky1DPpv/ZkeBlAX1IiIq1s7171d7V7u4tS2YfnGrc7xGhMpIp/Cdlyxh2I X-Received: by 2002:a17:90b:4d11:b0:23d:1143:c664 with SMTP id mw17-20020a17090b4d1100b0023d1143c664mr2476510pjb.31.1680608181228; Tue, 04 Apr 2023 04:36:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680608181; cv=none; d=google.com; s=arc-20160816; b=gNrpSMIo4ddjUoqkFkyQ3XONsFpV1Tbe0jP7RtmIWGK7/PB7++jOwuWYtGP2L2LFY0 SpvYkAleMoHWEG4m37Ak9hjICjZ57WNVkAJlVR0ssusTDKkCwAeRIHnN9ePGbwbswy8y MpvOCukXn8qxOiG/weJAREAJ+5UDFffllvalr33VEjqWiv/n7wDgeOcyVEVHYfsYCa+b VFNBwpLWc17z9vL7S26Y2ft0K17H8CZtykfB/wXdbYUqM0HUTeVQqdtvJ8xRIPWZANSg 038gRnS0ocIb2wxDtqMYki3PH1m5+Y4jvFNpKXBwrxhGaagBmvb3Ap0+iKhLwg7H9DYz F3AA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=HXWU+EothhAOstFqFMAbdES8hja1CkXrrCI4kIOxLxM=; b=VCefAhOJj748Tzp3PBBV4K8vGXshibPLmxy9kh5wb3xYAgSLWoqGJz3es+CaOsN8A9 yJmO8f0EfleQ70PVizCMYJZz9C/KcH4geV2fLdYqvp0iMnVfBGhjZ6Wd4BlndxCOL9pL GLwWiKSFIgCmk2RLo/JfmTR2xQ4jMD/EDX3J5IIDiNBe0I7AeamOyqUPMiIFob/yiM6A UE6+u2QLb3j2PAIil7nsYzY0LcSbePgchMWVpMUNxS5euo3kJjkXo1HY4704cF62dmIy kbJsgHg+KuRCQYVp+o0Qh0ISUMu6vwzEXtWyu7/f5HECjF1o5sM5HEPOPqwGwwMhDAFn VE+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=YSxjUTsl; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:53:05 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 24/33] x86/fred: disallow the swapgs instruction when FRED is enabled Date: Tue, 4 Apr 2023 03:27:07 -0700 Message-Id: <20230404102716.1795-25-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762245404106982815?= X-GMAIL-MSGID: =?utf-8?q?1762245404106982815?= From: "H. Peter Anvin (Intel)" The FRED architecture establishes the full supervisor/user through: 1) FRED event delivery swaps the value of the GS base address and that of the IA32_KERNEL_GS_BASE MSR. 2) ERETU swaps the value of the GS base address and that of the IA32_KERNEL_GS_BASE MSR. Thus, the swapgs instruction is disallowed when FRED is enabled, otherwise it causes #UD. Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/kernel/process_64.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index a1aa74864c8b..2bea86073646 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -165,7 +165,8 @@ static noinstr unsigned long __rdgsbase_inactive(void) lockdep_assert_irqs_disabled(); - if (!cpu_feature_enabled(X86_FEATURE_XENPV)) { + if (!cpu_feature_enabled(X86_FEATURE_FRED) && + !cpu_feature_enabled(X86_FEATURE_XENPV)) { native_swapgs(); gsbase = rdgsbase(); native_swapgs(); @@ -190,7 +191,8 @@ static noinstr void __wrgsbase_inactive(unsigned long gsbase) { lockdep_assert_irqs_disabled(); - if (!cpu_feature_enabled(X86_FEATURE_XENPV)) { + if (!cpu_feature_enabled(X86_FEATURE_FRED) && + !cpu_feature_enabled(X86_FEATURE_XENPV)) { native_swapgs(); wrgsbase(gsbase); native_swapgs(); From patchwork Tue Apr 4 10:27:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 79008 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2943092vqo; Tue, 4 Apr 2023 04:17:38 -0700 (PDT) X-Google-Smtp-Source: AKy350bkeWbcn4wL3F3lMJ0nFGlKoUNfp9MizqcLxJ21cq/QSuJ9kGNGMrgV4AOelrxrZkJQSAem X-Received: by 2002:a17:902:c40b:b0:1a1:da3c:6065 with SMTP id k11-20020a170902c40b00b001a1da3c6065mr2637859plk.22.1680607056727; Tue, 04 Apr 2023 04:17:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680607056; cv=none; d=google.com; s=arc-20160816; b=naMGukcdyqLs0h5MnEXqvALFy6KGPyYiDshBZNFPQmd8hWWJzes+ayYs4dtqVT4unV zJ1Qy0KMyn+1dx8nW47c1opWGs3xczutuvB0xr/CehChFBdM/+fTPuIMgR+8DzYvaZ5P q2xO2M7G0yOecHadgDbJkqt7W4iFZs88GyNrK7ywzVIXDxbhVNh3R6TriJn/sUB5ZpuM VeZzl51Sbd8LKtBZwKbEIeYb3LPC90KZOaMvt6sZuH8EpetVpWSp7bqMDGLhWDxrNSoL oIwRl7Nj4h0TJvxCfn6eFz2c1kfwLVc/i6MyKpw9LQ+X6DINmXnKddGYApZKIhL7Glco CUAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=vxjy11Tsv/mgkUj27ibhp2UA7uqHHL7WLXhaKKIvcCY=; b=ESldp6pCGv2GrQWSDuyHKzLoMzPPzMpuw8jFt0qfnSthyf2ToJdjjr2omCpKBWX0an FhB+76W4CS4RIIKxGLo8A/DBSVjfscKESZp3x37ulidMLIXnEA4DMESDz6Lna1cvN+0M VgTgwJ/e095fg3aQkPg/mRX+O67HedpZU02udUQiI+52u69cUwBnp4RbohNg2YGYs6Hp lU5ZBf6R1iU5LMtRHrwU217/1isky95XfHtmN1p26jfrikcvvYTP9OaK6i2G9uop7fWR 7RXNbUOMLMnzUnL/zZLc2Vlcx9iBCn1CHO7263zcaN+odJgN7uPKtXQOmqvEDJHOc2N7 H+mQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=miyLgQnl; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:53:05 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 25/33] x86/fred: no ESPFIX needed when FRED is enabled Date: Tue, 4 Apr 2023 03:27:08 -0700 Message-Id: <20230404102716.1795-26-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762244224882279976?= X-GMAIL-MSGID: =?utf-8?q?1762244224882279976?= From: "H. Peter Anvin (Intel)" Because FRED always restores the full value of %rsp, ESPFIX is no longer needed when it's enabled. Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/kernel/espfix_64.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/x86/kernel/espfix_64.c b/arch/x86/kernel/espfix_64.c index 16f9814c9be0..48d133a54f45 100644 --- a/arch/x86/kernel/espfix_64.c +++ b/arch/x86/kernel/espfix_64.c @@ -106,6 +106,10 @@ void __init init_espfix_bsp(void) pgd_t *pgd; p4d_t *p4d; + /* FRED systems don't need ESPFIX */ + if (cpu_feature_enabled(X86_FEATURE_FRED)) + return; + /* Install the espfix pud into the kernel page directory */ pgd = &init_top_pgt[pgd_index(ESPFIX_BASE_ADDR)]; p4d = p4d_alloc(&init_mm, pgd, ESPFIX_BASE_ADDR); @@ -129,6 +133,10 @@ void init_espfix_ap(int cpu) void *stack_page; pteval_t ptemask; + /* FRED systems don't need ESPFIX */ + if (cpu_feature_enabled(X86_FEATURE_FRED)) + return; + /* We only have to do this once... */ if (likely(per_cpu(espfix_stack, cpu))) return; /* Already initialized */ From patchwork Tue Apr 4 10:27:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 79007 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2942027vqo; Tue, 4 Apr 2023 04:15:50 -0700 (PDT) X-Google-Smtp-Source: AKy350adWwUAZbPuqAKsIlrNjnpLYT5FSBlqqvuRx9JAEWLyrF0DB1EbELYokKmoBnmCsZWzFgxt X-Received: by 2002:a17:902:cf45:b0:1a1:b7fc:eeba with SMTP id e5-20020a170902cf4500b001a1b7fceebamr2003633plg.19.1680606950086; Tue, 04 Apr 2023 04:15:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680606950; cv=none; d=google.com; s=arc-20160816; b=CPd3gSg3k9YHUCK3bv2/YVrzkdBbh1T/MmmL+pmvsTrVFCeLM4Y99qujxr/PlcX8Kk fmMxFImxebmaUZaWmKfxJkmlNcGLTr6d3qam43IUIDjJ6ShMBWB0kTZ9IjdVLkpZYRga 2uRDYLx9JcJ8GiLyUP5I1S3wm3uEJgIgIocXA3F2E5nIHnVqQwXOdpDgJO6Jx8vPijka iNSsmCJfRkdJkz8Mee3ZiJ82qumy8JjvzBtvlKO1kVFbgfbt7fFMPEWtifuTy03oOcYr 9uy5d/8+bfLZkSgt9g0g5Nw7cDhmuPa+KcovS1/XVQSPKtGKmR1a8eaGPzRH4lnbhTbM XuPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=dXk7rGWXn1+raSuko+HE7ZydNglgwfgo+bHOiS4p1Pg=; b=cT4LyYAZmWzIXNyTWpmn1Uw2XBxVrnYuE5Uydg/eHViY+wXSFascP6yvHEX5x+ti35 xdn/XajGii8C7AON4NEIFjUqnBeI1kJxNYyP64YrYP9IWzXPp7LN5xQTVoWiqCLHI8sp QWyTVBoOIgX9id32iHNFMqK1SrcZLwayy9ewTOPPPIWQYsjuPIrML/ivuJfj70lkcr1W 9b+f1tZMVl4nPspI0qxH4SM4HRzrcZJfnsPwoTfwWZKL73nRcVEnbv0SvOkEi7RODUSo tJeVsQ7L3VRvQQT90/X6/NWpBgIZqf4KZ+ZYjC1Ma7E55Duc0/UKEM1emA8cEFSNAnq+ 7ivA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=jabhYiQg; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:53:05 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 26/33] x86/fred: allow single-step trap and NMI when starting a new thread Date: Tue, 4 Apr 2023 03:27:09 -0700 Message-Id: <20230404102716.1795-27-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762244113345323558?= X-GMAIL-MSGID: =?utf-8?q?1762244113345323558?= From: "H. Peter Anvin (Intel)" Allow single-step trap and NMI when starting a new thread, thus once the new thread returns to ring3, single-step trap and NMI are both enabled immediately. High-order 48 bits above the lowest 16 bit CS are discarded by the legacy IRET instruction, thus can be set unconditionally, even when FRED is not enabled. Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/asm/fred.h | 11 +++++++++++ arch/x86/kernel/process_64.c | 13 +++++++------ 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/arch/x86/include/asm/fred.h b/arch/x86/include/asm/fred.h index c5fbc4f18059..f7caf3b2f3f7 100644 --- a/arch/x86/include/asm/fred.h +++ b/arch/x86/include/asm/fred.h @@ -70,6 +70,14 @@ */ #define FRED_DF_STACK_LEVEL 3 +/* + * High-order 48 bits above the lowest 16 bit CS are discarded by the + * legacy IRET instruction, thus can be set unconditionally, even when + * FRED is not enabled. + */ +#define CSX_PROCESS_START \ + (FRED_CSX_ENABLE_NMI | FRED_CSX_ALLOW_SINGLE_STEP) + #ifndef __ASSEMBLY__ #include @@ -133,6 +141,9 @@ void fred_setup_apic(void); #else #define cpu_init_fred_exceptions() BUG() #define fred_setup_apic() BUG() + +#define CSX_PROCESS_START 0 + #endif /* CONFIG_X86_FRED */ #endif /* ASM_X86_FRED_H */ diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index 2bea86073646..c732d9dbff3a 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -55,6 +55,7 @@ #include #include #include +#include #ifdef CONFIG_IA32_EMULATION /* Not included via unistd.h */ #include @@ -506,7 +507,7 @@ void x86_gsbase_write_task(struct task_struct *task, unsigned long gsbase) static void start_thread_common(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp, - unsigned int _cs, unsigned int _ss, unsigned int _ds) + u16 _cs, u16 _ss, u16 _ds) { WARN_ON_ONCE(regs != current_pt_regs()); @@ -521,11 +522,11 @@ start_thread_common(struct pt_regs *regs, unsigned long new_ip, loadsegment(ds, _ds); load_gs_index(0); - regs->ip = new_ip; - regs->sp = new_sp; - regs->cs = _cs; - regs->ss = _ss; - regs->flags = X86_EFLAGS_IF; + regs->ip = new_ip; + regs->sp = new_sp; + regs->csx = _cs | CSX_PROCESS_START; + regs->ssx = _ss; + regs->flags = X86_EFLAGS_IF | X86_EFLAGS_FIXED; } void From patchwork Tue Apr 4 10:27:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 79005 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2941421vqo; Tue, 4 Apr 2023 04:14:50 -0700 (PDT) X-Google-Smtp-Source: AKy350b+Ol2RxsiEoVtrhcxIWG6Bj7dsEa61rFPdEiIONdhbGwhDwlLwD3gUTLHw4OKzoKVALR5V X-Received: by 2002:aa7:9553:0:b0:624:894d:c494 with SMTP id w19-20020aa79553000000b00624894dc494mr1904488pfq.19.1680606890107; Tue, 04 Apr 2023 04:14:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680606890; cv=none; d=google.com; s=arc-20160816; b=CTU2QOmUzgNeEk6CFQKLTsMd3rGikNpjX/FcbWQpHC62hnotzrM+1iPxk3Dv3QiRUe vupO8tKqrOg2/Y0FfMjy+kFVq7XKOOLbOhAhDAMn2kDe4QTrYYMgm1Mvej71bFXjWCf3 O1G6Llbmm7ilkRBGlyj5F9ObnXux+Ls7KEdtQU6wTzWlkOHde2mk7ncId6A+YJf4o0Il OoGTLiGkrXMkP32rbRyE84B0ndmGVwi0H2fd8ycB/1kIw3K2VTwWE5xSIyXVq103awll 4+fbzVhpzmMhohtE+5y7MqUj7qk3QdnoZFJmmruedWPiYAVUPVrNQZW4s10W6pb0gsSk tUMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=exDGCc8X2G7/6JXDtAe6rSBKL9gtva1p+jz7FZPd4y4=; b=N3u5XpH+BSRH4u9BvAx88ulIHQ4afirpshmvbc6yLclKnCDsROhE3nbFT1J3TE2oJG bJ9gmooqgE1csFDxQY7RgOue5UrxDVQAu7CSMYqPKCX4HNH2Obu4LU581NDzixeuFxra P8cg+CU7FwQGFgD3vOkWLTYoetJKRo9+AI+vS8UzUt+JnAraDSwCATS/GqopxGOunfFp KJzt1xTM9OP0JQEuGj7QgKarr80Za08jlKHE6j+zuuhEILHRkdKbqSOiChqUW5JkMFjR eU0QBeN/UEF40Lq9Yi01R1H4rA7flu29gQlWHRv38GdJXYExhzMtqseKTW0xc3oTdqJN j9GA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=dkNfTZLK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:53:05 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 27/33] x86/fred: fixup fault on ERETU by jumping to fred_entrypoint_user Date: Tue, 4 Apr 2023 03:27:10 -0700 Message-Id: <20230404102716.1795-28-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762244050617274778?= X-GMAIL-MSGID: =?utf-8?q?1762244050617274778?= If the stack frame contains an invalid user context (e.g. due to invalid SS, a non-canonical RIP, etc.) the ERETU instruction will trap (#SS or #GP). From a Linux point of view, this really should be considered a user space failure, so use the standard fault fixup mechanism to intercept the fault, fix up the exception frame, and redirect execution to fred_entrypoint_user. The end result is that it appears just as if the hardware had taken the exception immediately after completing the transition to user space. Suggested-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- Changes since v6: * Add a comment to explain why it is safe to write to a previous FRED stack frame. (Lai Jiangshan). Changes since v5: * Move the NMI bit from an invalid stack frame, which caused ERETU to fault, to the fault handler's stack frame, thus to unblock NMI ASAP if NMI is blocked (Lai Jiangshan). --- arch/x86/entry/entry_64_fred.S | 8 ++- arch/x86/include/asm/extable_fixup_types.h | 4 +- arch/x86/mm/extable.c | 76 ++++++++++++++++++++++ 3 files changed, 85 insertions(+), 3 deletions(-) diff --git a/arch/x86/entry/entry_64_fred.S b/arch/x86/entry/entry_64_fred.S index d975cacd060f..efe2bcd11273 100644 --- a/arch/x86/entry/entry_64_fred.S +++ b/arch/x86/entry/entry_64_fred.S @@ -5,8 +5,10 @@ * The actual FRED entry points. */ #include -#include +#include #include +#include +#include #include #include "calling.h" @@ -38,7 +40,9 @@ SYM_CODE_START_NOALIGN(fred_entrypoint_user) call fred_entry_from_user SYM_INNER_LABEL(fred_exit_user, SYM_L_GLOBAL) FRED_EXIT - ERETU +1: ERETU + + _ASM_EXTABLE_TYPE(1b, fred_entrypoint_user, EX_TYPE_ERETU) SYM_CODE_END(fred_entrypoint_user) .fill fred_entrypoint_kernel - ., 1, 0xcc diff --git a/arch/x86/include/asm/extable_fixup_types.h b/arch/x86/include/asm/extable_fixup_types.h index 991e31cfde94..1585c798a02f 100644 --- a/arch/x86/include/asm/extable_fixup_types.h +++ b/arch/x86/include/asm/extable_fixup_types.h @@ -64,6 +64,8 @@ #define EX_TYPE_UCOPY_LEN4 (EX_TYPE_UCOPY_LEN | EX_DATA_IMM(4)) #define EX_TYPE_UCOPY_LEN8 (EX_TYPE_UCOPY_LEN | EX_DATA_IMM(8)) -#define EX_TYPE_ZEROPAD 20 /* longword load with zeropad on fault */ +#define EX_TYPE_ZEROPAD 20 /* longword load with zeropad on fault */ + +#define EX_TYPE_ERETU 21 #endif diff --git a/arch/x86/mm/extable.c b/arch/x86/mm/extable.c index 60814e110a54..9d82193adf3c 100644 --- a/arch/x86/mm/extable.c +++ b/arch/x86/mm/extable.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -195,6 +196,77 @@ static bool ex_handler_ucopy_len(const struct exception_table_entry *fixup, return ex_handler_uaccess(fixup, regs, trapnr); } +#ifdef CONFIG_X86_FRED +static bool ex_handler_eretu(const struct exception_table_entry *fixup, + struct pt_regs *regs, unsigned long error_code) +{ + struct pt_regs *uregs = (struct pt_regs *)(regs->sp - offsetof(struct pt_regs, ip)); + unsigned short ss = uregs->ss; + unsigned short cs = uregs->cs; + + /* + * Move the NMI bit from the invalid stack frame, which caused ERETU + * to fault, to the fault handler's stack frame, thus to unblock NMI + * with the fault handler's ERETS instruction ASAP if NMI is blocked. + */ + regs->nmi = uregs->nmi; + + fred_info(uregs)->edata = fred_event_data(regs); + uregs->ssx = regs->ssx; + uregs->ss = ss; + uregs->csx = regs->csx; + uregs->nmi = 0; /* The NMI bit was moved away above */ + uregs->current_stack_level = 0; + uregs->cs = cs; + + /* + * Copy error code to uregs and adjust stack pointer accordingly. + * + * The RSP used by FRED to push a stack frame is not the value in %rsp, + * it is calculated from %rsp with the following 2 steps: + * 1) RSP = %rsp - (IA32_FRED_CONFIG & 0x1c0) // Reserve N*64 bytes + * 2) RSP = RSP & ~0x3f // Align to a 64-byte cache line + * when the event delivery doesn't trigger a stack level change. + * + * Here is an example with N*64 (N=1) bytes reserved: + * + * 64-byte cache line ==> ______________ + * |___Reserved___| + * |__Event_data__| + * |_____SS_______| + * |_____RSP______| + * |_____FLAGS____| + * |_____CS_______| + * |_____IP_______| <== ERETU stack frame + * 64-byte cache line ==> |__Error_code__| + * |______________| + * |______________| + * |______________| + * |______________| + * |______________| + * |______________| + * |______________| <== RSP after step 1) + * 64-byte cache line ==> |______________| <== RSP after step 2) + * |___Reserved___| + * |__Event_data__| + * |_____SS_______| + * |_____RSP______| + * |_____FLAGS____| + * |_____CS_______| + * |_____IP_______| <== ERETS stack frame + * 64-byte cache line ==> |__Error_code__| + * + * Thus a new FRED stack frame will always be pushed below a previous + * FRED stack frame ((N*64) bytes may be reserved between), and it is + * safe to write to a previous FRED stack frame as they never overlap. + */ + uregs->orig_ax = error_code; + regs->sp -= 8; + + return ex_handler_default(fixup, regs); +} +#endif + int ex_get_fixup_type(unsigned long ip) { const struct exception_table_entry *e = search_exception_tables(ip); @@ -272,6 +344,10 @@ int fixup_exception(struct pt_regs *regs, int trapnr, unsigned long error_code, return ex_handler_ucopy_len(e, regs, trapnr, reg, imm); case EX_TYPE_ZEROPAD: return ex_handler_zeropad(e, regs, fault_addr); +#ifdef CONFIG_X86_FRED + case EX_TYPE_ERETU: + return ex_handler_eretu(e, regs, error_code); +#endif } BUG(); } From patchwork Tue Apr 4 10:27:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 79018 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2951754vqo; Tue, 4 Apr 2023 04:31:57 -0700 (PDT) X-Google-Smtp-Source: AKy350b1SkRJ+qihwYAIyEqt5frGyfSoIxfsfPnAzyxkd0RrFPa7CKTlUtD103OMGJN9xRZzOStP X-Received: by 2002:aa7:df81:0:b0:4fd:2675:3785 with SMTP id b1-20020aa7df81000000b004fd26753785mr2180768edy.22.1680607917382; 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([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:53:06 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 28/33] x86/ia32: do not modify the DPL bits for a null selector Date: Tue, 4 Apr 2023 03:27:11 -0700 Message-Id: <20230404102716.1795-29-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762245127675187195?= X-GMAIL-MSGID: =?utf-8?q?1762245127675187195?= When a null selector is to be loaded into a segment register, reload_segments() sets its DPL bits to 3. Later when the IRET instruction loads it, it zeros the segment register. The two operations offset each other to actually effect a nop. Unlike IRET, ERETU does not make any of DS, ES, FS, or GS null if it is found to have DPL < 3. It is expected that a FRED-enabled operating system will return to ring 3 (in compatibility mode) only when those segments all have DPL = 3. Thus when FRED is enabled, we end up with having 3 in a segment register even when it is initially set to 0. Fix it by not modifying the DPL bits for a null selector. Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/kernel/signal_32.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/arch/x86/kernel/signal_32.c b/arch/x86/kernel/signal_32.c index 9027fc088f97..7796cf84fca2 100644 --- a/arch/x86/kernel/signal_32.c +++ b/arch/x86/kernel/signal_32.c @@ -36,22 +36,27 @@ #ifdef CONFIG_IA32_EMULATION #include +static inline u16 usrseg(u16 sel) +{ + return sel <= 3 ? sel : sel | 3; +} + static inline void reload_segments(struct sigcontext_32 *sc) { unsigned int cur; savesegment(gs, cur); - if ((sc->gs | 0x03) != cur) - load_gs_index(sc->gs | 0x03); + if (usrseg(sc->gs) != cur) + load_gs_index(usrseg(sc->gs)); savesegment(fs, cur); - if ((sc->fs | 0x03) != cur) - loadsegment(fs, sc->fs | 0x03); + if (usrseg(sc->fs) != cur) + loadsegment(fs, usrseg(sc->fs)); savesegment(ds, cur); - if ((sc->ds | 0x03) != cur) - loadsegment(ds, sc->ds | 0x03); + if (usrseg(sc->ds) != cur) + loadsegment(ds, usrseg(sc->ds)); savesegment(es, cur); - if ((sc->es | 0x03) != cur) - loadsegment(es, sc->es | 0x03); + if (usrseg(sc->es) != cur) + loadsegment(es, usrseg(sc->es)); } #define sigset32_t compat_sigset_t From patchwork Tue Apr 4 10:27:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 79000 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2931928vqo; Tue, 4 Apr 2023 03:59:43 -0700 (PDT) X-Google-Smtp-Source: AKy350b1um43dzTp6y88EAnvCM/sPdUgNljxOv6kfzicx3hgkTnhASgMKwuxeEobGXaLMT1Me6PG X-Received: by 2002:a17:90b:1e49:b0:23f:ef7:7897 with SMTP id pi9-20020a17090b1e4900b0023f0ef77897mr2226531pjb.49.1680605981930; Tue, 04 Apr 2023 03:59:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680605981; cv=none; d=google.com; s=arc-20160816; b=Uv7F6Yo7to8/Mx2i4LiFEnRvweUMnunU9tr+UC+3q6G6BCewETN4nDUAJyWoH5Y1MU KgfWotA3uzBNm7QZIguH8abHCzMFXWeZp/Fa354+8Dmkx+KdQSPIORwMo84tNmWwAnIv ukorp4L3EoS6LZXZUr2pfBXW3sS0LZ+t0OU7LfcXzzDhFmjb5zesPyyREWElCVgEeEbZ ob6RXNyWCC4h8rZCP/bPOeXmML9VqR0na6jJOX7890/PpcwkNkDqCMGKkOTpsaqPQKOS 4CfZWmXbnDhrQfvamYlBcHpxW6F0i2cnI5BuaeKJm2C8kUsNP1u2dHKCcPUOyJ3LpQZt j+nQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=LEBKkhzkCpkXO8dBR7DHU0kFn55u5RMjoLHOy5+hYK8=; b=vQMY2wWbmHO1bLv9FWBHQtuOybjEv0+19ym5abRSXChWq+EMAeJJ0SGtyY//42dS0M RcdhErerCgNUZeuaYC9NKAlrWhcVGmyVyUhF5Fr19qz3YPJXf6ZE2ifBxBCYKwva3PQW hd1TC31Ft3sj4SmWiDpahMRhss6ZzgXPInavRHx6CvaAbV+h5KRsDIwzrELva2q2yaoo HTxGW47/vrzU9WtmFliBxaRUcas9uILQ/3pmuorVkybESO6jkZcSvOJeSN2BO3fsCSov Fj6cDLWVIzzzWkiBLquwUANY369Cx/mjIUa6TRAWSf3vj56jAZiI3j9CtquavUDqfLVm 37gQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=J8Fyt7+r; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:53:06 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 29/33] x86/fred: allow FRED systems to use interrupt vectors 0x10-0x1f Date: Tue, 4 Apr 2023 03:27:12 -0700 Message-Id: <20230404102716.1795-30-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762243097873050841?= X-GMAIL-MSGID: =?utf-8?q?1762243097873050841?= From: "H. Peter Anvin (Intel)" FRED inherits the Intel VT-x enhancement of classified events with a two-level event dispatch logic. The first-level dispatch is on the event type, and the second-level is on the event vector. This also means that vectors in different event types are orthogonal, thus, vectors 0x10-0x1f become available as hardware interrupts. Enable interrupt vectors 0x10-0x1f on FRED systems (interrupt 0x80 is already enabled.) Most of these changes are about removing the assumption that the lowest-priority vector is hard-wired to 0x20. Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/asm/idtentry.h | 4 ++-- arch/x86/include/asm/irq.h | 5 +++++ arch/x86/include/asm/irq_vectors.h | 15 +++++++++++---- arch/x86/kernel/apic/apic.c | 11 ++++++++--- arch/x86/kernel/apic/vector.c | 8 +++++++- arch/x86/kernel/fred.c | 4 ++-- arch/x86/kernel/idt.c | 6 +++--- arch/x86/kernel/irq.c | 2 +- arch/x86/kernel/traps.c | 2 ++ 9 files changed, 41 insertions(+), 16 deletions(-) diff --git a/arch/x86/include/asm/idtentry.h b/arch/x86/include/asm/idtentry.h index bd43866f9c3e..57c891148b59 100644 --- a/arch/x86/include/asm/idtentry.h +++ b/arch/x86/include/asm/idtentry.h @@ -546,8 +546,8 @@ __visible noinstr void func(struct pt_regs *regs, \ */ .align IDT_ALIGN SYM_CODE_START(irq_entries_start) - vector=FIRST_EXTERNAL_VECTOR - .rept NR_EXTERNAL_VECTORS + vector=FIRST_EXTERNAL_VECTOR_IDT + .rept FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR_IDT UNWIND_HINT_IRET_REGS 0 : ENDBR diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h index 768aa234cbb4..e4be6f8409ad 100644 --- a/arch/x86/include/asm/irq.h +++ b/arch/x86/include/asm/irq.h @@ -11,6 +11,11 @@ #include #include +/* + * The first available IRQ vector + */ +extern unsigned int __ro_after_init first_external_vector; + /* * The irq entry code is in the noinstr section and the start/end of * __irqentry_text is emitted via labels. Make the build fail if diff --git a/arch/x86/include/asm/irq_vectors.h b/arch/x86/include/asm/irq_vectors.h index 43dcb9284208..cb3670a7c18f 100644 --- a/arch/x86/include/asm/irq_vectors.h +++ b/arch/x86/include/asm/irq_vectors.h @@ -31,15 +31,23 @@ /* * IDT vectors usable for external interrupt sources start at 0x20. - * (0x80 is the syscall vector, 0x30-0x3f are for ISA) + * (0x80 is the syscall vector, 0x30-0x3f are for ISA). + * + * With FRED we can also use 0x10-0x1f even though those overlap + * exception vectors as FRED distinguishes exceptions and interrupts. + * Therefore, FIRST_EXTERNAL_VECTOR is no longer a constant. */ -#define FIRST_EXTERNAL_VECTOR 0x20 +#define FIRST_EXTERNAL_VECTOR_IDT 0x20 +#define FIRST_EXTERNAL_VECTOR_FRED 0x10 +#define FIRST_EXTERNAL_VECTOR first_external_vector /* * Reserve the lowest usable vector (and hence lowest priority) 0x20 for * triggering cleanup after irq migration. 0x21-0x2f will still be used * for device interrupts. */ +#define IRQ_MOVE_CLEANUP_VECTOR_IDT FIRST_EXTERNAL_VECTOR_IDT +#define IRQ_MOVE_CLEANUP_VECTOR_FRED FIRST_EXTERNAL_VECTOR_FRED #define IRQ_MOVE_CLEANUP_VECTOR FIRST_EXTERNAL_VECTOR #define IA32_SYSCALL_VECTOR 0x80 @@ -48,7 +56,7 @@ * Vectors 0x30-0x3f are used for ISA interrupts. * round up to the next 16-vector boundary */ -#define ISA_IRQ_VECTOR(irq) (((FIRST_EXTERNAL_VECTOR + 16) & ~15) + irq) +#define ISA_IRQ_VECTOR(irq) (((FIRST_EXTERNAL_VECTOR_IDT + 16) & ~15) + irq) /* * Special IRQ vectors used by the SMP architecture, 0xf0-0xff @@ -114,7 +122,6 @@ #define FIRST_SYSTEM_VECTOR NR_VECTORS #endif -#define NR_EXTERNAL_VECTORS (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR) #define NR_SYSTEM_VECTORS (NR_VECTORS - FIRST_SYSTEM_VECTOR) /* diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 20d9a604da7c..eef67f64aa81 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -1621,12 +1621,17 @@ static void setup_local_APIC(void) /* * Set Task Priority to 'accept all except vectors 0-31'. An APIC * vector in the 16-31 range could be delivered if TPR == 0, but we - * would think it's an exception and terrible things will happen. We - * never change this later on. + * would think it's an exception and terrible things will happen, + * unless we are using FRED in which case interrupts and + * exceptions are distinguished by type code. + * + * We never change this later on. */ + BUG_ON(!first_external_vector); + value = apic_read(APIC_TASKPRI); value &= ~APIC_TPRI_MASK; - value |= 0x10; + value |= (first_external_vector - 0x10) & APIC_TPRI_MASK; apic_write(APIC_TASKPRI, value); /* Clear eventually stale ISR/IRR bits */ diff --git a/arch/x86/kernel/apic/vector.c b/arch/x86/kernel/apic/vector.c index c1efebd27e6c..f4325445fd78 100644 --- a/arch/x86/kernel/apic/vector.c +++ b/arch/x86/kernel/apic/vector.c @@ -46,6 +46,7 @@ static struct irq_matrix *vector_matrix; #ifdef CONFIG_SMP static DEFINE_PER_CPU(struct hlist_head, cleanup_list); #endif +unsigned int first_external_vector = FIRST_EXTERNAL_VECTOR_IDT; void lock_vector_lock(void) { @@ -796,7 +797,12 @@ int __init arch_early_irq_init(void) * Allocate the vector matrix allocator data structure and limit the * search area. */ - vector_matrix = irq_alloc_matrix(NR_VECTORS, FIRST_EXTERNAL_VECTOR, + if (cpu_feature_enabled(X86_FEATURE_FRED)) + first_external_vector = FIRST_EXTERNAL_VECTOR_FRED; + else + first_external_vector = FIRST_EXTERNAL_VECTOR_IDT; + + vector_matrix = irq_alloc_matrix(NR_VECTORS, first_external_vector, FIRST_SYSTEM_VECTOR); BUG_ON(!vector_matrix); diff --git a/arch/x86/kernel/fred.c b/arch/x86/kernel/fred.c index 907abfd69f3f..8d6dda8c8e71 100644 --- a/arch/x86/kernel/fred.c +++ b/arch/x86/kernel/fred.c @@ -56,7 +56,7 @@ void __init fred_setup_apic(void) { int i; - for (i = 0; i < FIRST_EXTERNAL_VECTOR; i++) + for (i = 0; i < FIRST_EXTERNAL_VECTOR_FRED; i++) set_bit(i, system_vectors); /* @@ -65,7 +65,7 @@ void __init fred_setup_apic(void) * /proc/interrupts. */ #ifdef CONFIG_SMP - set_bit(IRQ_MOVE_CLEANUP_VECTOR, system_vectors); + set_bit(IRQ_MOVE_CLEANUP_VECTOR_FRED, system_vectors); #endif for (i = 0; i < NR_SYSTEM_VECTORS; i++) { diff --git a/arch/x86/kernel/idt.c b/arch/x86/kernel/idt.c index a58c6bc1cd68..d3fd86f85de9 100644 --- a/arch/x86/kernel/idt.c +++ b/arch/x86/kernel/idt.c @@ -131,7 +131,7 @@ static const __initconst struct idt_data apic_idts[] = { INTG(RESCHEDULE_VECTOR, asm_sysvec_reschedule_ipi), INTG(CALL_FUNCTION_VECTOR, asm_sysvec_call_function), INTG(CALL_FUNCTION_SINGLE_VECTOR, asm_sysvec_call_function_single), - INTG(IRQ_MOVE_CLEANUP_VECTOR, asm_sysvec_irq_move_cleanup), + INTG(IRQ_MOVE_CLEANUP_VECTOR_IDT, asm_sysvec_irq_move_cleanup), INTG(REBOOT_VECTOR, asm_sysvec_reboot), #endif @@ -274,13 +274,13 @@ static void __init idt_map_in_cea(void) */ void __init idt_setup_apic_and_irq_gates(void) { - int i = FIRST_EXTERNAL_VECTOR; + int i = FIRST_EXTERNAL_VECTOR_IDT; void *entry; idt_setup_from_table(idt_table, apic_idts, ARRAY_SIZE(apic_idts), true); for_each_clear_bit_from(i, system_vectors, FIRST_SYSTEM_VECTOR) { - entry = irq_entries_start + IDT_ALIGN * (i - FIRST_EXTERNAL_VECTOR); + entry = irq_entries_start + IDT_ALIGN * (i - FIRST_EXTERNAL_VECTOR_IDT); set_intr_gate(i, entry); } diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c index 7e125fff45ab..b7511e02959c 100644 --- a/arch/x86/kernel/irq.c +++ b/arch/x86/kernel/irq.c @@ -359,7 +359,7 @@ void fixup_irqs(void) * vector_lock because the cpu is already marked !online, so * nothing else will touch it. */ - for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { + for (vector = first_external_vector; vector < NR_VECTORS; vector++) { if (IS_ERR_OR_NULL(__this_cpu_read(vector_irq[vector]))) continue; diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index ecfaf4d647bb..73471053ed02 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -1489,6 +1489,8 @@ DEFINE_IDTENTRY_IRQ(spurious_interrupt) pr_info("Spurious interrupt (vector 0x%x) on CPU#%d, should never happen.\n", vector, smp_processor_id()); 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([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:53:06 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 30/33] x86/fred: allow dynamic stack frame size Date: Tue, 4 Apr 2023 03:27:13 -0700 Message-Id: <20230404102716.1795-31-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762243321862617811?= X-GMAIL-MSGID: =?utf-8?q?1762243321862617811?= A FRED stack frame could contain different amount of information for different event types, or perhaps even for different instances of the same event type. Thus we need to eliminate the need of any advance information of the stack frame size to allow dynamic stack frame size. Implement it through: 1) add a new field user_pt_regs to thread_info, and initialize it with a pointer to a virtual pt_regs structure at the top of a thread stack. 2) save a pointer to the user-space pt_regs structure created by fred_entrypoint_user() to user_pt_regs in fred_entry_from_user(). 3) initialize the init_thread_info's user_pt_regs with a pointer to a virtual pt_regs structure at the top of init stack. This approach also works for IDT, thus we unify the code. Suggested-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/entry/entry_32.S | 2 +- arch/x86/entry/entry_fred.c | 2 ++ arch/x86/include/asm/entry-common.h | 3 +++ arch/x86/include/asm/processor.h | 12 +++------ arch/x86/include/asm/switch_to.h | 3 +-- arch/x86/include/asm/thread_info.h | 41 ++++------------------------- arch/x86/kernel/head_32.S | 3 +-- arch/x86/kernel/process.c | 5 ++++ kernel/fork.c | 6 +++++ 9 files changed, 27 insertions(+), 50 deletions(-) diff --git a/arch/x86/entry/entry_32.S b/arch/x86/entry/entry_32.S index 91397f58ac30..5adc4cf33d92 100644 --- a/arch/x86/entry/entry_32.S +++ b/arch/x86/entry/entry_32.S @@ -1244,7 +1244,7 @@ SYM_CODE_START(rewind_stack_and_make_dead) xorl %ebp, %ebp movl PER_CPU_VAR(pcpu_hot + X86_top_of_stack), %esi - leal -TOP_OF_KERNEL_STACK_PADDING-PTREGS_SIZE(%esi), %esp + leal -PTREGS_SIZE(%esi), %esp call make_task_dead 1: jmp 1b diff --git a/arch/x86/entry/entry_fred.c b/arch/x86/entry/entry_fred.c index 0bff1db913b8..18852d9d83fb 100644 --- a/arch/x86/entry/entry_fred.c +++ b/arch/x86/entry/entry_fred.c @@ -178,6 +178,8 @@ __visible noinstr void fred_entry_from_user(struct pt_regs *regs) [EVENT_TYPE_OTHER] = fred_syscall_slow }; + current->thread_info.user_pt_regs = regs; + /* * FRED employs a two-level event dispatch mechanism, with * the first-level on the type of an event and the second-level diff --git a/arch/x86/include/asm/entry-common.h b/arch/x86/include/asm/entry-common.h index 117903881fe4..5b7d0f47f188 100644 --- a/arch/x86/include/asm/entry-common.h +++ b/arch/x86/include/asm/entry-common.h @@ -12,6 +12,9 @@ /* Check that the stack and regs on entry from user mode are sane. */ static __always_inline void arch_enter_from_user_mode(struct pt_regs *regs) { + if (!cpu_feature_enabled(X86_FEATURE_FRED)) + current->thread_info.user_pt_regs = regs; + if (IS_ENABLED(CONFIG_DEBUG_ENTRY)) { /* * Make sure that the entry code gave us a sensible EFLAGS diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 8d73004e4cac..4a50d2a2c14b 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -626,17 +626,11 @@ static inline void spin_lock_prefetch(const void *x) prefetchw(x); } -#define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \ - TOP_OF_KERNEL_STACK_PADDING) +#define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack)) -#define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1)) +#define task_top_of_stack(task) ((unsigned long)task_stack_page(task) + THREAD_SIZE) -#define task_pt_regs(task) \ -({ \ - unsigned long __ptr = (unsigned long)task_stack_page(task); \ - __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \ - ((struct pt_regs *)__ptr) - 1; \ -}) +#define task_pt_regs(task) ((task)->thread_info.user_pt_regs) #ifdef CONFIG_X86_32 #define INIT_THREAD { \ diff --git a/arch/x86/include/asm/switch_to.h b/arch/x86/include/asm/switch_to.h index 00fd85abc1d2..0a31da150808 100644 --- a/arch/x86/include/asm/switch_to.h +++ b/arch/x86/include/asm/switch_to.h @@ -72,8 +72,7 @@ static inline void update_task_stack(struct task_struct *task) /* * Will use WRMSRNS/WRMSRLIST for performance once it's upstreamed. */ - wrmsrl(MSR_IA32_FRED_RSP0, - task_top_of_stack(task) + TOP_OF_KERNEL_STACK_PADDING); + wrmsrl(MSR_IA32_FRED_RSP0, task_top_of_stack(task)); } else if (cpu_feature_enabled(X86_FEATURE_XENPV)) { /* Xen PV enters the kernel on the thread stack. */ load_sp0(task_top_of_stack(task)); diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h index 998483078d5f..ced0a01e0a3e 100644 --- a/arch/x86/include/asm/thread_info.h +++ b/arch/x86/include/asm/thread_info.h @@ -13,42 +13,6 @@ #include #include -/* - * TOP_OF_KERNEL_STACK_PADDING is a number of unused bytes that we - * reserve at the top of the kernel stack. We do it because of a nasty - * 32-bit corner case. On x86_32, the hardware stack frame is - * variable-length. Except for vm86 mode, struct pt_regs assumes a - * maximum-length frame. If we enter from CPL 0, the top 8 bytes of - * pt_regs don't actually exist. Ordinarily this doesn't matter, but it - * does in at least one case: - * - * If we take an NMI early enough in SYSENTER, then we can end up with - * pt_regs that extends above sp0. On the way out, in the espfix code, - * we can read the saved SS value, but that value will be above sp0. - * Without this offset, that can result in a page fault. (We are - * careful that, in this case, the value we read doesn't matter.) - * - * In vm86 mode, the hardware frame is much longer still, so add 16 - * bytes to make room for the real-mode segments. - * - * x86-64 has a fixed-length stack frame, but it depends on whether - * or not FRED is enabled. Future versions of FRED might make this - * dynamic, but for now it is always 2 words longer. - */ -#ifdef CONFIG_X86_32 -# ifdef CONFIG_VM86 -# define TOP_OF_KERNEL_STACK_PADDING 16 -# else -# define TOP_OF_KERNEL_STACK_PADDING 8 -# endif -#else /* x86-64 */ -# ifdef CONFIG_X86_FRED -# define TOP_OF_KERNEL_STACK_PADDING (2*8) -# else -# define TOP_OF_KERNEL_STACK_PADDING 0 -# endif -#endif - /* * low level task data that entry.S needs immediate access to * - this struct should fit entirely inside of one cache line @@ -56,6 +20,7 @@ */ #ifndef __ASSEMBLY__ struct task_struct; +struct pt_regs; #include #include @@ -66,11 +31,14 @@ struct thread_info { #ifdef CONFIG_SMP u32 cpu; /* current CPU */ #endif + struct pt_regs *user_pt_regs; }; +#define INIT_TASK_PT_REGS ((struct pt_regs *)TOP_OF_INIT_STACK - 1) #define INIT_THREAD_INFO(tsk) \ { \ .flags = 0, \ + .user_pt_regs = INIT_TASK_PT_REGS, \ } #else /* !__ASSEMBLY__ */ @@ -240,6 +208,7 @@ static inline int arch_within_stack_frames(const void * const stack, extern void arch_task_cache_init(void); extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src); +extern void arch_init_user_pt_regs(struct task_struct *tsk); extern void arch_release_task_struct(struct task_struct *tsk); extern void arch_setup_new_exec(void); #define arch_setup_new_exec arch_setup_new_exec diff --git a/arch/x86/kernel/head_32.S b/arch/x86/kernel/head_32.S index 67c8ed99144b..0201ddcd7576 100644 --- a/arch/x86/kernel/head_32.S +++ b/arch/x86/kernel/head_32.S @@ -517,8 +517,7 @@ SYM_DATA_END(initial_page_table) * reliably detect the end of the stack. */ SYM_DATA(initial_stack, - .long init_thread_union + THREAD_SIZE - - SIZEOF_PTREGS - TOP_OF_KERNEL_STACK_PADDING) + .long init_thread_union + THREAD_SIZE - SIZEOF_PTREGS) __INITRODATA int_msg: diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index b650cde3f64d..e1c6350290ae 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -98,6 +98,11 @@ int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) return 0; } +void arch_init_user_pt_regs(struct task_struct *tsk) +{ + tsk->thread_info.user_pt_regs = (struct pt_regs *)task_top_of_stack(tsk)- 1; +} + #ifdef CONFIG_X86_64 void arch_release_task_struct(struct task_struct *tsk) { diff --git a/kernel/fork.c b/kernel/fork.c index c0257cbee093..c5a6c23ec6d4 100644 --- a/kernel/fork.c +++ b/kernel/fork.c @@ -953,6 +953,10 @@ int __weak arch_dup_task_struct(struct task_struct *dst, return 0; } +void __weak arch_init_user_pt_regs(struct task_struct *tsk) +{ +} + void set_task_stack_end_magic(struct task_struct *tsk) { unsigned long *stackend; @@ -980,6 +984,8 @@ static struct task_struct *dup_task_struct(struct task_struct *orig, int node) if (err) goto free_tsk; + arch_init_user_pt_regs(tsk); + #ifdef CONFIG_THREAD_INFO_IN_TASK refcount_set(&tsk->stack_refcount, 1); #endif From patchwork Tue Apr 4 10:27:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 79004 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2941121vqo; Tue, 4 Apr 2023 04:14:16 -0700 (PDT) X-Google-Smtp-Source: AKy350Yr5uYMoB2vSYp7US5dteqQZY6fHy0aUs5RmRDQsw0yiEOz7OqRa5/Mljp6clVnCoeqStxm X-Received: by 2002:a17:90b:1e03:b0:234:d3a:2a38 with SMTP id pg3-20020a17090b1e0300b002340d3a2a38mr2293326pjb.43.1680606856023; Tue, 04 Apr 2023 04:14:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680606856; cv=none; d=google.com; s=arc-20160816; b=I7TzsBF9SoYgPnVtVczpqz6oNON8uJpsFPTZGRGytgRLytH+72Yl0wtbk+rTyHZJIC Nlzge9avQNGnRuECzfov4DaKGTSLLninWNo7clg+N1uAYumIaBqkMUkIq5GrveKcgI11 Ttod5a/ONxpudsLH4OAW4Zy4i5pOjw6bW7nHparO6RxSiqyWJqASXlf33aqnHhlJ5grK kGKorUsNtl4Us56bulLSL5VafpjO7Amw9QKB2/oQ3MQrEzkwbMWu12c05E5b93xcIgfT jMwoacl9rkEGyNF5pz7JA6kqzxCmp8QOGX9dsUTAH2yolAbuNfPmYFtGZDl8SPd6OpDD YHHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=W7XedNztJ0mTK2b/JAIVrms4PBeui63Rn/5g9sSZqqs=; b=fjuPuKzntcXZcxh1CQrBGW9fR5wCDdmvozZ/hth8i9wOH9QHgWUY1bqDpdADgJ/GJD OUt+v3j0Adl7m9KHfuwwUJJGilRkImyL1gwqMl72ArMf3dr/LAIga5DZTi2IY1zAYoCn IdM6+FIY64kwi6aWSFDoheA8DmCv7+XBEKKgX7U/V7qznhWOVgHHBhE4JvMvvD0Z4MA6 uzjHx/uzoqx8HQT85jKCG2u0lWYXw8hY4tJjRlSfKnKvSumd/phv0jJ7uBhaUKTyTvIy ZUnhg3Jqs5JxONaUZkDK0ZXRkcVxUJdaAAh/zQN0v/iUfG0u3U7zyMHrAvd99mLGUt6B cP0w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=F2koYtLc; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:53:06 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 31/33] x86/fred: BUG() when ERETU with %rsp not equal to that when the ring 3 event was just delivered Date: Tue, 4 Apr 2023 03:27:14 -0700 Message-Id: <20230404102716.1795-32-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762244014592083210?= X-GMAIL-MSGID: =?utf-8?q?1762244014592083210?= A FRED stack frame generated by a ring 3 event should never be messed up, and the first thing we must make sure is that at the time an ERETU instruction is executed, %rsp must have the same address as that when the user level event was just delivered. However we don't want to bother the normal code path of ERETU because it's on the hotest code path, a good choice is to do this check when ERETU faults. Suggested-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/mm/extable.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/x86/mm/extable.c b/arch/x86/mm/extable.c index 9d82193adf3c..be297d4b137b 100644 --- a/arch/x86/mm/extable.c +++ b/arch/x86/mm/extable.c @@ -204,6 +204,14 @@ static bool ex_handler_eretu(const struct exception_table_entry *fixup, unsigned short ss = uregs->ss; unsigned short cs = uregs->cs; + /* + * A FRED stack frame generated by a ring 3 event should never be + * messed up, and the first thing we must make sure is that at the + * time an ERETU instruction is executed, %rsp must have the same + * address as that when the user level event was just delivered. + */ + BUG_ON(uregs != current->thread_info.user_pt_regs); + /* * Move the NMI bit from the invalid stack frame, which caused ERETU * to fault, to the fault handler's stack frame, thus to unblock NMI From patchwork Tue Apr 4 10:27:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 79002 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2934806vqo; Tue, 4 Apr 2023 04:03:39 -0700 (PDT) X-Google-Smtp-Source: AKy350YVq7b7LITx13Tj/Ed0tc2strhZGR5O2i/7OdaQ3CNI9PbWnXmekyaUmAFbjkuf/PjVzV4a X-Received: by 2002:a17:906:68ca:b0:92c:6fbf:4d with SMTP id y10-20020a17090668ca00b0092c6fbf004dmr1780541ejr.40.1680606219397; Tue, 04 Apr 2023 04:03:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680606219; cv=none; d=google.com; s=arc-20160816; b=vfpuQ+pLNWXkETLDdSIVe/NZSgrP2PjnmLsgneErWk0OvmAb+Bseq1ehU4ZgR2DCC4 jqG/Uw2VLhdKCkequvTGSYLm6xY0poSJRII/fado4CfDkMZ/Ie6ubIVgZvVZGL99aZ89 1ytEDi1FrOmxgYXfucHHCjzjBKViVb4/+kSzsDDHb9Wz6jr2M7AmgrbytOqPmN+8sSD1 iLYxkNJgZrSzmIWSt/RM9tKbzaMBp/dnvFo94UhZToSru9eypT8fUrZONiE3Kz85yA2x 4pCPdiwC1iuDNXGyBVDO601DkVwPZY05SB5utI4fBVuIx8V0QxyG6/zWKZfLySvCKr/l IdsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=kTBcKAMTLKESJNxm3nGpE/vMc0d6+JyySFIu52kBSMM=; b=OXLG+zN/4JVgT+fysQpT5V+svpItuck47mHRsUcbCN/oJHkg5JcCLtBAwARsOqkL2f +YRRj9QLvUViCK6s84eZeok+q3rrziIRUiqJGbmkScHg0Yw5xsPTBl74VUCjGmvcPdMK SXr1MshNOicsdulm4VHW/nPmGSmI1JHd7nmBa7TOXK71CciVUDIG8gIGKVgsUHGHycaZ Pzd9w6cubIWYHE6ojUl3ZZ5s6XzFpALxbF9hUnlLeiIBTN/DPFhaeWvbTg3skfn/UXRC hXDMmNIC75hR13D5w3xWnO+La08io2nJ3rG4Dhj4XcJ+/08k69eOwJpUu4V0ctxNdmg4 FNvw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=fJio8BMx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:53:06 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 32/33] x86/fred: disable FRED by default in its early stage Date: Tue, 4 Apr 2023 03:27:15 -0700 Message-Id: <20230404102716.1795-33-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762243346988879054?= X-GMAIL-MSGID: =?utf-8?q?1762243346988879054?= Disable FRED by default in its early stage. To enable FRED, a new kernel command line option "fred" needs to be added. Tested-by: Shan Kang Signed-off-by: Xin Li --- Documentation/admin-guide/kernel-parameters.txt | 4 ++++ arch/x86/kernel/cpu/common.c | 3 +++ 2 files changed, 7 insertions(+) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 6221a1d057dd..c55ea60e1a0c 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1498,6 +1498,10 @@ Warning: use of this parameter will taint the kernel and may cause unknown problems. + fred + Forcefully enable flexible return and event delivery, + which is otherwise disabled by default. + ftrace=[tracer] [FTRACE] will set and start the specified tracer as early as possible in order to facilitate early diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index eea41cb8722e..4db5e619fc97 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1467,6 +1467,9 @@ static void __init cpu_parse_early_param(void) char *argptr = arg, *opt; int arglen, taint = 0; + if (!cmdline_find_option_bool(boot_command_line, "fred")) + setup_clear_cpu_cap(X86_FEATURE_FRED); + #ifdef CONFIG_X86_32 if (cmdline_find_option_bool(boot_command_line, "no387")) #ifdef CONFIG_MATH_EMULATION From patchwork Tue Apr 4 10:27:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 79023 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2953576vqo; Tue, 4 Apr 2023 04:34:52 -0700 (PDT) X-Google-Smtp-Source: AKy350ZRrA/0f7Em9Z1IJNfTZph2cGbBxtzziHIUg9jYr802YlEuXEoi+4pW//9C7/KEnZphyvC0 X-Received: by 2002:aa7:9521:0:b0:627:e690:eacd with SMTP id c1-20020aa79521000000b00627e690eacdmr1858974pfp.29.1680608092566; Tue, 04 Apr 2023 04:34:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680608092; cv=none; d=google.com; s=arc-20160816; b=FdIOs6Ab+AqqPGWVClKoRxpPYxb9WckT0yKjlA1lY/wGwJFdqkqmip5KRK9Q1nCLQT REyg/PsWVCQXTF1eSFGkjMXpLk+pRzoqFRIu89ts31Fj2raFY7IIOeDKSHoCFTwZqja6 mmbq/hNZPg4Or+tKmO/471PEmNEIfKtVPCKWksosD3c5bpbwnn4bu28LU8wK3eO8zwvt 7UeyRehhY3ff9NsbfAnEEhe7rzsTd1r0DuxpXKSS21Vivou2n8clcDZKbnKTk65hd99V qIlD0KT2/kwh4IbM2VzcPGmhplHr5AFKUA2I2IKFRp3KcXfp86KyA1HR+9yQGpZjJ0SI TWTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=PrFmWeUdWkwvuLYVPGsXMWjUbO/MiCX3Sl+f1h0fEek=; b=m51j4Svhc4+BeDxSJQN4k4As9+oEY0IfQJinuoalRiFiir2zQ3AmTKn/cXO494NEL+ zI6w3oB8WbYWWC8e4VTGhA/fGLv2z60uVWzoWgGraYY5QVKyw6AHa/0Mf8MPLXP5MVlJ sYkLAa2hVLJFErnIDNJhJ0y0Fre64wh6YM4Fh3D64iBuhzQkJ6B4uzSTfz8isoV6/uYi 6JdLzx7DYvjzxeggSY74gAsA93HsARSDAZ7vG3ejs53o7T6vC1QC/PG0lC9J1jBm2r9Y JEwQ1Y76SU1yUBwyA8KSF7ZH4GQ9W9WhtBo6zgS7IHstWirvTWshIb45PPAU+Hj2U5ed qIlw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="m/x/Twa9"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:53:07 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 33/33] KVM: x86/vmx: refactor VMX_DO_EVENT_IRQOFF to generate FRED stack frames Date: Tue, 4 Apr 2023 03:27:16 -0700 Message-Id: <20230404102716.1795-34-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762245310898926963?= X-GMAIL-MSGID: =?utf-8?q?1762245310898926963?= Comparing to an IDT stack frame, a FRED stack frame has extra 16 bytes of information pushed at the regular stack top and 8 bytes of error code _always_ pushed at the regular stack bottom, VMX_DO_EVENT_IRQOFF can be refactored to generate FRED stack frames with event type and vector properly set. Thus, IRQ/NMI can be handled with the existing approach when FRED is enabled. As a FRED stack frame always contains an error code pushed by hardware, call a trampoline function first to have the return instruction address pushed on the regular stack. Then the trampoline function pushes an error code (0 for both IRQ and NMI) and jumps to fred_entrypoint_kernel() for NMI handling or calls external_interrupt() for IRQ handling. The trampoline function for IRQ handling pushes general purpose registers to form a pt_regs structure and then use it to call external_interrupt(). As a result, IRQ handling does not execute any noinstr code. Export fred_entrypoint_kernel() and external_interrupt() for above changes. Tested-by: Shan Kang Signed-off-by: Xin Li --- Changes since v6: * Export fred_entrypoint_kernel(), required when kvm-intel built as a module. * Reserve a REDZONE for CALL emulation and Align RSP to a 64-byte boundary before pushing a new FRED stack frame. --- arch/x86/entry/entry_64_fred.S | 1 + arch/x86/include/asm/asm-prototypes.h | 1 + arch/x86/include/asm/fred.h | 1 + arch/x86/include/asm/traps.h | 2 + arch/x86/kernel/traps.c | 5 ++ arch/x86/kvm/vmx/vmenter.S | 74 ++++++++++++++++++++++++++- arch/x86/kvm/vmx/vmx.c | 16 +++++- 7 files changed, 96 insertions(+), 4 deletions(-) diff --git a/arch/x86/entry/entry_64_fred.S b/arch/x86/entry/entry_64_fred.S index efe2bcd11273..de74ab97ff00 100644 --- a/arch/x86/entry/entry_64_fred.S +++ b/arch/x86/entry/entry_64_fred.S @@ -59,3 +59,4 @@ SYM_CODE_START_NOALIGN(fred_entrypoint_kernel) FRED_EXIT ERETS SYM_CODE_END(fred_entrypoint_kernel) +EXPORT_SYMBOL(fred_entrypoint_kernel) diff --git a/arch/x86/include/asm/asm-prototypes.h b/arch/x86/include/asm/asm-prototypes.h index b1a98fa38828..076bf8dee702 100644 --- a/arch/x86/include/asm/asm-prototypes.h +++ b/arch/x86/include/asm/asm-prototypes.h @@ -12,6 +12,7 @@ #include #include #include +#include #include #ifndef CONFIG_X86_CMPXCHG64 diff --git a/arch/x86/include/asm/fred.h b/arch/x86/include/asm/fred.h index f7caf3b2f3f7..d00b9cab6aa6 100644 --- a/arch/x86/include/asm/fred.h +++ b/arch/x86/include/asm/fred.h @@ -129,6 +129,7 @@ DECLARE_FRED_HANDLER(fred_exc_machine_check); * The actual assembly entry and exit points */ extern __visible void fred_entrypoint_user(void); +extern __visible void fred_entrypoint_kernel(void); /* * Initialization diff --git a/arch/x86/include/asm/traps.h b/arch/x86/include/asm/traps.h index 612b3d6fec53..017b95624325 100644 --- a/arch/x86/include/asm/traps.h +++ b/arch/x86/include/asm/traps.h @@ -58,4 +58,6 @@ typedef DECLARE_SYSTEM_INTERRUPT_HANDLER((*system_interrupt_handler)); system_interrupt_handler get_system_interrupt_handler(unsigned int i); +int external_interrupt(struct pt_regs *regs); + #endif /* _ASM_X86_TRAPS_H */ diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index 73471053ed02..0f1fcd53cb52 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -1573,6 +1573,11 @@ int external_interrupt(struct pt_regs *regs) return 0; } +#if IS_ENABLED(CONFIG_KVM_INTEL) +/* For KVM VMX to handle IRQs in IRQ induced VM exits. */ +EXPORT_SYMBOL_GPL(external_interrupt); +#endif + #endif /* CONFIG_X86_64 */ void __init install_system_interrupt_handler(unsigned int n, const void *asm_addr, const void *addr) diff --git a/arch/x86/kvm/vmx/vmenter.S b/arch/x86/kvm/vmx/vmenter.S index 631fd7da2bc3..f64b05b3d775 100644 --- a/arch/x86/kvm/vmx/vmenter.S +++ b/arch/x86/kvm/vmx/vmenter.S @@ -2,12 +2,14 @@ #include #include #include +#include #include #include #include #include #include "kvm-asm-offsets.h" #include "run_flags.h" +#include "../../entry/calling.h" #define WORD_SIZE (BITS_PER_LONG / 8) @@ -31,7 +33,7 @@ #define VCPU_R15 __VCPU_REGS_R15 * WORD_SIZE #endif -.macro VMX_DO_EVENT_IRQOFF call_insn call_target +.macro VMX_DO_EVENT_IRQOFF call_insn call_target fred=0 nmi=0 /* * Unconditionally create a stack frame, getting the correct RSP on the * stack (for x86-64) would take two instructions anyways, and RBP can @@ -41,16 +43,56 @@ mov %_ASM_SP, %_ASM_BP #ifdef CONFIG_X86_64 + .if \fred +#ifdef CONFIG_X86_FRED + /* + * It's not necessary to change current stack level for handling IRQ/NMI + * because the state of the kernel stack is well defined in this place + * in the code, and it is known not to be deep in a bunch of nested I/O + * layer handlers that eat up the stack. + */ + + /* Reserve a REDZONE for CALL emulation. */ + sub $(FRED_CONFIG_REDZONE_AMOUNT << 6), %rsp + + /* Align RSP to a 64-byte boundary before pushing a new stack frame */ + and $FRED_STACK_FRAME_RSP_MASK, %rsp + + push $0 /* Reserved by FRED, must be 0 */ + push $0 /* FRED event data, 0 for NMI and external interrupts */ +#endif + .else /* * Align RSP to a 16-byte boundary (to emulate CPU behavior) before * creating the synthetic interrupt stack frame for the IRQ/NMI. */ and $-16, %rsp + .endif + + .if \fred + .if \nmi + mov $(2 << 32 | 2 << 48), %_ASM_AX /* NMI event type and vector */ + .else + mov %_ASM_ARG1, %_ASM_AX + shl $32, %_ASM_AX /* external interrupt vector */ + .endif + add $__KERNEL_DS, %_ASM_AX + bts $57, %_ASM_AX /* bit 57: 64-bit mode */ + push %_ASM_AX + .else push $__KERNEL_DS + .endif + push %rbp #endif pushf + .if \nmi + mov $__KERNEL_CS, %_ASM_AX + bts $28, %_ASM_AX /* set the NMI bit */ + push %_ASM_AX + .else push $__KERNEL_CS + .endif \call_insn \call_target /* @@ -300,9 +342,19 @@ SYM_INNER_LABEL(vmx_vmexit, SYM_L_GLOBAL) SYM_FUNC_END(__vmx_vcpu_run) SYM_FUNC_START(vmx_do_nmi_irqoff) - VMX_DO_EVENT_IRQOFF call asm_exc_nmi_kvm_vmx + VMX_DO_EVENT_IRQOFF call asm_exc_nmi_kvm_vmx nmi=1 SYM_FUNC_END(vmx_do_nmi_irqoff) +#ifdef CONFIG_X86_FRED +SYM_FUNC_START(vmx_do_fred_nmi_trampoline) + push $0 /* FRED error code, 0 for NMI */ + jmp fred_entrypoint_kernel +SYM_FUNC_END(vmx_do_fred_nmi_trampoline) + +SYM_FUNC_START(vmx_do_fred_nmi_irqoff) + VMX_DO_EVENT_IRQOFF call vmx_do_fred_nmi_trampoline fred=1 nmi=1 +SYM_FUNC_END(vmx_do_fred_nmi_irqoff) +#endif .section .text, "ax" @@ -360,3 +412,21 @@ SYM_FUNC_END(vmread_error_trampoline) SYM_FUNC_START(vmx_do_interrupt_irqoff) VMX_DO_EVENT_IRQOFF CALL_NOSPEC _ASM_ARG1 SYM_FUNC_END(vmx_do_interrupt_irqoff) + +#ifdef CONFIG_X86_FRED +SYM_FUNC_START(vmx_do_fred_interrupt_trampoline) + push $0 /* FRED error code, 0 for NMI and external interrupts */ + PUSH_REGS + + movq %rsp, %rdi /* %rdi -> pt_regs */ + call external_interrupt + + POP_REGS + addq $8,%rsp /* Drop FRED error code */ + RET +SYM_FUNC_END(vmx_do_fred_interrupt_trampoline) + +SYM_FUNC_START(vmx_do_fred_interrupt_irqoff) + VMX_DO_EVENT_IRQOFF call vmx_do_fred_interrupt_trampoline fred=1 +SYM_FUNC_END(vmx_do_fred_interrupt_irqoff) +#endif diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index d2d6e1b6c788..6dfe692dfd6a 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -6875,7 +6875,9 @@ static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu) } void vmx_do_interrupt_irqoff(unsigned long entry); +void vmx_do_fred_interrupt_irqoff(unsigned int vector); void vmx_do_nmi_irqoff(void); +void vmx_do_fred_nmi_irqoff(void); static void handle_nm_fault_irqoff(struct kvm_vcpu *vcpu) { @@ -6923,7 +6925,12 @@ static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu) return; kvm_before_interrupt(vcpu, KVM_HANDLING_IRQ); - vmx_do_interrupt_irqoff(gate_offset(desc)); +#ifdef CONFIG_X86_64 + if (cpu_feature_enabled(X86_FEATURE_FRED)) + vmx_do_fred_interrupt_irqoff(vector); + else +#endif + vmx_do_interrupt_irqoff(gate_offset(desc)); kvm_after_interrupt(vcpu); vcpu->arch.at_instruction_boundary = true; @@ -7209,7 +7216,12 @@ static noinstr void vmx_vcpu_enter_exit(struct kvm_vcpu *vcpu, if ((u16)vmx->exit_reason.basic == EXIT_REASON_EXCEPTION_NMI && is_nmi(vmx_get_intr_info(vcpu))) { kvm_before_interrupt(vcpu, KVM_HANDLING_NMI); - vmx_do_nmi_irqoff(); +#ifdef CONFIG_X86_64 + if (cpu_feature_enabled(X86_FEATURE_FRED)) + vmx_do_fred_nmi_irqoff(); + else +#endif + vmx_do_nmi_irqoff(); kvm_after_interrupt(vcpu); }