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Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index 543feb3b6c58..35540f292bfd 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -40,6 +40,7 @@ properties: - qcom,scm-msm8994 - qcom,scm-msm8996 - qcom,scm-msm8998 + - qcom,scm-qcm2290 - qcom,scm-qdu1000 - qcom,scm-sa8775p - qcom,scm-sc7180 @@ -109,6 +110,7 @@ allOf: - qcom,scm-msm8960 - qcom,scm-msm8974 - qcom,scm-msm8976 + - qcom,scm-qcm2290 - qcom,scm-sm6375 then: required: @@ -127,6 +129,7 @@ allOf: - qcom,scm-apq8064 - qcom,scm-msm8660 - qcom,scm-msm8960 + - qcom,scm-qcm2290 - qcom,scm-sm6375 then: properties: From patchwork Mon Apr 3 17:36:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 78650 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2474796vqo; Mon, 3 Apr 2023 10:43:40 -0700 (PDT) X-Google-Smtp-Source: AK7set/0d8GNyT9j07o3ac4FiLbjkWF41bhem1xIj1gBEuD6q+9jWfR8Rv+FZu8fAW2HfGk3pS2x X-Received: by 2002:a05:6a20:8c01:b0:d6:df31:8ac2 with SMTP id j1-20020a056a208c0100b000d6df318ac2mr33946311pzh.42.1680543820721; Mon, 03 Apr 2023 10:43:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680543820; cv=none; d=google.com; s=arc-20160816; b=LYzzdxn4WjLdx8gk67NZxAndG+eheG8Ir9TKbSUpTr20VzOkHSmO1xlVDyHLC8pww+ aVSsef4fpHzuafamInsRtGUziI0KhcnX8QdeX8gp4sSu43A4rj5Z58eIz1qsM8lDMgBY VS1VIpAqRS9KQXcghMy34ASLrymQTPhcVEMzkGiDa63YJ4QO2SyX8g0r+TU6X6p8gOb9 lB+Yy4fyDSB15yW5c2sQAtPttxa0wq0N+mJiDmNYiIluiaDOMwwfTA4V7vmwW9lwOQJh GUX5LLdfQjjOzvuwTGCzVZ6QcqRPDa16qRCnzK+mq9M2ss9v8HTv4YEEZ5F45SYz3h7Y tVyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=s2Gfp4ouQK4BWK0PrRYjNegXpUm2LWNClNwwcmLs7w4=; b=ipYrr+fitIap6lxHB9NktyU8tZDBZBW9UO8LeMhaW3z6IOPF7GWtQnGHeqCxbG9naV uH7o2FpElgwKNfCJdzT/gt7X5enCj4FUF/L4VZycnl3S1/3vgQSwXP71RirlSS57aLRr PTxqHYNcu9y9eoFAXPTTaHRj4PFjqdpgF3GRSyQ0VBipcBtQS82uIkkqJ8XvJqvX/KhS LqwSo0mThS3xsIiPj4a55Yj7/T9EInBecD0MxYw+f44aPSZX8nnpZ7Etap2TdNC9Y/w+ k1HcGwb6i88LSMmR5JwBCWF3p8SLUZ1Vu11jA2E6X8ZrzbxzmNjR+xN6f/T4B6BC0DSX 5ARQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tenijuDX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.3.135]) by smtp.gmail.com with ESMTPSA id v2-20020a056512096200b004cc5f44747dsm1871094lft.220.2023.04.03.10.36.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Apr 2023 10:36:28 -0700 (PDT) From: Konrad Dybcio Date: Mon, 03 Apr 2023 19:36:00 +0200 Subject: [PATCH 2/9] dt-bindings: arm: qcom: Add QRB2210/QCM2290 and RB1 board MIME-Version: 1.0 Message-Id: <20230403-topic-rb1_qcm-v1-2-ca849b62ba07@linaro.org> References: <20230403-topic-rb1_qcm-v1-0-ca849b62ba07@linaro.org> In-Reply-To: <20230403-topic-rb1_qcm-v1-0-ca849b62ba07@linaro.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Robert Marko , Das Srinagesh Cc: Bhupesh Sharma , Vladimir Zapolskiy , Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680543384; l=1125; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=K1uCi7RaJN7lMlJeAejUJpCXXekP7RaotMQIk58D8DU=; b=9/RAdxgHqVwNW5PUmUGjkrh1TQQCR8HTp6YX+E/9q1B9rFm8wzuvXe3nTvSsSHoYbYg6+YhQGTr5 7UV+ewIXDVoykJtUQSH7A7m839r+i0nVUNswXuas35qr5/RMIjhj X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762177916963551269?= X-GMAIL-MSGID: =?utf-8?q?1762177916963551269?= Document QRB210, a QRB version of QCM2290. Document QTI Robotics RB1 as a QRB2210 device. Signed-off-by: Konrad Dybcio --- Documentation/devicetree/bindings/arm/qcom.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 05badce5fedc..f663af451eb2 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -47,6 +47,8 @@ description: | msm8996 msm8998 qcs404 + qcm2290 + qrb2210 qdu1000 qru1000 sa8155p @@ -353,6 +355,12 @@ properties: - const: swir,wp8548 - const: qcom,mdm9615 + - description: Qualcomm Technologies, Inc. Robotics RB1 + items: + - const: qcom,qrb2210-rb1 + - const: qcom,qrb2210 + - const: qcom,qcm2290 + - description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform items: - enum: From patchwork Mon Apr 3 17:36:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 78652 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2475533vqo; Mon, 3 Apr 2023 10:44:58 -0700 (PDT) X-Google-Smtp-Source: AKy350YqeO7ltouH8WbHHdUNX87suPpvQaLsXqpMjt+y5ECIv1OJc6sR66wQvR8N6ssUuIy+i/DE X-Received: by 2002:a17:907:a424:b0:93e:6f40:d141 with SMTP id sg36-20020a170907a42400b0093e6f40d141mr42820996ejc.40.1680543898312; Mon, 03 Apr 2023 10:44:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680543898; cv=none; d=google.com; s=arc-20160816; b=LYm6nJ/mnHy2+2MOkr8nREr9PJ5m2NKwqnqIsdQPQU3vEHwZ4Ox5ujyks1eQOWmzcg lEzJjTLJVhhDuSphQd4jpcEyIRjvTfPEfodxvaT++pPNYIMa8hmbZChX3ugQfHIlwghb YtMHGqsjHtkhpNwxG0X+rBbW0DguzZsTczwHYgIPpQpLhSlBMWMVFliL/wdnk1M5szpv jvMKy7qBvgwE1hqb7c1CG9B6nLpi0JJqr1Zz3ie20Xgr4DuLy00pNlCxLPgszQkxx3Df gs7MncQrk8AqIcShT63WXZlyVMug3fE49ee9PAKn4a5/cfeZhrQHuw9PMEz+uLz8GO+5 1aNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=g23+EGx4vbM+tIPH+iw75Al/HAOh0U2bUD0TNr2qG48=; b=dn/6kojPveLJeDNYtQlllgJ2z9nRZiVxzMPVLabgw/MEu06B8drvL9/ugSCnLwE7tU 6gq6J6kwSFVwBGB3ES8A9K0PvKEG2GsmxP1OFcwVU+1m9KVv95jGDU5wamonOwsEYyf5 qmdJQpnZx/erHCDlV8oXuJgRSXo8XOpY0ICYvIfQiHrpu1vPV5K8WUzXzYHfMlTU34J8 ffAL7A4gtTdSdLdQeIbw4aAyJ0LAJ1h7JZmpD3Fb3mirLWwlnr2rKqrtfEfvzicmFXKW 7P9bjEITOCL/PtOBSpvl9oJOud6Z/iUZWhCT+6LmwKhhn5owd+reeM6ENW0uzcp3YNgR 1Pxg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L2aCh3C7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.3.135]) by smtp.gmail.com with ESMTPSA id v2-20020a056512096200b004cc5f44747dsm1871094lft.220.2023.04.03.10.36.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Apr 2023 10:36:29 -0700 (PDT) From: Konrad Dybcio Date: Mon, 03 Apr 2023 19:36:01 +0200 Subject: [PATCH 3/9] arm64: dts: qcom: Add initial QCM2290, PM2250 & RB1 device trees MIME-Version: 1.0 Message-Id: <20230403-topic-rb1_qcm-v1-3-ca849b62ba07@linaro.org> References: <20230403-topic-rb1_qcm-v1-0-ca849b62ba07@linaro.org> In-Reply-To: <20230403-topic-rb1_qcm-v1-0-ca849b62ba07@linaro.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Robert Marko , Das Srinagesh Cc: Bhupesh Sharma , Vladimir Zapolskiy , Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680543384; l=28839; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=tUOXV/CqLlhenaOCipvuHX/hCy02O+5mrytX6ELmC1k=; b=+f6ru+F9Zh6F8As37x0woLbPsfyOwJx6MkVRX1s7d6my1ASwRq2R2ULu8pZSL6ZN8NiEOwSWN22x 7VoRAbKzCYnOKtXff+sBhYrb7wjnFKWGWstobLwB1Fj6R/5T52Fn X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762177998860208203?= X-GMAIL-MSGID: =?utf-8?q?1762177998860208203?= Add initial device trees for the QCM2290 SoC, QC Robotics RB1 board, as well as the bundled PM2250 PMIC. On the SoC part, CA53 compatibles were used, as Qualcomm claims that's what has been implemented, despite the cores reporting a Qualcomm Kryo MIDR_EL1[PART_NUM]. To get a successful boot on RB1, run: cat arch/arm64/boot/Image.gz arch/arm64/boot/dts/qcom/qrb2210-rb1.dtb >\ .Image.gz-dtb mkbootimg \ --kernel .Image.gz-dtb \ --ramdisk some_initrd \ --output rb1-boot.img \ --pagesize 4096 \ --base 0x8000 \ --cmdline 'some cmdline' fastboot boot rb1-boot.img There's no dtbo or other craziness to worry about. For the best dev experience, you can erase boot and use fastboot boot everytime, so that the bootloader doesn't mess with you. If you have a SoM revision 3 or older (there should be a sticker on it with text like -r00, where r is the revision), you will need to apply this additional diff: aliases { - serial0 = &uart0; + serial0 = &uart4; /* UART connected to the Micro-USB port via a FTDI chip */ -&uart0 { +&uart4 { That should however only concern preproduction boards. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/pm2250.dtsi | 63 +++ arch/arm64/boot/dts/qcom/qcm2290.dtsi | 848 +++++++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 107 ++++ 4 files changed, 1019 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 1a29403400b7..6fc8d6664f0c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -70,6 +70,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-xiaomi-sagit.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb +dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5-vision-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb diff --git a/arch/arm64/boot/dts/qcom/pm2250.dtsi b/arch/arm64/boot/dts/qcom/pm2250.dtsi new file mode 100644 index 000000000000..c5344d6e47c4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm2250.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2023, Linaro Ltd + */ + +#include +#include +#include +#include + +&spmi_bus { + pmic@0 { + compatible = "qcom,pm2250", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pon@800 { + compatible = "qcom,pm8916-pon"; + reg = <0x800>; + + pm2250_pwrkey: pwrkey { + compatible = "qcom,pm8941-pwrkey"; + interrupts-extended = <&spmi_bus 0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + debounce = <15625>; + bias-pull-up; + }; + + pm2250_resin: resin { + compatible = "qcom,pm8941-resin"; + interrupts-extended = <&spmi_bus 0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + status = "disabled"; + }; + }; + + rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>, <0x6100>; + reg-names = "rtc", "alarm"; + interrupts-extended = <&spmi_bus 0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; + }; + + pm2250_gpios: gpio@c000 { + compatible = "qcom,pm2250-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + gpio-ranges = <&pm2250_gpios 0 0 10>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmic@1 { + compatible = "qcom,pm2250", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi new file mode 100644 index 000000000000..27d4742cdb19 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -0,0 +1,848 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2023, Linaro Ltd + * + * Based on sm6115.dtsi and previous efforts by Shawn Guo & Loic Poulain. + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + clocks = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + clocks = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + clocks = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-qcm2290", "qcom,scm"; + clocks = <&rpmcc RPM_SMD_CE1_CLK>; + clock-names = "core"; + #reset-cells = <1>; + }; + }; + + memory@40000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0 0x40000000 0 0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp@45700000 { + reg = <0x0 0x45700000 0x0 0x600000>; + no-map; + }; + + xbl_aop_mem: xbl-aop@45e00000 { + reg = <0x0 0x45e00000 0x0 0x140000>; + no-map; + }; + + sec_apps_mem: sec-apps@45fff000 { + reg = <0x0 0x45fff000 0x0 0x1000>; + no-map; + }; + + smem_mem: smem@46000000 { + compatible = "qcom,smem"; + reg = <0x0 0x46000000 0x0 0x200000>; + no-map; + + hwlocks = <&tcsr_mutex 3>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + }; + + pil_modem_mem: modem@4ab00000 { + reg = <0x0 0x4ab00000 0x0 0x6900000>; + no-map; + }; + + pil_video_mem: video@51400000 { + reg = <0x0 0x51400000 0x0 0x500000>; + no-map; + }; + + wlan_msa_mem: wlan-msa@51900000 { + reg = <0x0 0x51900000 0x0 0x100000>; + no-map; + }; + + pil_adsp_mem: adsp@51a00000 { + reg = <0x0 0x51a00000 0x0 0x1c00000>; + no-map; + }; + + pil_ipa_fw_mem: ipa-fw@53600000 { + reg = <0x0 0x53600000 0x0 0x10000>; + no-map; + }; + + pil_ipa_gsi_mem: ipa-gsi@53610000 { + reg = <0x0 0x53610000 0x0 0x5000>; + no-map; + }; + + pil_gpu_mem: zap@53615000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x53615000 0x0 0x2000>; + no-map; + }; + + cont_splash_memory: framebuffer@5c000000 { + reg = <0x0 0x5c000000 0x0 0x00f00000>; + no-map; + }; + + dfps_data_memory: dpfs-data@5cf00000 { + reg = <0x0 0x5cf00000 0x0 0x0100000>; + no-map; + }; + + removed_mem: reserved@60000000 { + reg = <0x0 0x60000000 0x0 0x3900000>; + no-map; + }; + + rmtfs_mem: memory@89b01000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0x89b01000 0x0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = ; + }; + }; + + rpm-glink { + compatible = "qcom,glink-rpm"; + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-qcm2290"; + qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-qcm2290", "qcom,rpmcc"; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <1>; + }; + + rpmpd: power-controller { + compatible = "qcom,qcm2290-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_min_svs: opp1 { + opp-level = ; + }; + + rpmpd_opp_low_svs: opp2 { + opp-level = ; + }; + + rpmpd_opp_svs: opp3 { + opp-level = ; + }; + + rpmpd_opp_svs_plus: opp4 { + opp-level = ; + }; + + rpmpd_opp_nom: opp5 { + opp-level = ; + }; + + rpmpd_opp_nom_plus: opp6 { + opp-level = ; + }; + + rpmpd_opp_turbo: opp7 { + opp-level = ; + }; + + rpmpd_opp_turbo_plus: opp8 { + opp-level = ; + }; + }; + }; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + + tcsr_mutex: hwlock@340000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x00340000 0x0 0x20000>; + #hwlock-cells = <1>; + }; + + tlmm: pinctrl@500000 { + compatible = "qcom,qcm2290-tlmm"; + reg = <0x0 0x00500000 0x0 0x300000>; + interrupts = ; + gpio-controller; + gpio-ranges = <&tlmm 0 0 127>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + qup_uart0_default: qup-uart0-default-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "qup0"; + drive-strength = <2>; + bias-disable; + }; + + sdc1_state_on: sdc1-on-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_state_off: sdc1-off-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <2>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_state_on: sdc2-on-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdc2_state_off: sdc2-off-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + gcc: clock-controller@1400000 { + compatible = "qcom,gcc-qcm2290"; + reg = <0x0 0x01400000 0x0 0x1f0000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; + clock-names = "bi_tcxo", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + usb_hsphy: phy@1613000 { + compatible = "qcom,qcm2290-qusb2-phy"; + reg = <0x0 0x01613000 0x0 0x180>; + + clocks = <&gcc GCC_AHB2PHY_USB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + nvmem-cells = <&qusb2_hstx_trim>; + #phy-cells = <0>; + + status = "disabled"; + }; + + qfprom@1b44000 { + compatible = "qcom,qcm2290-qfprom", "qcom,qfprom"; + reg = <0x0 0x01b44000 0x0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + + qusb2_hstx_trim: hstx-trim@25b { + reg = <0x25b 0x1>; + bits = <1 4>; + }; + }; + + spmi_bus: spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0x01c40000 0x0 0x1100>, + <0x0 0x01e00000 0x0 0x2000000>, + <0x0 0x03e00000 0x0 0x100000>, + <0x0 0x03f00000 0x0 0xa0000>, + <0x0 0x01c0a000 0x0 0x26000>; + reg-names = "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + interrupts = ; + interrupt-names = "periph_irq"; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + tsens0: thermal-sensor@4411000 { + compatible = "qcom,qcm2290-tsens", "qcom,tsens-v2"; + reg = <0x0 0x04411000 0x0 0x1ff>, + <0x0 0x04410000 0x0 0x8>; + #qcom,sensors = <10>; + interrupts = , + ; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + rng: rng@4453000 { + compatible = "qcom,prng-ee"; + reg = <0x0 0x04453000 0x0 0x1000>; + clocks = <&rpmcc RPM_SMD_HWKM_CLK>; + clock-names = "core"; + }; + + rpm_msg_ram: sram@45f0000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x0 0x045f0000 0x0 0x7000>; + }; + + sram@4690000 { + compatible = "qcom,rpm-stats"; + reg = <0x0 0x04690000 0x0 0x10000>; + }; + + sdhc_1: mmc@4744000 { + compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0 0x04744000 0x0 0x1000>, + <0x0 0x04745000 0x0 0x1000>, + <0x0 0x04748000 0x0 0x8000>; + reg-names = "hc", + "cqhci", + "ice"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "iface", + "core", + "xo", + "ice"; + + resets = <&gcc GCC_SDCC1_BCR>; + + power-domains = <&rpmpd QCM2290_VDDCX>; + iommus = <&apps_smmu 0xc0 0x0>; + + qcom,dll-config = <0x000f642c>; + qcom,ddr-config = <0x80040868>; + bus-width = <8>; + + status = "disabled"; + }; + + sdhc_2: mmc@4784000 { + compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0 0x04784000 0x0 0x1000>; + reg-names = "hc"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", + "core", + "xo"; + + resets = <&gcc GCC_SDCC2_BCR>; + + power-domains = <&rpmpd QCM2290_VDDCX>; + operating-points-v2 = <&sdhc2_opp_table>; + iommus = <&apps_smmu 0xa0 0x0>; + + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + bus-width = <4>; + + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmpd_opp_svs_plus>; + }; + }; + }; + + gpi_dma0: dma-controller@4a00000 { + compatible = "qcom,qcm2290-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x04a00000 0x0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + ; + dma-channels = <10>; + dma-channel-mask = <0x1f>; + iommus = <&apps_smmu 0xf6 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + + qupv3_id_0: geniqup@4ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x04ac0000 0x0 0x2000>; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; + iommus = <&apps_smmu 0xe3 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + uart0: serial@4a80000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a80000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart0_default>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usb: usb@4ef8800 { + compatible = "qcom,qcm2290-dwc3", "qcom,dwc3"; + reg = <0x0 0x04ef8800 0x0 0x400>; + interrupts = , + ; + interrupt-names = "hs_phy_irq", "ss_phy_irq"; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <133333333>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + wakeup-source; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + usb_dwc3: usb@4e00000 { + compatible = "snps,dwc3"; + reg = <0x0 0x04e00000 0x0 0xcd00>; + interrupts = ; + phys = <&usb_hsphy>; + phy-names = "usb2-phy"; + iommus = <&apps_smmu 0x120 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + }; + + apps_smmu: iommu@c600000 { + compatible = "qcom,qcm2290-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x0c600000 0x0 0x80000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + watchdog@f017000 { + compatible = "qcom,apss-wdt-qcm2290", "qcom,kpss-wdt"; + reg = <0x0 0x0f017000 0x0 0x1000>; + interrupts = , + ; + clocks = <&sleep_clk>; + }; + + apcs_glb: mailbox@f111000 { + compatible = "qcom,qcm2290-apcs-hmss-global"; + reg = <0x0 0x0f111000 0x0 0x1000>; + #mbox-cells = <1>; + }; + + timer@f120000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x0f120000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x0f121000 0x8000>; + + frame@0 { + reg = <0x0 0x1000>, + <0x1000 0x1000>; + interrupts = , + ; + frame-number = <0>; + }; + + frame@2000 { + reg = <0x2000 0x1000>; + interrupts = ; + frame-number = <1>; + status = "disabled"; + }; + + frame@3000 { + reg = <0x3000 0x1000>; + interrupts = ; + frame-number = <2>; + status = "disabled"; + }; + + frame@4000 { + reg = <0x4000 0x1000>; + interrupts = ; + frame-number = <3>; + status = "disabled"; + }; + + frame@5000 { + reg = <0x5000 0x1000>; + interrupts = ; + frame-number = <4>; + status = "disabled"; + }; + + frame@6000 { + reg = <0x6000 0x1000>; + interrupts = ; + frame-number = <5>; + status = "disabled"; + }; + + frame@7000 { + reg = <0x7000 0x1000>; + interrupts = ; + frame-number = <6>; + status = "disabled"; + }; + }; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x0f200000 0x0 0x10000>, + <0x0 0x0f300000 0x0 0x100000>; + interrupts = ; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&intc>; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + }; + + cpufreq_hw: cpufreq@f521000 { + compatible = "qcom,qcm2290-cpufreq-hw", "qcom,cpufreq-hw"; + reg = <0x0 0x0f521000 0x0 0x1000>; + reg-names = "freq-domain0"; + interrupts = ; + interrupt-names = "dcvsh-irq-0"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + #clock-cells = <1>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts new file mode 100644 index 000000000000..539a06456334 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2023, Linaro Ltd + */ + +/dts-v1/; + +#include "qcm2290.dtsi" +#include "pm2250.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Robotics RB1"; + compatible = "qcom,qrb2210-rb1", "qcom,qrb2210", "qcom,qcm2290"; + + aliases { + serial0 = &uart0; + sdhc1 = &sdhc_1; + sdhc2 = &sdhc_2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-0 = <&key_volp_n>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + linux,code = ; + gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&sdhc_1 { + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; + pinctrl-names = "default", "sleep"; + non-removable; + supports-cqe; + no-sdio; + no-sd; + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 88 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&sdc2_state_on &sd_det_in_on>; + pinctrl-1 = <&sdc2_state_off &sd_det_in_off>; + pinctrl-names = "default", "sleep"; + no-sdio; + no-mmc; + status = "okay"; +}; + +&tlmm { + sd_det_in_on: sd-det-in-on-state { + pins = "gpio88"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + sd_det_in_off: sd-det-in-off-state { + pins = "gpio88"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + key_volp_n: key-volp-n-state { + pins = "gpio96"; + function = "gpio"; + bias-pull-up; + output-disable; + }; +}; + +/* UART connected to the Micro-USB port via a FTDI chip */ +&uart0 { + compatible = "qcom,geni-debug-uart"; + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&usb_hsphy { + status = "okay"; +}; + +&xo_board { + clock-frequency = <38400000>; +}; From patchwork Mon Apr 3 17:36:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 78655 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2475607vqo; Mon, 3 Apr 2023 10:45:06 -0700 (PDT) X-Google-Smtp-Source: AKy350ZDxYWjCkUcII0zT+SkBxDLuxg+YMfFQuETIKuHwYrRubufTwQP+bwGyYegYZ00MgjfV6Jm X-Received: by 2002:a05:6a20:3544:b0:e3:6feb:fb6a with SMTP id f4-20020a056a20354400b000e36febfb6amr16441501pze.40.1680543905969; Mon, 03 Apr 2023 10:45:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680543905; cv=none; d=google.com; s=arc-20160816; b=NdSsKJHpM3afzURJnD1R1DnGn54UVNceX393gqfgrBOo9ds4AYf3IsncWHd5dR5FHa el6ZDnJjA44BFb/LiZjdYfuCF6ik7onOgF8vDhAa2wby82/F+JIOb9ex3eA1V77WislF JsLQygHT0inp1Gfi46irPDJnExmEumadlBFnYapzWEJSULZu1Evs29IEW5OOZkKJz9yx N4sESioYKBurLpvcdRhW42GS9+g3STlkImQ8FiHReIGz4mHh2BHCqM0WGRSlXfYRw3Wy qwnCOiXXVTsDpt75v3wWYwIy+J7Y9rNT+EJCUPEibAC7FK+QcM2lv4wdEmx9z6JJXkRU SeaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=YDSUqIgZc3vuE7G0wttUjC5sMF8eoKNUAXbG/+xBz7o=; b=ZPFxHqYtM+4I7PvpnQAaShaqyMZkDc59+fi0dhIoSXmTndP9yNYBdWDNBvlGDPSiM4 xjm7TPDcvVsh9OJQuoG1uLC3+hCbrROWbeUrsCSodS8gAQPRFBLUA0kNiiOHpwsM0SqD H7UW3R4mwRiF7dVQ9ibydRM6V4kYQv/VFDwE696p3oawIZj+DLbimvvQGjmpqL0VHpkH /l19SPthlXjpA5czeQEG8vA2uvAuUhHNIdAOMxbCbkJuebv5C8AQO5oytWrgpkdjk8oj L54YCUHnauNgVk9P4bBAUceQHbaYDaYU7N2S1TvKlEg0LZm8c/dpPKIdbXcrKQPWXQYs AJJA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dfpkob28; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.3.135]) by smtp.gmail.com with ESMTPSA id v2-20020a056512096200b004cc5f44747dsm1871094lft.220.2023.04.03.10.36.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Apr 2023 10:36:31 -0700 (PDT) From: Konrad Dybcio Date: Mon, 03 Apr 2023 19:36:02 +0200 Subject: [PATCH 4/9] arm64: dts: qcom: qcm2290: Add most QUPs MIME-Version: 1.0 Message-Id: <20230403-topic-rb1_qcm-v1-4-ca849b62ba07@linaro.org> References: <20230403-topic-rb1_qcm-v1-0-ca849b62ba07@linaro.org> In-Reply-To: <20230403-topic-rb1_qcm-v1-0-ca849b62ba07@linaro.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Robert Marko , Das Srinagesh Cc: Bhupesh Sharma , Vladimir Zapolskiy , Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680543384; l=9924; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=h7DNqy7zdnStNn/U/kT1rG4OFD58lx5f9HKEurJdSgg=; b=HU+/8bML8aHHs2aPAEF2zaGH2jMAMzXTreqe8YRJrsMTJjHv2hTqysMh2xyBtV2SCICl1mxQvKNw lLTC1M5wD5KC0SNLR6Dl8T0mTWLkD3nXExVlnDYp3D0Hi8GjlID2 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762178006936160320?= X-GMAIL-MSGID: =?utf-8?q?1762178006936160320?= Add all I2C and SPI hosts, the debug UART port and the related pinctrl. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 294 ++++++++++++++++++++++++++++++++++ 1 file changed, 294 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index 27d4742cdb19..edfa18190454 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -310,6 +310,90 @@ tlmm: pinctrl@500000 { interrupt-controller; #interrupt-cells = <2>; + qup_i2c0_default: qup-i2c0-default-state { + pins = "gpio0", "gpio1"; + function = "qup0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c1_default: qup-i2c1-default-state { + pins = "gpio4", "gpio5"; + function = "qup1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c2_default: qup-i2c2-default-state { + pins = "gpio6", "gpio7"; + function = "qup2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c3_default: qup-i2c3-default-state { + pins = "gpio8", "gpio9"; + function = "qup3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c4_default: qup-i2c4-default-state { + pins = "gpio12", "gpio13"; + function = "qup4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c5_default: qup-i2c5-default-state { + pins = "gpio14", "gpio15"; + function = "qup5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi0_default: qup-spi0-default-state { + pins = "gpio0", "gpio1","gpio2", "gpio3"; + function = "qup0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi1_default: qup-spi1-default-state { + pins = "gpio4", "gpio5", "gpio69", "gpio70"; + function = "qup1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi2_default: qup-spi2-default-state { + pins = "gpio6", "gpio7", "gpio71", "gpio80"; + function = "qup2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi3_default: qup-spi3-default-state { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "qup3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi4_default: qup-spi4-default-state { + pins = "gpio12", "gpio13", "gpio96", "gpio97"; + function = "qup4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi5_default: qup-spi5-default-state { + pins = "gpio14", "gpio15", "gpio16", "gpio17"; + function = "qup5"; + drive-strength = <2>; + bias-pull-up; + }; + qup_uart0_default: qup-uart0-default-state { pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "qup0"; @@ -317,6 +401,13 @@ qup_uart0_default: qup-uart0-default-state { bias-disable; }; + qup_uart4_default: qup-uart4-default-state { + pins = "gpio12", "gpio13"; + function = "qup4"; + drive-strength = <2>; + bias-disable; + }; + sdc1_state_on: sdc1-on-state { clk-pins { pins = "sdc1_clk"; @@ -604,6 +695,38 @@ qupv3_id_0: geniqup@4ac0000 { ranges; status = "disabled"; + i2c0: i2c@4a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a80000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c0_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@4a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a80000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi0_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + uart0: serial@4a80000 { compatible = "qcom,geni-uart"; reg = <0x0 0x04a80000 0x0 0x4000>; @@ -614,6 +737,177 @@ uart0: serial@4a80000 { pinctrl-names = "default"; status = "disabled"; }; + + i2c1: i2c@4a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a84000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c1_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@4a84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a84000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi1_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@4a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a88000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c2_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@4a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a88000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi2_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@4a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a8c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c3_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@4a8c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a8c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi3_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@4a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a90000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c4_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@4a90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a90000 0x0 0x4000>; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi4_default>; + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart4: serial@4a90000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a90000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart4_default>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c5: i2c@4a94000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a94000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c5_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@4a94000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a94000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi5_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; usb: usb@4ef8800 { From patchwork Mon Apr 3 17:36:03 2023 Content-Type: text/plain; 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[83.9.3.135]) by smtp.gmail.com with ESMTPSA id v2-20020a056512096200b004cc5f44747dsm1871094lft.220.2023.04.03.10.36.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Apr 2023 10:36:32 -0700 (PDT) From: Konrad Dybcio Date: Mon, 03 Apr 2023 19:36:03 +0200 Subject: [PATCH 5/9] arm64: dts: qcom: qcm2290: Add thermal zones MIME-Version: 1.0 Message-Id: <20230403-topic-rb1_qcm-v1-5-ca849b62ba07@linaro.org> References: <20230403-topic-rb1_qcm-v1-0-ca849b62ba07@linaro.org> In-Reply-To: <20230403-topic-rb1_qcm-v1-0-ca849b62ba07@linaro.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Robert Marko , Das Srinagesh Cc: Bhupesh Sharma , Vladimir Zapolskiy , Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680543384; l=6064; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=ZBHwGxxehL+0owRFdXHZJ0e8cp4AHvcKk4/jCwnA2m0=; b=+3Qrae1rdVWhCWGKLtdGUrAoOyfgfvuVOYG1WtQEZyS9f5PZdZHtpfJiR+jIsqg5coyl3+GAJfqL 6e8eCfJEB8kFZWJBBt/+B/F0ONWo6oPRDbsaMQ/617XgeoyaALE8 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762177885066282164?= X-GMAIL-MSGID: =?utf-8?q?1762177885066282164?= Add thermal zones associated with the TSENS sensors. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 272 ++++++++++++++++++++++++++++++++++ 1 file changed, 272 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index edfa18190454..1ea558bc35dc 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -1132,6 +1132,278 @@ cpufreq_hw: cpufreq@f521000 { }; }; + thermal-zones { + mapss-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 0>; + + trips { + mapss_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + mapss_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + mapss_crit: mapss-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + video-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 1>; + + trips { + video_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + video_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + video_crit: video-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + wlan-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 2>; + + trips { + wlan_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + wlan_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + wlan_crit: wlan-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 3>; + + trips { + cpuss0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpuss0_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpuss0_crit: cpuss0-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 4>; + + trips { + cpuss1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpuss1_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpuss1_crit: cpuss1-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + mdm0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 5>; + + trips { + mdm0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + mdm0_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + mdm0_crit: mdm0-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + mdm1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 6>; + + trips { + mdm1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + mdm1_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + mdm1_crit: mdm1-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 7>; + + trips { + gpu_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu_crit: gpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + hm-center-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 8>; + + trips { + hm_center_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + hm_center_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + hm_center_crit: hm-center-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + camera-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 9>; + + trips { + camera_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + camera_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + camera_crit: camera-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , From patchwork Mon Apr 3 17:36:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 78651 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2475010vqo; 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Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 52 +++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index 1ea558bc35dc..228a1d94501b 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -287,6 +287,58 @@ rpmpd_opp_turbo_plus: opp8 { }; }; + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + + interrupts = ; + + mboxes = <&apcs_glb 10>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-mpss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupts = ; + + mboxes = <&apcs_glb 14>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + wlan_smp2p_in: wlan-wpss-to-ap { + qcom,entry-name = "wlan"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc@0 { compatible = "simple-bus"; #address-cells = <2>; From patchwork Mon Apr 3 17:36:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 78654 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2475564vqo; Mon, 3 Apr 2023 10:45:00 -0700 (PDT) X-Google-Smtp-Source: AKy350Yu7y/M5LON+Tc7IM/lW1tetD0Oy2mWJaG0TqAN7j83PIWsGZSy4JlXvl2xpZyEy28WiA1S X-Received: by 2002:a17:907:7788:b0:932:c1e2:9984 with SMTP id ky8-20020a170907778800b00932c1e29984mr35098183ejc.58.1680543900749; Mon, 03 Apr 2023 10:45:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680543900; cv=none; d=google.com; s=arc-20160816; b=KlSSUPt/MESnxQj7nl43zXlcKm/4izcjuOO5OAAmZ3abC47aG/uOz76zi6uOOCegza 2uNgaT+pRV2FaAZ5ULcdJm1Z9qMCi8GK0Kk+wHyyrjWN9X2hLU/NolVFg/4O85S/091v vkDWAW+I2Ltt27ilQHf/G5CXyrVVdo5Y1RfHga8b1o6GkrCwVVPnoOneiEMgwbevaeyE pRoD17shFWQ5LNoGox31NyttdP6x4cmDKdQVbWTj01ClsTwn7GVtQimtPp4J1XNMYC34 n9Zj3Hw8xpjKVhI+TNYMpARDvuEDGO0STOjc4bn5r/xTG/Qp76BvS49YRXokotXJfPYg yibQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=Ex9xMh3gTSM9WsBX8GKkun9yHoiTNR6HSOi61NvUkJ4=; b=VOfgJttoF//+DdHwJGv8vFG4Kf3P9VLLJkUHoK1cz65EyE8srQQ+T8YVT1cxdo01oQ hzeHfArMY78KKjmbPPi4aqbhnT9dEUy0zPQVIPcj9YwkS7A/H1lEeuEOyWrAwMnRzHof hGMdjAL7tMWWekTwn3Yt1DZZkLDHurhaOy7PJDfMiQlUFHr/3JOLPfZ9mju5rf74Dr6j TUyKh4JnzC4tyMvSLyHk1iqaAMuvBbAseypRSUHVawIp4ChVSdp3moPyz4Wqp4QgZMOh v3WZOn4rS3iPanKKkSEa+gQS8cSFnAL6feHx4C3LDrztuhftTs1+J0EXiP46V6tAJ+QN lauQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JDcOz3RD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 73 +++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index 228a1d94501b..825623243787 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -1013,6 +1013,79 @@ usb_dwc3: usb@4e00000 { }; }; + remoteproc_mpss: remoteproc@6080000 { + compatible = "qcom,qcm2290-mpss-pas", "qcom,sm6115-mpss-pas"; + reg = <0x0 0x06080000 0x0 0x100>; + + interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + power-domains = <&rpmpd QCM2290_VDDCX>; + + memory-region = <&pil_modem_mem>; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + label = "mpss"; + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 12>; + }; + }; + + remoteproc_adsp: remoteproc@ab00000 { + compatible = "qcom,qcm2290-adsp-pas", "qcom,sm6115-adsp-pas"; + reg = <0x0 0x0ab00000 0x0 0x100>; + + interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + power-domains = <&rpmpd QCM2290_VDD_LPI_CX>, + <&rpmpd QCM2290_VDD_LPI_MX>; + + memory-region = <&pil_adsp_mem>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + label = "lpass"; + qcom,remote-pid = <2>; + mboxes = <&apcs_glb 8>; + }; + }; + apps_smmu: iommu@c600000 { compatible = "qcom,qcm2290-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x0 0x0c600000 0x0 0x80000>; From patchwork Mon Apr 3 17:36:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 78657 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2475719vqo; Mon, 3 Apr 2023 10:45:19 -0700 (PDT) X-Google-Smtp-Source: AKy350bMpA6D0BUixvUFjL/slLdGU/eeNfh0kGCr/u+fbFM1lIyDYiTpNnrVGozJBe+3vkrsxQnJ X-Received: by 2002:a17:906:298c:b0:933:37f4:2fe0 with SMTP id x12-20020a170906298c00b0093337f42fe0mr37857074eje.46.1680543919002; Mon, 03 Apr 2023 10:45:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680543918; cv=none; d=google.com; s=arc-20160816; b=WWMTJeZOaSttCKKCOJiplJUBooYLk1QEFiV+2XRH0JX6gUKB/5hMDI0Kh0kzipPBEZ UcuavMQez5UGZmPv7LioxlwUsIt+HGqAne4k8wJda7uASCxzqu6DDBlSHSXYdFplmaJr 7Q1f1VcsTBg7ViZ3e8f6PnikCZoMJUvsiK0D30wUX+gZgeBgWVM00wtRP40SLv8SCsqf VgCaLEWZJPlQiLAGG5erxIQ8QQqZRVw5WZO0T5yj4rU9c5iU/WumURixJNsnedUBIGhj yByvU925uiszHr2ioJL3JvVQ1WqiYzbVoMr29jI9hVI6BlH4MWSNsVDNJhca6TwF196t EdjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=q78NH+UaU1k2JYnzdD9GjMmztSwW1iJ5zaXHWLUjDuA=; b=clGiUCGG1/dy0GOxBuYfxH4dB4xPQ4RDBGUBqtP9C2byUNqbsf4snlnuHzGlgLX+iC vYe2tokqVzFDUGLiFaIg0CGgrF+1GJxML/Ac6HijT6OwmVjCP9+rbz0chGSyra4tc1JT SKq1R5GuQbtagRC4luV8rwgflLcPBcAfurI+klG0bejlmRuA+HOMZ7S5PKVZONeVXkNW xttfSBl7BL+XYqHCFzvitDcQUwyZuvDXQVyCB5ls8FDVeejx8Xv44Js7MTdm0n9rh08I UA0MqPwOx6lDD26Kcjiz/i40DcDi3WhcSk/V2vbY2YYumedBRucGcP630mvxzZUpSH1p gsCQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ybQFVZ0R; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.3.135]) by smtp.gmail.com with ESMTPSA id v2-20020a056512096200b004cc5f44747dsm1871094lft.220.2023.04.03.10.36.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Apr 2023 10:36:37 -0700 (PDT) From: Konrad Dybcio Date: Mon, 03 Apr 2023 19:36:06 +0200 Subject: [PATCH 8/9] arm64: dts: qcom: qcm2290: Add WCN3990 Wi-Fi node MIME-Version: 1.0 Message-Id: <20230403-topic-rb1_qcm-v1-8-ca849b62ba07@linaro.org> References: <20230403-topic-rb1_qcm-v1-0-ca849b62ba07@linaro.org> In-Reply-To: <20230403-topic-rb1_qcm-v1-0-ca849b62ba07@linaro.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Robert Marko , Das Srinagesh Cc: Bhupesh Sharma , Vladimir Zapolskiy , Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680543384; l=1523; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=G8+7P12a2FAQaZ56sk4Rf7dxNO+WX1mJoPvrRVY3txE=; b=Xa16zwCkAqGz6fJ6Roo3Zuy4oemeqRIFtsBhZtYLyfOH1c0ts1EIkB3q2ISdLOrsl3jKgbULdiTv bxLwMqmcD96+ByQyx85uJs9wirDbW2ddqTnSjWSHORWf4s4DHdw9 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762178020431985655?= X-GMAIL-MSGID: =?utf-8?q?1762178020431985655?= Add a node for the ATH10K SNoC-managed WCN3990 Wi-Fi. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index 825623243787..ae5abc76bcc7 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -1159,6 +1159,28 @@ apps_smmu: iommu@c600000 { ; }; + wifi: wifi@c800000 { + compatible = "qcom,wcn3990-wifi"; + reg = <0x0 0x0c800000 0x0 0x800000>; + reg-names = "membase"; + memory-region = <&wlan_msa_mem>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + iommus = <&apps_smmu 0x1a0 0x1>; + qcom,msa-fixed-perm; + status = "disabled"; + }; + watchdog@f017000 { compatible = "qcom,apss-wdt-qcm2290", "qcom,kpss-wdt"; reg = <0x0 0x0f017000 0x0 0x1000>; From patchwork Mon Apr 3 17:36:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 78656 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2475664vqo; Mon, 3 Apr 2023 10:45:12 -0700 (PDT) X-Google-Smtp-Source: AKy350Y/8HPJFmL/2WAZV12BJjqxHlP6wuzjhripVZHQcpimvN+IEY8MVnzE/ap4i/Fcc2beV2M5 X-Received: by 2002:a17:906:d966:b0:7c0:e30a:d3e5 with SMTP id rp6-20020a170906d96600b007c0e30ad3e5mr34909103ejb.18.1680543911954; Mon, 03 Apr 2023 10:45:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680543911; cv=none; d=google.com; s=arc-20160816; b=yfHUtm+3Z87HHACh8gyraa6/b4YvKbwmmgPiIjpfEwJwX6FSP+IUaeG98wqLFTxPdA XDDTLsj9KMz4dnVd2H/UEhDnSv8FC8RZ50xsU3N6oWJ6xU8nC12trafXlqIFktF7Zuxv BRFfsp3VgObL7Of+t7CIJqtH2xbkVBcLSXV119aPgvWUQm7m6RNX+7yekxpC9oFwNKne CutdTr43H6QMRjYrYB8HBKkdtpzpv7SpJpZ+d6z4Zd1k7en+p/187tjisxr/wZdK6Cbj pJMgebGOG7FPk14SSIwxSpMWy0JW6j46QszEOKKnHxhN0hOBE8OttxbZ+SzZvwLoduTV RQ2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=VG1Z/PAYBy2HTkfroTsP0RD/589mq3Zv0lGIJ6IlK9M=; b=nKrEZ30HLVRe3H6eAS2b95zEfviIfQ2BCNKUzjGU479+AfIft4SRB64V3lK0iqS3d1 DtExAoqdN6+6ct8zJaWpiUUuIgSdAXw9NBtY8dNsojI5pHIO2x84eS/1fxdhkcb6zg6B Ln+WCNrpVCe5EOk4rtXvnw1OMdQW+0+TZIHbTV8YkeoFaob+TakpnD52BJKoetAD3+8g Z3XkYPBFtAnb8BlAgh7VAnGWiX/OAZsF3d/khlj1vJI6rx3/I9X62nQzRRKnMMLZdZBk evk+hgLOY7oBafbaJ0Q1E0wd4Qs76AnaYN9asjsqP/3gomiWrRTAKebq4PA1HPlWuKqR KDrg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vgiQPAQ2; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.3.135]) by smtp.gmail.com with ESMTPSA id v2-20020a056512096200b004cc5f44747dsm1871094lft.220.2023.04.03.10.36.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Apr 2023 10:36:38 -0700 (PDT) From: Konrad Dybcio Date: Mon, 03 Apr 2023 19:36:07 +0200 Subject: [PATCH 9/9] arm64: dts: qcom: qrb2210-rb1: Enable RESIN Volume Down MIME-Version: 1.0 Message-Id: <20230403-topic-rb1_qcm-v1-9-ca849b62ba07@linaro.org> References: <20230403-topic-rb1_qcm-v1-0-ca849b62ba07@linaro.org> In-Reply-To: <20230403-topic-rb1_qcm-v1-0-ca849b62ba07@linaro.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Robert Marko , Das Srinagesh Cc: Bhupesh Sharma , Vladimir Zapolskiy , Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680543384; l=675; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=nMXvXyIJXzMgyB2m7D3cD3hqNd8nV6QKFZj5jPwhtS8=; b=UELeCJ5UDxYClrydmV8W6uXF9LG3WnTrJQTtwrjy7yrh746RV8fQ/DNq7X8ou7CccZqcEydqebO8 L+NJZW20CVDoiO5tVAvyscKftX1VRfWaPHiVQq6Fke1SnULZIj6y X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762178013213700378?= X-GMAIL-MSGID: =?utf-8?q?1762178013213700378?= The RB1 has a Volume Down key (the one near the power button) connected via PMIC RESIN. Enable it. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts index 539a06456334..ef3616093289 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts @@ -40,6 +40,11 @@ key-volume-up { }; }; +&pm2250_resin { + linux,code = ; + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; };