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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id y2-20020a17090668c200b009324eea0cedsi6798876ejr.72.2023.04.03.01.53.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Apr 2023 01:53:14 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=mH4u0nvX; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D511E3858C74 for ; Mon, 3 Apr 2023 08:53:12 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D511E3858C74 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1680511992; bh=oLpmxPWVojUIP7RrsX2cHGc0VKodI7pQtrmvdGipIhM=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=mH4u0nvXENJeubbEJIrq15UHrj9GC3Qu0LiCET6lgUBhscr2z2icSrFQ5D414R8Xn yG+RwRa5MERT1a3FFud63+20yLPZ5LQX6NmlmpbsKsk7b9quHRDMSI2i2KTCSj1GNx MPW8TBQFxo+tIhLfafFU4wmZpAFr4umvyy4k2hLg= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by sourceware.org (Postfix) with ESMTPS id 5A2763858C00 for ; Mon, 3 Apr 2023 08:51:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5A2763858C00 X-IronPort-AV: E=McAfee;i="6600,9927,10668"; a="369653379" X-IronPort-AV: E=Sophos;i="5.98,314,1673942400"; d="scan'208";a="369653379" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2023 01:51:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10668"; a="716218209" X-IronPort-AV: E=Sophos;i="5.98,314,1673942400"; d="scan'208";a="716218209" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga008.jf.intel.com with ESMTP; 03 Apr 2023 01:51:26 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id BE00B1005673; Mon, 3 Apr 2023 16:51:25 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: ubizjak@gmail.com, hongtao.liu@intel.com Subject: [PATCH 1/2] Support Intel AMX-COMPLEX Date: Mon, 3 Apr 2023 16:49:22 +0800 Message-Id: <20230403084923.2904086-2-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230403084923.2904086-1-haochen.jiang@intel.com> References: <20230403084923.2904086-1-haochen.jiang@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Haochen Jiang via Gcc-patches From: "Jiang, Haochen" Reply-To: Haochen Jiang Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762144488434051169?= X-GMAIL-MSGID: =?utf-8?q?1762144545204605568?= gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect AMX-COMPLEX. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AMX_COMPLEX_SET, OPTION_MASK_ISA2_AMX_COMPLEX_UNSET): New. (ix86_handle_option): Handle -mamx-complex. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AMX_COMPLEX. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for amx-complex. * config.gcc: Add amxcomplexintrin.h. * config/i386/cpuid.h (bit_AMX_COMPLEX): New. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __AMX_COMPLEX__. * config/i386/i386-isa.def (AMX_COMPLEX): Add DEF_PTA(AMX_COMPLEX). * config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p): Handle amx-complex. * config/i386/i386.opt: Add option -mamx-complex. * config/i386/immintrin.h: Include amxcomplexintrin.h. * doc/extend.texi: Document amx-complex. * doc/invoke.texi: Document -mamx-complex. * doc/sourcebuild.texi: Document target amx-complex. * config/i386/amxcomplexintrin.h: New file. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Add -mamx-complex. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/amx-check.h: Add cpu check for AMX-COMPLEX. * gcc.target/i386/amx-helper.h: Add amx-complex support. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-12.c: Add -mamx-complex. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add amx-complex. * gcc.target/i386/sse-23.c: Ditto. * lib/target-supports.exp (check_effective_target_amx_complex): New. * gcc.target/i386/amxcomplex-asmatt-1.c: New test. * gcc.target/i386/amxcomplex-asmintel-1.c: Ditto. * gcc.target/i386/amxcomplex-cmmimfp16ps-2.c: Ditto. * gcc.target/i386/amxcomplex-cmmrlfp16ps-2.c: Ditto. --- gcc/common/config/i386/cpuinfo.h | 2 + gcc/common/config/i386/i386-common.cc | 19 +++++- gcc/common/config/i386/i386-cpuinfo.h | 1 + gcc/common/config/i386/i386-isas.h | 2 + gcc/config.gcc | 2 +- gcc/config/i386/amxcomplexintrin.h | 59 +++++++++++++++++++ gcc/config/i386/cpuid.h | 1 + gcc/config/i386/i386-c.cc | 2 + gcc/config/i386/i386-isa.def | 1 + gcc/config/i386/i386-options.cc | 4 +- gcc/config/i386/i386.opt | 4 ++ gcc/config/i386/immintrin.h | 2 + gcc/doc/extend.texi | 5 ++ gcc/doc/invoke.texi | 11 ++-- gcc/doc/sourcebuild.texi | 3 + gcc/testsuite/g++.dg/other/i386-2.C | 2 +- gcc/testsuite/g++.dg/other/i386-3.C | 2 +- gcc/testsuite/gcc.target/i386/amx-check.h | 3 + gcc/testsuite/gcc.target/i386/amx-helper.h | 4 +- .../gcc.target/i386/amxcomplex-asmatt-1.c | 15 +++++ .../gcc.target/i386/amxcomplex-asmintel-1.c | 12 ++++ .../i386/amxcomplex-cmmimfp16ps-2.c | 53 +++++++++++++++++ .../i386/amxcomplex-cmmrlfp16ps-2.c | 53 +++++++++++++++++ gcc/testsuite/gcc.target/i386/funcspec-56.inc | 2 + gcc/testsuite/gcc.target/i386/sse-12.c | 2 +- gcc/testsuite/gcc.target/i386/sse-13.c | 2 +- gcc/testsuite/gcc.target/i386/sse-14.c | 2 +- gcc/testsuite/gcc.target/i386/sse-22.c | 4 +- gcc/testsuite/gcc.target/i386/sse-23.c | 2 +- gcc/testsuite/lib/target-supports.exp | 11 ++++ 30 files changed, 270 insertions(+), 17 deletions(-) create mode 100644 gcc/config/i386/amxcomplexintrin.h create mode 100644 gcc/testsuite/gcc.target/i386/amxcomplex-asmatt-1.c create mode 100644 gcc/testsuite/gcc.target/i386/amxcomplex-asmintel-1.c create mode 100644 gcc/testsuite/gcc.target/i386/amxcomplex-cmmimfp16ps-2.c create mode 100644 gcc/testsuite/gcc.target/i386/amxcomplex-cmmrlfp16ps-2.c diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h index 5bde0cddb24..61559ed9de2 100644 --- a/gcc/common/config/i386/cpuinfo.h +++ b/gcc/common/config/i386/cpuinfo.h @@ -879,6 +879,8 @@ get_available_features (struct __processor_model *cpu_model, { if (eax & bit_AMX_FP16) set_feature (FEATURE_AMX_FP16); + if (edx & bit_AMX_COMPLEX) + set_feature (FEATURE_AMX_COMPLEX); } } diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc index 0181e06b1c5..d90c558311b 100644 --- a/gcc/common/config/i386/i386-common.cc +++ b/gcc/common/config/i386/i386-common.cc @@ -117,6 +117,8 @@ along with GCC; see the file COPYING3. If not see (OPTION_MASK_ISA2_AMX_TILE | OPTION_MASK_ISA2_AMX_FP16) #define OPTION_MASK_ISA2_PREFETCHI_SET OPTION_MASK_ISA2_PREFETCHI #define OPTION_MASK_ISA2_RAOINT_SET OPTION_MASK_ISA2_RAOINT +#define OPTION_MASK_ISA2_AMX_COMPLEX_SET \ + (OPTION_MASK_ISA2_AMX_TILE | OPTION_MASK_ISA2_AMX_COMPLEX) /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same as -msse4.2. */ @@ -282,7 +284,8 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_TSXLDTRK_UNSET OPTION_MASK_ISA2_TSXLDTRK #define OPTION_MASK_ISA2_AMX_TILE_UNSET \ (OPTION_MASK_ISA2_AMX_TILE | OPTION_MASK_ISA2_AMX_INT8_UNSET \ - | OPTION_MASK_ISA2_AMX_BF16_UNSET | OPTION_MASK_ISA2_AMX_FP16_UNSET) + | OPTION_MASK_ISA2_AMX_BF16_UNSET | OPTION_MASK_ISA2_AMX_FP16_UNSET \ + | OPTION_MASK_ISA2_AMX_COMPLEX_UNSET) #define OPTION_MASK_ISA2_AMX_INT8_UNSET OPTION_MASK_ISA2_AMX_INT8 #define OPTION_MASK_ISA2_AMX_BF16_UNSET OPTION_MASK_ISA2_AMX_BF16 #define OPTION_MASK_ISA2_UINTR_UNSET OPTION_MASK_ISA2_UINTR @@ -296,6 +299,7 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_AMX_FP16_UNSET OPTION_MASK_ISA2_AMX_FP16 #define OPTION_MASK_ISA2_PREFETCHI_UNSET OPTION_MASK_ISA2_PREFETCHI #define OPTION_MASK_ISA2_RAOINT_UNSET OPTION_MASK_ISA2_RAOINT +#define OPTION_MASK_ISA2_AMX_COMPLEX_UNSET OPTION_MASK_ISA2_AMX_COMPLEX /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same as -mno-sse4.1. */ @@ -1246,6 +1250,19 @@ ix86_handle_option (struct gcc_options *opts, } return true; + case OPT_mamx_complex: + if (value) + { + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_COMPLEX_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_COMPLEX_SET; + } + else + { + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_COMPLEX_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_COMPLEX_UNSET; + } + return true; + case OPT_mfma: if (value) { diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h index b5933b859eb..2dafbb25a49 100644 --- a/gcc/common/config/i386/i386-cpuinfo.h +++ b/gcc/common/config/i386/i386-cpuinfo.h @@ -253,6 +253,7 @@ enum processor_features FEATURE_AMX_FP16, FEATURE_PREFETCHI, FEATURE_RAOINT, + FEATURE_AMX_COMPLEX, CPU_FEATURE_MAX }; diff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/i386-isas.h index 8ed14283823..d4b0b23b417 100644 --- a/gcc/common/config/i386/i386-isas.h +++ b/gcc/common/config/i386/i386-isas.h @@ -184,4 +184,6 @@ ISA_NAMES_TABLE_START ISA_NAMES_TABLE_ENTRY("amx-fp16", FEATURE_AMX_FP16, P_NONE, "-mamx-fp16") ISA_NAMES_TABLE_ENTRY("prefetchi", FEATURE_PREFETCHI, P_NONE, "-mprefetchi") ISA_NAMES_TABLE_ENTRY("raoint", FEATURE_RAOINT, P_NONE, "-mraoint") + ISA_NAMES_TABLE_ENTRY("amx-complex", FEATURE_AMX_COMPLEX, + P_NONE, "-mamx-complex") ISA_NAMES_TABLE_END diff --git a/gcc/config.gcc b/gcc/config.gcc index 629d324b5ef..6fd1594480a 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -435,7 +435,7 @@ i[34567]86-*-* | x86_64-*-*) mwaitintrin.h avx512fp16intrin.h avx512fp16vlintrin.h avxifmaintrin.h avxvnniint8intrin.h avxneconvertintrin.h cmpccxaddintrin.h amxfp16intrin.h prfchiintrin.h - raointintrin.h" + raointintrin.h amxcomplexintrin.h" ;; ia64-*-*) extra_headers=ia64intrin.h diff --git a/gcc/config/i386/amxcomplexintrin.h b/gcc/config/i386/amxcomplexintrin.h new file mode 100644 index 00000000000..6ea1eca0400 --- /dev/null +++ b/gcc/config/i386/amxcomplexintrin.h @@ -0,0 +1,59 @@ +/* Copyright (C) 2023 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +#if !defined _IMMINTRIN_H_INCLUDED +#error "Never use directly; include instead." +#endif + +#ifndef _AMXCOMPLEXINTRIN_H_INCLUDED +#define _AMXCOMPLEXINTRIN_H_INCLUDED + +#if !defined(__AMX_COMPLEX__) +#pragma GCC push_options +#pragma GCC target("amx-complex") +#define __DISABLE_AMX_COMPLEX__ +#endif /* __AMX_COMPLEX__ */ + +#if defined(__x86_64__) +#define _tile_cmmimfp16ps_internal(src1_dst,src2,src3) \ + __asm__ volatile\ + ("{tcmmimfp16ps\t%%tmm"#src3", %%tmm"#src2", %%tmm"#src1_dst"|tcmmimfp16ps\t%%tmm"#src1_dst", %%tmm"#src2", %%tmm"#src3"}" ::) + +#define _tile_cmmrlfp16ps_internal(src1_dst,src2,src3) \ + __asm__ volatile\ + ("{tcmmrlfp16ps\t%%tmm"#src3", %%tmm"#src2", %%tmm"#src1_dst"|tcmmrlfp16ps\t%%tmm"#src1_dst", %%tmm"#src2", %%tmm"#src3"}" ::) + +#define _tile_cmmimfp16ps(src1_dst,src2,src3) \ + _tile_cmmimfp16ps_internal (src1_dst, src2, src3) + +#define _tile_cmmrlfp16ps(src1_dst,src2,src3) \ + _tile_cmmrlfp16ps_internal (src1_dst, src2, src3) + +#endif + +#ifdef __DISABLE_AMX_COMPLEX__ +#undef __DISABLE_AMX_COMPLEX__ +#pragma GCC pop_options +#endif /* __DISABLE_AMX_COMPLEX__ */ + +#endif /* _AMXCOMPLEXINTRIN_H_INCLUDED */ diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h index be162dd8c78..e1d6d2ff77c 100644 --- a/gcc/config/i386/cpuid.h +++ b/gcc/config/i386/cpuid.h @@ -141,6 +141,7 @@ #define bit_AMX_BF16 (1 << 22) #define bit_AMX_TILE (1 << 24) #define bit_AMX_INT8 (1 << 25) +#define bit_AMX_COMPLEX (1 << 8) /* Extended State Enumeration Sub-leaf (%eax == 0xd, %ecx == 1) */ #define bit_XSAVEOPT (1 << 0) diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc index 88689d165e6..e7bd7cc706c 100644 --- a/gcc/config/i386/i386-c.cc +++ b/gcc/config/i386/i386-c.cc @@ -675,6 +675,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__PREFETCHI__"); if (isa_flag2 & OPTION_MASK_ISA2_RAOINT) def_or_undef (parse_in, "__RAOINT__"); + if (isa_flag2 & OPTION_MASK_ISA2_AMX_COMPLEX) + def_or_undef (parse_in, "__AMX_COMPLEX__"); if (TARGET_IAMCU) { def_or_undef (parse_in, "__iamcu"); diff --git a/gcc/config/i386/i386-isa.def b/gcc/config/i386/i386-isa.def index 5181a0db18e..0634c6f5bac 100644 --- a/gcc/config/i386/i386-isa.def +++ b/gcc/config/i386/i386-isa.def @@ -116,3 +116,4 @@ DEF_PTA(CMPCCXADD) DEF_PTA(AMX_FP16) DEF_PTA(PREFETCHI) DEF_PTA(RAOINT) +DEF_PTA(AMX_COMPLEX) diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc index 80fe655cac5..2cb0bddcd35 100644 --- a/gcc/config/i386/i386-options.cc +++ b/gcc/config/i386/i386-options.cc @@ -238,7 +238,8 @@ static struct ix86_target_opts isa2_opts[] = { "-mcmpccxadd", OPTION_MASK_ISA2_CMPCCXADD }, { "-mamx-fp16", OPTION_MASK_ISA2_AMX_FP16 }, { "-mprefetchi", OPTION_MASK_ISA2_PREFETCHI }, - { "-mraoint", OPTION_MASK_ISA2_RAOINT } + { "-mraoint", OPTION_MASK_ISA2_RAOINT }, + { "-mamx-complex", OPTION_MASK_ISA2_AMX_COMPLEX } }; static struct ix86_target_opts isa_opts[] = { @@ -1089,6 +1090,7 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[], IX86_ATTR_ISA ("amx-fp16", OPT_mamx_fp16), IX86_ATTR_ISA ("prefetchi", OPT_mprefetchi), IX86_ATTR_ISA ("raoint", OPT_mraoint), + IX86_ATTR_ISA ("amx-complex", OPT_mamx_complex), /* enum options */ IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_), diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index 94fdd639ff1..d74f6b1f8fc 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -1274,3 +1274,7 @@ Enum(lam_type) String(u48) Value(lam_u48) EnumValue Enum(lam_type) String(u57) Value(lam_u57) + +mamx-complex +Target Mask(ISA2_AMX_COMPLEX) Var(ix86_isa_flags2) Save +Support AMX-COMPLEX built-in functions and code generation. diff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h index 740de63e5d5..b220d871942 100644 --- a/gcc/config/i386/immintrin.h +++ b/gcc/config/i386/immintrin.h @@ -132,6 +132,8 @@ #include +#include + #include #include diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 3adb67aa47a..b2a1643c53f 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -7069,6 +7069,11 @@ Enable/disable the generation of the PREFETCHI instructions. @itemx no-raoint Enable/disable the generation of the RAOINT instructions. +@cindex @code{target("amx-complex")} function attribute, x86 +@item amx-complex +@itemx no-amx-complex +Enable/disable the generation of the AMX-COMPLEX instructions. + @cindex @code{target("cld")} function attribute, x86 @item cld @itemx no-cld diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index def2df4584b..262db898fe8 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1429,7 +1429,7 @@ See RS/6000 and PowerPC Options. -mrdseed -msgx -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -muintr -mhreset -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 --mprefetchi -mraoint +-mprefetchi -mraoint -mamx-complex -mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops -minline-stringops-dynamically -mstringop-strategy=@var{alg} -mkl -mwidekl @@ -33333,6 +33333,9 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}. @need 200 @opindex mraoint @itemx -mraoint +@need 200 +@opindex mamx-complex +@itemx -mamx-complex These switches enable the use of instructions in the MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4A, SSE4.1, SSE4.2, AVX, AVX2, AVX512F, AVX512PF, AVX512ER, AVX512CD, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, SHA, @@ -33343,9 +33346,9 @@ XSAVEOPT, XSAVEC, XSAVES, RTM, HLE, TBM, MWAITX, CLZERO, PKU, AVX512VBMI2, GFNI, VAES, WAITPKG, VPCLMULQDQ, AVX512BITALG, MOVDIRI, MOVDIR64B, AVX512BF16, ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, SERIALIZE, UINTR, HRESET, AMXTILE, AMXINT8, AMXBF16, KL, WIDEKL, AVXVNNI, AVX512-FP16, -AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AMX-FP16, PREFETCHI, RAOINT or -CLDEMOTE extended instruction sets. Each has a corresponding @option{-mno-} -option to disable use of these instructions. +AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AMX-FP16, PREFETCHI, RAOINT, +AMX-COMPLEX or CLDEMOTE extended instruction sets. Each has a corresponding +@option{-mno-} option to disable use of these instructions. These extensions are also available as built-in functions: see @ref{x86 Built-in Functions}, for details of the functions enabled and diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index 8f1c7b65d69..204bf245b26 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -2514,6 +2514,9 @@ Target supports the execution of @code{amx-int8} instructions. @item amx_bf16 Target supports the execution of @code{amx-bf16} instructions. +@item amx_complex +Target supports the execution of @code{amx-complex} instructions. + @item amx_fp16 Target supports the execution of @code{amx-fp16} instructions. diff --git a/gcc/testsuite/g++.dg/other/i386-2.C b/gcc/testsuite/g++.dg/other/i386-2.C index fc910cec78a..6fe07e18fc6 100644 --- a/gcc/testsuite/g++.dg/other/i386-2.C +++ b/gcc/testsuite/g++.dg/other/i386-2.C @@ -1,5 +1,5 @@ /* { dg-do compile { target i?86-*-* x86_64-*-* } } */ -/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint" } */ +/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex" } */ /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h, xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h, diff --git a/gcc/testsuite/g++.dg/other/i386-3.C b/gcc/testsuite/g++.dg/other/i386-3.C index 64741b11685..55c81677300 100644 --- a/gcc/testsuite/g++.dg/other/i386-3.C +++ b/gcc/testsuite/g++.dg/other/i386-3.C @@ -1,5 +1,5 @@ /* { dg-do compile { target i?86-*-* x86_64-*-* } } */ -/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint" } */ +/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex" } */ /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h, xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h, diff --git a/gcc/testsuite/gcc.target/i386/amx-check.h b/gcc/testsuite/gcc.target/i386/amx-check.h index 27dd37bf993..f1a04cf1f3c 100644 --- a/gcc/testsuite/gcc.target/i386/amx-check.h +++ b/gcc/testsuite/gcc.target/i386/amx-check.h @@ -216,6 +216,9 @@ main () #ifdef AMX_FP16 && __builtin_cpu_supports ("amx-fp16") #endif +#ifdef AMX_COMPLEX + && __builtin_cpu_supports ("amx-complex") +#endif #ifdef __linux__ && request_perm_xtile_data () #endif diff --git a/gcc/testsuite/gcc.target/i386/amx-helper.h b/gcc/testsuite/gcc.target/i386/amx-helper.h index fe24d7067a5..6ed9f5eb30e 100644 --- a/gcc/testsuite/gcc.target/i386/amx-helper.h +++ b/gcc/testsuite/gcc.target/i386/amx-helper.h @@ -1,6 +1,6 @@ #ifndef AMX_HELPER_H_INCLUDED #define AMX_HELPER_H_INCLUDED -#if defined(AMX_FP16) +#if defined(AMX_FP16) || defined(AMX_COMPLEX) #include #include #endif @@ -12,7 +12,7 @@ typedef union uint16_t u; } union16f_uw; -#if defined(AMX_FP16) +#if defined(AMX_FP16) || defined(AMX_COMPLEX) /* Transformation functions between fp16/float */ static uint16_t make_f32_fp16 (float f) { diff --git a/gcc/testsuite/gcc.target/i386/amxcomplex-asmatt-1.c b/gcc/testsuite/gcc.target/i386/amxcomplex-asmatt-1.c new file mode 100644 index 00000000000..b6745e34b8b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/amxcomplex-asmatt-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mamx-complex" } */ +/* { dg-final { scan-assembler "tcmmimfp16ps\[ \\t]+\[^\n\]*%tmm3+\[^\n\]*%tmm2+\[^\n\]*%tmm1" } } */ +/* { dg-final { scan-assembler "tcmmrlfp16ps\[ \\t]+\[^\n\]*%tmm3+\[^\n\]*%tmm2+\[^\n\]*%tmm1" } } */ +#include + +#define TMM1 1 +#define TMM2 2 +#define TMM3 3 + +void TEST() +{ + _tile_cmmimfp16ps (TMM1, TMM2, TMM3); + _tile_cmmrlfp16ps (TMM1, TMM2, TMM3); +} diff --git a/gcc/testsuite/gcc.target/i386/amxcomplex-asmintel-1.c b/gcc/testsuite/gcc.target/i386/amxcomplex-asmintel-1.c new file mode 100644 index 00000000000..305465e8860 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/amxcomplex-asmintel-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-require-effective-target masm_intel } */ +/* { dg-options "-O2 -mamx-complex -masm=intel" } */ +/* { dg-final { scan-assembler "tcmmimfp16ps\[ \\t]+\[^\n\]*%tmm1+\[^\n\]*%tmm2+\[^\n\]*%tmm3" } } */ +/* { dg-final { scan-assembler "tcmmrlfp16ps\[ \\t]+\[^\n\]*%tmm1+\[^\n\]*%tmm2+\[^\n\]*%tmm3" } } */ +#include + +void TEST() +{ + _tile_cmmimfp16ps (1, 2, 3); + _tile_cmmrlfp16ps (1, 2, 3); +} diff --git a/gcc/testsuite/gcc.target/i386/amxcomplex-cmmimfp16ps-2.c b/gcc/testsuite/gcc.target/i386/amxcomplex-cmmimfp16ps-2.c new file mode 100644 index 00000000000..6e3762c9f6f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/amxcomplex-cmmimfp16ps-2.c @@ -0,0 +1,53 @@ +/* { dg-do run { target { ! ia32 } } } */ +/* { dg-require-effective-target amx_complex } */ +/* { dg-require-effective-target avx512fp16 } */ +/* { dg-options "-O2 -mamx-complex -mavx512fp16" } */ +#define AMX_COMPLEX +#define DO_TEST test_amx_complex_cmmimfp16ps +void test_amx_complex_cmmimfp16ps (); +#include "amx-helper.h" + +void calc_matrix_cmmimfp16ps (__tile *dst, __tile *src1, __tile *src2) +{ + uint16_t *src1_buf = (uint16_t *) src1->buf; + uint16_t *src2_buf = (uint16_t *) src2->buf; + float *dst_buf = (float *) dst->buf; + + int M = src1->rows; + int N = src1->colsb / 4; + int K = src2->colsb / 4; + int i, j, k, t; + + for (i = 0; i < M; i++) + for (j = 0; j < N; j++) + for (k = 0; k < K; k++) + for (t = 0; t < 2; t+=2) + dst_buf[i * N + k] += + (make_fp16_f32(src1_buf[i * 2 * N + 2 * j + t]) * + make_fp16_f32(src2_buf[j * 2 * K + 2 * k + t + 1])) + + (make_fp16_f32(src1_buf[i * 2 * N + 2 * j + t + 1]) * + make_fp16_f32(src2_buf[j * 2 * K + 2 * k + t])); +} + +void test_amx_complex_cmmimfp16ps () +{ + __tilecfg_u cfg; + __tile dst, dst_ref, src1, src2; + uint8_t tmp_dst_buf[1024], tmp_dst_zero_buf[1024]; + + init_fp16_max_tile_buffer (tmp_dst_buf); + init_fp16_max_tile_zero_buffer (tmp_dst_zero_buf); + + init_tile_config (&cfg); + init_tile_reg_and_src_with_buffer (1, dst, tmp_dst_zero_buf); + init_tile_reg_and_src_with_buffer (2, src1, tmp_dst_buf); + init_tile_reg_and_src_with_buffer (3, src2, tmp_dst_buf); + + calc_matrix_cmmimfp16ps (&dst, &src1, &src2); + + _tile_cmmimfp16ps (1, 2, 3); + _tile_stored (1, dst_ref.buf, _STRIDE); + + if (!check_tile_register (&dst_ref, &dst)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/amxcomplex-cmmrlfp16ps-2.c b/gcc/testsuite/gcc.target/i386/amxcomplex-cmmrlfp16ps-2.c new file mode 100644 index 00000000000..15940708a02 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/amxcomplex-cmmrlfp16ps-2.c @@ -0,0 +1,53 @@ +/* { dg-do run { target { ! ia32 } } } */ +/* { dg-require-effective-target amx_complex } */ +/* { dg-require-effective-target avx512fp16 } */ +/* { dg-options "-O2 -mamx-complex -mavx512fp16" } */ +#define AMX_COMPLEX +#define DO_TEST test_amx_complex_cmmrlfp16ps +void test_amx_complex_cmmrlfp16ps(); +#include "amx-helper.h" + +void calc_matrix_cmmrlfp16ps (__tile *dst, __tile *src1, __tile *src2) +{ + uint16_t *src1_buf = (uint16_t *) src1->buf; + uint16_t *src2_buf = (uint16_t *) src2->buf; + float *dst_buf = (float *) dst->buf; + + int M = src1->rows; + int N = src1->colsb / 4; + int K = src2->colsb / 4; + int i, j, k, t; + + for (i = 0; i < M; i++) + for (j = 0; j < N; j++) + for (k = 0; k < K; k++) + for (t = 0; t < 2; t+=2) + dst_buf[i * N + k] += + (make_fp16_f32 (src1_buf[i * 2 * N + 2 * j + t]) * + make_fp16_f32 (src2_buf[j * 2 * K + 2 * k + t])) - + (make_fp16_f32 (src1_buf[i * 2 * N + 2 * j + t + 1]) * + make_fp16_f32 (src2_buf[j * 2 * K + 2 * k + t + 1])); +} + +void test_amx_complex_cmmrlfp16ps () +{ + __tilecfg_u cfg; + __tile dst, dst_ref, src1, src2; + uint8_t tmp_dst_buf[1024], tmp_dst_zero_buf[1024]; + + init_fp16_max_tile_buffer (tmp_dst_buf); + init_fp16_max_tile_zero_buffer (tmp_dst_zero_buf); + + init_tile_config (&cfg); + init_tile_reg_and_src_with_buffer (1, dst, tmp_dst_zero_buf); + init_tile_reg_and_src_with_buffer (2, src1, tmp_dst_buf); + init_tile_reg_and_src_with_buffer (3, src2, tmp_dst_buf); + + calc_matrix_cmmrlfp16ps (&dst, &src1, &src2); + + _tile_cmmrlfp16ps (1, 2, 3); + _tile_stored (1, dst_ref.buf, _STRIDE); + + if (!check_tile_register (&dst_ref, &dst)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc b/gcc/testsuite/gcc.target/i386/funcspec-56.inc index 37802307bcf..cf2899f9c32 100644 --- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc +++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc @@ -87,6 +87,7 @@ extern void test_cmpccxadd (void) __attribute__((__target__("cmpccxadd"))); extern void test_amx_fp16 (void) __attribute__((__target__("amx-fp16"))); extern void test_prefetchi (void) __attribute__((__target__("prefetchi"))); extern void test_raoint (void) __attribute__((__target__("raoint"))); +extern void test_amx_complex (void) __attribute__((__target__("amx-complex"))); extern void test_no_sgx (void) __attribute__((__target__("no-sgx"))); extern void test_no_avx5124fmaps(void) __attribute__((__target__("no-avx5124fmaps"))); @@ -175,6 +176,7 @@ extern void test_no_cmpccxadd (void) __attribute__((__target__("no-cm extern void test_no_amx_fp16 (void) __attribute__((__target__("no-amx-fp16"))); extern void test_no_prefetchi (void) __attribute__((__target__("no-prefetchi"))); extern void test_no_raoint (void) __attribute__((__target__("no-raoint"))); +extern void test_no_amx_complex (void) __attribute__((__target__("no-amx-complex"))); extern void test_arch_nocona (void) __attribute__((__target__("arch=nocona"))); extern void test_arch_core2 (void) __attribute__((__target__("arch=core2"))); diff --git a/gcc/testsuite/gcc.target/i386/sse-12.c b/gcc/testsuite/gcc.target/i386/sse-12.c index 3210a5c18c2..ae4ffd1975f 100644 --- a/gcc/testsuite/gcc.target/i386/sse-12.c +++ b/gcc/testsuite/gcc.target/i386/sse-12.c @@ -3,7 +3,7 @@ popcntintrin.h gfniintrin.h and mm_malloc.h are usable with -O -std=c89 -pedantic-errors. */ /* { dg-do compile } */ -/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint" } */ +/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex" } */ #include diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c index 66423ec3c0f..f046a68ddbb 100644 --- a/gcc/testsuite/gcc.target/i386/sse-13.c +++ b/gcc/testsuite/gcc.target/i386/sse-13.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint" } */ +/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex" } */ /* { dg-add-options bind_pic_locally } */ #include diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c index 2953318ff66..05322f7e914 100644 --- a/gcc/testsuite/gcc.target/i386/sse-14.c +++ b/gcc/testsuite/gcc.target/i386/sse-14.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -mavx512vl -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint" } */ +/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -mavx512vl -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex" } */ /* { dg-add-options bind_pic_locally } */ #include diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c index f600bb544b2..53c38b70241 100644 --- a/gcc/testsuite/gcc.target/i386/sse-22.c +++ b/gcc/testsuite/gcc.target/i386/sse-22.c @@ -103,7 +103,7 @@ #ifndef DIFFERENT_PRAGMAS -#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,avx512vl,avx512bw,avx512dq,avx512vbmi,avx512vbmi2,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint") +#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,avx512vl,avx512bw,avx512dq,avx512vbmi,avx512vbmi2,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex") #endif /* Following intrinsics require immediate arguments. They @@ -220,7 +220,7 @@ test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int, 1) /* immintrin.h (AVX/AVX2/RDRND/FSGSBASE/F16C/RTM/AVX512F/SHA) */ #ifdef DIFFERENT_PRAGMAS -#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,avx512cd,avx512pf,sha,avx512vl,avx512bw,avx512dq,avx512ifma,avx512vbmi,avx512vbmi2,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint") +#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,avx512cd,avx512pf,sha,avx512vl,avx512bw,avx512dq,avx512ifma,avx512vbmi,avx512vbmi2,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex") #endif #include test_1 (_cvtss_sh, unsigned short, float, 1) diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c index 37cc2fd50df..50bf85a3392 100644 --- a/gcc/testsuite/gcc.target/i386/sse-23.c +++ b/gcc/testsuite/gcc.target/i386/sse-23.c @@ -847,6 +847,6 @@ #define __builtin_ia32_cmpccxadd(A, B, C, D) __builtin_ia32_cmpccxadd(A, B, C, 1) #define __builtin_ia32_cmpccxadd64(A, B, C, D) __builtin_ia32_cmpccxadd64(A, B, C, 1) -#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2,vpclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint") +#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2,vpclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,amx-complex") #include diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 1d6cc6f8d88..ad68af51f91 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -9750,6 +9750,17 @@ proc check_effective_target_raoint { } { } "-mraoint" ] } +# Return 1 if amx-complex instructions can be compiled. +proc check_effective_target_amx_complex { } { + return [check_no_compiler_messages amx_complex object { + void + foo () + { + __asm__ volatile ("tcmmimfp16ps\t%%tmm1, %%tmm2, %%tmm3" ::); + } + } "-mamx-complex" ] +} + # Return 1 if sse instructions can be compiled. proc check_effective_target_sse { } { return [check_no_compiler_messages sse object { From patchwork Mon Apr 3 08:49:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jiang, Haochen" X-Patchwork-Id: 78414 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2153076vqo; Mon, 3 Apr 2023 01:52:22 -0700 (PDT) X-Google-Smtp-Source: AKy350bqJpbdDVCtW4IyTbonIznfUdsaIOAbh/jOqoxtZUgIPPS1cf7TBZp9Jq33v20rQ0hah0SW X-Received: by 2002:a17:906:6710:b0:8af:22b4:99d2 with SMTP id a16-20020a170906671000b008af22b499d2mr16669754ejp.5.1680511942768; Mon, 03 Apr 2023 01:52:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680511942; cv=none; d=google.com; s=arc-20160816; b=u2T8Cu6RzgLhpX2wFYIGXYTNdQdRFtrXyNUoPiwSi588m3VzQHWLzni0IGd2J37Lko f5ICicvu0j5WNdNqqYsUmlBnDzuPhRH7G+stlTyDL6BH9HTcv6ZS2MdBQezx8/3ZWZR7 7GSldynKSC/ap6r5xCmsxbOffGBxA6gVs8VYnigUvMOEmT9hcc2jYKMKG8hAYEgUaQMj e9xhC5imy+oBZEsxZQlnd+AoVfPkiy694Xd/Av+pXSGY8CLz4NX59Bu/hAw8Jwa94/lL 3tuOr3Qn+fbuuh1aORvsYP/sUgAgN1igdVBOg40MmG39JXTlvinHWhoGmiwam0Q9KoJp 4azQ== ARC-Message-Signature: i=1; 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[8.43.85.97]) by mx.google.com with ESMTPS id l4-20020aa7d944000000b005002aad5850si5193685eds.589.2023.04.03.01.52.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Apr 2023 01:52:22 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=HhlTfMJx; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D9C623858404 for ; Mon, 3 Apr 2023 08:52:13 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D9C623858404 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1680511933; bh=BRYrSmRLjw8i7LrM2FiRcEeqXyz+VZsqCehYRwVhLfM=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=HhlTfMJxjEoPbeoavHlpDit0Iru69KIPbBLsCmNYoxsIO+wSeGn1h1d1WUrer9b6f dG7z6N3GpoU0gDYXpAr3WxE8N1lp3aynLkB0Rd1rz0BZA4tuzwG71nuyTCnKudCLEi zsJ8p2Z+GfRoGadTXawJxVK9xQ1BcgmqUX2BAb1E= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by sourceware.org (Postfix) with ESMTPS id EDF773858C5E for ; Mon, 3 Apr 2023 08:51:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EDF773858C5E X-IronPort-AV: E=McAfee;i="6600,9927,10668"; a="369653360" X-IronPort-AV: E=Sophos;i="5.98,314,1673942400"; d="scan'208";a="369653360" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2023 01:51:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10668"; a="716218188" X-IronPort-AV: E=Sophos;i="5.98,314,1673942400"; d="scan'208";a="716218188" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga008.jf.intel.com with ESMTP; 03 Apr 2023 01:51:26 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id C2BBF1005676; Mon, 3 Apr 2023 16:51:25 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: ubizjak@gmail.com, hongtao.liu@intel.com Subject: [PATCH 2/2] i386: Add AMX-COMPLEX to Granite Rapids Date: Mon, 3 Apr 2023 16:49:23 +0800 Message-Id: <20230403084923.2904086-3-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230403084923.2904086-1-haochen.jiang@intel.com> References: <20230403084923.2904086-1-haochen.jiang@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Haochen Jiang via Gcc-patches From: "Jiang, Haochen" Reply-To: Haochen Jiang Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762144490787213759?= X-GMAIL-MSGID: =?utf-8?q?1762144490787213759?= gcc/Changelog: * config/gcc/i386.h (PTA_GRANITERAPIDS): Add PTA_AMX_COMPLEX. --- gcc/config/i386/i386.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index dd9391c492b..1da6dce8e0b 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -2361,7 +2361,7 @@ constexpr wide_int_bitmask PTA_ALDERLAKE = PTA_TREMONT | PTA_ADX | PTA_AVX constexpr wide_int_bitmask PTA_SIERRAFOREST = PTA_ALDERLAKE | PTA_AVXIFMA | PTA_AVXVNNIINT8 | PTA_AVXNECONVERT | PTA_CMPCCXADD; constexpr wide_int_bitmask PTA_GRANITERAPIDS = PTA_SAPPHIRERAPIDS | PTA_AMX_FP16 - | PTA_PREFETCHI; + | PTA_PREFETCHI | PTA_AMX_COMPLEX; constexpr wide_int_bitmask PTA_GRANDRIDGE = PTA_SIERRAFOREST | PTA_RAOINT; constexpr wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ;