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Peter Anvin" , Michael Kelley Subject: [PATCH v5 01/15] x86/mtrr: split off physical address size calculation Date: Sat, 1 Apr 2023 08:36:38 +0200 Message-Id: <20230401063652.23522-2-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230401063652.23522-1-jgross@suse.com> References: <20230401063652.23522-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761956439527578358?= X-GMAIL-MSGID: =?utf-8?q?1761956439527578358?= Move the calculation of the physical address size in mtrr_bp_init() into a helper function. This will be needed later. Do only the pure code movement without optimizing it. Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V2: - new patch V3: - only move code, split off optimizations (Boris Petkov) --- arch/x86/kernel/cpu/mtrr/mtrr.c | 57 ++++++++++++++++++--------------- 1 file changed, 32 insertions(+), 25 deletions(-) diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtrr.c index 783f3210d582..8310bdb111d0 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -620,22 +620,14 @@ static struct syscore_ops mtrr_syscore_ops = { int __initdata changed_by_mtrr_cleanup; #define SIZE_OR_MASK_BITS(n) (~((1ULL << ((n) - PAGE_SHIFT)) - 1)) -/** - * mtrr_bp_init - initialize mtrrs on the boot CPU - * - * This needs to be called early; before any of the other CPUs are - * initialized (i.e. before smp_init()). - * - */ -void __init mtrr_bp_init(void) + +static unsigned int __init mtrr_calc_physbits(bool generic) { - const char *why = "(not available)"; - u32 phys_addr; + unsigned int phys_addr; phys_addr = 32; - if (boot_cpu_has(X86_FEATURE_MTRR)) { - mtrr_if = &generic_mtrr_ops; + if (generic) { size_or_mask = SIZE_OR_MASK_BITS(36); size_and_mask = 0x00f00000; phys_addr = 36; @@ -667,29 +659,44 @@ void __init mtrr_bp_init(void) size_and_mask = 0; phys_addr = 32; } + } else { + size_or_mask = SIZE_OR_MASK_BITS(32); + size_and_mask = 0; + } + + return phys_addr; +} + +/** + * mtrr_bp_init - initialize mtrrs on the boot CPU + * + * This needs to be called early; before any of the other CPUs are + * initialized (i.e. before smp_init()). + * + */ +void __init mtrr_bp_init(void) +{ + const char *why = "(not available)"; + unsigned int phys_addr; + + phys_addr = mtrr_calc_physbits(boot_cpu_has(X86_FEATURE_MTRR)); + + if (boot_cpu_has(X86_FEATURE_MTRR)) { + mtrr_if = &generic_mtrr_ops; } else { switch (boot_cpu_data.x86_vendor) { case X86_VENDOR_AMD: - if (cpu_feature_enabled(X86_FEATURE_K6_MTRR)) { - /* Pre-Athlon (K6) AMD CPU MTRRs */ + /* Pre-Athlon (K6) AMD CPU MTRRs */ + if (cpu_feature_enabled(X86_FEATURE_K6_MTRR)) mtrr_if = &amd_mtrr_ops; - size_or_mask = SIZE_OR_MASK_BITS(32); - size_and_mask = 0; - } break; case X86_VENDOR_CENTAUR: - if (cpu_feature_enabled(X86_FEATURE_CENTAUR_MCR)) { + if (cpu_feature_enabled(X86_FEATURE_CENTAUR_MCR)) mtrr_if = ¢aur_mtrr_ops; - size_or_mask = SIZE_OR_MASK_BITS(32); - size_and_mask = 0; - } break; case X86_VENDOR_CYRIX: - if (cpu_feature_enabled(X86_FEATURE_CYRIX_ARR)) { + if (cpu_feature_enabled(X86_FEATURE_CYRIX_ARR)) mtrr_if = &cyrix_mtrr_ops; - size_or_mask = SIZE_OR_MASK_BITS(32); - size_and_mask = 0; - } break; default: break; From patchwork Sat Apr 1 06:36:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 78069 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1078331vqo; Sat, 1 Apr 2023 00:51:10 -0700 (PDT) X-Google-Smtp-Source: AKy350ZnpFCQjMrPhs87c0DY+GkInnR+/xtnEDCNKZCW3kTf+pto8brsKKM/xyHkp5J+f18EluHM X-Received: by 2002:a17:906:31d0:b0:8f4:809e:faee with SMTP id f16-20020a17090631d000b008f4809efaeemr11374529ejf.19.1680335470627; Sat, 01 Apr 2023 00:51:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680335470; cv=none; d=google.com; s=arc-20160816; b=DhaLbS9vhEnMvsUUs0EQbraXI9DBwh4vmG4v9JRbRpli2yWgrRMh7Mm7Hoh9OAET5o 3WIa3b3n0IkwMXlvOsJ0QcxTVFOiQMyi4wSy1tVCIm+b6agiGOyOSqGYKDWAdDaoDasY olAe+fDqtU5vBZirCXuM9Ct+JHkHtP2EHljMBSdflXkQIMDoPqBqsckur4i60/BMvGgS JJ7fLZH7BmubFsnm8MRz8MIcMYuEwE89YE08wVqyxix87gHvqUBVFNw7PJj5D+JuBeE9 v2n5weWyRqPde78aQndY3GWhah5O2C/HngYNrXaiuwxi90JSahy9P2t7JntezTnJ8lCp qouQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=7+r4owlpRl68SnHTZez3F/1Q0HJdHfyMYOiLaES+G08=; b=RXvR2IUsiLt2XQuc+jjUV8IQadqSg0EQR7DSvo7bpN5kG5WJPrYlRFNGnXaIglJihm DmU6BBwSEAX2vfGr26yizEfWp/rT0jO3nLL3OYi6IJswfEFgqcUzG5tNtJn+XurKE9Tc h1MtXL2Z256gDgo9v3iKJ16Rd95Eh/qEtx5wtqY0sfRJn9Kr1EOzHeWoI0EUD2zY5JbC ARJtHs4k3bIAhPRmH46ugjmDJ3/1tD2+Gd778gmzY3mlWXngE0Xgp0NGF6gABqDPd8Po zthIOytIPqMQATQWCLgjONS3le5/051ZIfSc8EgwBNG+7Z1O6cLqEWJXfvcLmx5ysJfA r3ZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@suse.com header.s=susede1 header.b=IeBqVbmI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=suse.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" , Michael Kelley Subject: [PATCH v5 02/15] x86/mtrr: optimize mtrr_calc_physbits() Date: Sat, 1 Apr 2023 08:36:39 +0200 Message-Id: <20230401063652.23522-3-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230401063652.23522-1-jgross@suse.com> References: <20230401063652.23522-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761959446557745825?= X-GMAIL-MSGID: =?utf-8?q?1761959446557745825?= Optimize mtrr_calc_physbits() for better readability. Drop a stale comment, as reality has made it obsolete. [ bp: - s/mtrr/MTRR/ - s/boot_cpu_has/cpu_feature_enabled/ - use GENMASK_ULL - simplify. ] Signed-off-by: Juergen Gross Signed-off-by: Borislav Petkov (AMD) Tested-by: Michael Kelley --- V3: - new patch, split off from previous patch (Boris Petkov) V5: - add some modifications by Boris Petkov --- arch/x86/kernel/cpu/mtrr/mtrr.c | 27 +++++++-------------------- 1 file changed, 7 insertions(+), 20 deletions(-) diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtrr.c index 8310bdb111d0..ce0b82209ad3 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -619,8 +619,6 @@ static struct syscore_ops mtrr_syscore_ops = { int __initdata changed_by_mtrr_cleanup; -#define SIZE_OR_MASK_BITS(n) (~((1ULL << ((n) - PAGE_SHIFT)) - 1)) - static unsigned int __init mtrr_calc_physbits(bool generic) { unsigned int phys_addr; @@ -628,15 +626,8 @@ static unsigned int __init mtrr_calc_physbits(bool generic) phys_addr = 32; if (generic) { - size_or_mask = SIZE_OR_MASK_BITS(36); - size_and_mask = 0x00f00000; phys_addr = 36; - /* - * This is an AMD specific MSR, but we assume(hope?) that - * Intel will implement it too when they extend the address - * bus of the Xeon. - */ if (cpuid_eax(0x80000000) >= 0x80000008) { phys_addr = cpuid_eax(0x80000008) & 0xff; /* CPUID workaround for Intel 0F33/0F34 CPU */ @@ -647,41 +638,37 @@ static unsigned int __init mtrr_calc_physbits(bool generic) boot_cpu_data.x86_stepping == 0x4)) phys_addr = 36; - size_or_mask = SIZE_OR_MASK_BITS(phys_addr); - size_and_mask = ~size_or_mask & 0xfffff00000ULL; } else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR && boot_cpu_data.x86 == 6) { /* * VIA C* family have Intel style MTRRs, * but don't support PAE */ - size_or_mask = SIZE_OR_MASK_BITS(32); - size_and_mask = 0; phys_addr = 32; } - } else { - size_or_mask = SIZE_OR_MASK_BITS(32); - size_and_mask = 0; } + size_or_mask = ~GENMASK_ULL(phys_addr - PAGE_SHIFT - 1, 0); + size_and_mask = ~size_or_mask & GENMASK_ULL(39, 20); + return phys_addr; } /** - * mtrr_bp_init - initialize mtrrs on the boot CPU + * mtrr_bp_init - initialize MTRRs on the boot CPU * * This needs to be called early; before any of the other CPUs are * initialized (i.e. before smp_init()). - * */ void __init mtrr_bp_init(void) { + bool generic_mtrrs = cpu_feature_enabled(X86_FEATURE_MTRR); const char *why = "(not available)"; unsigned int phys_addr; - phys_addr = mtrr_calc_physbits(boot_cpu_has(X86_FEATURE_MTRR)); + phys_addr = mtrr_calc_physbits(generic_mtrrs); - if (boot_cpu_has(X86_FEATURE_MTRR)) { + if (generic_mtrrs) { mtrr_if = &generic_mtrr_ops; } else { switch (boot_cpu_data.x86_vendor) { From patchwork Sat Apr 1 06:36:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 78068 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1077871vqo; Sat, 1 Apr 2023 00:49:44 -0700 (PDT) X-Google-Smtp-Source: AKy350aX45QzKOORnLSUUtKUkmLNeTcgj36DghZHpevB+4jT1PlS6jXj9ecNCdd4+fETSWGJryga X-Received: by 2002:a17:907:1c09:b0:930:f953:9608 with SMTP id nc9-20020a1709071c0900b00930f9539608mr41832998ejc.0.1680335384653; Sat, 01 Apr 2023 00:49:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680335384; cv=none; d=google.com; s=arc-20160816; b=B6LaUSn2HFaDNnFoCwAbcDBuw4ygHLwevVcL/Mp73tO0kWE/RItUslnwY75pbxZrYt pJLksj8zjqBWKEu3sETuWmMf1EPQz+QZ+kem3ICicc0Im9na1gPA+FmF/LxFssEohxzW AYsp0SLE67MzO/vxZgRwgU028ir/lZ1OYaeFCI/tj40V+3m7aDR6NsuiIq+60r6IdV93 lhkLMRetqOkUtDPBZZx9kypzVfd2szErWVzbdSfcaFq1aTkTOzjMBEq+mwRRA4WG1Ae7 tl+o0Io+jLuwADNvQnP7n5NGWQjH9h6nZCiQiVd0Bs7heL8bkV+iG4hZ+7TDPd0A1TqA fJgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=5tBXsp0muXYt38fiqF48mI0NM1nAHxNxMRiNpwrq0p8=; b=mDLtRvjdB+AH/2nYZLy2J0jqyegohcB6LhQ0jZauLJqXVbj0xjcht0GLmXM/WStq/x PL/L76qN/CJo+zNc49OF7OZuD3wlbQroDk+yhR3tlQFj/hIFPSRLj1kDbTTdL/A/FOHN X53Eu0abkd2CNGGTnJGyP/7UTvbkg7v5LSw7mRyP1Z5jM4e+CkaR8RYJ15bCPeHWpvg9 NWXIObvXuzMobgBcU7at0WbORe3AFhPwYLHrg66u3An+mQq1yUn4ms0X3gwrfepH3k+6 XXuBlciVQLqFHykZUzbu5uSST3n47sS1C8uxn8MJyNqrQoVP1Pg1BV7Rynhxi0z56fpq rV9g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@suse.com header.s=susede1 header.b=pkYfCnFp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=suse.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" Subject: [PATCH v5 03/15] x86/mtrr: replace some constants with defines Date: Sat, 1 Apr 2023 08:36:40 +0200 Message-Id: <20230401063652.23522-4-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230401063652.23522-1-jgross@suse.com> References: <20230401063652.23522-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761959356570532342?= X-GMAIL-MSGID: =?utf-8?q?1761959356570532342?= Instead of using constants in MTRR code, use some new #defines. Signed-off-by: Juergen Gross --- V5: - new patch (inspired by a request of Boris Petkov) --- arch/x86/include/asm/mtrr.h | 25 +++++++++++++-- arch/x86/kernel/cpu/mtrr/cleanup.c | 2 +- arch/x86/kernel/cpu/mtrr/generic.c | 51 +++++++++++++++++------------- arch/x86/kernel/cpu/mtrr/mtrr.c | 2 +- 4 files changed, 54 insertions(+), 26 deletions(-) diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index f0eeaf6e5f5f..4e59f7854950 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -23,8 +23,26 @@ #ifndef _ASM_X86_MTRR_H #define _ASM_X86_MTRR_H +#include #include +/* Defines for hardware MTRR registers. */ +#define MTRR_CONFIG_NUM_VAR_MASK GENMASK(7, 0) +#define MTRR_CONFIG_HAVE_FIXED BIT_MASK(8) +#define MTRR_CONFIG_HAVE_WC BIT_MASK(10) + +#define MTRR_DEFTYPE_TYPE_MASK GENMASK(7, 0) +#define MTRR_DEFTYPE_FIXED_ENABLED BIT_MASK(10) +#define MTRR_DEFTYPE_ENABLED BIT_MASK(11) +#define MTRR_DEFTYPE_ENABLE_MASK (MTRR_DEFTYPE_FIXED_ENABLED | \ + MTRR_DEFTYPE_ENABLED) +#define MTRR_DEFTYPE_DISABLE_MASK ~(MTRR_DEFTYPE_TYPE_MASK | \ + MTRR_DEFTYPE_ENABLE_MASK) + +#define MTRR_BASE_TYPE_MASK GENMASK_ULL(7, 0) + +#define MTRR_MASK_VALID BIT_ULL_MASK(11) + /* * The following functions are for use by other drivers that cannot use * arch_phys_wc_add and arch_phys_wc_del. @@ -121,7 +139,10 @@ struct mtrr_gentry32 { #endif /* CONFIG_COMPAT */ /* Bit fields for enabled in struct mtrr_state_type */ -#define MTRR_STATE_MTRR_FIXED_ENABLED 0x01 -#define MTRR_STATE_MTRR_ENABLED 0x02 +#define MTRR_STATE_SHIFT 10 +#define MTRR_STATE_MTRR_FIXED_ENABLED \ + (MTRR_DEFTYPE_FIXED_ENABLED >> MTRR_STATE_SHIFT) +#define MTRR_STATE_MTRR_ENABLED \ + (MTRR_DEFTYPE_ENABLED >> MTRR_STATE_SHIFT) #endif /* _ASM_X86_MTRR_H */ diff --git a/arch/x86/kernel/cpu/mtrr/cleanup.c b/arch/x86/kernel/cpu/mtrr/cleanup.c index b5f43049fa5f..ce45d7617874 100644 --- a/arch/x86/kernel/cpu/mtrr/cleanup.c +++ b/arch/x86/kernel/cpu/mtrr/cleanup.c @@ -890,7 +890,7 @@ int __init mtrr_trim_uncached_memory(unsigned long end_pfn) return 0; rdmsr(MSR_MTRRdefType, def, dummy); - def &= 0xff; + def &= MTRR_DEFTYPE_TYPE_MASK; if (def != MTRR_TYPE_UNCACHABLE) return 0; diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c index ee09d359e08f..9a12da76635c 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -171,7 +171,7 @@ static u8 mtrr_type_lookup_variable(u64 start, u64 end, u64 *partial_end, for (i = 0; i < num_var_ranges; ++i) { unsigned short start_state, end_state, inclusive; - if (!(mtrr_state.var_ranges[i].mask_lo & (1 << 11))) + if (!(mtrr_state.var_ranges[i].mask_lo & MTRR_MASK_VALID)) continue; base = (((u64)mtrr_state.var_ranges[i].base_hi) << 32) + @@ -223,7 +223,8 @@ static u8 mtrr_type_lookup_variable(u64 start, u64 end, u64 *partial_end, if ((start & mask) != (base & mask)) continue; - curr_match = mtrr_state.var_ranges[i].base_lo & 0xff; + curr_match = mtrr_state.var_ranges[i].base_lo & + MTRR_BASE_TYPE_MASK; if (prev_match == MTRR_TYPE_INVALID) { prev_match = curr_match; continue; @@ -425,7 +426,7 @@ static void __init print_mtrr_state(void) high_width = (__ffs64(size_or_mask) - (32 - PAGE_SHIFT) + 3) / 4; for (i = 0; i < num_var_ranges; ++i) { - if (mtrr_state.var_ranges[i].mask_lo & (1 << 11)) + if (mtrr_state.var_ranges[i].mask_lo & MTRR_MASK_VALID) pr_debug(" %u base %0*X%05X000 mask %0*X%05X000 %s\n", i, high_width, @@ -434,7 +435,8 @@ static void __init print_mtrr_state(void) high_width, mtrr_state.var_ranges[i].mask_hi, mtrr_state.var_ranges[i].mask_lo >> 12, - mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo & 0xff)); + mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo & + MTRR_BASE_TYPE_MASK)); else pr_debug(" %u disabled\n", i); } @@ -452,7 +454,7 @@ bool __init get_mtrr_state(void) vrs = mtrr_state.var_ranges; rdmsr(MSR_MTRRcap, lo, dummy); - mtrr_state.have_fixed = (lo >> 8) & 1; + mtrr_state.have_fixed = !!(lo & MTRR_CONFIG_HAVE_FIXED); for (i = 0; i < num_var_ranges; i++) get_mtrr_var_range(i, &vrs[i]); @@ -460,8 +462,9 @@ bool __init get_mtrr_state(void) get_fixed_ranges(mtrr_state.fixed_ranges); rdmsr(MSR_MTRRdefType, lo, dummy); - mtrr_state.def_type = (lo & 0xff); - mtrr_state.enabled = (lo & 0xc00) >> 10; + mtrr_state.def_type = lo & MTRR_DEFTYPE_TYPE_MASK; + mtrr_state.enabled = (lo & MTRR_DEFTYPE_ENABLE_MASK) >> + MTRR_STATE_SHIFT; if (amd_special_default_mtrr()) { unsigned low, high; @@ -574,7 +577,7 @@ static void generic_get_mtrr(unsigned int reg, unsigned long *base, rdmsr(MTRRphysMask_MSR(reg), mask_lo, mask_hi); - if ((mask_lo & 0x800) == 0) { + if ((mask_lo & MTRR_MASK_VALID) == 0) { /* Invalid (i.e. free) range */ *base = 0; *size = 0; @@ -606,7 +609,7 @@ static void generic_get_mtrr(unsigned int reg, unsigned long *base, */ *size = -mask; *base = (u64)base_hi << (32 - PAGE_SHIFT) | base_lo >> PAGE_SHIFT; - *type = base_lo & 0xff; + *type = base_lo & MTRR_BASE_TYPE_MASK; out_put_cpu: put_cpu(); @@ -643,10 +646,12 @@ static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr) unsigned int lo, hi; bool changed = false; +#define BASE_MASK (MTRR_BASE_TYPE_MASK | (size_and_mask << PAGE_SHIFT)) +#define MASK_MASK (MTRR_MASK_VALID | (size_and_mask << PAGE_SHIFT)) + rdmsr(MTRRphysBase_MSR(index), lo, hi); - if ((vr->base_lo & 0xfffff0ffUL) != (lo & 0xfffff0ffUL) - || (vr->base_hi & (size_and_mask >> (32 - PAGE_SHIFT))) != - (hi & (size_and_mask >> (32 - PAGE_SHIFT)))) { + if ((vr->base_lo & BASE_MASK) != (lo & BASE_MASK) + || (vr->base_hi & (BASE_MASK >> 32)) != (hi & (BASE_MASK >> 32))) { mtrr_wrmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi); changed = true; @@ -654,9 +659,8 @@ static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr) rdmsr(MTRRphysMask_MSR(index), lo, hi); - if ((vr->mask_lo & 0xfffff800UL) != (lo & 0xfffff800UL) - || (vr->mask_hi & (size_and_mask >> (32 - PAGE_SHIFT))) != - (hi & (size_and_mask >> (32 - PAGE_SHIFT)))) { + if ((vr->mask_lo & MASK_MASK) != (lo & MASK_MASK) + || (vr->mask_hi & (MASK_MASK >> 32)) != (hi & (MASK_MASK >> 32))) { mtrr_wrmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi); changed = true; } @@ -691,11 +695,13 @@ static unsigned long set_mtrr_state(void) * Set_mtrr_restore restores the old value of MTRRdefType, * so to set it we fiddle with the saved value: */ - if ((deftype_lo & 0xff) != mtrr_state.def_type - || ((deftype_lo & 0xc00) >> 10) != mtrr_state.enabled) { + if ((deftype_lo & MTRR_DEFTYPE_TYPE_MASK) != mtrr_state.def_type + || ((deftype_lo & MTRR_DEFTYPE_ENABLE_MASK) >> MTRR_STATE_SHIFT) != + mtrr_state.enabled) { - deftype_lo = (deftype_lo & ~0xcff) | mtrr_state.def_type | - (mtrr_state.enabled << 10); + deftype_lo = (deftype_lo & MTRR_DEFTYPE_DISABLE_MASK) | + mtrr_state.def_type | + (mtrr_state.enabled << MTRR_STATE_SHIFT); change_mask |= MTRR_CHANGE_MASK_DEFTYPE; } @@ -708,7 +714,8 @@ void mtrr_disable(void) rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi); /* Disable MTRRs, and set the default type to uncached */ - mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & ~0xcff, deftype_hi); + mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & MTRR_DEFTYPE_DISABLE_MASK, + deftype_hi); } void mtrr_enable(void) @@ -763,7 +770,7 @@ static void generic_set_mtrr(unsigned int reg, unsigned long base, } else { vr->base_lo = base << PAGE_SHIFT | type; vr->base_hi = (base & size_and_mask) >> (32 - PAGE_SHIFT); - vr->mask_lo = -size << PAGE_SHIFT | 0x800; + vr->mask_lo = -size << PAGE_SHIFT | MTRR_MASK_VALID; vr->mask_hi = (-size & size_and_mask) >> (32 - PAGE_SHIFT); mtrr_wrmsr(MTRRphysBase_MSR(reg), vr->base_lo, vr->base_hi); @@ -817,7 +824,7 @@ static int generic_have_wrcomb(void) { unsigned long config, dummy; rdmsr(MSR_MTRRcap, config, dummy); - return config & (1 << 10); + return config & MTRR_CONFIG_HAVE_WC; } int positive_have_wrcomb(void) diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtrr.c index ce0b82209ad3..1beb38f7a7a3 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -117,7 +117,7 @@ static void __init set_num_var_ranges(bool use_generic) else if (is_cpu(CYRIX) || is_cpu(CENTAUR)) config = 8; - num_var_ranges = config & 0xff; + num_var_ranges = config & MTRR_CONFIG_NUM_VAR_MASK; } static void __init init_table(void) From patchwork Sat Apr 1 06:36:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 78063 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1062577vqo; Sat, 1 Apr 2023 00:05:39 -0700 (PDT) X-Google-Smtp-Source: AKy350bc/GUljnjnf2R6S0q65efnFWyXFOfhtCO4263+M4llLSf9eV+eYn7EiOltGImTKNBrhG5X X-Received: by 2002:a62:7bce:0:b0:625:e051:e462 with SMTP id w197-20020a627bce000000b00625e051e462mr30476069pfc.15.1680332738833; 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Peter Anvin" , Michael Kelley Subject: [PATCH v5 04/15] x86/mtrr: support setting MTRR state for software defined MTRRs Date: Sat, 1 Apr 2023 08:36:41 +0200 Message-Id: <20230401063652.23522-5-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230401063652.23522-1-jgross@suse.com> References: <20230401063652.23522-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761956582199133903?= X-GMAIL-MSGID: =?utf-8?q?1761956582199133903?= When running virtualized, MTRR access can be reduced (e.g. in Xen PV guests or when running as a SEV-SNP guest under Hyper-V). Typically the hypervisor will reset the MTRR feature in CPUID data, resulting in no MTRR memory type information being available for the kernel. This has turned out to result in problems: - Hyper-V SEV-SNP guests using uncached mappings where they shouldn't - Xen PV dom0 mapping memory as WB which should be UC- instead Solve those problems by supporting to set a static MTRR state, overwriting the empty state used today. In case such a state has been set, don't call get_mtrr_state() in mtrr_bp_init(). The set state will only be used by mtrr_type_lookup(), as in all other cases mtrr_enabled() is being checked, which will return false. Accept the overwrite call only for selected cases when running as a guest. Disable X86_FEATURE_MTRR in order to avoid any MTRR modifications by just refusing them. Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V2: - new patch V3: - omit fixed MTRRs, as those are currently not needed - disable X86_FEATURE_MTRR instead of testing it - provide a stub for !CONFIG_MTRR (Michael Kelley) - use cpu_feature_enabled() (Boris Petkov) - add tests for mtrr_overwrite_state() being allowed (Boris Petkov) V4: - add test for hv_is_isolation_supported() (Michael Kelley) V5: - drop test for running as native (Boris Petkov) - split large complex test into multiple simple ones (Boris Petkov) - enhance test in mtrr_bp_init() (Boris Petkov) --- arch/x86/include/asm/mtrr.h | 8 +++++ arch/x86/kernel/cpu/mtrr/generic.c | 58 +++++++++++++++++++++++++++++- arch/x86/kernel/cpu/mtrr/mtrr.c | 9 +++++ arch/x86/kernel/setup.c | 2 ++ 4 files changed, 76 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index 4e59f7854950..6decb18e22ed 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -49,6 +49,8 @@ */ # ifdef CONFIG_MTRR void mtrr_bp_init(void); +void mtrr_overwrite_state(struct mtrr_var_range *var, unsigned int num_var, + mtrr_type def_type); extern u8 mtrr_type_lookup(u64 addr, u64 end, u8 *uniform); extern void mtrr_save_fixed_ranges(void *); extern void mtrr_save_state(void); @@ -66,6 +68,12 @@ void mtrr_disable(void); void mtrr_enable(void); void mtrr_generic_set_state(void); # else +static inline void mtrr_overwrite_state(struct mtrr_var_range *var, + unsigned int num_var, + mtrr_type def_type) +{ +} + static inline u8 mtrr_type_lookup(u64 addr, u64 end, u8 *uniform) { /* diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c index 9a12da76635c..0794f3f1cc27 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -8,10 +8,12 @@ #include #include #include - +#include #include #include #include +#include +#include #include #include #include @@ -241,6 +243,60 @@ static u8 mtrr_type_lookup_variable(u64 start, u64 end, u64 *partial_end, return mtrr_state.def_type; } +/** + * mtrr_overwrite_state - set static MTRR state + * + * Used to set MTRR state via different means (e.g. with data obtained from + * a hypervisor). + * Is allowed only for special cases when running virtualized. Must be called + * from the x86_init.hyper.init_platform() hook. + */ +void mtrr_overwrite_state(struct mtrr_var_range *var, unsigned int num_var, + mtrr_type def_type) +{ + unsigned int i; + + /* Only allowed to be called once before mtrr_bp_init(). */ + if (WARN_ON(mtrr_state_set)) + return; + + /* Only allowed when running virtualized. */ + if (!cpu_feature_enabled(X86_FEATURE_HYPERVISOR)) + return; + + /* + * Only allowed for special virtualization cases: + * - when running as SEV-SNP guest + * - when running as Hyper-V isolated guest + * - when running as Xen PV guest + * - when running as TSX guest + */ + if (!cc_platform_has(CC_ATTR_GUEST_SEV_SNP) && + !hv_is_isolation_supported() && + !cpu_feature_enabled(X86_FEATURE_XENPV) && + !cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) + return; + + /* Disable MTRR in order to disable MTRR modifications. */ + setup_clear_cpu_cap(X86_FEATURE_MTRR); + + if (var) { + if (num_var > MTRR_MAX_VAR_RANGES) { + pr_warn("Trying to overwrite MTRR state with %u variable entries\n", + num_var); + num_var = MTRR_MAX_VAR_RANGES; + } + for (i = 0; i < num_var; i++) + mtrr_state.var_ranges[i] = var[i]; + num_var_ranges = num_var; + } + + mtrr_state.def_type = def_type; + mtrr_state.enabled |= MTRR_STATE_MTRR_ENABLED; + + mtrr_state_set = 1; +} + /** * mtrr_type_lookup - look up memory type in MTRR * diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtrr.c index 1beb38f7a7a3..1c19d67ddab3 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -666,6 +666,15 @@ void __init mtrr_bp_init(void) const char *why = "(not available)"; unsigned int phys_addr; + if (!generic_mtrrs && mtrr_state.enabled) { + /* Software overwrite of MTRR state, only for generic case. */ + mtrr_calc_physbits(true); + init_table(); + pr_info("MTRRs set to read-only\n"); + + return; + } + phys_addr = mtrr_calc_physbits(generic_mtrrs); if (generic_mtrrs) { diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c index 16babff771bd..0cccfeb67c3a 100644 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -1037,6 +1037,8 @@ void __init setup_arch(char **cmdline_p) /* * VMware detection requires dmi to be available, so this * needs to be done after dmi_setup(), for the boot CPU. + * For some guest types (Xen PV, SEV-SNP, TDX) it is required to be + * called before cache_bp_init() for setting up MTRR state. */ init_hypervisor_platform(); From patchwork Sat Apr 1 06:36:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 78055 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1053570vqo; Fri, 31 Mar 2023 23:38:55 -0700 (PDT) X-Google-Smtp-Source: AKy350ad01hAiH/AW5LjV2tjPZrW/O1U7hpJk+w+msKR27QR1SauZMLLqWPu1g21C1MQOenE9+cF X-Received: by 2002:a17:90b:1b49:b0:23f:9439:9a27 with SMTP id nv9-20020a17090b1b4900b0023f94399a27mr32954623pjb.20.1680331135496; Fri, 31 Mar 2023 23:38:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680331135; cv=none; d=google.com; s=arc-20160816; b=i3M7Jt26yMUjsj3uQt63p0WJVd9c8gsEYSF/Q0EYEO0+4iAQ+ftZzbDI4UQ+BQ1sSm 7eoTQl1d9t7Ct6tupotSYvvZkcnaNpljM1Cqi305IqvcVN/ES0BvLeUT3gEnl8jrlSN7 p+t5lzSUzYai/+nZziSRRO1bix4knOZrFtK+Z02feFzlg5Bw82rHuRUGE705h10WtTSc Riiaxo/jIoQucRp6nanhK69lj+RH+Tc+cyWyuayYXtlmdRjG8s9jm55EQ1O0MQ2eyHgC EP7Pf0nyAuS69jnjFmoiJ03l2hC3Pt+dx5xvGYu5/PVxk4EJdL9GyD0XxNRf+oBtUkZs GS6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Pb/qNhjjqBGVJo7Fmuv925HQ9Z5bT3aQVdQm6MKlfSg=; b=hXyFY1zB1nW06wrDWwH8Q9kUygVjbKwD0gCShr4hS819b/uOYcw8l8q6bK5IDMQHji LhXfaF0CDbkGqcxBAr1dbyYeg+7p+ZCOVv0r+vqoNCpDQzUWPZxSb7aq9KfIx6qvFYxl WesLBzIwf6QAgnUkPyAYGOwjr3jxn1nktOUh7AIUkB+oJ8BKteNTpxcDIoC9WolUx3Js WHFTQCpIuCyafCrI5NQLHWfswPTIIyoBVCK/GnGGjrPRHkeDyLQDkZN6wQp/whkFj0U/ yTeIVZAimZGKZWfed37UKYPfbz2kfNNkATDhOCV/qTbzfL/RsuYU1dD1xeAfUj8iRJae RTYQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@suse.com header.s=susede1 header.b=TGo1WV1P; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=suse.com Received: from out1.vger.email (out1.vger.email. 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Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Michael Kelley Subject: [PATCH v5 05/15] x86/hyperv: set MTRR state when running as SEV-SNP Hyper-V guest Date: Sat, 1 Apr 2023 08:36:42 +0200 Message-Id: <20230401063652.23522-6-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230401063652.23522-1-jgross@suse.com> References: <20230401063652.23522-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761954900398851124?= X-GMAIL-MSGID: =?utf-8?q?1761954900398851124?= In order to avoid mappings using the UC- cache attribute, set the MTRR state to use WB caching as the default. This is needed in order to cope with the fact that PAT is enabled, while MTRRs are not supported by the hypervisor. Fixes: 90b926e68f50 ("x86/pat: Fix pat_x_mtrr_type() for MTRR disabled case") Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V2: - new patch --- arch/x86/kernel/cpu/mshyperv.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c index f36dc2f796c5..0a6cc3cf8919 100644 --- a/arch/x86/kernel/cpu/mshyperv.c +++ b/arch/x86/kernel/cpu/mshyperv.c @@ -34,6 +34,7 @@ #include #include #include +#include /* Is Linux running as the root partition? */ bool hv_root_partition; @@ -408,6 +409,9 @@ static void __init ms_hyperv_init_platform(void) #ifdef CONFIG_SWIOTLB swiotlb_unencrypted_base = ms_hyperv.shared_gpa_boundary; #endif + + /* Set WB as the default cache mode. */ + mtrr_overwrite_state(NULL, 0, MTRR_TYPE_WRBACK); } /* Isolation VMs are unenlightened SEV-based VMs, thus this check: */ if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT)) { From patchwork Sat Apr 1 06:36:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 78059 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1060829vqo; Sat, 1 Apr 2023 00:01:54 -0700 (PDT) X-Google-Smtp-Source: AKy350a0SNMVJAqYFO0WXdSePObnDBBac/NmvPjgazaIfEA+mxVkZpzHlI6hTlhfi0K3Uo/i3BWI X-Received: by 2002:a17:902:c952:b0:1a2:79f0:f059 with SMTP id i18-20020a170902c95200b001a279f0f059mr13369556pla.28.1680332514567; Sat, 01 Apr 2023 00:01:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680332514; cv=none; d=google.com; s=arc-20160816; b=cD/Dy5J2lnh1tsDzqeJ8BCCykybC3mlsc0/f4SoKdbnUbgu1msi7AcncHOfeebyn1e QKnEAWTC9k4aW5+xPzBVBKDzqk/b2Zyh/y+k7cna7TEAjqBgZfDLqTxypt0W+YkuTVhP TDNpXKPhxxgHngBk+zBOxomYjiUrFpYRvDxNJ3lBHNgo/DoiWH3o7QIAIP6ZrxvFgEE7 OQ9LMPpcIw7NoztRdgCNj0h3fSmD3Vb+3BHc5je4A7YYJzkviKWLS0i8kHpBI3EZZob+ 5FLpQaed6cqifaJgkyc4QYMSYoqYg3LlZV0OjaIZOP/nnU2bOAp7MllyeL0ByDSMlltC LavA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=BBSVwIjfh8GqolcmguccgHbT9FXyjh+eQq+oIFQmSnw=; b=DfDPm57Dz0RtBJWuBQi9ZmPxlK4553eaHpvkwDjgcsrig41Yt3+WEsnXLIQYl6vIGU qh5bP0rs7KBiDTK0eZw3wMXBgg/1KGhBCpxsD19rb5YXutsTJPxZ19n1GG0/AGajotiO VagQBmAl6gXsxsj6V6HB9jJh9sXHL0ZDibdTYpoEEMsCXNTQT86Zg7yNQm2ohmO+qQ3J NieXX+UxH1v5VLz50Pve8L28XmGqD8oVH8wttKpsJi5B89VPNC6X4F59lsovgkopnngC NR60V93XQ/iJx29q4ksferd8dlf9tDR2/8iVTb2SAgvkUgZ+Hj7t2BK9C+U75eevaVGd aLNw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@suse.com header.s=susede1 header.b="ajS/iUmK"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=suse.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" , xen-devel@lists.xenproject.org Subject: [PATCH v5 06/15] x86/xen: set MTRR state when running as Xen PV initial domain Date: Sat, 1 Apr 2023 08:36:43 +0200 Message-Id: <20230401063652.23522-7-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230401063652.23522-1-jgross@suse.com> References: <20230401063652.23522-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761956346741832089?= X-GMAIL-MSGID: =?utf-8?q?1761956346741832089?= When running as Xen PV initial domain (aka dom0), MTRRs are disabled by the hypervisor, but the system should nevertheless use correct cache memory types. This has always kind of worked, as disabled MTRRs resulted in disabled PAT, too, so that the kernel avoided code paths resulting in inconsistencies. This bypassed all of the sanity checks the kernel is doing with enabled MTRRs in order to avoid memory mappings with conflicting memory types. This has been changed recently, leading to PAT being accepted to be enabled, while MTRRs stayed disabled. The result is that mtrr_type_lookup() no longer is accepting all memory type requests, but started to return WB even if UC- was requested. This led to driver failures during initialization of some devices. In reality MTRRs are still in effect, but they are under complete control of the Xen hypervisor. It is possible, however, to retrieve the MTRR settings from the hypervisor. In order to fix those problems, overwrite the MTRR state via mtrr_overwrite_state() with the MTRR data from the hypervisor, if the system is running as a Xen dom0. Fixes: 72cbc8f04fe2 ("x86/PAT: Have pat_enabled() properly reflect state when running on Xen") Signed-off-by: Juergen Gross Reviewed-by: Boris Ostrovsky --- V2: - new patch V3: - move the call of mtrr_overwrite_state() to xen_pv_init_platform() V4: - only call mtrr_overwrite_state() if any MTRR got from Xen (Boris Ostrovsky) --- arch/x86/xen/enlighten_pv.c | 52 +++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index 093b78c8bbec..fdaea02ab5ab 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -68,6 +68,7 @@ #include #include #include +#include #include #include #include @@ -119,6 +120,54 @@ static int __init parse_xen_msr_safe(char *str) } early_param("xen_msr_safe", parse_xen_msr_safe); +/* Get MTRR settings from Xen and put them into mtrr_state. */ +static void __init xen_set_mtrr_data(void) +{ +#ifdef CONFIG_MTRR + struct xen_platform_op op = { + .cmd = XENPF_read_memtype, + .interface_version = XENPF_INTERFACE_VERSION, + }; + unsigned int reg; + unsigned long mask; + uint32_t eax, width; + static struct mtrr_var_range var[MTRR_MAX_VAR_RANGES] __initdata; + + /* Get physical address width (only 64-bit cpus supported). */ + width = 36; + eax = cpuid_eax(0x80000000); + if ((eax >> 16) == 0x8000 && eax >= 0x80000008) { + eax = cpuid_eax(0x80000008); + width = eax & 0xff; + } + + for (reg = 0; reg < MTRR_MAX_VAR_RANGES; reg++) { + op.u.read_memtype.reg = reg; + if (HYPERVISOR_platform_op(&op)) + break; + + /* + * Only called in dom0, which has all RAM PFNs mapped at + * RAM MFNs, and all PCI space etc. is identity mapped. + * This means we can treat MFN == PFN regarding MTRR settings. + */ + var[reg].base_lo = op.u.read_memtype.type; + var[reg].base_lo |= op.u.read_memtype.mfn << PAGE_SHIFT; + var[reg].base_hi = op.u.read_memtype.mfn >> (32 - PAGE_SHIFT); + mask = ~((op.u.read_memtype.nr_mfns << PAGE_SHIFT) - 1); + mask &= (1UL << width) - 1; + if (mask) + mask |= MTRR_MASK_VALID; + var[reg].mask_lo = mask; + var[reg].mask_hi = mask >> 32; + } + + /* Only overwrite MTRR state if any MTRR could be got from Xen. */ + if (reg) + mtrr_overwrite_state(var, reg, MTRR_TYPE_UNCACHABLE); +#endif +} + static void __init xen_pv_init_platform(void) { /* PV guests can't operate virtio devices without grants. */ @@ -135,6 +184,9 @@ static void __init xen_pv_init_platform(void) /* pvclock is in shared info area */ xen_init_time_ops(); + + if (xen_initial_domain()) + xen_set_mtrr_data(); } static void __init xen_pv_guest_late_init(void) From patchwork Sat Apr 1 06:36:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 78056 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1054053vqo; Fri, 31 Mar 2023 23:40:22 -0700 (PDT) X-Google-Smtp-Source: AKy350bUfyQ0qR+qt3ohmA8Vui2beY0m/BMgFsnflJvy9MAS58BZCr8UarbhWyMJtmezj75tKOiw X-Received: by 2002:a17:906:5d05:b0:947:c8d5:fb2a with SMTP id g5-20020a1709065d0500b00947c8d5fb2amr4566710ejt.48.1680331222056; Fri, 31 Mar 2023 23:40:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680331222; cv=none; d=google.com; s=arc-20160816; b=jzA0fdigv+42QdXstoi07zfos6ZrcAbz+VQfq/V2CrfkSNd7tZrsbtJjf6APU12uC3 ojpzWLcXf7Q+gPV2dmvymog+e7RLVKfPneEuLMPKehjq2AJtRBlZhs5X82LYtPdcpb/h B0zixD/Mkx5wtLZUJ2KtN8xrUXuy7tpwbtja312UgSl64QQryAycVPiPM98lyWsxTj7v 3DFjkf4q3mZZeWM4dDevZ4ITPZ7R2nJ4Qc3a8mOPa63uBBMAnH/PgkO+HkMlIdOpxQP1 lafViqMzhH3WIVLJ4F9A8ERO0qrBxVn7KHEnshXAu4VgVAcMu89H4z8YnEg7N0SUfaT+ g3Pw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=mZHEzRhRpsOluDYn0rKzRSXTPPE43ZmgbokxRzXTPPA=; b=K9F/gjY9gnF2mBStPmhqbNUExHHPwMdR8f81gvufWDZrKjCcO1l1Ew4JmPCg9HLtBd DKLFq/SbbtuKOjkDPKMofdOFgsEEbpl0Hcbmk433bsKYariQyRDROrrDi/Cgn2dchpQe x1rdLWPvZM5yAWQVcgF+6O7cvuwVOwsnxNY0hezqBu5mlBQJdr2G1YLxtlbBKIyJuKYZ oXXHXGEKRItIPR4XDB1dwpRWLIGdJkt46SCGgOyNYhl0XIvncWrFe1WWD1AGrFBtClSE Jm7mCZlW4wGzohO5oH2veyfK4tDlKs5eKO8X3TTFYl3OJmPav9jFA5qKeVtU5rAcBiKW g6Jg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@suse.com header.s=susede1 header.b=uUgy4V32; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=suse.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" , Michael Kelley Subject: [PATCH v5 07/15] x86/mtrr: replace vendor tests in MTRR code Date: Sat, 1 Apr 2023 08:36:44 +0200 Message-Id: <20230401063652.23522-8-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230401063652.23522-1-jgross@suse.com> References: <20230401063652.23522-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761954991591962634?= X-GMAIL-MSGID: =?utf-8?q?1761954991591962634?= Modern CPUs all share the same MTRR interface implemented via generic_mtrr_ops. At several places in MTRR code this generic interface is deduced via is_cpu(INTEL) tests, which is only working due to X86_VENDOR_INTEL being 0 (the is_cpu() macro is testing mtrr_if->vendor, which isn't explicitly set in generic_mtrr_ops). Fix that by replacing the is_cpu(INTEL) tests with testing for mtrr_if to be &generic_mtrr_ops. The only other place where the .vendor member of struct mtrr_ops is being used is in set_num_var_ranges(), where depending on the vendor the number of MTRR registers is determined. This can easily be changed by replacing .vendor with the static number of MTRR registers. It should be noted that the test "is_cpu(HYGON)" wasn't ever returning true, as there is no struct mtrr_ops with that vendor information. Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V3: - new patch V4: - use cpu_feature_enabled(X86_FEATURE_MTRR) for testing generic MTRRs (Boris Petkov) --- arch/x86/kernel/cpu/mtrr/amd.c | 2 +- arch/x86/kernel/cpu/mtrr/centaur.c | 2 +- arch/x86/kernel/cpu/mtrr/cleanup.c | 4 ++-- arch/x86/kernel/cpu/mtrr/cyrix.c | 2 +- arch/x86/kernel/cpu/mtrr/generic.c | 2 +- arch/x86/kernel/cpu/mtrr/mtrr.c | 8 +++----- arch/x86/kernel/cpu/mtrr/mtrr.h | 4 +--- 7 files changed, 10 insertions(+), 14 deletions(-) diff --git a/arch/x86/kernel/cpu/mtrr/amd.c b/arch/x86/kernel/cpu/mtrr/amd.c index eff6ac62c0ff..ef3e8e42b782 100644 --- a/arch/x86/kernel/cpu/mtrr/amd.c +++ b/arch/x86/kernel/cpu/mtrr/amd.c @@ -110,7 +110,7 @@ amd_validate_add_page(unsigned long base, unsigned long size, unsigned int type) } const struct mtrr_ops amd_mtrr_ops = { - .vendor = X86_VENDOR_AMD, + .var_regs = 2, .set = amd_set_mtrr, .get = amd_get_mtrr, .get_free_region = generic_get_free_region, diff --git a/arch/x86/kernel/cpu/mtrr/centaur.c b/arch/x86/kernel/cpu/mtrr/centaur.c index b8a74eddde83..4466ddeb0125 100644 --- a/arch/x86/kernel/cpu/mtrr/centaur.c +++ b/arch/x86/kernel/cpu/mtrr/centaur.c @@ -112,7 +112,7 @@ centaur_validate_add_page(unsigned long base, unsigned long size, unsigned int t } const struct mtrr_ops centaur_mtrr_ops = { - .vendor = X86_VENDOR_CENTAUR, + .var_regs = 8, .set = centaur_set_mcr, .get = centaur_get_mcr, .get_free_region = centaur_get_free_region, diff --git a/arch/x86/kernel/cpu/mtrr/cleanup.c b/arch/x86/kernel/cpu/mtrr/cleanup.c index ce45d7617874..0f27c38f3ff9 100644 --- a/arch/x86/kernel/cpu/mtrr/cleanup.c +++ b/arch/x86/kernel/cpu/mtrr/cleanup.c @@ -689,7 +689,7 @@ int __init mtrr_cleanup(unsigned address_bits) int index_good; int i; - if (!is_cpu(INTEL) || enable_mtrr_cleanup < 1) + if (!cpu_feature_enabled(X86_FEATURE_MTRR) || enable_mtrr_cleanup < 1) return 0; rdmsr(MSR_MTRRdefType, def, dummy); @@ -886,7 +886,7 @@ int __init mtrr_trim_uncached_memory(unsigned long end_pfn) * Make sure we only trim uncachable memory on machines that * support the Intel MTRR architecture: */ - if (!is_cpu(INTEL) || disable_mtrr_trim) + if (!cpu_feature_enabled(X86_FEATURE_MTRR) || disable_mtrr_trim) return 0; rdmsr(MSR_MTRRdefType, def, dummy); diff --git a/arch/x86/kernel/cpu/mtrr/cyrix.c b/arch/x86/kernel/cpu/mtrr/cyrix.c index 173b9e01e623..238dad57d4d6 100644 --- a/arch/x86/kernel/cpu/mtrr/cyrix.c +++ b/arch/x86/kernel/cpu/mtrr/cyrix.c @@ -235,7 +235,7 @@ static void cyrix_set_arr(unsigned int reg, unsigned long base, } const struct mtrr_ops cyrix_mtrr_ops = { - .vendor = X86_VENDOR_CYRIX, + .var_regs = 8, .set = cyrix_set_arr, .get = cyrix_get_arr, .get_free_region = cyrix_get_free_region, diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c index 0794f3f1cc27..5d60b46187f7 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -846,7 +846,7 @@ int generic_validate_add_page(unsigned long base, unsigned long size, * For Intel PPro stepping <= 7 * must be 4 MiB aligned and not touch 0x70000000 -> 0x7003FFFF */ - if (is_cpu(INTEL) && boot_cpu_data.x86 == 6 && + if (mtrr_if == &generic_mtrr_ops && boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 1 && boot_cpu_data.x86_stepping <= 7) { if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) { diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtrr.c index 1c19d67ddab3..46aae69d259e 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -108,14 +108,12 @@ static int have_wrcomb(void) /* This function returns the number of variable MTRRs */ static void __init set_num_var_ranges(bool use_generic) { - unsigned long config = 0, dummy; + unsigned long config, dummy; if (use_generic) rdmsr(MSR_MTRRcap, config, dummy); - else if (is_cpu(AMD) || is_cpu(HYGON)) - config = 2; - else if (is_cpu(CYRIX) || is_cpu(CENTAUR)) - config = 8; + else + config = mtrr_if->var_regs; num_var_ranges = config & MTRR_CONFIG_NUM_VAR_MASK; } diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.h b/arch/x86/kernel/cpu/mtrr/mtrr.h index 02eb5871492d..a3c362d3d5bf 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.h +++ b/arch/x86/kernel/cpu/mtrr/mtrr.h @@ -13,7 +13,7 @@ extern unsigned int mtrr_usage_table[MTRR_MAX_VAR_RANGES]; struct mtrr_ops { - u32 vendor; + u32 var_regs; void (*set)(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type); void (*get)(unsigned int reg, unsigned long *base, @@ -54,8 +54,6 @@ bool get_mtrr_state(void); extern u64 size_or_mask, size_and_mask; extern const struct mtrr_ops *mtrr_if; -#define is_cpu(vnd) (mtrr_if && mtrr_if->vendor == X86_VENDOR_##vnd) - extern unsigned int num_var_ranges; extern u64 mtrr_tom2; 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Peter Anvin" Subject: [PATCH v5 08/15] x86/mtrr: have only one set_mtrr() variant Date: Sat, 1 Apr 2023 08:36:45 +0200 Message-Id: <20230401063652.23522-9-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230401063652.23522-1-jgross@suse.com> References: <20230401063652.23522-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761959030758572494?= X-GMAIL-MSGID: =?utf-8?q?1761959030758572494?= Today there are two variants of set_mtrr(): one calling stop_machine() and one calling stop_machine_cpuslocked(). The first one (set_mtrr()) has only one caller, and this caller is always running with only one CPU online and interrupts being off. Remove the first variant completely and replace the call of it with a call of mtrr_if->set(). Rename the second variant set_mtrr_cpuslocked() to set_mtrr() now that there is only one variant left. Signed-off-by: Juergen Gross --- V5: - new patch --- arch/x86/kernel/cpu/mtrr/mtrr.c | 28 ++++++++-------------------- 1 file changed, 8 insertions(+), 20 deletions(-) diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtrr.c index 46aae69d259e..4fa3d0f94f39 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -192,20 +192,8 @@ static inline int types_compatible(mtrr_type type1, mtrr_type type2) * Note that the mechanism is the same for UP systems, too; all the SMP stuff * becomes nops. */ -static void -set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type) -{ - struct set_mtrr_data data = { .smp_reg = reg, - .smp_base = base, - .smp_size = size, - .smp_type = type - }; - - stop_machine(mtrr_rendezvous_handler, &data, cpu_online_mask); -} - -static void set_mtrr_cpuslocked(unsigned int reg, unsigned long base, - unsigned long size, mtrr_type type) +static void set_mtrr(unsigned int reg, unsigned long base, unsigned long size, + mtrr_type type) { struct set_mtrr_data data = { .smp_reg = reg, .smp_base = base, @@ -335,7 +323,7 @@ int mtrr_add_page(unsigned long base, unsigned long size, /* Search for an empty MTRR */ i = mtrr_if->get_free_region(base, size, replace); if (i >= 0) { - set_mtrr_cpuslocked(i, base, size, type); + set_mtrr(i, base, size, type); if (likely(replace < 0)) { mtrr_usage_table[i] = 1; } else { @@ -343,7 +331,7 @@ int mtrr_add_page(unsigned long base, unsigned long size, if (increment) mtrr_usage_table[i]++; if (unlikely(replace != i)) { - set_mtrr_cpuslocked(replace, 0, 0, 0); + set_mtrr(replace, 0, 0, 0); mtrr_usage_table[replace] = 0; } } @@ -471,7 +459,7 @@ int mtrr_del_page(int reg, unsigned long base, unsigned long size) goto out; } if (--mtrr_usage_table[reg] < 1) - set_mtrr_cpuslocked(reg, 0, 0, 0); + set_mtrr(reg, 0, 0, 0); error = reg; out: mutex_unlock(&mtrr_mutex); @@ -601,9 +589,9 @@ static void mtrr_restore(void) for (i = 0; i < num_var_ranges; i++) { if (mtrr_value[i].lsize) { - set_mtrr(i, mtrr_value[i].lbase, - mtrr_value[i].lsize, - mtrr_value[i].ltype); + mtrr_if->set(i, mtrr_value[i].lbase, + mtrr_value[i].lsize, + mtrr_value[i].ltype); } } } From patchwork Sat Apr 1 06:36:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 78058 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1055272vqo; Fri, 31 Mar 2023 23:44:33 -0700 (PDT) X-Google-Smtp-Source: AKy350ZMGkSNdfy830lsBaGg+yvgN7aq9fasixMvIXr7JNXwTWIjoZ2stKnsa/9bqdbKmQIDRH1C X-Received: by 2002:a17:906:7241:b0:935:1565:d661 with SMTP id n1-20020a170906724100b009351565d661mr29771994ejk.66.1680331472958; Fri, 31 Mar 2023 23:44:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680331472; cv=none; d=google.com; s=arc-20160816; b=jSZ3pNkqyTrLgsBuL6neFt6rMsqb5ZNyPskZm23zFI0RT57+ikJJaUM+eSuDAFG61S JksGPAZOX0ZklBTXnrpQekpfvfbZBuwQc2rJtXOChjFEdZ2hm+lzzhJweLuLs/HC0j2w s3GbiwgKOKd8GxTtba39SC83aDUq98d80JfHOzSS2tCa41cr+B30hj3yFEboeCpBM9Sa kq8CG+z53yZNbkHWAwYD6jJDMJaBsfqtn6NxzZzhQl8OZZvZ2AeoAdLh26I1m+x9S+od 4aBQxs31Cu6Y9+AOED7PEUx5gROBPLHgThwlBZUinMD/DfFWZ+7XK7lAEENiEnD1cz5S YpRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=K2ik7sM7MKDAhj6hnR4NNX3zRxA2aEkPlgWNeKuOI4M=; b=0Q7yU9z4+7av4UseGScPvq5/jHJ8KRYc9TsjUcWknx9Jl7UHjX3OhVj3IVq6uv6Uws jOgy7aBe16blQ60tX81/xYOKX8qfKR0rNj5s9sKZObn2rEbxumPIU5sq2ZDu7W1VAb1D JabcfLP9POB8zqGUCRrxoJzHzDPfj2C5XajSxSdL/boX0fsl+JDdDKWTKGUFzdphAbB6 fbA4zYCcmWKGptDiREty2g/96ujmF6Ci1gIQBEll9EvdphMtB1zT0GIIO+OsGuuE+KRU NMLqpLdwWBb7RLm2VLzAwlq/l5wTBYPRMiLKYejl6iozkV9TRAZGyzVvCPqaFHsQ9M5S jVNQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@suse.com header.s=susede1 header.b=lX+D5Iwc; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=suse.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" , Michael Kelley Subject: [PATCH v5 09/15] x86/mtrr: allocate mtrr_value array dynamically Date: Sat, 1 Apr 2023 08:36:46 +0200 Message-Id: <20230401063652.23522-10-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230401063652.23522-1-jgross@suse.com> References: <20230401063652.23522-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761955254530187976?= X-GMAIL-MSGID: =?utf-8?q?1761955254530187976?= The mtrr_value[] array is a static variable, which is used only in a few configurations. Consuming 6kB is ridiculous for this case, especially as the array doesn't need to be that large and it can easily be allocated dynamically. The "few configurations" are all 32-bit ones, so put the code inside a CONFIG_X86_32 #ifdef. Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V5: - check for allocation failure (Kai Huang, Boris Petkov) - add #ifdef --- arch/x86/kernel/cpu/mtrr/mtrr.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtrr.c index 4fa3d0f94f39..76f5b5e1128b 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -560,8 +560,10 @@ int arch_phys_wc_index(int handle) } EXPORT_SYMBOL_GPL(arch_phys_wc_index); -/* The suspend/resume methods are only for CPU without MTRR. CPU using generic - * MTRR driver doesn't require this +#ifdef CONFIG_X86_32 +/* + * The suspend/resume methods are only for CPUs without MTRR. CPUs using generic + * MTRR driver don't require this. */ struct mtrr_value { mtrr_type ltype; @@ -569,12 +571,15 @@ struct mtrr_value { unsigned long lsize; }; -static struct mtrr_value mtrr_value[MTRR_MAX_VAR_RANGES]; +static struct mtrr_value *mtrr_value; static int mtrr_save(void) { int i; + if (!mtrr_value) + return -ENOMEM; + for (i = 0; i < num_var_ranges; i++) { mtrr_if->get(i, &mtrr_value[i].lbase, &mtrr_value[i].lsize, @@ -596,12 +601,11 @@ static void mtrr_restore(void) } } - - static struct syscore_ops mtrr_syscore_ops = { .suspend = mtrr_save, .resume = mtrr_restore, }; +#endif /* CONFIG_X86_32 */ int __initdata changed_by_mtrr_cleanup; @@ -730,15 +734,20 @@ static int __init mtrr_init_finialize(void) return 0; } +#ifdef CONFIG_X86_32 + mtrr_value = kcalloc(num_var_ranges, sizeof(*mtrr_value), GFP_KERNEL); + /* * The CPU has no MTRR and seems to not support SMP. They have * specific drivers, we use a tricky method to support - * suspend/resume for them. + * suspend/resume for them. In case above allocation failed we can't + * support suspend/resume (handled in mtrr_save()). * * TBD: is there any system with such CPU which supports * suspend/resume? If no, we should remove the code. */ register_syscore_ops(&mtrr_syscore_ops); +#endif return 0; } From patchwork Sat Apr 1 06:36:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 78057 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1055207vqo; Fri, 31 Mar 2023 23:44:21 -0700 (PDT) X-Google-Smtp-Source: AKy350a5CJV2sSO932S1noXUa4teOknWZPVf3lDDvsGQmNUW7Dar3Yk1WBoJFPniEof3HnrjFQp8 X-Received: by 2002:a05:6402:658:b0:4fb:6523:2b38 with SMTP id u24-20020a056402065800b004fb65232b38mr30175690edx.27.1680331461511; Fri, 31 Mar 2023 23:44:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680331461; cv=none; d=google.com; s=arc-20160816; b=prwfrDtNQDQ82J4/2HcKU/UpEP4Zu5YBtbbg8cKpnl4OSFizun0UfzdmLzHxFSMzrZ msXVnas8XiIpiX1rdATDwSWLQblDeDOOPn7ftlQSyLAne+yYmdosXQkZc3v41JLhy9JJ ljlB63NcbD+vhEnjQD7vxbs9S65wVEypfYdYnAlCHnsmUMLQ2ombITcwWFmasw57ILWT wqMm6J+wO4uhSiUdG+eVuQSDqkvKdCDQL7f43LjYq0bjPZGt0kKT3K4yeaD6R45EJp8B Dvwl7iOCKgdc06MDSpOvKbsbmlHmqKceAoWY4fbn9s2oRPFjptXZHMN8Vebz3QbH8aA/ dvIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=8lUW3P9mpcWjI7lNcX7PnUpBYL4zKefFnDWcjHwwm2k=; b=FT1XUpu673uFvPefqNZiIbbghnpQoNT9IiCOh0mUm7ligwuboQO2gK89geP++rllQt bmLIUex5p/xatbhhFUQuzceJEPNYuECa7fBcBUzB84rvjDST+PwNxzJt4XkdgZ+1sL8k 4gd4Ddg9a6q/A/aNUQZbRub4QYeDXguK5m6jBaT7YcQuFcNmyzVpdlGMdntD37NVjfMV 4CQH/0OGqHr+cQJMJhZGv7G/jJrhaBbchlVHQoJ1L6SzfbAlBWBhFuJEPWXHCNMomHC4 XRpZcnLps/SyATDvjzcCgJ+EmHImj6blYJeQLSS8PBGWkm1rRhdn1HNfS1x0Eurh2/Mz Brjw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@suse.com header.s=susede1 header.b=HexWFFQQ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=suse.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" , Michael Kelley Subject: [PATCH v5 10/15] x86/mtrr: add get_effective_type() service function Date: Sat, 1 Apr 2023 08:36:47 +0200 Message-Id: <20230401063652.23522-11-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230401063652.23522-1-jgross@suse.com> References: <20230401063652.23522-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761955242638261306?= X-GMAIL-MSGID: =?utf-8?q?1761955242638261306?= Add a service function for obtaining the effective cache mode of overlapping MTRR registers. Make use of that function in check_type_overlap(). Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V3: - new patch --- arch/x86/kernel/cpu/mtrr/generic.c | 39 +++++++++++++++--------------- 1 file changed, 19 insertions(+), 20 deletions(-) diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c index 5d60b46187f7..005f07ebb3a3 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -78,31 +78,30 @@ static u64 get_mtrr_size(u64 mask) return size; } +static u8 get_effective_type(u8 type1, u8 type2) +{ + if (type1 == MTRR_TYPE_UNCACHABLE || type2 == MTRR_TYPE_UNCACHABLE) + return MTRR_TYPE_UNCACHABLE; + + if ((type1 == MTRR_TYPE_WRBACK && type2 == MTRR_TYPE_WRTHROUGH) || + (type1 == MTRR_TYPE_WRTHROUGH && type2 == MTRR_TYPE_WRBACK)) + return MTRR_TYPE_WRTHROUGH; + + if (type1 != type2) + return MTRR_TYPE_UNCACHABLE; + + return type1; +} + /* * Check and return the effective type for MTRR-MTRR type overlap. - * Returns 1 if the effective type is UNCACHEABLE, else returns 0 + * Returns true if the effective type is UNCACHEABLE, else returns false */ -static int check_type_overlap(u8 *prev, u8 *curr) +static bool check_type_overlap(u8 *prev, u8 *curr) { - if (*prev == MTRR_TYPE_UNCACHABLE || *curr == MTRR_TYPE_UNCACHABLE) { - *prev = MTRR_TYPE_UNCACHABLE; - *curr = MTRR_TYPE_UNCACHABLE; - return 1; - } - - if ((*prev == MTRR_TYPE_WRBACK && *curr == MTRR_TYPE_WRTHROUGH) || - (*prev == MTRR_TYPE_WRTHROUGH && *curr == MTRR_TYPE_WRBACK)) { - *prev = MTRR_TYPE_WRTHROUGH; - *curr = MTRR_TYPE_WRTHROUGH; - } + *prev = *curr = get_effective_type(*curr, *prev); - if (*prev != *curr) { - *prev = MTRR_TYPE_UNCACHABLE; - *curr = MTRR_TYPE_UNCACHABLE; - return 1; - } - - return 0; + return *prev == MTRR_TYPE_UNCACHABLE; } /** From patchwork Sat Apr 1 06:36:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 78070 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1080684vqo; Sat, 1 Apr 2023 00:58:17 -0700 (PDT) X-Google-Smtp-Source: AKy350Y3uSPWDqVs/13TlafHqpdcGMS5uJrdvoIySAGYsSlsYdTiFSdQqTV/nFHms99NEebRv7IM X-Received: by 2002:aa7:c245:0:b0:4fb:279b:b38 with SMTP id y5-20020aa7c245000000b004fb279b0b38mr26352849edo.33.1680335897065; Sat, 01 Apr 2023 00:58:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680335897; cv=none; d=google.com; s=arc-20160816; b=t0+sLrDF+UJ7yW8kSf84/ETrvIPTT/tfKnIwsPpXEron73U7NrLov7dQVbVq9IMVdr a1MKK3O7eQ7vrkV2JpfDyyWkidiMTeSEdEcboeBd1on3XWicft2bsndv3C+AR1KSnjNz D8LSpTp1qWQeAHRa2bLA7zuSLzifNeiidENTFMSPuqLMWH567zUlOwom9XmJDuwks+n2 C0VbFoeSygBgHaMbzO0DT7Jtd3eYly3PPKbznkFnWyY30ULA9OftxlJceXOIwai8CY0p cI2GLrU9emUBzLRA5oC0uNx2q4/6bhm3UaQX9g6ToTefoS1/dNAzZ/jH5KEHlmSRl4pP /zgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=bwSaz6R/hqFIdk9RQ54LfqY77b02L677o5EAWpdjphI=; b=gsbh3jvKPiOPG9ky18FN3QuFmjMI3bQbLg8ZwDspF3GTVzJiZVMnJaTCKNNAov1THU SFsTFr0T8nN4EFEeyYh5tVy9gh6g6GF4YR5WUG+vmQK9JwFVjcpRNuUj2/XnOErUIhTj 5i/4EDYW36KlE/FU53otgI++uoJt6VHyGzhG0Fyftx3z1HX2HM/t04QhLwepMUWm8uuQ NaPwfeW5g8Zvh/yvc3iuUtsGSsNKuwFFig4lfog7wtZILAgLeFwN5XcY0sCBWR+DJMkL qUtSVcnYL/K8WVKOSNkOVMfdS9PpZsHX+QvRxLu/gr5OrEEIbAwxQmrVxAiMBDPH69mO /5hg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@suse.com header.s=susede1 header.b="swx/QoA+"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=suse.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" , Michael Kelley Subject: [PATCH v5 11/15] x86/mtrr: construct a memory map with cache modes Date: Sat, 1 Apr 2023 08:36:48 +0200 Message-Id: <20230401063652.23522-12-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230401063652.23522-1-jgross@suse.com> References: <20230401063652.23522-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761959893115412466?= X-GMAIL-MSGID: =?utf-8?q?1761959893115412466?= After MTRR initialization construct a memory map with cache modes from MTRR values. This will speed up lookups via mtrr_lookup_type() especially in case of overlapping MTRRs. This will be needed when switching the semantics of the "uniform" parameter of mtrr_lookup_type() from "only covered by one MTRR" to "memory range has a uniform cache mode", which is the data the callers really want to know. Today this information is not easily available, in case MTRRs are not well sorted regarding base address. The map will be built in __initdata. When memory management is up, the map will be moved to dynamically allocated memory, in order to avoid the need of an overly large array. The size of this array is calculated using the number of variable MTRR registers and the needed size for fixed entries. Only add the map creation and expansion for now. The lookup will be added later. When writing new MTRR entries in the running system rebuild the map inside the call from mtrr_rendezvous_handler() in order to avoid nasty race conditions with concurrent lookups. Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V3: - new patch V5: - fix setting of mtrr_tom2 - change cache_map .type and .fixed to bitfields (Boris Petkov) - use memmove() (Boris Petkov) - a lot of comments (Boris Petkov) - rewrite setting of merge bools (Boris Petkov) - mark mtrr_build_map() as __init - add pr_info() (Boris Petkov) --- arch/x86/kernel/cpu/mtrr/generic.c | 288 +++++++++++++++++++++++++++++ arch/x86/kernel/cpu/mtrr/mtrr.c | 10 +- arch/x86/kernel/cpu/mtrr/mtrr.h | 3 + 3 files changed, 300 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c index 005f07ebb3a3..fe8238832095 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -33,6 +33,38 @@ static struct fixed_range_block fixed_range_blocks[] = { {} }; +struct cache_map { + u64 start; + u64 end; + u64 flags; + u64 type:8; + u64 fixed:1; +}; + +/* + * CACHE_MAP_MAX is the maximum number of memory ranges in cache_map, where + * no 2 adjacent ranges have the same cache mode (those would be merged). + * The number is based on the worst case: + * - no two adjacent fixed MTRRs share the same cache mode + * - one variable MTRR is spanning a huge area with mode WB + * - 255 variable MTRRs with mode UC all overlap with the WB MTRR, creating 2 + * additional ranges each (result like "ababababa...aba" with a = WB, b = UC), + * accounting for MTRR_MAX_VAR_RANGES * 2 - 1 range entries + * - a TOM2 area (even with overlapping an UC MTRR can't add 2 range entries + * to the possible maximum, as it always starts at 4GB, thus it can't be in + * the middle of that MTRR, unless that MTRR starts at 0, which would remove + * the initial "a" from the "abababa" pattern above) + * The map won't contain ranges with no matching MTRR (those fall back to the + * default cache mode). + */ +#define CACHE_MAP_MAX (MTRR_NUM_FIXED_RANGES + MTRR_MAX_VAR_RANGES * 2) + +static struct cache_map init_cache_map[CACHE_MAP_MAX] __initdata; +static struct cache_map *cache_map __refdata = init_cache_map; +static unsigned int cache_map_size = CACHE_MAP_MAX; +static unsigned int cache_map_n; +static unsigned int cache_map_fixed; + static unsigned long smp_changes_mask; static int mtrr_state_set; u64 mtrr_tom2; @@ -78,6 +110,20 @@ static u64 get_mtrr_size(u64 mask) return size; } +static u8 get_var_mtrr_state(unsigned int reg, u64 *start, u64 *size) +{ + struct mtrr_var_range *mtrr = mtrr_state.var_ranges + reg; + + if (!(mtrr->mask_lo & MTRR_MASK_VALID)) + return MTRR_TYPE_INVALID; + + *start = (((u64)mtrr->base_hi) << 32) + (mtrr->base_lo & PAGE_MASK); + *size = get_mtrr_size((((u64)mtrr->mask_hi) << 32) + + (mtrr->mask_lo & PAGE_MASK)); + + return mtrr->base_lo & MTRR_BASE_TYPE_MASK; +} + static u8 get_effective_type(u8 type1, u8 type2) { if (type1 == MTRR_TYPE_UNCACHABLE || type2 == MTRR_TYPE_UNCACHABLE) @@ -242,6 +288,244 @@ static u8 mtrr_type_lookup_variable(u64 start, u64 end, u64 *partial_end, return mtrr_state.def_type; } +static void rm_map_entry_at(int idx) +{ + cache_map_n--; + memmove(cache_map + idx, cache_map + idx + 1, + sizeof(*cache_map) * (cache_map_n - idx)); +} + +/* + * Add an entry into cache_map at a specific index. Merges adjacent entries if + * appropriate. Return the number of merges for correcting the scan index + * (this is needed as merging will reduce the number of entries, which will + * result in skipping entries in future iterations if the scan index isn't + * corrected). + * Note that the corrected index can never go below -1 (resulting in being 0 in + * the next scan iteration), as "2" is returned only if the current index is + * larger than zero. + */ +static int add_map_entry_at(u64 start, u64 end, u8 type, int idx) +{ + bool merge_prev = false, merge_next = false; + + if (start >= end) + return 0; + + if (idx > 0) { + struct cache_map *prev = cache_map + idx - 1; + + if (!prev->fixed && start == prev->end && type == prev->type) + merge_prev = true; + } + + if (idx < cache_map_n) { + struct cache_map *next = cache_map + idx; + + if (!next->fixed && end == next->start && type == next->type) + merge_next = true; + } + + if (merge_prev && merge_next) { + cache_map[idx - 1].end = cache_map[idx].end; + rm_map_entry_at(idx); + return 2; + } + if (merge_prev) { + cache_map[idx - 1].end = end; + return 1; + } + if (merge_next) { + cache_map[idx].start = start; + return 1; + } + + /* Sanity check: the array should NEVER be too small! */ + if (cache_map_n == cache_map_size) { + WARN(1, "MTRR cache mode memory map exhausted!\n"); + cache_map_n = cache_map_fixed; + return 0; + } + + memmove(cache_map + idx + 1, cache_map + idx, + sizeof(*cache_map) * (cache_map_n - idx)); + + cache_map[idx].start = start; + cache_map[idx].end = end; + cache_map[idx].type = type; + cache_map[idx].fixed = 0; + cache_map_n++; + + return 0; +} + +/* Clear a part of an entry. Return 1 if start of entry is still valid. */ +static int clr_map_range_at(u64 start, u64 end, int idx) +{ + int ret = start != cache_map[idx].start; + u64 tmp; + + if (start == cache_map[idx].start && end == cache_map[idx].end) { + rm_map_entry_at(idx); + } else if (start == cache_map[idx].start) { + cache_map[idx].start = end; + } else if (end == cache_map[idx].end) { + cache_map[idx].end = start; + } else { + tmp = cache_map[idx].end; + cache_map[idx].end = start; + add_map_entry_at(end, tmp, cache_map[idx].type, idx + 1); + } + + return ret; +} + +/* + * Add MTRR to the map. The current map is scanned and each part of the MTRR + * either overlapping with an existing entry or with a hole in the map is + * handled separately. + */ +static void add_map_entry(u64 start, u64 end, u8 type) +{ + u8 new_type, old_type; + u64 tmp; + int i; + + for (i = 0; i < cache_map_n && start < end; i++) { + if (start >= cache_map[i].end) + continue; + + if (start < cache_map[i].start) { + /* Region start has no overlap. */ + tmp = min(end, cache_map[i].start); + i -= add_map_entry_at(start, tmp, type, i); + start = tmp; + continue; + } + + new_type = get_effective_type(type, cache_map[i].type); + old_type = cache_map[i].type; + + if (cache_map[i].fixed || new_type == old_type) { + /* Cut off start of new entry. */ + start = cache_map[i].end; + continue; + } + + /* Handle only overlapping part of region. */ + tmp = min(end, cache_map[i].end); + i += clr_map_range_at(start, tmp, i); + i -= add_map_entry_at(start, tmp, new_type, i); + start = tmp; + } + + /* Add rest of region after last map entry (rest might be empty). */ + add_map_entry_at(start, end, type, i); +} + +/* Add variable MTRRs to cache map. */ +static void map_add_var(void) +{ + u64 start, size; + unsigned int i; + u8 type; + + /* + * Add AMD TOM2 MTRR. Can't be added in mtrr_build_map(), as it needs + * to be added again when rebuilding the map due to potentially having + * moved as a result of variable MTRRs for memory below 4GB. + */ + if (mtrr_tom2) { + add_map_entry(BIT_ULL(32), mtrr_tom2, MTRR_TYPE_WRBACK); + cache_map[cache_map_n - 1].fixed = 1; + } + + for (i = 0; i < num_var_ranges; i++) { + type = get_var_mtrr_state(i, &start, &size); + if (type != MTRR_TYPE_INVALID) + add_map_entry(start, start + size, type); + } +} + +/* Rebuild map by replacing variable entries. */ +static void rebuild_map(void) +{ + cache_map_n = cache_map_fixed; + + map_add_var(); +} + +static unsigned int __init get_cache_map_size(void) +{ + return cache_map_fixed + 2 * num_var_ranges + (mtrr_tom2 != 0); +} + +/* Build the cache_map containing the cache modes per memory range. */ +void __init mtrr_build_map(void) +{ + u64 start, end, size; + unsigned int i; + u8 type; + + if (!mtrr_state.enabled) + return; + + /* Add fixed MTRRs, optimize for adjacent entries with same type. */ + if (mtrr_state.enabled & MTRR_STATE_MTRR_FIXED_ENABLED) { + /* + * Start with 64k size fixed entries, preset 1st one (hence the + * loop below is starting with index 1). + */ + start = 0; + end = size = 0x10000; + type = mtrr_state.fixed_ranges[0]; + + for (i = 1; i < MTRR_NUM_FIXED_RANGES; i++) { + /* 8 64k entries, then 16 16k ones, rest 4k. */ + if (i == 8 || i == 24) + size >>= 2; + + if (mtrr_state.fixed_ranges[i] != type) { + add_map_entry(start, end, type); + start = end; + type = mtrr_state.fixed_ranges[i]; + } + end += size; + } + add_map_entry(start, end, type); + } + + /* Mark fixed, they take precedence. */ + for (i = 0; i < cache_map_n; i++) + cache_map[i].fixed = 1; + cache_map_fixed = cache_map_n; + + map_add_var(); + + pr_info("MTRR map: %u entries (%u fixed + %u variable; max %u), built from %u variable MTRRs\n", + cache_map_n, cache_map_fixed, cache_map_n - cache_map_fixed, + get_cache_map_size(), num_var_ranges + (mtrr_tom2 != 0)); +} + +/* Copy the cache_map from __initdata memory to dynamically allocated one. */ +void __init mtrr_copy_map(void) +{ + unsigned int new_size = get_cache_map_size(); + + if (!mtrr_state.enabled || !new_size) { + cache_map = NULL; + return; + } + + mutex_lock(&mtrr_mutex); + + cache_map = kcalloc(new_size, sizeof(*cache_map), GFP_KERNEL); + memmove(cache_map, init_cache_map, cache_map_n * sizeof(*cache_map)); + cache_map_size = new_size; + + mutex_unlock(&mtrr_mutex); +} + /** * mtrr_overwrite_state - set static MTRR state * @@ -834,6 +1118,10 @@ static void generic_set_mtrr(unsigned int reg, unsigned long base, cache_enable(); local_irq_restore(flags); + + /* On the first CPU rebuild the cache mode memory map. */ + if (smp_processor_id() == cpumask_first(cpu_online_mask)) + rebuild_map(); } int generic_validate_add_page(unsigned long base, unsigned long size, diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtrr.c index 76f5b5e1128b..d44e4c2670cc 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -65,7 +65,7 @@ static bool mtrr_enabled(void) } unsigned int mtrr_usage_table[MTRR_MAX_VAR_RANGES]; -static DEFINE_MUTEX(mtrr_mutex); +DEFINE_MUTEX(mtrr_mutex); u64 size_or_mask, size_and_mask; @@ -660,6 +660,7 @@ void __init mtrr_bp_init(void) /* Software overwrite of MTRR state, only for generic case. */ mtrr_calc_physbits(true); init_table(); + mtrr_build_map(); pr_info("MTRRs set to read-only\n"); return; @@ -697,6 +698,7 @@ void __init mtrr_bp_init(void) if (get_mtrr_state()) { memory_caching_control |= CACHE_MTRR; changed_by_mtrr_cleanup = mtrr_cleanup(phys_addr); + mtrr_build_map(); } else { mtrr_if = NULL; why = "by BIOS"; @@ -725,6 +727,12 @@ void mtrr_save_state(void) static int __init mtrr_init_finialize(void) { + /* + * Map might exist if mtrr_overwrite_state() has been called or if + * mtrr_enabled() returns true. + */ + mtrr_copy_map(); + if (!mtrr_enabled()) return 0; diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.h b/arch/x86/kernel/cpu/mtrr/mtrr.h index a3c362d3d5bf..6246a1d8650b 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.h +++ b/arch/x86/kernel/cpu/mtrr/mtrr.h @@ -53,6 +53,7 @@ bool get_mtrr_state(void); extern u64 size_or_mask, size_and_mask; extern const struct mtrr_ops *mtrr_if; +extern struct mutex mtrr_mutex; extern unsigned int num_var_ranges; extern u64 mtrr_tom2; @@ -61,6 +62,8 @@ extern struct mtrr_state_type mtrr_state; void mtrr_state_warn(void); const char *mtrr_attrib_to_str(int x); void mtrr_wrmsr(unsigned, unsigned, unsigned); +void mtrr_build_map(void); +void mtrr_copy_map(void); /* CPU specific mtrr_ops vectors. */ extern const struct mtrr_ops amd_mtrr_ops; From patchwork Sat Apr 1 06:36:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 78065 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1074662vqo; Sat, 1 Apr 2023 00:39:14 -0700 (PDT) X-Google-Smtp-Source: AKy350aFIsL1j3Y2kNf5jAF4Uj/Lgm7FKWpAhi5Z7SMybbCJSntqYEugj8P/GS9KlGW1n8NrUpJQ X-Received: by 2002:a05:6402:1149:b0:4fc:5888:473a with SMTP id g9-20020a056402114900b004fc5888473amr29948335edw.9.1680334753778; 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Peter Anvin" , Michael Kelley Subject: [PATCH v5 12/15] x86/mtrr: use new cache_map in mtrr_type_lookup() Date: Sat, 1 Apr 2023 08:36:49 +0200 Message-Id: <20230401063652.23522-13-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230401063652.23522-1-jgross@suse.com> References: <20230401063652.23522-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761958694263097045?= X-GMAIL-MSGID: =?utf-8?q?1761958694263097045?= Instead of crawling through the MTRR register state, use the new cache_map for looking up the cache type(s) of a memory region. This allows now to set the uniform parameter according to the uniformity of the cache mode of the region, instead of setting it only if the complete region is mapped by a single MTRR. This now includes even the region covered by the fixed MTRR registers. Make sure uniform is always set. Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V3: - new patch V3.1: - fix type_merge() (Michael Kelley) V4: - fix type_merge() again (Michael Kelley) --- arch/x86/kernel/cpu/mtrr/generic.c | 228 ++++------------------------- 1 file changed, 32 insertions(+), 196 deletions(-) diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c index fe8238832095..5d502b926dd8 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -139,155 +139,6 @@ static u8 get_effective_type(u8 type1, u8 type2) return type1; } -/* - * Check and return the effective type for MTRR-MTRR type overlap. - * Returns true if the effective type is UNCACHEABLE, else returns false - */ -static bool check_type_overlap(u8 *prev, u8 *curr) -{ - *prev = *curr = get_effective_type(*curr, *prev); - - return *prev == MTRR_TYPE_UNCACHABLE; -} - -/** - * mtrr_type_lookup_fixed - look up memory type in MTRR fixed entries - * - * Return the MTRR fixed memory type of 'start'. - * - * MTRR fixed entries are divided into the following ways: - * 0x00000 - 0x7FFFF : This range is divided into eight 64KB sub-ranges - * 0x80000 - 0xBFFFF : This range is divided into sixteen 16KB sub-ranges - * 0xC0000 - 0xFFFFF : This range is divided into sixty-four 4KB sub-ranges - * - * Return Values: - * MTRR_TYPE_(type) - Matched memory type - * MTRR_TYPE_INVALID - Unmatched - */ -static u8 mtrr_type_lookup_fixed(u64 start, u64 end) -{ - int idx; - - if (start >= 0x100000) - return MTRR_TYPE_INVALID; - - /* 0x0 - 0x7FFFF */ - if (start < 0x80000) { - idx = 0; - idx += (start >> 16); - return mtrr_state.fixed_ranges[idx]; - /* 0x80000 - 0xBFFFF */ - } else if (start < 0xC0000) { - idx = 1 * 8; - idx += ((start - 0x80000) >> 14); - return mtrr_state.fixed_ranges[idx]; - } - - /* 0xC0000 - 0xFFFFF */ - idx = 3 * 8; - idx += ((start - 0xC0000) >> 12); - return mtrr_state.fixed_ranges[idx]; -} - -/** - * mtrr_type_lookup_variable - look up memory type in MTRR variable entries - * - * Return Value: - * MTRR_TYPE_(type) - Matched memory type or default memory type (unmatched) - * - * Output Arguments: - * repeat - Set to 1 when [start:end] spanned across MTRR range and type - * returned corresponds only to [start:*partial_end]. Caller has - * to lookup again for [*partial_end:end]. - * - * uniform - Set to 1 when an MTRR covers the region uniformly, i.e. the - * region is fully covered by a single MTRR entry or the default - * type. - */ -static u8 mtrr_type_lookup_variable(u64 start, u64 end, u64 *partial_end, - int *repeat, u8 *uniform) -{ - int i; - u64 base, mask; - u8 prev_match, curr_match; - - *repeat = 0; - *uniform = 1; - - prev_match = MTRR_TYPE_INVALID; - for (i = 0; i < num_var_ranges; ++i) { - unsigned short start_state, end_state, inclusive; - - if (!(mtrr_state.var_ranges[i].mask_lo & MTRR_MASK_VALID)) - continue; - - base = (((u64)mtrr_state.var_ranges[i].base_hi) << 32) + - (mtrr_state.var_ranges[i].base_lo & PAGE_MASK); - mask = (((u64)mtrr_state.var_ranges[i].mask_hi) << 32) + - (mtrr_state.var_ranges[i].mask_lo & PAGE_MASK); - - start_state = ((start & mask) == (base & mask)); - end_state = ((end & mask) == (base & mask)); - inclusive = ((start < base) && (end > base)); - - if ((start_state != end_state) || inclusive) { - /* - * We have start:end spanning across an MTRR. - * We split the region into either - * - * - start_state:1 - * (start:mtrr_end)(mtrr_end:end) - * - end_state:1 - * (start:mtrr_start)(mtrr_start:end) - * - inclusive:1 - * (start:mtrr_start)(mtrr_start:mtrr_end)(mtrr_end:end) - * - * depending on kind of overlap. - * - * Return the type of the first region and a pointer - * to the start of next region so that caller will be - * advised to lookup again after having adjusted start - * and end. - * - * Note: This way we handle overlaps with multiple - * entries and the default type properly. - */ - if (start_state) - *partial_end = base + get_mtrr_size(mask); - else - *partial_end = base; - - if (unlikely(*partial_end <= start)) { - WARN_ON(1); - *partial_end = start + PAGE_SIZE; - } - - end = *partial_end - 1; /* end is inclusive */ - *repeat = 1; - *uniform = 0; - } - - if ((start & mask) != (base & mask)) - continue; - - curr_match = mtrr_state.var_ranges[i].base_lo & - MTRR_BASE_TYPE_MASK; - if (prev_match == MTRR_TYPE_INVALID) { - prev_match = curr_match; - continue; - } - - *uniform = 0; - if (check_type_overlap(&prev_match, &curr_match)) - return curr_match; - } - - if (prev_match != MTRR_TYPE_INVALID) - return prev_match; - - return mtrr_state.def_type; -} - static void rm_map_entry_at(int idx) { cache_map_n--; @@ -580,6 +431,20 @@ void mtrr_overwrite_state(struct mtrr_var_range *var, unsigned int num_var, mtrr_state_set = 1; } +static u8 type_merge(u8 type, u8 new_type, u8 *uniform) +{ + u8 effective_type; + + if (type == MTRR_TYPE_INVALID) + return new_type; + + effective_type = get_effective_type(type, new_type); + if (type != effective_type) + *uniform = 0; + + return effective_type; +} + /** * mtrr_type_lookup - look up memory type in MTRR * @@ -588,66 +453,37 @@ void mtrr_overwrite_state(struct mtrr_var_range *var, unsigned int num_var, * MTRR_TYPE_INVALID - MTRR is disabled * * Output Argument: - * uniform - Set to 1 when an MTRR covers the region uniformly, i.e. the - * region is fully covered by a single MTRR entry or the default - * type. + * uniform - Set to 1 when the returned MTRR type is valid for the whole + * region, set to 0 else. */ u8 mtrr_type_lookup(u64 start, u64 end, u8 *uniform) { - u8 type, prev_type, is_uniform = 1, dummy; - int repeat; - u64 partial_end; - - /* Make end inclusive instead of exclusive */ - end--; + u8 type = MTRR_TYPE_INVALID; + unsigned int i; - if (!mtrr_state_set) + if (!mtrr_state_set) { + *uniform = 0; /* Uniformity is unknown. */ return MTRR_TYPE_INVALID; + } + + *uniform = 1; if (!(mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED)) return MTRR_TYPE_INVALID; - /* - * Look up the fixed ranges first, which take priority over - * the variable ranges. - */ - if ((start < 0x100000) && - (mtrr_state.have_fixed) && - (mtrr_state.enabled & MTRR_STATE_MTRR_FIXED_ENABLED)) { - is_uniform = 0; - type = mtrr_type_lookup_fixed(start, end); - goto out; - } - - /* - * Look up the variable ranges. Look of multiple ranges matching - * this address and pick type as per MTRR precedence. - */ - type = mtrr_type_lookup_variable(start, end, &partial_end, - &repeat, &is_uniform); + for (i = 0; i < cache_map_n && start < end; i++) { + if (start >= cache_map[i].end) + continue; + if (start < cache_map[i].start) + type = type_merge(type, mtrr_state.def_type, uniform); + type = type_merge(type, cache_map[i].type, uniform); - /* - * Common path is with repeat = 0. - * However, we can have cases where [start:end] spans across some - * MTRR ranges and/or the default type. Do repeated lookups for - * that case here. - */ - while (repeat) { - prev_type = type; - start = partial_end; - is_uniform = 0; - type = mtrr_type_lookup_variable(start, end, &partial_end, - &repeat, &dummy); - - if (check_type_overlap(&prev_type, &type)) - goto out; + start = cache_map[i].end; } - if (mtrr_tom2 && (start >= (1ULL<<32)) && (end < mtrr_tom2)) - type = MTRR_TYPE_WRBACK; + if (start < end) + type = type_merge(type, mtrr_state.def_type, uniform); -out: - *uniform = is_uniform; return type; } From patchwork Sat Apr 1 06:36:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 78067 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1077705vqo; Sat, 1 Apr 2023 00:49:01 -0700 (PDT) X-Google-Smtp-Source: AKy350ZRDgVIJnlMKzsxpfYLcvMFA7UAGac9Yzmy55+nLZ/gJq8hcGFfLR2eIfdvN162+WadZCbA X-Received: by 2002:a17:906:71d7:b0:8a6:5720:9101 with SMTP id i23-20020a17090671d700b008a657209101mr31019112ejk.4.1680335341555; Sat, 01 Apr 2023 00:49:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680335341; cv=none; d=google.com; s=arc-20160816; b=fI/vNyoKp7C8S+KAvubJuYXz+Rh2NlH8E+01G34vxvkJysB5lhG86NpEXoO0ranloY yD9KVNlG2SZFHOP4yxUt/BBuLIWM58lB12YimDmfzI/TdG9K/GSaNbNuDoaOCO3jxkmI 7Ycxc898qRepFsJW6F3m+NOB6SvRUf7n3JkHOndHqsTm6pvWNHMMi44JsDWocTq0OUYX 6qz2wMrAi8y8DEp8/gUioHm7fzYmB9eCJFPSuJQ2ufWjU3ohI2ui3yozHck5uij3JwGq 7TGawOWTz5az05nFGSKA9GPbiltcA/LPABpbm/Csc8KbW0RG5/tW/ZQlqlBaIcmwUO8H KYAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=V3mHtqPo7I900IUU9mKC4TzJ6vMfpxeByTBPYTni3oA=; b=R8LxeU4Ljm4gOGLJDG5bn+FNeyqHDvXd03DvkDC76FPtW5oJxQLivN5HBgv4bEiq++ S2J+jGDMtC//2ncVRFMkbNx85d/f14ivFRkbTE8GKsFi6hN6zfuS7jJwvR6YL2YIcJPq LDhvGP8ug2o5wihd6D5p5mR0MMBZG4lflbPGbU8K3oI6DYKF14BINVabkiN70s3aHXE3 solyAgTVzvTOP2Foyd+XB5gqdNG7nr5PNdWXvzynBTFFB4cKrBzQhWoKPlNLa5mFY7Ip ZOjf8Wusfu0ENcgZ/crBsXwqIKILiV2W0BHzXhF9aAsDPvg/5k8GApWoVAuXvat9C0UJ /rQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@suse.com header.s=susede1 header.b=vLYErCtx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=suse.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" , Linus Torvalds , Michael Kelley Subject: [PATCH v5 13/15] x86/mtrr: don't let mtrr_type_lookup() return MTRR_TYPE_INVALID Date: Sat, 1 Apr 2023 08:36:50 +0200 Message-Id: <20230401063652.23522-14-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230401063652.23522-1-jgross@suse.com> References: <20230401063652.23522-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761959311068410448?= X-GMAIL-MSGID: =?utf-8?q?1761959311068410448?= mtrr_type_lookup() should always return a valid memory type. In case there is no information available, it should return the default UC. This will remove the last case where mtrr_type_lookup() can return MTRR_TYPE_INVALID, so adjust the comment in include/uapi/asm/mtrr.h. Note that removing the MTRR_TYPE_INVALID #define from that header could break user code, so it has to stay. At the same time the mtrr_type_lookup() stub for the !CONFIG_MTRR case should set uniform to 1, as if the memory range would be covered by no MTRR at all. Suggested-by: Linus Torvalds Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V2: - always set uniform - set uniform to 1 in case of disabled MTRRs (Linus Torvalds) V3: - adjust include/uapi/asm/mtrr.h comment --- arch/x86/include/asm/mtrr.h | 7 +++++-- arch/x86/include/uapi/asm/mtrr.h | 6 +++--- arch/x86/kernel/cpu/mtrr/generic.c | 4 ++-- 3 files changed, 10 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index 6decb18e22ed..b17a66da1237 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -77,9 +77,12 @@ static inline void mtrr_overwrite_state(struct mtrr_var_range *var, static inline u8 mtrr_type_lookup(u64 addr, u64 end, u8 *uniform) { /* - * Return no-MTRRs: + * Return the default MTRR type, without any known other types in + * that range. */ - return MTRR_TYPE_INVALID; + *uniform = 1; + + return MTRR_TYPE_UNCACHABLE; } #define mtrr_save_fixed_ranges(arg) do {} while (0) #define mtrr_save_state() do {} while (0) diff --git a/arch/x86/include/uapi/asm/mtrr.h b/arch/x86/include/uapi/asm/mtrr.h index 376563f2bac1..4aa05c2ffa78 100644 --- a/arch/x86/include/uapi/asm/mtrr.h +++ b/arch/x86/include/uapi/asm/mtrr.h @@ -115,9 +115,9 @@ struct mtrr_state_type { #define MTRR_NUM_TYPES 7 /* - * Invalid MTRR memory type. mtrr_type_lookup() returns this value when - * MTRRs are disabled. Note, this value is allocated from the reserved - * values (0x7-0xff) of the MTRR memory types. + * Invalid MTRR memory type. No longer used outside of MTRR code. + * Note, this value is allocated from the reserved values (0x7-0xff) of + * the MTRR memory types. */ #define MTRR_TYPE_INVALID 0xff diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c index 5d502b926dd8..178253d117c6 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -463,13 +463,13 @@ u8 mtrr_type_lookup(u64 start, u64 end, u8 *uniform) if (!mtrr_state_set) { *uniform = 0; /* Uniformity is unknown. */ - return MTRR_TYPE_INVALID; + return MTRR_TYPE_UNCACHABLE; } *uniform = 1; if (!(mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED)) - return MTRR_TYPE_INVALID; + return MTRR_TYPE_UNCACHABLE; for (i = 0; i < cache_map_n && start < end; i++) { if (start >= cache_map[i].end) From patchwork Sat Apr 1 06:36:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 78064 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1064776vqo; Sat, 1 Apr 2023 00:10:55 -0700 (PDT) X-Google-Smtp-Source: AKy350ZqkTAYO1MNGRyXL73RoMZfFAGUNVDjejE+WT/m61uyA1gEh80R/tlq9wNnUf3OvJ78TEBb X-Received: by 2002:a17:903:2448:b0:1a0:5349:6606 with SMTP id l8-20020a170903244800b001a053496606mr35153694pls.56.1680333055740; Sat, 01 Apr 2023 00:10:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680333055; cv=none; d=google.com; s=arc-20160816; b=tS+FKFE7uxHRKUcCvB/A9rtH5cQG1u09o2CdvlzQA/gn7kwLahKoo8+QW1f5KWu0UY dDQ3jqPYQXr2X/2eHRC41rCafI7RX8P63Ov6hsloJh2tLXLQ6cs4cmzEJWJp1M+TwNFN brzyf/U+FEf6M8ZCcP7nzOPHmDBSD7D7cewt/xLzn5HSQzzi+WP4PD16JCNy121E0W4C v7pUxoW+ZqBSXd3AguJdKoccaGXVmvFvjjPWHlWSHET/1cPDT9O7gJYt9mVzQbfbRHjU SFvH94WNkRP2xwbVh7iUosKgbhpgBrKGuYhNcni9/xtEsfYu6yo4LntSefkTnIx2+4MI X7pw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=PLhZnRzaTF/w19VvaTwREzeMUwLtgou6VVO1Iy9aXOI=; b=VwF4N4RRZ+UOVtCEZbQau6R0SoCNcP5VoBo0/9SuhHE83jl6TmMKb/ygE3SS6BLHlS kYP+MD+GuKXmGI5JGn8GQSqXaReAIc/QExaPlH5jhnYZqyml32DAZI68l0dYbSLbshYi m67wFd7S/u1boz1le/rHJtQSbonb5lL4kjEHsq2YLatn+XYKsM/ccFYG/ZSWtXgce0tZ rj77moX4xYYB63dDDa70DOJmZeWSl4n3jmynzdW6Smwv9fsFScAPenJIcrwURTDiZVKb 7aDmzWXxoasR21yiBdhEsAQE2PIlKmLLjHKEkw3XJ9hUZab+DqyswgCyh3M5swFqkqyS XgLQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@suse.com header.s=susede1 header.b=hlJX4+mn; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=suse.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" , Linus Torvalds , Michael Kelley Subject: [PATCH v5 14/15] x86/mm: only check uniform after calling mtrr_type_lookup() Date: Sat, 1 Apr 2023 08:36:51 +0200 Message-Id: <20230401063652.23522-15-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230401063652.23522-1-jgross@suse.com> References: <20230401063652.23522-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761956914353488829?= X-GMAIL-MSGID: =?utf-8?q?1761956914353488829?= Today pud_set_huge() and pmd_set_huge() test for the MTRR type to be WB or INVALID after calling mtrr_type_lookup(). Those tests can be dropped, as the only reason to not use a large mapping would be uniform being 0. Any MTRR type can be accepted as long as it applies to the whole memory range covered by the mapping, as the alternative would only be to map the same region with smaller pages instead, using the same PAT type as for the large mapping. Suggested-by: Linus Torvalds Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V3: - adapt comment for pud_set_huge() --- arch/x86/mm/pgtable.c | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c index e4f499eb0f29..15a8009a4480 100644 --- a/arch/x86/mm/pgtable.c +++ b/arch/x86/mm/pgtable.c @@ -702,14 +702,8 @@ void p4d_clear_huge(p4d_t *p4d) * pud_set_huge - setup kernel PUD mapping * * MTRRs can override PAT memory types with 4KiB granularity. Therefore, this - * function sets up a huge page only if any of the following conditions are met: - * - * - MTRRs are disabled, or - * - * - MTRRs are enabled and the range is completely covered by a single MTRR, or - * - * - MTRRs are enabled and the corresponding MTRR memory type is WB, which - * has no effect on the requested PAT memory type. + * function sets up a huge page only if the complete range has the same MTRR + * caching mode. * * Callers should try to decrease page size (1GB -> 2MB -> 4K) if the bigger * page mapping attempt fails. @@ -718,11 +712,10 @@ void p4d_clear_huge(p4d_t *p4d) */ int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot) { - u8 mtrr, uniform; + u8 uniform; - mtrr = mtrr_type_lookup(addr, addr + PUD_SIZE, &uniform); - if ((mtrr != MTRR_TYPE_INVALID) && (!uniform) && - (mtrr != MTRR_TYPE_WRBACK)) + mtrr_type_lookup(addr, addr + PUD_SIZE, &uniform); + if (!uniform) return 0; /* Bail out if we are we on a populated non-leaf entry: */ @@ -745,11 +738,10 @@ int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot) */ int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot) { - u8 mtrr, uniform; + u8 uniform; - mtrr = mtrr_type_lookup(addr, addr + PMD_SIZE, &uniform); - if ((mtrr != MTRR_TYPE_INVALID) && (!uniform) && - (mtrr != MTRR_TYPE_WRBACK)) { + mtrr_type_lookup(addr, addr + PMD_SIZE, &uniform); + if (!uniform) { pr_warn_once("%s: Cannot satisfy [mem %#010llx-%#010llx] with a huge-page mapping due to MTRR override.\n", __func__, addr, addr + PMD_SIZE); return 0; From patchwork Sat Apr 1 06:36:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 78073 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1099630vqo; Sat, 1 Apr 2023 01:48:24 -0700 (PDT) X-Google-Smtp-Source: AKy350aBLjh2iAsNGKvYmfmoS6pZhE7TAzVWh5dh1rm+OczoJNEyqmviE5iVPlPpCz4RuEz9PWa/ X-Received: by 2002:a17:907:8a19:b0:947:fb8a:f2d2 with SMTP id sc25-20020a1709078a1900b00947fb8af2d2mr2083212ejc.62.1680338904216; Sat, 01 Apr 2023 01:48:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680338904; cv=none; d=google.com; s=arc-20160816; b=OUY9AaS9jTpDy8i9qOUeFb33MQwoDFkHqiNrunMM0owqjBqiDEcaY32m9ffNsx4GWw AyjxSGIDOdO5lc9c2RL1YhsKth06AZpLrigVr1tZe4jheon8cWZmuLPdSp1xPX/JVKZb gXWkYPU8XFivdJgGLKOAC5ypCv19WukgDvSz/gGydrTcKWgPLNs27B7gwprqwkYnFksl Mt7T/+q0Bgc4ELRqzmL/oBGsBvni3o+ajKCwkkhTIpG1HtCf7iZ0yhm5S+EfA0wjlBQK A8ydqDMXsBlMliSaj3KKjSTfgULy0UFPHvaWh3CBCxsS82O3VqlYms9SDFcVI1Ml+t8l CuHg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=E7DHxTtJvlqvZrPXbQiV8NhXaH2BVGP/WAcxWNnt620=; b=g5n9vj74tU86/ZIbQ5Gwp0En1oh5ONGVFNNHPca4Opr1gm97RPz9MatENQbrTBrUAv ZVM69vWnFhq9JI+Ll4du5gwcvPu+rNhQ1GcbxDBZbrhJ5pJ3CYJ2iQNhZM4T0tLlb4SH 3PDiNqGXUMaFnKN5QNXEU+pHKD7x8xUkNL+QGxvOMAhGQrUIQSmnXDtaVjI7MM2+B4O+ YIDs/bl+WghcNfhYrknj6xQwWSgesdjhzlf+i2l2PTzJIW7hsG1Mi8VD7LXcGYvjZJOz yMqAt9DI/2ZZ8IhuGuzrw8lC+9qHT3q3ra3056atq/iI2vraOYDHX0HIG62ILPf16yHv GzHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@suse.com header.s=susede1 header.b=G372kCwa; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=suse.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" Subject: [PATCH v5 15/15] x86/mtrr: remove unused code Date: Sat, 1 Apr 2023 08:36:52 +0200 Message-Id: <20230401063652.23522-16-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230401063652.23522-1-jgross@suse.com> References: <20230401063652.23522-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761963046895082601?= X-GMAIL-MSGID: =?utf-8?q?1761963046895082601?= mtrr_centaur_report_mcr() isn't used by anyone, so it can be removed. Signed-off-by: Juergen Gross --- V5: - new patch --- arch/x86/include/asm/mtrr.h | 4 ---- arch/x86/kernel/cpu/mtrr/centaur.c | 9 --------- 2 files changed, 13 deletions(-) diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index b17a66da1237..3aced3568e2b 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -60,7 +60,6 @@ extern int mtrr_add_page(unsigned long base, unsigned long size, unsigned int type, bool increment); extern int mtrr_del(int reg, unsigned long base, unsigned long size); extern int mtrr_del_page(int reg, unsigned long base, unsigned long size); -extern void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi); extern void mtrr_bp_restore(void); extern int mtrr_trim_uncached_memory(unsigned long end_pfn); extern int amd_special_default_mtrr(void); @@ -108,9 +107,6 @@ static inline int mtrr_trim_uncached_memory(unsigned long end_pfn) { return 0; } -static inline void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi) -{ -} #define mtrr_bp_init() do {} while (0) #define mtrr_bp_restore() do {} while (0) #define mtrr_disable() do {} while (0) diff --git a/arch/x86/kernel/cpu/mtrr/centaur.c b/arch/x86/kernel/cpu/mtrr/centaur.c index 4466ddeb0125..6f6c3ae92943 100644 --- a/arch/x86/kernel/cpu/mtrr/centaur.c +++ b/arch/x86/kernel/cpu/mtrr/centaur.c @@ -45,15 +45,6 @@ centaur_get_free_region(unsigned long base, unsigned long size, int replace_reg) return -ENOSPC; } -/* - * Report boot time MCR setups - */ -void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi) -{ - centaur_mcr[mcr].low = lo; - centaur_mcr[mcr].high = hi; -} - static void centaur_get_mcr(unsigned int reg, unsigned long *base, unsigned long *size, mtrr_type * type)