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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id dy20-20020a05640231f400b00502241c86afsi1503686edb.320.2023.03.30.23.59.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 23:59:20 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=fTuK+c9G; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DD5353858CDB for ; Fri, 31 Mar 2023 06:59:18 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DD5353858CDB DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1680245958; bh=vJexjoraD4cGCfHqSCGjKMIgydtkBK3syGRHZpZH6JM=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=fTuK+c9Gf2XbygHN5QVNqdqhJ/HopWBGbvJ6SzZQ3zlsWLUsyLTp+SrnCN+fg1kmM ozrEAxJx5UXa+bcB/1lYWH0pHm32TWW3ndINIymMC7nvOkEsNmWmM7z4eANRWnJ30L +B8mGGi4GvxlEMRUMQajRyPOG4nHk2j8nZm8Pwnw= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by sourceware.org (Postfix) with ESMTPS id DC64A3858D20 for ; Fri, 31 Mar 2023 06:58:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DC64A3858D20 X-IronPort-AV: E=McAfee;i="6600,9927,10665"; a="321031781" X-IronPort-AV: E=Sophos;i="5.98,307,1673942400"; d="scan'208";a="321031781" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2023 23:58:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10665"; a="796003182" X-IronPort-AV: E=Sophos;i="5.98,307,1673942400"; d="scan'208";a="796003182" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga002.fm.intel.com with ESMTP; 30 Mar 2023 23:58:10 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 1C7D2100519C; Fri, 31 Mar 2023 14:58:10 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: crazylht@gmail.com Subject: [PATCH] Document signbitm2. Date: Fri, 31 Mar 2023 14:58:10 +0800 Message-Id: <20230331065810.4012545-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.39.1.388.g2fc9e9ca3c MIME-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_PASS, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: liuhongt Reply-To: liuhongt Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761865588050143381?= X-GMAIL-MSGID: =?utf-8?q?1761865588050143381?= Look through all backends which defined signbitm2. 1. When m is a scalar mode, the dest is SImode. 2. When m is a vector mode, the dest mode is the vector integer mode has the same size and elements number as m. Ok for trunk? gcc/ChangeLog: * doc/md.texi: Document signbitm2. --- gcc/doc/md.texi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 8e3113599fd..edfa51e867a 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -6030,6 +6030,17 @@ floating-point mode. This pattern is not allowed to @code{FAIL}. +@cindex @code{signbit@var{m}2} instruction pattern +@item @samp{signbit@var{m}2} +Store the sign bit of floating-point operand 1 in operand 0. +@var{m} is either a scalar or vector mode. When it is a scalar, +operand 1 has mode @var{m} but operand 0 must have mode @code{SImode}. +When @var{m} is a vector, operand 1 has the mode @var{m}. +operand 0's mode should be an vector integer mode which has +the same number of elements and the same size as mode @var{m}. + +This pattern is not allowed to @code{FAIL}. + @cindex @code{significand@var{m}2} instruction pattern @item @samp{significand@var{m}2} Store the significand of floating-point operand 1 in operand 0.