From patchwork Thu Mar 30 23:25:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 77476 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp207138vqo; Thu, 30 Mar 2023 16:44:26 -0700 (PDT) X-Google-Smtp-Source: AKy350YyQHjgQ8AyPNoW+zbb9xYQJ8l8MGcx/YCXXQzuhxa4sJTIASw6DcglEsfxqgfzOnE7bzcp X-Received: by 2002:a17:90b:2247:b0:237:40a5:7acf with SMTP id hk7-20020a17090b224700b0023740a57acfmr27103773pjb.33.1680219866733; Thu, 30 Mar 2023 16:44:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680219866; cv=none; d=google.com; s=arc-20160816; b=jUIs1e1ElN6U4KrmG5jbJRyukoMcgowVP9m+h1X9REBGqI4tFO9aVZWD6Q7vR3SNaT AH5P7BE36MhW9WbS7WGBjMRdYCYVp2GToQlYIAFGFr8DoiVoSXX/Fe793fyYcI/fNj2s loZDDYLlI8LMusELYkJ30lAHY8gRdlYRKz/d52D7KH0x6OdqGc6ouWtIRrGQQdqVMab7 BFEV+dVI2hgh2sv/MoBSeyWpnBdzr2Upka78JYJj7gQ+Xb1X56ylp0YG/Lx/R4wk817i Q/wMfkRelPSRrWsj4ThMg9b5qTyeYNhz73cH08DUGcRI2IvH2kmXXUnBnUwiEiA3OjO2 XEeg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=Nm/XTs8kUm7gm8q4P4cfKXmAlTclT7Zyu7DRpRk628Y=; b=jAg7Aog4RZ4/sMB8rHomGa1KM4gfE4INSxQ4QApq1iFkg0Jv67S6wLRqZJfIIgLfTQ 4eNVdzwUbf/fcUz+9/ANUVCrGE/LHQ6D6OLyz3YtNJDb3ko9IsAqCIJ9uAiV2m9lsONG OiyUArF+YNNHGlrJYyhlIDtNHAgXiUbDVLbRUxZFo1D4igEsk6xC0e7rSXnFD5DkS3Wm Tzr9vKm6Gd/YlJDRdozyLhmsyoVTGlA/crZn8PSTTJMYNYH6Mx6s+gqxpU8L6ByVCrVr PMhev9FmBfYBbyD09EZzLvo5vWkJTOE0GLwBzvQeFo1br8KxlX4pmJRhzPa8ykmW4F2u IK5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BYtErKq2; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id iw12-20020a170903044c00b0019ceb4b753fsi695842plb.26.2023.03.30.16.44.14; Thu, 30 Mar 2023 16:44:26 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BYtErKq2; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231422AbjC3XZu (ORCPT + 99 others); Thu, 30 Mar 2023 19:25:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47790 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231134AbjC3XZg (ORCPT ); Thu, 30 Mar 2023 19:25:36 -0400 Received: from mail-lj1-x22b.google.com (mail-lj1-x22b.google.com [IPv6:2a00:1450:4864:20::22b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EEEFA6582 for ; Thu, 30 Mar 2023 16:25:24 -0700 (PDT) Received: by mail-lj1-x22b.google.com with SMTP id bx10so2963386ljb.8 for ; Thu, 30 Mar 2023 16:25:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680218723; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Nm/XTs8kUm7gm8q4P4cfKXmAlTclT7Zyu7DRpRk628Y=; b=BYtErKq2dxteRSgjjQL+mwZRyd9zpYOFbIkDF581CEse36BLDXFkH8njSk4IQuXWEl FiAzc9MEUl7bvHvZmnaEDyrZt1JDqnU3EMaeFm8qUnduETAyJbIAcixqy3df5pbsxgQu nslyToLngtR6nQnONdAPedi5+UWJgRNM7cRhMqFPZIqeeu5zMGa9KeH8aaLCBAqp6O7Q fczu6rgdZwaZ91EQFPyjbIV+OS8lQFWbR6Pm4qVJ/thRNQY1KqRzfkcPNzzsBK//aL7h oLNiyjA5grF+jUbmJmx2EgrWrIWs/uEfhy++vHFw8j1ZVaTbjJZPT2C7zVXHyf3BNoYB D6Lw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680218723; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Nm/XTs8kUm7gm8q4P4cfKXmAlTclT7Zyu7DRpRk628Y=; b=Rd9Y2SUHmfNNi6/TpzrrqJ57rLoRrSO+K1/Ukr6LIuiFRtfaXvnPALbBZCP7vR/9LX rKA2PlXZhoTZruOMg+tnARhlpY6ax3KRzChvo0XNjmCyodYAYepRyztdQux5ZYAmJpSZ ZdIAseJdwNFTPZchfE/fKRuzxnnKWJtzR3h50DsbibZASgQpKHpMx1viVWIJOvxmCILs lup26/43ip1Skp1ao37ctUyMWNUIpqdY7pOnfj8J0IUEkYNBAAq+n1lzuNZDeukC8eW+ afXfUR4+5LxEuoJugSvHZXqxdLLqaqSVMcNk2RqlS/9Sv+myqN0GJJQl2hcgm0cwFk94 OH9g== X-Gm-Message-State: AAQBX9eiT8DAlldZqc6LV5c8vNgKt+MnJwuDRjtl/kYKwo1tmxBhaqiz I54UiRKTN9InTL4WlTQ8a+X2bJ17IaoHJgwxbgQ= X-Received: by 2002:a2e:240b:0:b0:293:2c65:20c8 with SMTP id k11-20020a2e240b000000b002932c6520c8mr6554156ljk.1.1680218723191; Thu, 30 Mar 2023 16:25:23 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id g26-20020ac2539a000000b004dda80cabf0sm127241lfh.172.2023.03.30.16.25.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 16:25:22 -0700 (PDT) From: Konrad Dybcio Date: Fri, 31 Mar 2023 01:25:15 +0200 Subject: [PATCH v5 01/15] drm/msm/adreno: adreno_gpu: Don't set OPP scaling clock w/ GMU MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v5-1-bf774b9a902a@linaro.org> References: <20230223-topic-gmuwrapper-v5-0-bf774b9a902a@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v5-0-bf774b9a902a@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680218720; l=2082; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=J+NC5YC/ebMbVp5SWCJ3W7rySZtZPgfNfKIxNjYvw8s=; b=nnT3Xo8An9NkjO3ejLZCh5888RRNMto9J5UyzdIwiIHICQUr3SIDVK8O3ukDZ7+cZtZU4IrWrsF0 73sPX4KQBNED78yvgQLw9aOdxIvKNTl7MlvKQnrTqJz3HCX/fQBO X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761838227000045321?= X-GMAIL-MSGID: =?utf-8?q?1761838227000045321?= Recently I contributed the switch to OPP API for all Adreno generations. I did however also skip over the fact that GPUs with a GMU don't specify a core clock of any kind in the GPU node. While that didn't break anything, it did introduce unwanted spam in the dmesg: adreno 5000000.gpu: error -ENOENT: _opp_set_clknames: Couldn't find clock with name: core_clk Guard the entire logic so that it's not used with GMU-equipped GPUs. Fixes: 9f251f934012 ("drm/msm/adreno: Use OPP for every GPU generation") Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index d12f2f314022..84f25122afba 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -1021,18 +1021,22 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, u32 speedbin; int ret; - /* - * This can only be done before devm_pm_opp_of_add_table(), or - * dev_pm_opp_set_config() will WARN_ON() - */ - if (IS_ERR(devm_clk_get(dev, "core"))) { + /* Only handle the core clock when GMU is not in use */ + if (config->rev.core < 6) { /* - * If "core" is absent, go for the legacy clock name. - * If we got this far in probing, it's a given one of them exists. + * This can only be done before devm_pm_opp_of_add_table(), or + * dev_pm_opp_set_config() will WARN_ON() */ - devm_pm_opp_set_clkname(dev, "core_clk"); - } else - devm_pm_opp_set_clkname(dev, "core"); + if (IS_ERR(devm_clk_get(dev, "core"))) { + /* + * If "core" is absent, go for the legacy clock name. + * If we got this far in probing, it's a given one of + * them exists. + */ + devm_pm_opp_set_clkname(dev, "core_clk"); + } else + devm_pm_opp_set_clkname(dev, "core"); + } adreno_gpu->funcs = funcs; adreno_gpu->info = adreno_info(config->rev); From patchwork Thu Mar 30 23:25:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 77473 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp206845vqo; Thu, 30 Mar 2023 16:43:43 -0700 (PDT) X-Google-Smtp-Source: AKy350bPQm4sedx+ODPrM1GbpRgSiYqPgMl7vKz+N+BIc2etBHVgXBOc+lzuEIn9I/QgQsF6lDuT X-Received: by 2002:a17:902:e54d:b0:1a1:a90f:6766 with SMTP id n13-20020a170902e54d00b001a1a90f6766mr30505744plf.52.1680219823435; Thu, 30 Mar 2023 16:43:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680219823; cv=none; d=google.com; s=arc-20160816; b=vN80G6UVNM5wJBCxO2RHVd6YgR7IsX3OPk4VaWrS3ScLMJEf3VbRuWAMcSIEX898iq fn3NnW3bKc48bMQjKhyrBKA3aLMOjC3GvXnZiZ4QyMWZi5C/q4Bes3S+DYh7IBXcog8w kfvXlqjJWJbGq0QO2j5Qu63DvWSmI4s/I+UPuZpbilRyNnf6yqdpFVDU+0eZUwyC+dFv asTJEmgCyTptkMo/xY393XCcJeI+gks6TfnfkOJglDjWXryIxBQbY4rm8HLvBMiemtjI mfh2TNxOjZwCyIfxW8VKdkRtmLf1kLMe/5reYDl8alSYk1/6FJ/BBC6DINIxPdDOxbMu ujWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=1zLOaNti8US4yjllYIUZXiOKkjRQYJjDZ58RHJWDDs4=; b=05uWGp542sX6ioUii6uMjaScXM6P22Qi4qelg4sXbhiFor6wInwLWrmY7RL/OJvVLk 8Jgmr1Sj0pZbyWgbXJ2XdXT20ZftCSFiRBvqUbSDB21zk3P1RMZYLOtbOFnFQPlSnnk8 9bQVY2N9CaimmAe70gXdID9t007jUiklzDtdIGIXbvCkk96+12/7ZsaVssKl5zjAyzNd EPAz/z32QZs29skJrPbXZ+VARyzX/I74jL9xJqNgDPXg+SQpPmE3wBlG90qF7/Gq2LB9 Mpf/Bz9N7FL1ua/1klOT+zSltg3h82jIslRWHCDSEUSHVEBxNKYhRcgHsvIZWwMNexil 5g2w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="m0/n+I1/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id b5-20020a170902d88500b001a045fcd743si774187plz.142.2023.03.30.16.43.29; Thu, 30 Mar 2023 16:43:43 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="m0/n+I1/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231611AbjC3X0J (ORCPT + 99 others); Thu, 30 Mar 2023 19:26:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47748 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230484AbjC3XZl (ORCPT ); Thu, 30 Mar 2023 19:25:41 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 56B22113EE for ; Thu, 30 Mar 2023 16:25:26 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id h25so26657940lfv.6 for ; Thu, 30 Mar 2023 16:25:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680218724; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=1zLOaNti8US4yjllYIUZXiOKkjRQYJjDZ58RHJWDDs4=; b=m0/n+I1/rpVCuLYzGLyA+DdSFDWUHEW0zjoWQveb0CSVB7dFpJHcd4bM8YIjOg0yZe WfYR3m9h7WRhMe+KuydHADTAar48MOvj4k80PJ8Xd9lIs65AHoGepG1pCPf+2QGq/npG N0NhvqG8qBG9B2WIP9msAlEtR3d4QA2lOcZ9drv9ZypulWwOHhYAhG2WVMl/1tmg39yL IW6In+inoJDNOC9Axa42Xj3yvm807byLF5/DtxrESKDBmaQrcOgtf5iV0tZG8GsTiWxP 3UEWnfM2QUOMtJorWMljBfKsTIuKcxMjDCPfVfeYmYXt3KSQNpTMtOJB14N5BJ48b62+ tDsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680218724; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1zLOaNti8US4yjllYIUZXiOKkjRQYJjDZ58RHJWDDs4=; b=2z7butvhHXSns+pPwxMNy4IOjOzUNiUH+TXZ1usxMZO0ILGVIIql+KLr48dL2MCg1M +Z0AbU6gPeO6DyzKzGvBGxavQscyXBUrjdYW02xsVynaSiu7IcGKllDQa9fAMiCA3Rfn /A4dkM3XDyA1CQCQzmVpskd4lzHb3sdK+9CacPMsJXIyrY92/7vY+RiWdJVQtuPQwIXT rKIYqG/Qmi115QkPMlDeQvjR2BKFtDsGRviPMqgHD/1qeEmxYdOZVSHBA8xAeXgUcXrK yd/WMrNlJf22TM/RYxO5RMDGsV4K3kSoSNtyh7DwEHiHkxCcHYTFhoESH+w4Y3WTazsW 58dw== X-Gm-Message-State: AAQBX9eF/DrCCG5E9m6hnJlMfZK/U/fYE3gvCcRgj/qTBCdfDb3pB4Y5 4hjYI+ppAPnGjbrFbReZanthpA== X-Received: by 2002:ac2:418a:0:b0:4e8:595c:60f9 with SMTP id z10-20020ac2418a000000b004e8595c60f9mr6550954lfh.32.1680218724592; Thu, 30 Mar 2023 16:25:24 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id g26-20020ac2539a000000b004dda80cabf0sm127241lfh.172.2023.03.30.16.25.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 16:25:24 -0700 (PDT) From: Konrad Dybcio Date: Fri, 31 Mar 2023 01:25:16 +0200 Subject: [PATCH v5 02/15] dt-bindings: display/msm: gpu: Document GMU wrapper-equipped A6xx MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v5-2-bf774b9a902a@linaro.org> References: <20230223-topic-gmuwrapper-v5-0-bf774b9a902a@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v5-0-bf774b9a902a@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680218720; l=3273; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=PlpPtlQZuCcXGxNxg4tBwrBjp8RpPmQvuWz5XR9uQF0=; b=KUKJHvyF8TeKLZ1JC4RG82LkCQbs0eIjTo2BDGIuExX8mjD2ACUXufSJ+O8lmTu3l6DwK31ObAMz ZezGDG5fDNQyEQMQtlcKxbonhN8RJmDY9FKNyjVLlfpZWp8jDON5 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761838181561227294?= X-GMAIL-MSGID: =?utf-8?q?1761838181561227294?= The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks we'd normally assign to the GMU as if they were a part of the GMU, even though they are not". It's a (good) software representation of the GMU_CX and GMU_GX register spaces within the GPUSS that helps us programatically treat these de-facto GMU-less parts in a way that's very similar to their GMU-equipped cousins, massively saving up on code duplication. The "wrapper" register space was specifically designed to mimic the layout of a real GMU, though it rather obviously does not have the M3 core et al. GMU wrapper-equipped A6xx GPUs require clocks and clock-names to be specified under the GPU node, just like their older cousins. Account for that. Signed-off-by: Konrad Dybcio --- .../devicetree/bindings/display/msm/gpu.yaml | 61 ++++++++++++++++++---- 1 file changed, 52 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index 5dabe7b6794b..58ca8912a8c3 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -36,10 +36,7 @@ properties: reg-names: minItems: 1 - items: - - const: kgsl_3d0_reg_memory - - const: cx_mem - - const: cx_dbgc + maxItems: 3 interrupts: maxItems: 1 @@ -157,16 +154,62 @@ allOf: required: - clocks - clock-names + - if: properties: compatible: contains: - pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$' - - then: # Since Adreno 6xx series clocks should be defined in GMU + enum: + - qcom,adreno-610.0 + - qcom,adreno-619.1 + then: properties: - clocks: false - clock-names: false + clocks: + minItems: 6 + maxItems: 6 + + clock-names: + items: + - const: core + description: GPU Core clock + - const: iface + description: GPU Interface clock + - const: mem_iface + description: GPU Memory Interface clock + - const: alt_mem_iface + description: GPU Alternative Memory Interface clock + - const: gmu + description: CX GMU clock + - const: xo + description: GPUCC clocksource clock + + reg-names: + minItems: 1 + items: + - const: kgsl_3d0_reg_memory + - const: cx_dbgc + + required: + - clocks + - clock-names + else: + if: + properties: + compatible: + contains: + pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$' + + then: # Starting with A6xx, the clocks are usually defined in the GMU node + properties: + clocks: false + clock-names: false + + reg-names: + minItems: 1 + items: + - const: kgsl_3d0_reg_memory + - const: cx_mem + - const: cx_dbgc examples: - | From patchwork Thu Mar 30 23:25:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 77462 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp199632vqo; Thu, 30 Mar 2023 16:27:23 -0700 (PDT) X-Google-Smtp-Source: AKy350bPJkw5ymZNZry3cMrQ1umVFNlSCbm6PbaE9cfLfdBfk3R+L4wVUyS0Q9YyV1nq7QYfw9Qy X-Received: by 2002:a17:907:1c09:b0:930:f953:9608 with SMTP id nc9-20020a1709071c0900b00930f9539608mr35486423ejc.0.1680218843231; Thu, 30 Mar 2023 16:27:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680218843; cv=none; d=google.com; s=arc-20160816; b=SfcnM63z+Y62x5boR5oPkSUyJNUKNXkB6HPMAPm0X9qLbO1zwyoTi1OXa6tNhJqyG+ 0Y4DCEdbFaPgWhHRWeRvmt/AuikB8QdO9uMiGq6HLkimF8y55DLj1Mc1K0/ovRszNq3L O0CIu6Dd3nWdtjgjaoYlDzlgYYpV8t8NE6soavB+l0pdl5hzmecJ0Wwmtf5DlXkQNQGK gvu5BvxsV7X0bgaLvQmZ9/PKI75VxH+OM8h0J+ETrV4G2H7i0o7HLB4cmq/DNnZMBt/c 4+MNKIkCTeG1bClutT+NABMfnCrsxruILPBd7RHJANg4Z1biGFgpH/FBa1AthHJYTJnA nUYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=HnEMhNsn7kHL6KC8gQ4HhHhkok2Hiu0bEYeYgvAPNX0=; b=Cp0xwGPRLGaPRwEP8Glcc1aOx9dWbqkSDyeGENm1lwzFIgTbG0Mi/t94RDz0YJLX2u cjQ3fDWLyS0IY6eyUZJYfqWh64Y5sRr0YnpmBBl1Vf7T5YfHLRhXoMuloMKi4nnrL5jT 4lt5Lrdbvnuwbvlj9xzcK0iz+HbSgkaRMhxsvSUgc0OpSwv6oMDG7N429MEblCuXnBf4 RHcPVbtGjcuE0oENVUlmIYW+NzMmSw/OUZ6Oisex5vmm54QyBULAmWC2YGykfrqyAyEb lJCkjKFlCldR8DQ+iuUGlIp2uKRjfyx6TTmsduR7LacDWD81DgXP30wgrZasoy5pH4IM d5YQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WA4U34ZF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id y2-20020a170906914200b009354991f96bsi546470ejw.739.2023.03.30.16.26.58; Thu, 30 Mar 2023 16:27:23 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WA4U34ZF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231335AbjC3X0E (ORCPT + 99 others); Thu, 30 Mar 2023 19:26:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231388AbjC3XZm (ORCPT ); Thu, 30 Mar 2023 19:25:42 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE79811677 for ; Thu, 30 Mar 2023 16:25:27 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id y20so26699207lfj.2 for ; Thu, 30 Mar 2023 16:25:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680218726; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=HnEMhNsn7kHL6KC8gQ4HhHhkok2Hiu0bEYeYgvAPNX0=; b=WA4U34ZFDU5GEpA2HWjsfMPx0WY4xW4xHWtWqTFzepkEWOByY8/2692X7AXb/Sl6lZ Xspckf8n8aKQ6bE0Gp4BxYDtGt3hSSCIYRhxvS+LabVFtGuL+ervvzWF6BaqeRD67CHG mW1mr65rrZ1OjFkAC6HxjoMjeiK7TgnEw+EHxuUaWNeG8mAzdPzBeZzrzJPkujQxWZ8a 7sOw9w/TL/t/wDjlasBnebeYI7HCTiFCpoqg+IdLIxjDn9AL0Y4dPy/erwzMUbuC3ozp 6spDjFsI1LAXUt2I5pxr8My6h6d75sSUVj/pSatoNba9TlC+1Tps6di59E0g4SYpvunp t0Cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680218726; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HnEMhNsn7kHL6KC8gQ4HhHhkok2Hiu0bEYeYgvAPNX0=; b=TVaE5PmoOyqZCQvcOSuf+wTW62/Pi9rmnLjHtbK/Dnj6LPvcfmNEAjHpZ/9soPGnRW Il9g4OzXcXoMmYDEhlk+Ks9onIfp6FMRf8cvZ4n3cuhT6FNCYyem3v6I7rLtuvzQpfcD ohCb9eOGHcdWu6z26CBIbRTUYeJhNSIydgYfpXm+5W/3YUfVJ5HXvvmb6X276J/uAqLx mu93tRLrQGHsWibBx5jAGjHxIqp9c2zi3sXilKz7wsg9ulOfAyLNVbovpQUoKEC4lFKe 5MKHb2RAhUAwm7BxUZyTg2uuKxccyC+sK8UdYMuQb5sOBHbyNn70c9tarNMfe2NlMj/C u+rg== X-Gm-Message-State: AAQBX9c5PJ/90W34A8fa5WPWC/L34P6mPO3+wa8OIf9Dc4S7nsL10Krn Nse2AljpxhgWg7m9EHpHnAZEyA== X-Received: by 2002:ac2:5d6b:0:b0:4dc:828f:ef97 with SMTP id h11-20020ac25d6b000000b004dc828fef97mr8191364lft.60.1680218726076; Thu, 30 Mar 2023 16:25:26 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id g26-20020ac2539a000000b004dda80cabf0sm127241lfh.172.2023.03.30.16.25.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 16:25:25 -0700 (PDT) From: Konrad Dybcio Date: Fri, 31 Mar 2023 01:25:17 +0200 Subject: [PATCH v5 03/15] dt-bindings: display/msm/gmu: Add GMU wrapper MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v5-3-bf774b9a902a@linaro.org> References: <20230223-topic-gmuwrapper-v5-0-bf774b9a902a@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v5-0-bf774b9a902a@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio , Krzysztof Kozlowski X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680218720; l=3381; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=gRbQW6m4WkjCaooGTDuAvaThk4xamrj0048X6Oez/Ng=; b=L5yjYbAyIy1eaZUt6Fje84do7jlXCRtTNb0HkhOCqZub2opNvWhZ+3Qq3UpaP3XSSbi/XytuL5BK 1sGghhSVC/zERXFWxtHF/og72ZHZNB0bvpdo3zPXLUnQE8m2Rr7k X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761837154048216326?= X-GMAIL-MSGID: =?utf-8?q?1761837154048216326?= The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks we'd normally assign to the GMU as if they were a part of the GMU, even though they are not". It's a (good) software representation of the GMU_CX and GMU_GX register spaces within the GPUSS that helps us programatically treat these de-facto GMU-less parts in a way that's very similar to their GMU-equipped cousins, massively saving up on code duplication. The "wrapper" register space was specifically designed to mimic the layout of a real GMU, though it rather obviously does not have the M3 core et al. To sum it all up, the GMU wrapper is essentially a register space within the GPU, which Linux sees as a dumbed-down regular GMU: there's no clocks, interrupts, multiple reg spaces, iommus and OPP. Document it. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- .../devicetree/bindings/display/msm/gmu.yaml | 50 ++++++++++++++++------ 1 file changed, 38 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml index 029d72822d8b..e36c40b935de 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -19,16 +19,18 @@ description: | properties: compatible: - items: - - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$' - - const: qcom,adreno-gmu + oneOf: + - items: + - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$' + - const: qcom,adreno-gmu + - const: qcom,adreno-gmu-wrapper reg: - minItems: 3 + minItems: 1 maxItems: 4 reg-names: - minItems: 3 + minItems: 1 maxItems: 4 clocks: @@ -44,7 +46,6 @@ properties: - description: GMU HFI interrupt - description: GMU interrupt - interrupt-names: items: - const: hfi @@ -72,14 +73,8 @@ required: - compatible - reg - reg-names - - clocks - - clock-names - - interrupts - - interrupt-names - power-domains - power-domain-names - - iommus - - operating-points-v2 additionalProperties: false @@ -217,6 +212,28 @@ allOf: - const: axi - const: memnoc + - if: + properties: + compatible: + contains: + const: qcom,adreno-gmu-wrapper + then: + properties: + reg: + items: + - description: GMU wrapper register space + reg-names: + items: + - const: gmu + else: + required: + - clocks + - clock-names + - interrupts + - interrupt-names + - iommus + - operating-points-v2 + examples: - | #include @@ -249,3 +266,12 @@ examples: iommus = <&adreno_smmu 5>; operating-points-v2 = <&gmu_opp_table>; }; + + gmu_wrapper: gmu@596a000 { + compatible = "qcom,adreno-gmu-wrapper"; + reg = <0x0596a000 0x30000>; + reg-names = "gmu"; + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", "gx"; + }; From patchwork Thu Mar 30 23:25:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 77461 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp199613vqo; Thu, 30 Mar 2023 16:27:20 -0700 (PDT) X-Google-Smtp-Source: AKy350bRIA49oTL9B4Gpruchqc/S+sSG+lJoSMDVOqi+BoA+KyYEUP+o6IGofw+AMPEbnLiqoNR4 X-Received: by 2002:a17:906:a3ca:b0:926:e917:133c with SMTP id ca10-20020a170906a3ca00b00926e917133cmr24482893ejb.47.1680218840048; Thu, 30 Mar 2023 16:27:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680218840; cv=none; d=google.com; s=arc-20160816; b=S7W7LCVqYcM85J41tu1PyeGKAX6qhpXgkiFxkEN35McmcHij2U+fwAU16M3GHuCiI+ W8nirMl/JWqUcGTePGWViV/05WnhMfppluWX61nicTPpw3JSvxYLr7sGKK9Zb2p3D0VH pshGjWF0Mmx/n7B2Y33qilUYCMG8l1IYO4h/b+mDkJJ6HwMNeSZ4sYs+F3MMGXoL9EDA 3kV6nOfa/K2yyXOBnfPLB62wX9EvXX9SIkKUGk4x2mqTHXlzoUSEzXaALNGGBgxyUkZ0 EAKVealQYd0QxHpK8c2Tt2LtArNuQRusj5hlU1Vqr47fEanepNlxQo3f1VZK82/B4rg5 ijzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=ulzx50nltdBvd14PSoi/AyrNNr9j/GqEsVc35iPrtqQ=; b=iOjQqGWJ9Azg6NdGrtSDIEVKfx/LMWGHlp67mkods6jdVscmlNmeNRNvn2K6dDisAV VdWhOOk1xPuhayY40l8z1nroRzZC9MpIAQETOJQb4wjh2D0HxIaJoc1gV3fNxCO6fUqT bcr8SW7SJTtQgAck1fvaKhJzCJqTwTFI9WUlwKlbyDImqz4dP1MsMe7Wrvm5MQE/plP3 FTBUndZJ5DrX1nKWCl79+ZbekvLlLp3N5Pplx5pm3ogPMH5WgCNXLSQ2w5/9EsQFcdUD lhZb3dR60H6dsbpf3VNJKgpaFhutiU387+PL4BJPrNe/mllXNLrxFWOiVZxGHqYvApxR uMPA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fXwrEbMb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id bw12-20020a170906c1cc00b009330d1437a1si544184ejb.701.2023.03.30.16.26.56; Thu, 30 Mar 2023 16:27:20 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fXwrEbMb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231473AbjC3XZz (ORCPT + 99 others); Thu, 30 Mar 2023 19:25:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48350 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231305AbjC3XZn (ORCPT ); Thu, 30 Mar 2023 19:25:43 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1C03B1167A for ; Thu, 30 Mar 2023 16:25:29 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id x17so26679709lfu.5 for ; Thu, 30 Mar 2023 16:25:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680218727; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ulzx50nltdBvd14PSoi/AyrNNr9j/GqEsVc35iPrtqQ=; b=fXwrEbMbQSuULOzCc5FZSh9TsU7bIewyQVd/hNko2e/PZ9uLzQFtEK4cteKOKdLJFr gz7li7VW+2/OqqGK9gQNMpo4O9tesae0ieOoZQ9A3gPHBZq8JAgCg3StWwEonmit2USw UKoshL2RIFAOt0WH66nmGuBuNtlu//r4tERWzle7CxBvRswTx1QTE8kOsXkIHAbU3IDe dO72/BYpDBJtrYoreys9/NF7dG4eTkcVJOW396PrZnQgMUrk2RvAirmYbLm6LOQ17/7q 4yiduTUaAM0zmowThTcJlY2Xk7NHGhYnmIee6NQFuO8yJMoYJi2mrrWtlLcD6paqXi36 0hvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680218727; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ulzx50nltdBvd14PSoi/AyrNNr9j/GqEsVc35iPrtqQ=; b=fSCpQzvm0CWvugrEQk8U2fSYLjjWoupmLZiMlUjcgJi/rn2zF5mn+8rJWgscGjTz5Z 0LwvEGuoLkYwEQRcGUkigWeiuBzDEt3Yds4juHIu5teEewQdmkDbRCwLz1MrmjBxUBDz e5YZbhwWdbTycRpCHuGnOBPQTTBSx46upBanMciWuwoPtPwSIEsR1v3OdfyFHGrBZ2Ab AINFMSURxRKS7+2XdjokNXGHQhAx3Ecp21T5Y7bC6je7NOBjEqF6qMwGm+tOur6uq469 f8aK0QaFmBdik0Rq/ay/xJ8tRbhelQNepDiEKsdmNlZcusCmMFJ63FwbIe1yDGpf36uc 9WTQ== X-Gm-Message-State: AAQBX9fT856cx5XUl8OSq7T9HrHAVrXJ38LDuCNDO+Y4Sokd9kyML5Vb lPgTil8Nnpe4aqPcWgO/iEBqhQ== X-Received: by 2002:ac2:5e88:0:b0:4eb:c4e:bd87 with SMTP id b8-20020ac25e88000000b004eb0c4ebd87mr5700090lfq.58.1680218727463; Thu, 30 Mar 2023 16:25:27 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id g26-20020ac2539a000000b004dda80cabf0sm127241lfh.172.2023.03.30.16.25.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 16:25:27 -0700 (PDT) From: Konrad Dybcio Date: Fri, 31 Mar 2023 01:25:18 +0200 Subject: [PATCH v5 04/15] drm/msm/a6xx: Remove static keyword from sptprac en/disable functions MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v5-4-bf774b9a902a@linaro.org> References: <20230223-topic-gmuwrapper-v5-0-bf774b9a902a@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v5-0-bf774b9a902a@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680218720; l=1711; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=ve7dkZrYc5cSSMu89e01MZzyBYTeqWaeZyy4JZy7U0w=; b=Zke1xsMS3dnkdn+JdDDFWbcG6ov48tbnXWiZVfSJvfbVaMPHjiPK8ibVyXKOALdcGohtiQUDjEq3 +dAI+2q3B3cF8Ol2RVrRAj48FIvuMTM7CAjlyLWuwULoocsKuaOI X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761837150093692652?= X-GMAIL-MSGID: =?utf-8?q?1761837150093692652?= These two will be reused by at least A619_holi in the non-gmu paths. Turn them non-static them to make it possible. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 4 ++-- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index ba6b8ea27c71..1514b3ed0fcf 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -354,7 +354,7 @@ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) } /* Enable CPU control of SPTP power power collapse */ -static int a6xx_sptprac_enable(struct a6xx_gmu *gmu) +int a6xx_sptprac_enable(struct a6xx_gmu *gmu) { int ret; u32 val; @@ -376,7 +376,7 @@ static int a6xx_sptprac_enable(struct a6xx_gmu *gmu) } /* Disable CPU control of SPTP power power collapse */ -static void a6xx_sptprac_disable(struct a6xx_gmu *gmu) +void a6xx_sptprac_disable(struct a6xx_gmu *gmu) { u32 val; int ret; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h index 0bc3eb443fec..7ee5b606bc47 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h @@ -193,5 +193,7 @@ int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, int index); bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu); bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu); +void a6xx_sptprac_disable(struct a6xx_gmu *gmu); +int a6xx_sptprac_enable(struct a6xx_gmu *gmu); #endif From patchwork Thu Mar 30 23:25:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 77470 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp205133vqo; Thu, 30 Mar 2023 16:39:44 -0700 (PDT) X-Google-Smtp-Source: AKy350byvQwZa5zoM2rz70gCokLsx84eQ29QtmjPoCuEFnDkU+Z4KPtZ+SGzoU49HyvYQFJGINMf X-Received: by 2002:a17:903:124d:b0:1a2:4921:f9a1 with SMTP id u13-20020a170903124d00b001a24921f9a1mr22384878plh.44.1680219584638; Thu, 30 Mar 2023 16:39:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680219584; cv=none; d=google.com; s=arc-20160816; b=TLy4ActFFGm6wjo6JbEGnV/mAPhW89AJvCDZHnGr3zDzrd3wE8vq/zgyrjrRrs0ZgE dyXLHIXkCgO+ulKAe3Xl9q5zvL0Unx5obx7fZ9QTAV/asz1rOWj51aJ7/SY4Ynh2Dpkr lZzPEda98UG/vxFN47/m6D6W7FTgNxENiMpb6qe9oNfXHlJVb2LftNd6ggvPjFofjCNC HJub/8asx/aEg3GmmKmW4E9y7n2aypBWJ5bH16YeUl8P9ffgj5JCFA6zf4FZwnhoOZT5 AcqBMIDRzNs+B5aVYLBU8wuy/JFbhadIolRBAVZkz3fs9uddysfnz+ONj+6M+JQpFcI2 HsTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=YtGg6mbEC7K9haoa+JJffahHI7dimi0Is2Gw5+yUY9M=; b=XWV5P8K4i4zsAhRfPyLuoWcJH433FEsTn7oYT/NuCZeCF/6NPPtEmUPjWVRGd4ArYz BXndbu3u75vXfupB9RLm9cmlHiB2J+iZ9KfShgEKcrzGEk3gSybrHHDHkNL6HeHESlwI OIH8bk9bAHow+a5umYBGVQoF54eXZcBIiWcWxs4z3+4vQeuSbdhJAjpCCYOXmvLLHqbg pt+aQMvvYeNjAMpdF/EqxZrTfSbsAPNmJG8XzclZ1hWPi4aKMxbCDkJfgy7idx0UtkJH LSpM6FS4EWIU4G3sqrEeXCzv0QJ/2qTgxD3QT4qUhWDA69McrSKKZaMeD+g35Kw925Dz cEFQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=T0bq9ULX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id iw12-20020a170903044c00b0019ceb4b753fsi695842plb.26.2023.03.30.16.39.31; Thu, 30 Mar 2023 16:39:44 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=T0bq9ULX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231615AbjC3X0L (ORCPT + 99 others); Thu, 30 Mar 2023 19:26:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47708 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231451AbjC3XZo (ORCPT ); Thu, 30 Mar 2023 19:25:44 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D6F051164A for ; Thu, 30 Mar 2023 16:25:30 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id x17so26679782lfu.5 for ; Thu, 30 Mar 2023 16:25:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680218729; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=YtGg6mbEC7K9haoa+JJffahHI7dimi0Is2Gw5+yUY9M=; b=T0bq9ULX4cHf48ItQHwTeI+aSBRn3rUsrOI2ofEBEIRZ78a4JgVPoXEnVuFd3GHH2/ PuIP8sixgKOzzkDaxOyX/RfHTgqlofR2ng3ZwTfMWlG5HOqdpYDNi/lUI4m3Xopie1sk d5Lpp0HAo5ufHN9Pt7duBlQCmkq/rM92pFKt0hSYGykEK+gBV5HqcLB3rtPCirEoRIe1 GC0l4sITg8Nhxya2Z5pNAVmld30r1TTz/d3cNA/EZ1U1KueUW/tbn/xVoJ9OKLt3svEm 7xZ5Erqk3psHaakLewHfo6+4mmd+G1MWVrKQNwfUU9YCrXO1XqHfWdiF8+c/ATd7hJCq Jb5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680218729; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YtGg6mbEC7K9haoa+JJffahHI7dimi0Is2Gw5+yUY9M=; b=sigDqGcBO1uKV29JmyhpRsq79gJbh+dU2mVLBE2yqZmLbS9AOL1qvU4sZobwXwP6PN BhTvrBtaUXPHtLeWNMI7gXgf3uagkxcl3HGOj45U6hxkbVXIS4MyZhb5mtG0NsKzcR7n 4RTEB0o1fDbHKqTEncuH274DicW8WzK38PoDyqSUn/5xDVC9gbdERBOdSksZsqq4NUV6 GHCzO10PMPp+ecY/nhyK1Q0h9J5JgCmahsyOALHRjpmY9JLCSr1CvaJb0jpcVP908f7I u1MlVBFzF+78B5KKRVGNaov8GzQOZopm0nzvX2REFk/pbyFJ5PR4QOkuBRZyoBJXr9fn bh1w== X-Gm-Message-State: AAQBX9coh8gOdRo1/s8YfZzC+pMacDDplCN1X4ECa2uChrnAnpPwu5JN SGjJ+qt/UvE5Yg/W9nJVHOZ6Xw== X-Received: by 2002:a19:ad48:0:b0:4ea:ea00:5d45 with SMTP id s8-20020a19ad48000000b004eaea005d45mr6962305lfd.44.1680218729104; Thu, 30 Mar 2023 16:25:29 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id g26-20020ac2539a000000b004dda80cabf0sm127241lfh.172.2023.03.30.16.25.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 16:25:28 -0700 (PDT) From: Konrad Dybcio Date: Fri, 31 Mar 2023 01:25:19 +0200 Subject: [PATCH v5 05/15] drm/msm/a6xx: Extend and explain UBWC config MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v5-5-bf774b9a902a@linaro.org> References: <20230223-topic-gmuwrapper-v5-0-bf774b9a902a@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v5-0-bf774b9a902a@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680218720; l=3025; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=uv5LOb4J9bj2PZpW4eq/OCSd4qgrzTJM/32g49JBad4=; b=k+wdgfZ7L2fmksgwtFWf0rcEWhRPOLbt9F0VrO0ToSfjnB1TGbLowHuyK5xhWbnpcM6I8OZUuFMu +rhfg3O+C/FTMXC/04le0zy6dx/VQiHGgLThti3QKLqXBB5A5V4C X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761837931489318618?= X-GMAIL-MSGID: =?utf-8?q?1761837931489318618?= Rename lower_bit to hbb_lo and explain what it signifies. Add explanations (wherever possible to other tunables). Port setting min_access_length, ubwc_mode and hbb_hi from downstream. Reviewed-by: Rob Clark Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 39 +++++++++++++++++++++++++++-------- 1 file changed, 30 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index f2dbd5d13f7d..ae0a90b2834f 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -786,10 +786,25 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) static void a6xx_set_ubwc_config(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); - u32 lower_bit = 2; - u32 amsbc = 0; + /* Unknown, introduced with A650 family, related to UBWC mode/ver 4 */ u32 rgb565_predicator = 0; + /* Unknown, introduced with A650 family */ u32 uavflagprd_inv = 0; + /* Whether the minimum access length is 64 bits */ + u32 min_acc_len = 0; + /* Entirely magic, per-GPU-gen value */ + u32 ubwc_mode = 0; + /* + * The Highest Bank Bit value represents the bit of the highest DDR bank. + * We then subtract 13 from it (13 is the minimum value allowed by hw) and + * write the lowest two bits of the remaining value as hbb_lo and the + * one above it as hbb_hi to the hardware. This should ideally use DRAM + * type detection. + */ + u32 hbb_hi = 0; + u32 hbb_lo = 2; + /* Unknown, introduced with A640/680 */ + u32 amsbc = 0; /* a618 is using the hw default values */ if (adreno_is_a618(adreno_gpu)) @@ -800,25 +815,31 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) { /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ - lower_bit = 3; + hbb_lo = 3; amsbc = 1; rgb565_predicator = 1; uavflagprd_inv = 2; } if (adreno_is_7c3(adreno_gpu)) { - lower_bit = 1; + hbb_lo = 1; amsbc = 1; rgb565_predicator = 1; uavflagprd_inv = 2; } gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, - rgb565_predicator << 11 | amsbc << 4 | lower_bit << 1); - gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1); - gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, - uavflagprd_inv << 4 | lower_bit << 1); - gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21); + rgb565_predicator << 11 | hbb_hi << 10 | amsbc << 4 | + min_acc_len << 3 | hbb_lo << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, hbb_hi << 4 | + min_acc_len << 3 | hbb_lo << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, hbb_hi << 10 | + uavflagprd_inv << 4 | min_acc_len << 3 | + hbb_lo << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, min_acc_len << 23 | hbb_lo << 21); } static int a6xx_cp_init(struct msm_gpu *gpu) From patchwork Thu Mar 30 23:25:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 77469 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp202778vqo; Thu, 30 Mar 2023 16:34:21 -0700 (PDT) X-Google-Smtp-Source: AK7set8c22S98C2Ghjd/nH2SrljKDNEoLuey5I2xcZokxERyv9lgRcwi25opReXhrKRYfSTaL8Rp X-Received: by 2002:a05:6a20:4725:b0:da:2d16:db89 with SMTP id ek37-20020a056a20472500b000da2d16db89mr20171939pzb.28.1680219261511; Thu, 30 Mar 2023 16:34:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680219261; cv=none; d=google.com; s=arc-20160816; b=fURcp6F5s9KJtE5iCQdy+/TlbzBtgmTu04+Wk6VDxWXwPf3eXIx9qkYiKX3jeFRTK0 8C67XhujK1odnSFLNs7AgAIMl70UtoOR6KV8HhUlTZgYx5kOln2RmzW4GowzGghT7LZV vZICQh+XX/BnBt5MNusSohLAxb0V3LGeEXYacHwEXvGgT5mUUjWChYmPOmmSBviMl2YU MhboF6Z8G5lt1Dqrmo61m1U/sV4mU14F+GvjtzIbCrsrkCnfMmg4iAufWvOrHoprUyhw Adb+Oew4gJbuYjhM9l0mLDc/U7dw+ORlmhWcm9vpLlLRMtIDhKY4M80avMujx7z7SqlL Ik8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=n13bWzRBpiNtL9CQu36YeqfDtUKK84RaXXfz8bZOuSI=; b=uEfhQnzfe2rzHzzIWeAnIQ5/QXaex0JCye2CPQnj6qNX/1+3DzshKmEp6gVO4jTBv3 RdC9HVBO+tNYs0ze3UZfQiS9ZJDOQOw4WcaVRIzEd5ZbpWd5hH2bQ2/MwJXRg+Mctb04 BkxcqBkvjzfnXAGoEV52yicbWosEShs95eWMsCjoVpW4GNxrrSlbi1HML5LWlT2tBb3p mac10jzl4cfv5bnF+eTnxDjoMlkqCkLBiHOTCGAerHnOPl+PGBY8zIJrHYLKnVJ0uCJY i8izhePt5Ta/RwNl5ak6Ni7rdfrRnKmXoJa6u0CzjhkzoKDB9CG1Y39A6OMtCts2fgmo zA/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=X6vczdNv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id f26-20020aa79d9a000000b00627e9ad5918si929776pfq.193.2023.03.30.16.34.07; Thu, 30 Mar 2023 16:34:21 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=X6vczdNv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231621AbjC3X0O (ORCPT + 99 others); Thu, 30 Mar 2023 19:26:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48390 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231486AbjC3XZo (ORCPT ); Thu, 30 Mar 2023 19:25:44 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 997881204C for ; Thu, 30 Mar 2023 16:25:32 -0700 (PDT) Received: by mail-lf1-x130.google.com with SMTP id h11so19694248lfu.8 for ; Thu, 30 Mar 2023 16:25:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680218731; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=n13bWzRBpiNtL9CQu36YeqfDtUKK84RaXXfz8bZOuSI=; b=X6vczdNvXzzbk3fRvwxc+0qMBTFcu59UY0G19Wf0WxuTXIz/VLyOR72PFhgni5/3aD njgocSyeBXirlhf15HHVMtgEt5WZpotpTvMkL/+OxmJYdC0Ba01zvQtm/nJrzODnUR97 izXGlH1OfEm7WI4dMz9VQLA9kHbvRKqL0YJCt62oR2m/n09oHLoCLLOgEofCuCqEmmdD PZk5bwVWCAnflWvJB8+9241eQRDgv1whmNbLhQ29WrbN87cVjOAaakI3yi3xrSVgG1yy 9yLSPKiUOJAXKBwBxKsCneiZ8IGhTiv3f/HwtrvE1rQ5jh+vpgs7U364JZMTHKg5DauE 43ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680218731; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=n13bWzRBpiNtL9CQu36YeqfDtUKK84RaXXfz8bZOuSI=; b=mU1hqrrdHCO23GISeCDANbsM9Q8Ngti5CbH5WrBOXzxKfXFCNqavd3kH4A2pnCuEPK DCY4fCJqQz6NAqSYOCNwtEx8/9qZpA/B0mMWflw24w6grIiS3Zal4IyJFb2fjc/YvtuM Gz7Xr16QiZI4yylxwYB77VX2LrY8GJZ+XTPuuyNJEOoZr+RmxCEgyMnJDk9RedI3p2tL pJgYUdpy0Sm1gcJAYOQ0AIEAvmiFZxmOTOtoJdTaKerjw2fm8VVkpsEF23G4ENNBiO8l PTYgPxUg+iftSEmBczRXUwmZ6qkFRaV52ecFEg8UU9czXCT4oaNIWwHxrkTuDm4/Dpih rfYw== X-Gm-Message-State: AAQBX9dcgHOXij5yAQHvGZhZST6+4zgcsnuGEYtHHqvRDyzWdKxEtvTr EiK0GHURFsQnwJYw3lvTvubuGQ== X-Received: by 2002:a05:6512:51b:b0:4db:398e:699 with SMTP id o27-20020a056512051b00b004db398e0699mr8342079lfb.12.1680218730651; Thu, 30 Mar 2023 16:25:30 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id g26-20020ac2539a000000b004dda80cabf0sm127241lfh.172.2023.03.30.16.25.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 16:25:30 -0700 (PDT) From: Konrad Dybcio Date: Fri, 31 Mar 2023 01:25:20 +0200 Subject: [PATCH v5 06/15] drm/msm/a6xx: Introduce GMU wrapper support MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v5-6-bf774b9a902a@linaro.org> References: <20230223-topic-gmuwrapper-v5-0-bf774b9a902a@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v5-0-bf774b9a902a@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680218720; l=21124; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=4jAmAPUTWLlkx35tajjS1GJT3eVViKGB4Uxqx5m2pSo=; b=p9zDHxYrA8BHzi1xNES58iLx3KNKHTzkbjWrbV0dUP0ou89/hYO7XjRbgUyoDjs0iuVOv/WD4edI etldJZAuDKR1qbbXLIQIx0Zz7aQiAI02X5dR76Ogek5c+bFl2Dz1 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761837592394194911?= X-GMAIL-MSGID: =?utf-8?q?1761837592394194911?= Some (particularly SMD_RPM, a.k.a non-RPMh) SoCs implement A6XX GPUs but don't implement the associated GMUs. This is due to the fact that the GMU directly pokes at RPMh. Sadly, this means we have to take care of enabling & scaling power rails, clocks and bandwidth ourselves. Reuse existing Adreno-common code and modify the deeply-GMU-infused A6XX code to facilitate these GPUs. This involves if-ing out lots of GMU callbacks and introducing a new type of GMU - GMU wrapper (it's the actual name that Qualcomm uses in their downstream kernels). This is essentially a register region which is convenient to model as a device. We'll use it for managing the GDSCs. The register layout matches the actual GMU_CX/GX regions on the "real GMU" devices and lets us reuse quite a bit of gmu_read/write/rmw calls. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 72 +++++++- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 254 +++++++++++++++++++++++++--- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 14 +- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 8 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 + 6 files changed, 317 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 1514b3ed0fcf..c6001e82e03d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -1474,6 +1474,7 @@ static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev, void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) { + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; struct a6xx_gmu *gmu = &a6xx_gpu->gmu; struct platform_device *pdev = to_platform_device(gmu->dev); @@ -1499,10 +1500,12 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) gmu->mmio = NULL; gmu->rscc = NULL; - a6xx_gmu_memory_free(gmu); + if (!adreno_has_gmu_wrapper(adreno_gpu)) { + a6xx_gmu_memory_free(gmu); - free_irq(gmu->gmu_irq, gmu); - free_irq(gmu->hfi_irq, gmu); + free_irq(gmu->gmu_irq, gmu); + free_irq(gmu->hfi_irq, gmu); + } /* Drop reference taken in of_find_device_by_node */ put_device(gmu->dev); @@ -1521,6 +1524,69 @@ static int cxpd_notifier_cb(struct notifier_block *nb, return 0; } +int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) +{ + struct platform_device *pdev = of_find_device_by_node(node); + struct a6xx_gmu *gmu = &a6xx_gpu->gmu; + int ret; + + if (!pdev) + return -ENODEV; + + gmu->dev = &pdev->dev; + + of_dma_configure(gmu->dev, node, true); + + pm_runtime_enable(gmu->dev); + + /* Mark legacy for manual SPTPRAC control */ + gmu->legacy = true; + + /* Map the GMU registers */ + gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu"); + if (IS_ERR(gmu->mmio)) { + ret = PTR_ERR(gmu->mmio); + goto err_mmio; + } + + gmu->cxpd = dev_pm_domain_attach_by_name(gmu->dev, "cx"); + if (IS_ERR(gmu->cxpd)) { + ret = PTR_ERR(gmu->cxpd); + goto err_mmio; + } + + if (!device_link_add(gmu->dev, gmu->cxpd, DL_FLAG_PM_RUNTIME)) { + ret = -ENODEV; + goto detach_cxpd; + } + + init_completion(&gmu->pd_gate); + complete_all(&gmu->pd_gate); + gmu->pd_nb.notifier_call = cxpd_notifier_cb; + + /* Get a link to the GX power domain to reset the GPU */ + gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx"); + if (IS_ERR(gmu->gxpd)) { + ret = PTR_ERR(gmu->gxpd); + goto err_mmio; + } + + gmu->initialized = true; + + return 0; + +detach_cxpd: + dev_pm_domain_detach(gmu->cxpd, false); + +err_mmio: + iounmap(gmu->mmio); + + /* Drop reference taken in of_find_device_by_node */ + put_device(gmu->dev); + + return ret; +} + int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) { struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index ae0a90b2834f..a7ecb0a87e98 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -20,9 +20,11 @@ static inline bool _a6xx_check_idle(struct msm_gpu *gpu) struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); - /* Check that the GMU is idle */ - if (!a6xx_gmu_isidle(&a6xx_gpu->gmu)) - return false; + if (!adreno_has_gmu_wrapper(adreno_gpu)) { + /* Check that the GMU is idle */ + if (!a6xx_gmu_isidle(&a6xx_gpu->gmu)) + return false; + } /* Check tha the CX master is idle */ if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & @@ -612,13 +614,15 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) return; /* Disable SP clock before programming HWCG registers */ - gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); + if (!adreno_has_gmu_wrapper(adreno_gpu)) + gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); for (i = 0; (reg = &adreno_gpu->info->hwcg[i], reg->offset); i++) gpu_write(gpu, reg->offset, state ? reg->value : 0); /* Enable SP clock */ - gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); + if (!adreno_has_gmu_wrapper(adreno_gpu)) + gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0); } @@ -1002,10 +1006,13 @@ static int hw_init(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); + struct a6xx_gmu *gmu = &a6xx_gpu->gmu; int ret; - /* Make sure the GMU keeps the GPU on while we set it up */ - a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); + if (!adreno_has_gmu_wrapper(adreno_gpu)) { + /* Make sure the GMU keeps the GPU on while we set it up */ + a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); + } /* Clear GBIF halt in case GX domain was not collapsed */ if (a6xx_has_gbif(adreno_gpu)) @@ -1128,6 +1135,17 @@ static int hw_init(struct msm_gpu *gpu) 0x3f0243f0); } + if (adreno_has_gmu_wrapper(adreno_gpu)) { + /* Do it here, as GMU wrapper only inits the GMU for memory reservation etc. */ + + /* Set up the CX GMU counter 0 to count busy ticks */ + gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000); + + /* Enable power counter 0 */ + gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, BIT(5)); + gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); + } + /* Protect registers from the CP */ a6xx_set_cp_protect(gpu); @@ -1236,6 +1254,8 @@ static int hw_init(struct msm_gpu *gpu) } out: + if (adreno_has_gmu_wrapper(adreno_gpu)) + return ret; /* * Tell the GMU that we are done touching the GPU and it can start power * management @@ -1270,6 +1290,9 @@ static void a6xx_dump(struct msm_gpu *gpu) adreno_dump(gpu); } +#define GBIF_GX_HALT_MASK BIT(0) +#define GBIF_CLIENT_HALT_MASK BIT(0) +#define GBIF_ARB_HALT_MASK BIT(1) #define VBIF_RESET_ACK_TIMEOUT 100 #define VBIF_RESET_ACK_MASK 0x00f0 @@ -1302,7 +1325,8 @@ static void a6xx_recover(struct msm_gpu *gpu) * Turn off keep alive that might have been enabled by the hang * interrupt */ - gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0); + if (!adreno_has_gmu_wrapper(adreno_gpu)) + gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0); pm_runtime_dont_use_autosuspend(&gpu->pdev->dev); @@ -1332,6 +1356,32 @@ static void a6xx_recover(struct msm_gpu *gpu) dev_pm_genpd_remove_notifier(gmu->cxpd); + /* Software-reset the GPU */ + if (adreno_has_gmu_wrapper(adreno_gpu)) { + /* Halt the GX side of GBIF */ + gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, GBIF_GX_HALT_MASK); + spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) & + GBIF_GX_HALT_MASK); + + /* Halt new client requests on GBIF */ + gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK); + spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & + (GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK); + + /* Halt all AXI requests on GBIF */ + gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK); + spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & + (GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK); + + /* Clear the halts */ + gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); + + gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); + + /* This *really* needs to go through before we do anything else! */ + mb(); + } + pm_runtime_use_autosuspend(&gpu->pdev->dev); if (active_submits) @@ -1516,7 +1566,8 @@ static void a6xx_fault_detect_irq(struct msm_gpu *gpu) * Force the GPU to stay on until after we finish * collecting information */ - gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1); + if (!adreno_has_gmu_wrapper(adreno_gpu)) + gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1); DRM_DEV_ERROR(&gpu->pdev->dev, "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n", @@ -1677,7 +1728,7 @@ static void a6xx_llc_slices_init(struct platform_device *pdev, a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL); } -static int a6xx_pm_resume(struct msm_gpu *gpu) +static int a6xx_gmu_pm_resume(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); @@ -1697,10 +1748,61 @@ static int a6xx_pm_resume(struct msm_gpu *gpu) a6xx_llc_activate(a6xx_gpu); - return 0; + return ret; } -static int a6xx_pm_suspend(struct msm_gpu *gpu) +static int a6xx_pm_resume(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); + struct a6xx_gmu *gmu = &a6xx_gpu->gmu; + unsigned long freq = 0; + struct dev_pm_opp *opp; + int ret; + + gpu->needs_hw_init = true; + + trace_msm_gpu_resume(0); + + mutex_lock(&a6xx_gpu->gmu.lock); + + pm_runtime_resume_and_get(gmu->dev); + pm_runtime_resume_and_get(gmu->gxpd); + + /* Set the core clock, having VDD scaling in mind */ + ret = dev_pm_opp_set_rate(&gpu->pdev->dev, gpu->fast_rate); + if (ret) + goto err_core_clk; + + ret = clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks); + if (ret) + goto err_bulk_clk; + + ret = clk_prepare_enable(gpu->ebi1_clk); + if (ret) + goto err_mem_clk; + + /* If anything goes south, tear the GPU down piece by piece.. */ + if (ret) { +err_mem_clk: + clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); +err_bulk_clk: + opp = dev_pm_opp_find_freq_ceil(&gpu->pdev->dev, &freq); + dev_pm_opp_put(opp); + dev_pm_opp_set_rate(&gpu->pdev->dev, 0); +err_core_clk: + pm_runtime_put(gmu->gxpd); + pm_runtime_put(gmu->dev); + } + mutex_unlock(&a6xx_gpu->gmu.lock); + + if (!ret) + msm_devfreq_resume(gpu); + + return ret; +} + +static int a6xx_gmu_pm_suspend(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); @@ -1727,11 +1829,62 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu) return 0; } +static int a6xx_pm_suspend(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); + struct a6xx_gmu *gmu = &a6xx_gpu->gmu; + unsigned long freq = 0; + struct dev_pm_opp *opp; + int i, ret; + + trace_msm_gpu_suspend(0); + + opp = dev_pm_opp_find_freq_ceil(&gpu->pdev->dev, &freq); + dev_pm_opp_put(opp); + + msm_devfreq_suspend(gpu); + + mutex_lock(&a6xx_gpu->gmu.lock); + + clk_disable_unprepare(gpu->ebi1_clk); + + clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); + + /* Set frequency to the minimum supported level (no 27MHz on A6xx!) */ + ret = dev_pm_opp_set_rate(&gpu->pdev->dev, freq); + if (ret) + goto err; + + pm_runtime_put_sync(gmu->gxpd); + pm_runtime_put_sync(gmu->dev); + + mutex_unlock(&a6xx_gpu->gmu.lock); + + if (a6xx_gpu->shadow_bo) + for (i = 0; i < gpu->nr_rings; i++) + a6xx_gpu->shadow[i] = 0; + + gpu->suspend_count++; + + return 0; + +err: + mutex_unlock(&a6xx_gpu->gmu.lock); + + return ret; +} + static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); + if (adreno_has_gmu_wrapper(adreno_gpu)) { + *value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER); + return 0; + } + mutex_lock(&a6xx_gpu->gmu.lock); /* Force the GPU power on so we can read this register */ @@ -1769,7 +1922,8 @@ static void a6xx_destroy(struct msm_gpu *gpu) drm_gem_object_put(a6xx_gpu->shadow_bo); } - a6xx_llc_slices_destroy(a6xx_gpu); + if (!adreno_has_gmu_wrapper(adreno_gpu)) + a6xx_llc_slices_destroy(a6xx_gpu); mutex_lock(&a6xx_gpu->gmu.lock); a6xx_gmu_remove(a6xx_gpu); @@ -2009,8 +2163,8 @@ static const struct adreno_gpu_funcs funcs = { .get_param = adreno_get_param, .set_param = adreno_set_param, .hw_init = a6xx_hw_init, - .pm_suspend = a6xx_pm_suspend, - .pm_resume = a6xx_pm_resume, + .pm_suspend = a6xx_gmu_pm_suspend, + .pm_resume = a6xx_gmu_pm_resume, .recover = a6xx_recover, .submit = a6xx_submit, .active_ring = a6xx_active_ring, @@ -2034,6 +2188,34 @@ static const struct adreno_gpu_funcs funcs = { .get_timestamp = a6xx_get_timestamp, }; +static const struct adreno_gpu_funcs funcs_gmuwrapper = { + .base = { + .get_param = adreno_get_param, + .set_param = adreno_set_param, + .hw_init = a6xx_hw_init, + .pm_suspend = a6xx_pm_suspend, + .pm_resume = a6xx_pm_resume, + .recover = a6xx_recover, + .submit = a6xx_submit, + .active_ring = a6xx_active_ring, + .irq = a6xx_irq, + .destroy = a6xx_destroy, +#if defined(CONFIG_DRM_MSM_GPU_STATE) + .show = a6xx_show, +#endif + .gpu_busy = a6xx_gpu_busy, +#if defined(CONFIG_DRM_MSM_GPU_STATE) + .gpu_state_get = a6xx_gpu_state_get, + .gpu_state_put = a6xx_gpu_state_put, +#endif + .create_address_space = a6xx_create_address_space, + .create_private_address_space = a6xx_create_private_address_space, + .get_rptr = a6xx_get_rptr, + .progress = a6xx_progress, + }, + .get_timestamp = a6xx_get_timestamp, +}; + struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) { struct msm_drm_private *priv = dev->dev_private; @@ -2055,18 +2237,36 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) adreno_gpu->registers = NULL; + /* Check if there is a GMU phandle and set it up */ + node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0); + /* FIXME: How do we gracefully handle this? */ + BUG_ON(!node); + + adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper"); + /* * We need to know the platform type before calling into adreno_gpu_init * so that the hw_apriv flag can be correctly set. Snoop into the info * and grab the revision number */ info = adreno_info(config->rev); - - if (info && (info->revn == 650 || info->revn == 660 || - adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), info->rev))) + if (!info) + return ERR_PTR(-EINVAL); + + /* Assign these early so that we can use the is_aXYZ helpers */ + /* Numeric revision IDs (e.g. 630) */ + adreno_gpu->revn = info->revn; + /* New-style ADRENO_REV()-only */ + adreno_gpu->rev = info->rev; + /* Quirk data */ + adreno_gpu->info = info; + + if (adreno_is_a650(adreno_gpu) || adreno_is_a660_family(adreno_gpu)) adreno_gpu->base.hw_apriv = true; - a6xx_llc_slices_init(pdev, a6xx_gpu); + /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ + if (!adreno_has_gmu_wrapper(adreno_gpu)) + a6xx_llc_slices_init(pdev, a6xx_gpu); ret = a6xx_set_supported_hw(&pdev->dev, config->rev); if (ret) { @@ -2074,7 +2274,10 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) return ERR_PTR(ret); } - ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); + if (adreno_has_gmu_wrapper(adreno_gpu)) + ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_gmuwrapper, 1); + else + ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); if (ret) { a6xx_destroy(&(a6xx_gpu->base.base)); return ERR_PTR(ret); @@ -2087,13 +2290,10 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) if (adreno_is_a618(adreno_gpu) || adreno_is_7c3(adreno_gpu)) priv->gpu_clamp_to_idle = true; - /* Check if there is a GMU phandle and set it up */ - node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0); - - /* FIXME: How do we gracefully handle this? */ - BUG_ON(!node); - - ret = a6xx_gmu_init(a6xx_gpu, node); + if (adreno_has_gmu_wrapper(adreno_gpu)) + ret = a6xx_gmu_wrapper_init(a6xx_gpu, node); + else + ret = a6xx_gmu_init(a6xx_gpu, node); of_node_put(node); if (ret) { a6xx_destroy(&(a6xx_gpu->base.base)); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index eea2e60ce3b7..51a7656072fa 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -76,6 +76,7 @@ int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state); void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state); int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); +int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu); void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c index 30ecdff363e7..4e5d650578c6 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c @@ -1041,16 +1041,18 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu) /* Get the generic state from the adreno core */ adreno_gpu_state_get(gpu, &a6xx_state->base); - a6xx_get_gmu_registers(gpu, a6xx_state); + if (!adreno_has_gmu_wrapper(adreno_gpu)) { + a6xx_get_gmu_registers(gpu, a6xx_state); - a6xx_state->gmu_log = a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.log); - a6xx_state->gmu_hfi = a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.hfi); - a6xx_state->gmu_debug = a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.debug); + a6xx_state->gmu_log = a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.log); + a6xx_state->gmu_hfi = a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.hfi); + a6xx_state->gmu_debug = a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.debug); - a6xx_snapshot_gmu_hfi_history(gpu, a6xx_state); + a6xx_snapshot_gmu_hfi_history(gpu, a6xx_state); + } /* If GX isn't on the rest of the data isn't going to be accessible */ - if (!a6xx_gmu_gx_is_on(&a6xx_gpu->gmu)) + if (!adreno_has_gmu_wrapper(adreno_gpu) && !a6xx_gmu_gx_is_on(&a6xx_gpu->gmu)) return &a6xx_state->base; /* Get the banks of indexed registers */ diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 84f25122afba..e6216b4169be 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -468,6 +468,10 @@ int adreno_load_fw(struct adreno_gpu *adreno_gpu) if (!adreno_gpu->info->fw[i]) continue; + /* Skip loading GMU firwmare with GMU Wrapper */ + if (adreno_has_gmu_wrapper(adreno_gpu) && i == ADRENO_FW_GMU) + continue; + /* Skip if the firmware has already been loaded */ if (adreno_gpu->fw[i]) continue; @@ -1021,8 +1025,8 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, u32 speedbin; int ret; - /* Only handle the core clock when GMU is not in use */ - if (config->rev.core < 6) { + /* Only handle the core clock when GMU is not in use (or is absent). */ + if (adreno_has_gmu_wrapper(adreno_gpu) || config->rev.core < 6) { /* * This can only be done before devm_pm_opp_of_add_table(), or * dev_pm_opp_set_config() will WARN_ON() diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index b4f9b1343d63..2c0f0ef094cb 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -115,6 +115,7 @@ struct adreno_gpu { * code (a3xx_gpu.c) and stored in this common location. */ const unsigned int *reg_offsets; + bool gmu_is_wrapper; }; #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base) @@ -145,6 +146,11 @@ struct adreno_platform_config { bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2); +static inline bool adreno_has_gmu_wrapper(struct adreno_gpu *gpu) +{ + return gpu->gmu_is_wrapper; +} + static inline bool adreno_is_a2xx(struct adreno_gpu *gpu) { return (gpu->revn < 300); From patchwork Thu Mar 30 23:25:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 77474 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp207009vqo; Thu, 30 Mar 2023 16:44:08 -0700 (PDT) X-Google-Smtp-Source: AKy350YI+ytyBkDKs0sRs3gbDBG4wVI/SsV8+GAjAc1i4JtuMX2sDnd0SL5lGwHmw1Vmdt6jeKUA X-Received: by 2002:a17:907:3f27:b0:870:b950:18d4 with SMTP id hq39-20020a1709073f2700b00870b95018d4mr31876100ejc.5.1680219847977; Thu, 30 Mar 2023 16:44:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680219847; cv=none; d=google.com; s=arc-20160816; b=PlHc0e/EHbjoHNje9b5KoRcLPn+LFN6LlqqoTp53Jwsk6MPOWmgbniuYnPJ2CuhtUw wMx0o3kFt3czDlHcaUgLfWGCAavegIMH4cgkDrxu60hzGG1GqMNfNXjMUg/JWwu4c8OR JFCluTzAE5+IbqJeX8RdOlOGRJksEe7jbXQrlaXCgsL5kGniDtotpJexQyJaYIdy14QW tcTle5usKxSu54+FDlmbyViZEB9u4i4tWlLRTqRj/PMZse4Ka3D0d5ck12iWrPLOHlCu deqIMWchtjigJ+VEd5cPoYYHuCZR6PqCC6lo1r5mOFYgh24FOa7YagWRxpFam8PtzczH dchg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=tBl7yKVCwhjc6yO5z/z3JPkwp8Wjhy3CVWsctbwDdiM=; b=hdjfMhk8npWjZiEvX1MfoQHMeFVA5EclewfMjUyYNU8WjxMSkUsP6i5nFoH5cF/RGN MJpek20XBfXOlW4i93Z70kqXjd1xq5wxO4840qKaD8QxyV6/bznVdvWqFxVvWx03OXWI QJaNRM11mJxIu52V+lzDBgmPM6m3K2ed7nsncyGz1UuEjQin5mFjjweL8B2iSJGwiZwW 16fkbyUTWdwctU6+0RxZEt7hH2dM1dDYrwJgUv1nNYFBrpKrCungqyaXhcDQ0569wC6H GuSoHmru7jgHNOHL/XUDcqwdL6wTuJRIVEKfwhIVqxeXCSfmV3C5TsOmzjTfvVAT+q+U nfGA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=J7ShoQYm; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id p19-20020a1709060e9300b00947748a272bsi671739ejf.139.2023.03.30.16.43.44; Thu, 30 Mar 2023 16:44:07 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=J7ShoQYm; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231633AbjC3X0V (ORCPT + 99 others); Thu, 30 Mar 2023 19:26:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48160 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231515AbjC3XZo (ORCPT ); Thu, 30 Mar 2023 19:25:44 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF3FE12054 for ; Thu, 30 Mar 2023 16:25:33 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id j11so26631000lfg.13 for ; Thu, 30 Mar 2023 16:25:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680218732; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=tBl7yKVCwhjc6yO5z/z3JPkwp8Wjhy3CVWsctbwDdiM=; b=J7ShoQYmlST31y9vYBnakfBjPumtRbVT2+SIx+XvGQGWIxuk7JkKCbQA7Xk5dA7I7L yZ7Re0fmWUaIlXxfUVhl61dmv4UTqVVwn0/71RSOC8CCQlcZIbtTiBESgNAnO/Puz2sn dt99mGqLsUiJ5OzFZ710eUgzsIVVs5WCwE8SA3uhPrfeqrHqJqq0xEXKqiG+coxQ1HXV jfYiChhzN3ApQ6Cb5Rpo99/IX34BPRwfuFJkXGHr8oG7RnlsFsj1eneyi6vhRqUerjDY gYuCVVRPlj97Y7Y0qgme6ECacS78PL8jQuPZJZ5mozwctG7FeA1QuVUwfFV7LGJpffaP 0Vwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680218732; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tBl7yKVCwhjc6yO5z/z3JPkwp8Wjhy3CVWsctbwDdiM=; b=itqt4l6BkN4vPHGgGoJFBtHacjQBz1h0tpC6NVFxsZaEy5gU7pfA1AqW/S6AhIJNvi 5k3WLR7AK16ZNZFBwP3Umd9D7h1Ta+xCiZHGnuo8Vn7kaZvRxlsW5XOd7stl59QZfWko SWqtF+l/EyOTjT5IcAkvfMVhGWsJdgMSDP72Qk/ugbr40KufmNDL3bM87wry785doJPN DhB2x3GSiGK5ECM6scL5tWYBi2DdXwclBvvEJPmAW/sUFhqfdbXNY3DA83+PGa5yIgP7 +A7TtFnzE/F0OtconunaqPFD3/3/2sShbwdYUR8UKryee0WGP3m4fIU7n6c2tjnPnCNd v5Tg== X-Gm-Message-State: AAQBX9cYop18O3VZh+hDVztRWkExn5N4AfihHBaanfIMlMjwNM8k2Ih9 J/1fxA34K2NEMBRb66HNJEsBiA== X-Received: by 2002:a05:6512:503:b0:4dc:823c:8127 with SMTP id o3-20020a056512050300b004dc823c8127mr7083593lfb.57.1680218732024; Thu, 30 Mar 2023 16:25:32 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id g26-20020ac2539a000000b004dda80cabf0sm127241lfh.172.2023.03.30.16.25.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 16:25:31 -0700 (PDT) From: Konrad Dybcio Date: Fri, 31 Mar 2023 01:25:21 +0200 Subject: [PATCH v5 07/15] drm/msm/a6xx: Remove both GBIF and RBBM GBIF halt on hw init MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v5-7-bf774b9a902a@linaro.org> References: <20230223-topic-gmuwrapper-v5-0-bf774b9a902a@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v5-0-bf774b9a902a@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680218720; l=1312; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=hzdufW67WGWbz2ZzqJov4K9OFxkr5eIp/rEY9Lr23FQ=; b=jUpAGWsk1sjcau7+3KKia8exWl7xlfLIwI0u4knrO022fI0vktcWsJ0R7MQyEWT0sZmd1gp+64Ru JkqYnxAhC9bGuEEKKOY17qjaRgmcj95XUwAmqk/IC5lmDqAdZZnn X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761838207186444289?= X-GMAIL-MSGID: =?utf-8?q?1761838207186444289?= Currently we're only deasserting REG_A6XX_RBBM_GBIF_HALT, but we also need REG_A6XX_GBIF_HALT to be set to 0. For GMU-equipped GPUs this is done in a6xx_bus_clear_pending_transactions(), but for the GMU-less ones we have to do it *somewhere*. Unhalting both side by side sounds like a good plan and it won't cause any issues if it's unnecessary. Also, add a memory barrier to ensure it's gone through. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index a7ecb0a87e98..30dae3ddc1c5 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1015,8 +1015,12 @@ static int hw_init(struct msm_gpu *gpu) } /* Clear GBIF halt in case GX domain was not collapsed */ - if (a6xx_has_gbif(adreno_gpu)) + if (a6xx_has_gbif(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); + /* Let's make extra sure that the GPU can access the memory.. */ + mb(); + } gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); From patchwork Thu Mar 30 23:25:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 77463 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp199791vqo; Thu, 30 Mar 2023 16:27:47 -0700 (PDT) X-Google-Smtp-Source: AKy350bQ6DgIIYms0r7ioieO/xhm1+BQKToc8rANs3LvOYeIVqld6rBSUjrci+g56HqWsPRyBKMg X-Received: by 2002:a05:6402:159:b0:501:caaf:1e5 with SMTP id s25-20020a056402015900b00501caaf01e5mr21244368edu.18.1680218867458; Thu, 30 Mar 2023 16:27:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680218867; cv=none; d=google.com; s=arc-20160816; b=X51HOAztwkBSoQpDa7fEyhNCoFhhdvM1YSPvymbc3lFP1f5NmfveolGuGCvnl6ByeJ uN7MG3T2TLFYd5ib0bAnvJm7/TQmo9WVgQ79oXinw12svEwWKecg3tr78xIn3y3OQVj4 RnA6U57iS88Ze8l0P2EXmeW99PWrmOxB+PUB5JpmBAPfINYqohyIhYPWNe9Ry5Eqz6LA +MATEmrSSuZI/m34FLWDibo64wzz+1/mbrdWrdvM94PyF9bCyZ0GSIOrhanUgmURYVgG OZ1H2XTUFqIPe9oAMWEYxB6JFVSPjASNGl/TIT59/ZnBkulJDsQNz0B7wD/5NeoUqvHw Oxpg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=UaQqSlW0Hu7wuwFuXxr7ZB+drxQgUbdgeqKDpKp7IHg=; b=H6wwUKZg3SzTTjJcobHZ0sqB9or6ZiY24OElZOszACR403aleZuK7VrM6Svzv9Y/bA Kq+plrGScDQXd7TN4AgCOI4pIrrao3bdXhzGNNbiCa6pJQsqK2IJ8ZITSlLvs+c5eExP 20ROz7RIIA2s6yKFzfgn1syam5op9DWJ55mubhujy/3wRJfRy3iPxGmCANFDlgWYZtgD azJsyzPuMciB5wQc6QmMTViqCn8e1JIHMQcRjMh2I29A7jVhyUaPNbeJNSEOexw2wVqf 960WBOb8tua+ihaJdDCsuCcx2mArhwcCAgiYhvVknNeIuUBk+6WMLDXzl4/7E4jem2P/ ULxg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VoTrTlyv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id u1-20020a50eac1000000b004c21e05c798si804595edp.27.2023.03.30.16.27.23; Thu, 30 Mar 2023 16:27:47 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VoTrTlyv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231627AbjC3X0S (ORCPT + 99 others); Thu, 30 Mar 2023 19:26:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48392 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231513AbjC3XZo (ORCPT ); Thu, 30 Mar 2023 19:25:44 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D1E6A1206F for ; Thu, 30 Mar 2023 16:25:33 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id j11so26631116lfg.13 for ; Thu, 30 Mar 2023 16:25:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680218733; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=UaQqSlW0Hu7wuwFuXxr7ZB+drxQgUbdgeqKDpKp7IHg=; b=VoTrTlyva0/pRKXMl0hn4cMaA39/aoaR4/8ZZAh9o6WOKfKpR+gWirGoGwaSRDGqFz wZFmjn8nSY2p8xKPZA6lftR2MBAJQJMH27B6gJAaQA9y0t799nBnuBCVQNt1R0kuc8yh 8NaYDB4FQxsNk76tF+PLdXIZ7tdboZeL+M34QC/xXxHlaoq4CDmFx2+b1PQKAlr+FQeb xgTa6pjpqnN0quEsuz3cueAy8Y+NVJPCfynlVTG2xSkzY/r0Te9iCC7dt7JjL27XnWcL VVMyDrqZt1LBIUYz7hci1aBNAUCHySUNSDC6TYbybc8ciCZ8lGVZ0iEwlfj5zf9TXOo8 0Z3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680218733; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UaQqSlW0Hu7wuwFuXxr7ZB+drxQgUbdgeqKDpKp7IHg=; b=3V4yQ6bM06r3GGu06H75dhsDwndwLupnoFO+tHG6sWhYIw5+7brxOhynBDct+Bfy62 NRazEIS7PinvLxLIfhtA3xw7fznV4cshfFDRJzhK8tOCoZoLNSQrBBExJGuDL7anMGPR R7xabjHJ7vjafSou0zMByUNIisS8scmriL6I++JH/HUWSnlJcAxGK9t36KB7JLRmhmQh 7+y2J8KU4fdcSylsNUw8aogvcoxmzC6P087wQ1CQJXbcykNck7zK5qgm7RqHDK0TEUDn XweNhOYfL6x6KmHsTSbxwcE4l8nnu5MOm/f319p30VH6oCby85gEba5EqdEqpxKa10NB Ax1g== X-Gm-Message-State: AAQBX9f/6KEVzJ2CgLw3Qtnwi7x0pcju9WmdjPZ9CIVx/fx3z+soWuyX O98ocy3THU3Mc/zj7dkwyMy1Wg== X-Received: by 2002:ac2:4105:0:b0:4db:381d:4496 with SMTP id b5-20020ac24105000000b004db381d4496mr6099217lfi.51.1680218733408; Thu, 30 Mar 2023 16:25:33 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id g26-20020ac2539a000000b004dda80cabf0sm127241lfh.172.2023.03.30.16.25.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 16:25:33 -0700 (PDT) From: Konrad Dybcio Date: Fri, 31 Mar 2023 01:25:22 +0200 Subject: [PATCH v5 08/15] drm/msm/adreno: Disable has_cached_coherent in GMU wrapper configurations MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v5-8-bf774b9a902a@linaro.org> References: <20230223-topic-gmuwrapper-v5-0-bf774b9a902a@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v5-0-bf774b9a902a@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680218720; l=1374; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=pgsq2wrmx2dN+DhvHdVkqgJZhLfKKJzRqreYHhrCBpQ=; b=ZUd/VafLrjD0054XVcT6XP030VEirGQOXi/zbif+vu4oYlkpmNnSi/9Idamps4JWET8miFA8TTAL JVJVISW5AWVNY9mdNYozBMeaZK6UK7taSwr4866ybvsItP8zQM7E X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761837179253464060?= X-GMAIL-MSGID: =?utf-8?q?1761837179253464060?= A610 and A619_holi don't support the feature. Disable it to make the GPU stop crashing after almost each and every submission - the received data on the GPU end was simply incomplete in garbled, resulting in almost nothing being executed properly. Extend the disablement to adreno_has_gmu_wrapper, as none of the GMU wrapper Adrenos that don't support yet seem to feature it. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/adreno_device.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 745f59682737..2c6de326187b 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -545,7 +545,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) config.rev.minor, config.rev.patchid); priv->is_a2xx = config.rev.core == 2; - priv->has_cached_coherent = config.rev.core >= 6; gpu = info->init(drm); if (IS_ERR(gpu)) { @@ -557,6 +556,10 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) if (ret) return ret; + if (config.rev.core >= 6) + if (!adreno_has_gmu_wrapper(to_adreno_gpu(gpu))) + priv->has_cached_coherent = true; + return 0; } From patchwork Thu Mar 30 23:25:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 77464 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp199833vqo; Thu, 30 Mar 2023 16:27:54 -0700 (PDT) X-Google-Smtp-Source: AKy350aYl+XM/cjLtRiNS4kbgre9Vlz8wQHRzc1FiDgq/Qh/pHZTXW2vJcDIZRZD3UvTxluYEi4B X-Received: by 2002:a17:907:a808:b0:93f:fbe:c389 with SMTP id vo8-20020a170907a80800b0093f0fbec389mr22444181ejc.13.1680218874413; Thu, 30 Mar 2023 16:27:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680218874; cv=none; d=google.com; s=arc-20160816; b=0Tj32+u4e5KRI1spm8X+6SfmuS1OSFaWQFGsggRQ6vNPVXJOIKgt4v+33d1OMz2qVk 0NGOj93touYjHOV9JdQWeO1MCN7gsgDCcjPzjpPMY/578qBIOidNkfJLMyREzPpY16hi l4dLdfljIE8o5LRHfXNjIm1jn6cTKYDvskF+ASNGkANW/IAAuZ3YoMLSBZc4ERCM+7AR kCWVsu+MaG6mgH4FJmnF6eLBGb9F130OnOrdcfzx9FEalwdweJgkJ1N9ne7KJO5hmEVK z4vszKqVEeKNU6yFKUPD+WHA1TkIm/nmIwS6U8ofB4DIy7gmxeZrpi3qm6P4bGuDRbvf +I1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=jMYlGeM0Pum7ZWZdlHUkAZRW+tOVgC4i2VoiIZndCqI=; b=TrYJBCBQxRhFR3L6GExpfWsu9iSTuGMxezSPCnSH3BbZfHZWBRjN6Ej3lMMfP83rXw NaEtXYIG6csEcRu2pVUlGsWPpntNvlXD1wN07+dtxbB8oa75Gh/DilLoVsBXZB8WhZet nGjpWZdFRPlzGT8ft++7U7t8mPKKGgdfirZsOCDwVQbu81o37l4r4CB2mDjeBEvJlhk/ N6OxNZpLNaqVUslqAbgcauVdbR2aR5wJyJInSTkDrYGNoM90IQ40viFL+qBjziTBl/cO ZxMnh2oksbQGnMkqr02lPBFjmkSX4EF4/Nwa+wnhZupd2YVWpYHm01KdZOOlF4l5xsUt ag1Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iuC4ERq9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id w7-20020a1709064a0700b00939fb8e7aabsi548574eju.784.2023.03.30.16.27.30; Thu, 30 Mar 2023 16:27:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iuC4ERq9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231648AbjC3X0Z (ORCPT + 99 others); Thu, 30 Mar 2023 19:26:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48402 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231346AbjC3XZo (ORCPT ); Thu, 30 Mar 2023 19:25:44 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5D4E612047 for ; Thu, 30 Mar 2023 16:25:35 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id y20so26699798lfj.2 for ; Thu, 30 Mar 2023 16:25:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680218735; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=jMYlGeM0Pum7ZWZdlHUkAZRW+tOVgC4i2VoiIZndCqI=; b=iuC4ERq9SpHi8DfCS6jg+ET0Pl9MP9M9QXPXPL6e9p2Tss0ixwXHpFxrBqiTsPn8cZ rjKkQ23LgEMT1ixZk4xcEUaCoazHpbzKQ7ISMxLJ6Rbsip058e6pJivm50Cpbom4W2ej vPl8HsVeTPZI+x0Bret0qv3mGCymS/8K1/ztxinG0I/3QiHJyo8ImUtgjOW99RCSvIFd W4xBHqVmw6TMe6ZN6vyZ1EQfhdHeci64crX2zOMJIVU2R4QxhFr71cgDpG0eo+jDndQD kyLh7IOBLyfLRgia4Z1P9Oh372lKd9vJVLlc+qKtV7Bp5yNINGeoyIfJap+WnEhGEzt5 zgsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680218735; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jMYlGeM0Pum7ZWZdlHUkAZRW+tOVgC4i2VoiIZndCqI=; b=X6VnTy0gGNRWTNAGwtCU4iKt+hDX5GwRoMygD5nHuRddcUyAKIkgH5VoQeA7qWLJPT CEGS2IezA00TzqK1r55yhPwETjf3n2No5OhL5s/EXhpGhl0TNEOeEMyGuiBORwICaVqn n1iHaQgI78BItBHlCfTfqlxb2tTgCdnsKjXAp6BN4Yj2UgRH4pP3PbKGaw7X2YBvVtBV CwyqfED5/bT3sMnLEMmP0xXbZdSPlG8UR0x02rx5cOslbz+BycHxVCcvTGawPIQXMbLH 47VXNMp9TS2OCrL0bR9E1JZWJnI68F0d8k4GoOs06XoyAmx51h1OrNIAdaL/K17agfCC Y83A== X-Gm-Message-State: AAQBX9ckSie7B+YWUBdooRwr9X1RPqaQ7IGV7ykNNlp6rfLGBhBfJvm5 R90ANZ1vv6fZmzJkb9NS1OHKaw== X-Received: by 2002:ac2:484a:0:b0:4dd:a73f:aede with SMTP id 10-20020ac2484a000000b004dda73faedemr6777961lfy.10.1680218734912; Thu, 30 Mar 2023 16:25:34 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id g26-20020ac2539a000000b004dda80cabf0sm127241lfh.172.2023.03.30.16.25.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 16:25:34 -0700 (PDT) From: Konrad Dybcio Date: Fri, 31 Mar 2023 01:25:23 +0200 Subject: [PATCH v5 09/15] drm/msm/a6xx: Add support for A619_holi MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v5-9-bf774b9a902a@linaro.org> References: <20230223-topic-gmuwrapper-v5-0-bf774b9a902a@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v5-0-bf774b9a902a@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680218720; l=5408; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=BOvli+a8A2NKtDDU27JWYXOoc6fVy8bQjLNL9lXnjH8=; b=FgsFs8n/V/d+jQnCzG92Ptu3ZTvQMOL2mUrgIV+5E/e4Idd6AEDiQ0TXDGUDJXjUe7BchnRJVX5a 2kU6QSPIBI7PHlIrdmpZudf06ckm6PFCwtbGOo65Hk7CCYXmIiki X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761837186941415298?= X-GMAIL-MSGID: =?utf-8?q?1761837186941415298?= A619_holi is a GMU-less variant of the already-supported A619 GPU. It's present on at least SM4350 (holi) and SM6375 (blair). No mesa changes are required. Add the required kernel-side support for it. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 47 ++++++++++++++++++++++++++------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 ++++ 2 files changed, 43 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 30dae3ddc1c5..d5ec57985387 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -614,14 +614,16 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) return; /* Disable SP clock before programming HWCG registers */ - if (!adreno_has_gmu_wrapper(adreno_gpu)) + if (!adreno_has_gmu_wrapper(adreno_gpu) || + adreno_is_a619_holi(adreno_gpu)) gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); for (i = 0; (reg = &adreno_gpu->info->hwcg[i], reg->offset); i++) gpu_write(gpu, reg->offset, state ? reg->value : 0); /* Enable SP clock */ - if (!adreno_has_gmu_wrapper(adreno_gpu)) + if (!adreno_has_gmu_wrapper(adreno_gpu) || + adreno_is_a619_holi(adreno_gpu)) gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0); @@ -814,6 +816,9 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) if (adreno_is_a618(adreno_gpu)) return; + if (adreno_is_a619_holi(adreno_gpu)) + hbb_lo = 0; + if (adreno_is_a640_family(adreno_gpu)) amsbc = 1; @@ -1015,7 +1020,12 @@ static int hw_init(struct msm_gpu *gpu) } /* Clear GBIF halt in case GX domain was not collapsed */ - if (a6xx_has_gbif(adreno_gpu)) { + if (adreno_is_a619_holi(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); + gpu_write(gpu, 0x18, 0); + /* Let's make extra sure that the GPU can access the memory.. */ + mb(); + } else if (a6xx_has_gbif(adreno_gpu)) { gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); /* Let's make extra sure that the GPU can access the memory.. */ @@ -1024,6 +1034,9 @@ static int hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); + if (adreno_is_a619_holi(adreno_gpu)) + a6xx_sptprac_enable(gmu); + /* * Disable the trusted memory range - we don't actually supported secure * memory rendering at this point in time and we don't want to block off @@ -1298,7 +1311,8 @@ static void a6xx_dump(struct msm_gpu *gpu) #define GBIF_CLIENT_HALT_MASK BIT(0) #define GBIF_ARB_HALT_MASK BIT(1) #define VBIF_RESET_ACK_TIMEOUT 100 -#define VBIF_RESET_ACK_MASK 0x00f0 +#define VBIF_RESET_ACK_MASK 0xF0 +#define GPR0_GBIF_HALT_REQUEST 0x1E0 static void a6xx_recover(struct msm_gpu *gpu) { @@ -1362,10 +1376,16 @@ static void a6xx_recover(struct msm_gpu *gpu) /* Software-reset the GPU */ if (adreno_has_gmu_wrapper(adreno_gpu)) { - /* Halt the GX side of GBIF */ - gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, GBIF_GX_HALT_MASK); - spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) & - GBIF_GX_HALT_MASK); + if (adreno_is_a619_holi(adreno_gpu)) { + gpu_write(gpu, 0x18, GPR0_GBIF_HALT_REQUEST); + spin_until((gpu_read(gpu, REG_A6XX_RBBM_VBIF_GX_RESET_STATUS) & + (VBIF_RESET_ACK_MASK)) == VBIF_RESET_ACK_MASK); + } else { + /* Halt the GX side of GBIF */ + gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, GBIF_GX_HALT_MASK); + spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) & + GBIF_GX_HALT_MASK); + } /* Halt new client requests on GBIF */ gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK); @@ -1380,7 +1400,10 @@ static void a6xx_recover(struct msm_gpu *gpu) /* Clear the halts */ gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); - gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); + if (adreno_is_a619_holi(adreno_gpu)) + gpu_write(gpu, 0x18, 0); + else + gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); /* This *really* needs to go through before we do anything else! */ mb(); @@ -1786,6 +1809,9 @@ static int a6xx_pm_resume(struct msm_gpu *gpu) if (ret) goto err_mem_clk; + if (adreno_is_a619_holi(adreno_gpu)) + a6xx_sptprac_enable(gmu); + /* If anything goes south, tear the GPU down piece by piece.. */ if (ret) { err_mem_clk: @@ -1851,6 +1877,9 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu) mutex_lock(&a6xx_gpu->gmu.lock); + if (adreno_is_a619_holi(adreno_gpu)) + a6xx_sptprac_disable(gmu); + clk_disable_unprepare(gpu->ebi1_clk); clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 2c0f0ef094cb..92ece15ec7d8 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -252,6 +252,11 @@ static inline int adreno_is_a619(struct adreno_gpu *gpu) return gpu->revn == 619; } +static inline int adreno_is_a619_holi(struct adreno_gpu *gpu) +{ + return adreno_is_a619(gpu) && adreno_has_gmu_wrapper(gpu); +} + static inline int adreno_is_a630(struct adreno_gpu *gpu) { return gpu->revn == 630; From patchwork Thu Mar 30 23:25:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 77465 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp200147vqo; Thu, 30 Mar 2023 16:28:37 -0700 (PDT) X-Google-Smtp-Source: AKy350aVEu2OxSeDRkuuNBoRQuLluRlCSMFPYX1CVjTcjxnEarZoyFXF8hCKn/6/4J314DXiSlrC X-Received: by 2002:a17:907:1c09:b0:930:f953:9608 with SMTP id nc9-20020a1709071c0900b00930f9539608mr35489374ejc.0.1680218917317; Thu, 30 Mar 2023 16:28:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680218917; cv=none; d=google.com; s=arc-20160816; b=WyXjxpDuKYh0CoPQYX96xOjlILpkyzW0Fj5sFgJDXRbfr8lqPC1W/F2aUu6ae613jD Wb2jmsNXrp2NUbTSyawJbNEk69qiXqROj7UTqcblEZvwxo9Lhhv87af4qF2dEukyWycY +zGPKAZnzVRdUrDacaOQFen4H5DKSmbdY2N56BvH7hBoTf+C3LprBTvg2KVmnkLmfNJv OTE4jhRZ+2HRp+N9doKK4Pr6pIw1OoBB1kX4Nqc1UiKyCzRVSeC0R1eMA1nGz5TUjr+2 qxwofckM8nWVftVJP11FF3dBH9PGyreNCaj96ehq7HPYA1PgnDXj2Rz5p/YlbvoINWsQ UFBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=Mc3+02g30f4IUqTsV5CwNC0jC8ZOf2FYF0BgRYdH1Jg=; b=NQolk5/fTMLDiQrTN/MG0V/Ks2YdI+suRDptLgyM3frcD1UFWiBsQl9jOgLz8rKVo6 NN/d7wUWdX/KmBFzjyYjYPdsRNFvYfdqVSCZhnDH2F2oUyfJgT4NeYUywUSB5Mgez3Qo Y352o/U5cjf6MkhZWIjbY38nXuQco/xLbSDNGJVgckpNZSrEcAI4yhKa17Weon4jT87x vjqLg/TE7NFkLf7Nehm7Qr9kTmobmu5tM9znazHRG3zhz1JRFkoFaRxiTOPfrh61z9Xz pDSgY0h2yuOZYajg8p31WHhN+H5APsMx6EwpMgqlFNQY1HjkjdMRWt22/jQMYK0M9EXm /v/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aF4DxLt9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id lb5-20020a170907784500b0093e0b659bc3si654810ejc.493.2023.03.30.16.28.13; Thu, 30 Mar 2023 16:28:37 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aF4DxLt9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231674AbjC3X03 (ORCPT + 99 others); Thu, 30 Mar 2023 19:26:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48210 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231522AbjC3XZp (ORCPT ); Thu, 30 Mar 2023 19:25:45 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D7B981204A for ; Thu, 30 Mar 2023 16:25:36 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id g17so26676243lfv.4 for ; Thu, 30 Mar 2023 16:25:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680218736; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Mc3+02g30f4IUqTsV5CwNC0jC8ZOf2FYF0BgRYdH1Jg=; b=aF4DxLt9PGD1ztoHq04m0FqyhJo1st+8Xsi/9r4lruJROHVaQS/+5xdmtuKhfd810G 4Ug94NgBZO21Ki0Z/QC5Ab7TKITALR5W+92DmL//baoWy/3csP52OlKHBPya0K/fkrsD 6OL8GMefi5H9fPs+ApESTGIliCCVelkxH1FkUFgU9ZWYXMDnBWSxg4vlGGtjmd9+sEqf +H8DSTEwLstpmpv0SNvMdUfkIQn1QpZbGYtjrmhKfOzj6xxwCedevLUlT0mLZznFrMav ANdZEGRsesUel/3LLmKf+qvdMIO4ZgKjbsWOqkaYAgSDkTCpDPZ/umJKMcoBTKmuyJjC n6tQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680218736; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Mc3+02g30f4IUqTsV5CwNC0jC8ZOf2FYF0BgRYdH1Jg=; b=q4sHYmiKtkg6BUX3kEuncSQU+fEMBDt3ZQj3S4Kib4qRQvDwfbZrRajCHLYHUu4yxp fUNaOy5S99G7nDc/3PBrYsaHBrzxGQzCWEBH0yZL8fmursV2EdzHsz7HX7cPFy7n0b+y IrBHuMsJWQU1n8npKbXtip6lsuOsCZFgkGNiQFYKbhJVdMDU8omkPF1lCiCcJbXEhyvD oU4J6kuhaThlMwsa9tlfutoyCZ6EIswomjqLjUycytitzZ9xa8qtAc+GTyoIYZ5xr3TT iQyeBmCvVXHqTquXngV42Z7f96K76tUYO7Ntup9NcoZyBEGwcNsHXSLwQQU/qlJ31Jgg KWKg== X-Gm-Message-State: AAQBX9dO6qCp3jOtUihpBL8EG2M+rPMgMeNWQzSAy7wR88svmwF9CLJf sBR3pB/VlM8LPf74xNRBuKA3iQ== X-Received: by 2002:ac2:44d9:0:b0:4e8:61d2:72ee with SMTP id d25-20020ac244d9000000b004e861d272eemr8277870lfm.5.1680218736374; Thu, 30 Mar 2023 16:25:36 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id g26-20020ac2539a000000b004dda80cabf0sm127241lfh.172.2023.03.30.16.25.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 16:25:36 -0700 (PDT) From: Konrad Dybcio Date: Fri, 31 Mar 2023 01:25:24 +0200 Subject: [PATCH v5 10/15] drm/msm/a6xx: Add A610 support MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v5-10-bf774b9a902a@linaro.org> References: <20230223-topic-gmuwrapper-v5-0-bf774b9a902a@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v5-0-bf774b9a902a@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680218720; l=10110; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=GVrzcJW35u62OwIcu0O8oxOpw8LNii2j2J+Bv0AbUZs=; b=lcMsWSX1EeGwLALVG2jJ9nl2Q4N+8LKO3ZW5uauHqtxMA9GELFPViBnzhP7UNO0pD00q5mu8GMMc UEQNqkHKAxZCtD9vrIpGptn2Y9PcS/XtsMEAbf2yVd6TAqxsUnoW X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761837231257942590?= X-GMAIL-MSGID: =?utf-8?q?1761837231257942590?= A610 is one of (if not the) lowest-tier SKUs in the A6XX family. It features no GMU, as it's implemented solely on SoCs with SMD_RPM. What's more interesting is that it does not feature a VDDGX line either, being powered solely by VDDCX and has an unfortunate hardware quirk that makes its reset line broken - after a couple of assert/ deassert cycles, it will hang for good and will not wake up again. This GPU requires mesa changes for proper rendering, and lots of them at that. The command streams are quite far away from any other A6XX GPU and hence it needs special care. This patch was validated both by running an (incomplete) downstream mesa with some hacks (frames rendered correctly, though some instructions made the GPU hangcheck which is expected - garbage in, garbage out) and by replaying RD traces captured with the downstream KGSL driver - no crashes there, ever. Add support for this GPU on the kernel side, which comes down to pretty simply adding A612 HWCG tables, altering a few values and adding a special case for handling the reset line. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 97 +++++++++++++++++++++++++++--- drivers/gpu/drm/msm/adreno/adreno_device.c | 12 ++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 8 ++- 3 files changed, 107 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index d5ec57985387..7d14a9cfd410 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -254,6 +254,56 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) a6xx_flush(gpu, ring); } +const struct adreno_reglist a612_hwcg[] = { + {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, + {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081}, + {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf}, + {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, + {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, + {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222}, + {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, + {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00}, + {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, + {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, + {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, + {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, + {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222}, + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, + {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, + {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, + {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, + {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, + {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, + {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, + {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, + {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, + {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, + {}, +}; + /* For a615 family (a615, a616, a618 and a619) */ const struct adreno_reglist a615_hwcg[] = { {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, @@ -604,6 +654,8 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) if (adreno_is_a630(adreno_gpu)) clock_cntl_on = 0x8aa8aa02; + else if (adreno_is_a610(adreno_gpu)) + clock_cntl_on = 0xaaa8aa82; else clock_cntl_on = 0x8aa8aa82; @@ -812,6 +864,13 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) /* Unknown, introduced with A640/680 */ u32 amsbc = 0; + if (adreno_is_a610(adreno_gpu)) { + /* HBB = 14 */ + hbb_lo = 1; + min_acc_len = 1; + ubwc_mode = 1; + } + /* a618 is using the hw default values */ if (adreno_is_a618(adreno_gpu)) return; @@ -1063,13 +1122,13 @@ static int hw_init(struct msm_gpu *gpu) a6xx_set_hwcg(gpu, true); /* VBIF/GBIF start*/ - if (adreno_is_a640_family(adreno_gpu) || + if (adreno_is_a610(adreno_gpu) || + adreno_is_a640_family(adreno_gpu) || adreno_is_a650_family(adreno_gpu)) { gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620); gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620); gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620); gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); - gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3); } else { gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3); @@ -1097,18 +1156,26 @@ static int hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804); gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4); - if (adreno_is_a640_family(adreno_gpu) || - adreno_is_a650_family(adreno_gpu)) + if (adreno_is_a640_family(adreno_gpu) || adreno_is_a650_family(adreno_gpu)) { gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140); - else + gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); + } else if (adreno_is_a610(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x00800060); + gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x40201b16); + } else { gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0); - gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); + gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); + } if (adreno_is_a660_family(adreno_gpu)) gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020); /* Setting the mem pool size */ - gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128); + if (adreno_is_a610(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 48); + gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 47); + } else + gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128); /* Setting the primFifo thresholds default values, * and vccCacheSkipDis=1 bit (0x200) for A640 and newer @@ -1119,6 +1186,8 @@ static int hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200); else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200); + else if (adreno_is_a610(adreno_gpu)) + gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00080000); else gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00180000); @@ -1134,8 +1203,10 @@ static int hw_init(struct msm_gpu *gpu) a6xx_set_ubwc_config(gpu); /* Enable fault detection */ - gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, - (1 << 30) | 0x1fffff); + if (adreno_is_a610(adreno_gpu)) + gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3ffff); + else + gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x1fffff); gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1); @@ -1376,6 +1447,14 @@ static void a6xx_recover(struct msm_gpu *gpu) /* Software-reset the GPU */ if (adreno_has_gmu_wrapper(adreno_gpu)) { + /* 11nm chips (i.e. A610-hosting ones) have HW issues with the reset line */ + if (!adreno_is_a610(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, 1); + gpu_read(gpu, REG_A6XX_RBBM_SW_RESET_CMD); + udelay(100); + gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, 0); + } + if (adreno_is_a619_holi(adreno_gpu)) { gpu_write(gpu, 0x18, GPR0_GBIF_HALT_REQUEST); spin_until((gpu_read(gpu, REG_A6XX_RBBM_VBIF_GX_RESET_STATUS) & diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 2c6de326187b..f61896629be6 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -253,6 +253,18 @@ static const struct adreno_info gpulist[] = { .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, .init = a5xx_gpu_init, .zapfw = "a540_zap.mdt", + }, { + .rev = ADRENO_REV(6, 1, 0, ANY_ID), + .revn = 610, + .name = "A610", + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + }, + .gmem = (SZ_128K + SZ_4K), + .inactive_period = 500, + .init = a6xx_gpu_init, + .zapfw = "a610_zap.mdt", + .hwcg = a612_hwcg, }, { .rev = ADRENO_REV(6, 1, 8, ANY_ID), .revn = 618, diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 92ece15ec7d8..27c30a7694f4 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -55,7 +55,8 @@ struct adreno_reglist { u32 value; }; -extern const struct adreno_reglist a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[]; +extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[]; +extern const struct adreno_reglist a660_hwcg[]; struct adreno_info { struct adreno_rev rev; @@ -242,6 +243,11 @@ static inline int adreno_is_a540(struct adreno_gpu *gpu) return gpu->revn == 540; } +static inline int adreno_is_a610(struct adreno_gpu *gpu) +{ + return gpu->revn == 610; +} + static inline int adreno_is_a618(struct adreno_gpu *gpu) { return gpu->revn == 618; From patchwork Thu Mar 30 23:25:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 77475 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp207050vqo; Thu, 30 Mar 2023 16:44:14 -0700 (PDT) X-Google-Smtp-Source: AKy350bAhdoUpZdIUcQN+oXvdbBKGCjxhCKlD1zCfJySeAw79HQkDO5hx9tHMklDB5iCqdHh1Fxx X-Received: by 2002:a17:906:641:b0:933:9f43:5c3b with SMTP id t1-20020a170906064100b009339f435c3bmr26693959ejb.59.1680219854252; Thu, 30 Mar 2023 16:44:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680219854; cv=none; d=google.com; s=arc-20160816; b=0e2E8m7VJu/mGaLTadspMuyQNDyyoLgXH1JWeGHbQwDh65rwNSTTlPlH45r8lbCpHH 2+THXOd1lifT6HDsWOk4ABPceDh/C7NWBq81WgMZXCfBNZzCnZ6zO8vOwJdmszfJ5OLk jb8ACWObPENM+JVBXymacg2WRWPtrcwkaQN9VoE2bKMOQRlH1iKw/8EU340KCdn/reP8 QOgAl02DgdTAkPUpTiBAc7gLfs4V10an7iiabSOeorSykLDu+FGymXkrq11Hv1DJWSO8 GdBRwqUm50bpATT2qAH6BHKWNn6LkE1+5cb0SAjGyvzlzRoqVBICLU8pS9n8Yfv3m1+k BPNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=r1qkEAaQNTO/CD5dWLHAfXm+a6T+9M+SqzmBcYhiN1U=; b=tSnpmshuQBtfUXSSTPVUD3Olzvmc3eGkfbneXOeD1oXw0Zzv0fxRdF8qangKRjjLgx UkSmFcI1ePSwQB3e8+aaaPT2Zcn//LDYnXTDsmePHlGXOBOy7ABMhy23y94CzE831tAa 8XNfM2bhaiDaW24g3r+lGEHj+kzDuXjED2vsriPnRksR+c5fHo0kdnJCnjJhQKvDw6lr 09gXFe1f3+5fedroumlnnh5RdWSm9o8eIyyuEyBCcIVSFSUOBPgk/PawvGPSgsDmNXBo phQSIXv34MiXbXQv4JKvB1JhciHeZVwnIAT6nxvrfhvRp8m/IR8jGl/IL0pJ33nqLk70 zFsg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CCeeNvjD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id n3-20020a17090695c300b0093e3a33d7easi785486ejy.451.2023.03.30.16.43.50; Thu, 30 Mar 2023 16:44:14 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CCeeNvjD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231680AbjC3X0b (ORCPT + 99 others); Thu, 30 Mar 2023 19:26:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48420 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231361AbjC3XZp (ORCPT ); Thu, 30 Mar 2023 19:25:45 -0400 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6908012C for ; Thu, 30 Mar 2023 16:25:39 -0700 (PDT) Received: by mail-lf1-x12b.google.com with SMTP id y15so26655749lfa.7 for ; Thu, 30 Mar 2023 16:25:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680218737; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=r1qkEAaQNTO/CD5dWLHAfXm+a6T+9M+SqzmBcYhiN1U=; b=CCeeNvjDBGJBgtguU2LCva5SOHxRmjKNbrSLW+DIrcTTirGjkgnND/QAV+reebxVzx dhoirrKQbSD/jwdfub2xWCF9ICWALYsmwJpfT+O3ITzKdXxH7B5ukjKfYeivuLvdl4vH tQYgSy/4eysQhu5ORxdOIRuz/+WCFM1UQycow/Z2S+IYn25UIj8wo15UyOPOMVp40/47 skknMOsCcU1Lh2nqDn7yx6qtaZRRDdzw+sZdUgICRARqOy92vyuTej6FTf4D2m1UAqjt +snu5SnM1xf4ogsyxCYXWc9TpKgkH61HhtBl7yKY957g7YLrgLA34aQGk8gonRN5vZK6 e3TQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680218737; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r1qkEAaQNTO/CD5dWLHAfXm+a6T+9M+SqzmBcYhiN1U=; b=zPgwPLlNSI8KArg87q0FF+3fzzDL2482Mq7l2GuJqB+nc5NsUHDRvh1i7fDxLGYZpl oL5Cg2S2410p4Jw51dcAbuqp/gVXrTF+tGafBjqCo5GqhYIgdpZ/Gl8TuJgRgddvUXB6 VNUp+hn+MdE5r1+sz3z4wlqgzzBSOebcObxvcJpMjuLSkih8NYeS+0zQMd4I+/0s42FE 0uv4A30P30+Ec0e/IfDgGfc5+EAbnDvKI2Pc0Zs53XY09A3HBUkj4tf4HEOxvPldaM3o TuMr0/kBXpk/RSqai/KT51mxdnbM62GQ98YE0qOYOOnXrmGa4otx2dyr6TQO9IebWzeh iq5w== X-Gm-Message-State: AAQBX9dkJnq1I4zxl7TRfAmR8ndk1yOCSJIdcDIfrI4/U5+iTPLdIQoG WEYIK2kFj94ABno5zvPQU3SzgQ== X-Received: by 2002:ac2:5a03:0:b0:4e9:d53:a5ef with SMTP id q3-20020ac25a03000000b004e90d53a5efmr7058419lfn.1.1680218737770; Thu, 30 Mar 2023 16:25:37 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id g26-20020ac2539a000000b004dda80cabf0sm127241lfh.172.2023.03.30.16.25.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 16:25:37 -0700 (PDT) From: Konrad Dybcio Date: Fri, 31 Mar 2023 01:25:25 +0200 Subject: [PATCH v5 11/15] drm/msm/a6xx: Fix some A619 tunables MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v5-11-bf774b9a902a@linaro.org> References: <20230223-topic-gmuwrapper-v5-0-bf774b9a902a@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v5-0-bf774b9a902a@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680218720; l=1537; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=vSIgBLooy4SpPau69jLvwPl464u8HClYRgiP0Hf1QqY=; b=NJKrNhAXk0iryuQaH1Cq4X0A6u4XrEdf3rOBDV+BNa5JPIq8uIm8pH5yaiEBJnxqODbpjp+1c8VW MrRIbbAiCJSOCUgRmPBNMEBVZVf8eU999xXHzCUrK+K+GpjyJV7r X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761838213672238459?= X-GMAIL-MSGID: =?utf-8?q?1761838213672238459?= Adreno 619 expects some tunables to be set differently. Make up for it. Fixes: b7616b5c69e6 ("drm/msm/adreno: Add A619 support") Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 7d14a9cfd410..1f553451ffa5 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1186,6 +1186,8 @@ static int hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200); else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200); + else if (adreno_is_a619(adreno_gpu)) + gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00018000); else if (adreno_is_a610(adreno_gpu)) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00080000); else @@ -1203,7 +1205,9 @@ static int hw_init(struct msm_gpu *gpu) a6xx_set_ubwc_config(gpu); /* Enable fault detection */ - if (adreno_is_a610(adreno_gpu)) + if (adreno_is_a619(adreno_gpu)) + gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3fffff); + else if (adreno_is_a610(adreno_gpu)) gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3ffff); else gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x1fffff); From patchwork Thu Mar 30 23:25:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 77472 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp205770vqo; Thu, 30 Mar 2023 16:41:07 -0700 (PDT) X-Google-Smtp-Source: AKy350b5gu50sUKG9WcpWEPSs+dKWv0uhvMPpM8tU4qcpnF2k4Se6/vJZfHCWBb+9nOaLZqp/CNd X-Received: by 2002:a17:903:32d1:b0:196:595b:2580 with SMTP id i17-20020a17090332d100b00196595b2580mr26321362plr.0.1680219667000; Thu, 30 Mar 2023 16:41:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680219666; cv=none; d=google.com; s=arc-20160816; b=LPsSp0oCMKFs/fc8nGMfr0rJakTCArpypq272g73TNjJqPOuU2Mpg/exQ3QpeKwZUH VWPYy/YOQEQMb870JX4dARz9jGEFTsW1lZPBlmZMtEddb6Dy2r4IAJK6iBlDyzSi+TSY gucDDiLZMPnfDrmt1csfqKxANFWhGXgVmDKgi9Fmu7gMgzdq96T5phAIURE3AkGJDSvz Fl2I/vGCHtf8cjDbcPWNggrR3FObwwtqEM+7J6+CZkEagdzmccduByGxZkWk+qyOvZKj I/EVpOVH8TtLyme6EdRT0L6H9znCFf2TUDKhypUMQPn16QJ2mDN9SWiGndddfHdWqg1e rdPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=UJtkSDvqvd+N2tN3r+04S+rFblpzh6izfhKCgwy399E=; b=LDDzmpjNlqlz8UIgsCq7cpPvj8/V5Rxw6xlHFdD2Y56RhWOJfvatIwTCfdFdkDVTtc S5oGCtRcP+UiUfcsRPReLXHvjAyr/N01/Ed0ACDEDaEPsSDdy6KhhxmtvCBCTqvdwQ7X T3dPUuQIP9niPY00sIV09GuxFOSZPyf7MTFK862D7KVaCgh1vltMxIopmDeAUms/P1Yv HJNw87/4QhR1Hf1Gb7Gg2IQhHoNaaQ1OLMwlpMxSrnSs9p9Q3EfTZHjJzHMy1RsKb0i1 FKLQb+DMRFLgR810Z6zR3go62TNCuHVpXUHRd/AEZsxF6gtFQQPWuf25ro2GGoIvmTNm pJaQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="s/HQPOId"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id iw12-20020a170903044c00b0019ceb4b753fsi695842plb.26.2023.03.30.16.40.54; Thu, 30 Mar 2023 16:41:06 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="s/HQPOId"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231544AbjC3X0g (ORCPT + 99 others); Thu, 30 Mar 2023 19:26:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47828 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231265AbjC3XZp (ORCPT ); Thu, 30 Mar 2023 19:25:45 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AE7D661BF for ; Thu, 30 Mar 2023 16:25:39 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id x17so26680402lfu.5 for ; Thu, 30 Mar 2023 16:25:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680218739; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=UJtkSDvqvd+N2tN3r+04S+rFblpzh6izfhKCgwy399E=; b=s/HQPOIdCM2wx2RJyNPmcY8kV97ZK8TPWptMk4d6ChufFzl048iV/b0pKilbqFYFLM fctgLgBgPNtgNKads49nSe5vS+rLAtQVuL9a+yYSNcVoTB8JMy3Kk5m/b3jaqc2/XMvQ 0tVWo+ncgHjFdoUK3n4NOk/beBq1RiIIDAQJ3Qco1DQJQBN+IoG/2w9X+7Kia0WY3pRC ze/1Nrv13evTUnj68o0qPswjVD/wOlvfp9ZjP+xqoDC+OeKzABkYRkbfdXS2NYqmOa8E HBclZC+f95kzpkBktPHPl5FZZXOYiyZ4AyC9NUkCwl/yzZ4TTmyZc4UJTyDHdsqnW7oD kaOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680218739; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UJtkSDvqvd+N2tN3r+04S+rFblpzh6izfhKCgwy399E=; b=sRm3Ka2A6ZELZauJd14zRGZ2DvwmxGyiN6a1yqMF0xYFQtZbOdV+FqLtsUJbWzSjgQ Am50oSe/4L2r+S3IrHdlsH8l6gQiOufRp2Z+iyto+Z4m/F7jPCVhWfesjn2Xy1N7bu8E efChZ0IODUjSFEmJ3uAY1+rj6vwfAWV5bt3R5J6/trJW5W1dqTfi3TJOoSBjEXKWEXEB eoK0L1FU296S92w3gxvZT3lVZjemD2qFzHwR/fSOvmLsUEsAn8+R48PiDNacLDUZvAji uocVXtul9A0f/iWFUHLbuDSFDFYK7U7tHxSdvYufVzlfCn9mHV7/jfhbAwcrgvDtxPcl ieAQ== X-Gm-Message-State: AAQBX9cARHcQu4WH3XdaLFtHwANMaMhDTmg8x3zD/TNaRdhn4aMwVDhf vOxxk1Pgt08WCH+i97aU1JhV8g== X-Received: by 2002:a19:910f:0:b0:4dc:8049:6f36 with SMTP id t15-20020a19910f000000b004dc80496f36mr2150438lfd.1.1680218739267; Thu, 30 Mar 2023 16:25:39 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id g26-20020ac2539a000000b004dda80cabf0sm127241lfh.172.2023.03.30.16.25.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 16:25:38 -0700 (PDT) From: Konrad Dybcio Date: Fri, 31 Mar 2023 01:25:26 +0200 Subject: [PATCH v5 12/15] drm/msm/a6xx: Use "else if" in GPU speedbin rev matching MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v5-12-bf774b9a902a@linaro.org> References: <20230223-topic-gmuwrapper-v5-0-bf774b9a902a@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v5-0-bf774b9a902a@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680218720; l=1434; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=s5xbHS5B3ZCiDUXL36LQuQu/YVWHv1Qws9XL8zObDRw=; b=0lrLA/hfvQb9236UuY0WgfSVa7GWwFJWUOE4cP7zBhaQUQVZPEH06Zl/rGSuLhfW8wRkV8u9tTsT woreoyUMDHtF32a1vNknVlAKJy5ylWmHmItoggCtDa0EAchVD7A9 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761838017623406113?= X-GMAIL-MSGID: =?utf-8?q?1761838017623406113?= The GPU can only be one at a time. Turn a series of ifs into if + elseifs to save some CPU cycles. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 1f553451ffa5..87ff48f7f3be 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2224,16 +2224,16 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse) if (adreno_cmp_rev(ADRENO_REV(6, 1, 8, ANY_ID), rev)) val = a618_get_speed_bin(fuse); - if (adreno_cmp_rev(ADRENO_REV(6, 1, 9, ANY_ID), rev)) + else if (adreno_cmp_rev(ADRENO_REV(6, 1, 9, ANY_ID), rev)) val = a619_get_speed_bin(fuse); - if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev)) + else if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev)) val = adreno_7c3_get_speed_bin(fuse); - if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev)) + else if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev)) val = a640_get_speed_bin(fuse); - if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev)) + else if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev)) val = a650_get_speed_bin(fuse); if (val == UINT_MAX) { From patchwork Thu Mar 30 23:25:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 77466 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp200275vqo; Thu, 30 Mar 2023 16:29:00 -0700 (PDT) X-Google-Smtp-Source: AKy350bZhHYGAhxIU5RpGQGw8DQJtW/GqwBVl/i2UV266lgk95CG4hm9rE+nSH+wu9K+6zoQlmqM X-Received: by 2002:aa7:c7d4:0:b0:4fb:1b0d:9f84 with SMTP id o20-20020aa7c7d4000000b004fb1b0d9f84mr24173078eds.6.1680218940058; Thu, 30 Mar 2023 16:29:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680218940; cv=none; d=google.com; s=arc-20160816; b=x1+6D7pfBMWNsh6TbrXhgn6BUvltu5MTyjq5BGMnPq2Wea7YCfCSaFbnssCiSeeW7C 79DUChwaD8G3758UZETCCD1bx2VknKTbVJaMypbaCak2OXFHD9mZgLFT+KVtAt7HcJdV lOUHbDS40J4uQfM0T0uugY1DZjftZdUjFfkQweFX7+1rhqzw7sqmcpRn7HZ923ZSPXsz BUwoVdCrii5u4dN+shlgVyRxJu2pDB8X4ZQN4lFSGYh3aP2KW+1iye2g+e/b8uXDVoB6 O1qr/Mhzj8QGBkCGm3yytOGyhEc/YiiQn4///ZF5FtGZNOdBidYEdVxJU9aUYfW5gHt+ brWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=q1FWJRMGgz7aV9ZtXAOSh14E/RuMW29Ts/RhMsLc3qw=; b=QP4inZO5WHfDYYWXIqtCR6qAOk5/R9vsIcSYkJc5a4CGTWAB3940k5Yn3+ELZVCN4r WIwkPHq1wMJWAj3baYTLCD1pGdaMa309CfXaKmXU2AQGJ6BvMo3G++ZSZb+AnCrKDtQ5 1MdI0JCVWQ2eZojS1wzNBvVlpwmmNVyEKCpQusckZlLNyK12yF0/7CX8WFHbcwDSCu5v ooiqSc5JAbOlEc7qhCgYxmKCfce/CLEUL9fOWTqmmtQFRiHNNptGsLqGwKvsIsZ6sysl G1VfLzWarWMNvqhRhCEcmmFJHR9sBcU71cP28h+RLVV7AHoIa3rhlmuu2vBWh/iCUrw9 QpoQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=U+ovZeV0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id b22-20020a05640202d600b004fbc9801ff2si847860edx.86.2023.03.30.16.28.36; Thu, 30 Mar 2023 16:29:00 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=U+ovZeV0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231689AbjC3X0l (ORCPT + 99 others); Thu, 30 Mar 2023 19:26:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47744 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231534AbjC3XZq (ORCPT ); Thu, 30 Mar 2023 19:25:46 -0400 Received: from mail-lj1-x22b.google.com (mail-lj1-x22b.google.com [IPv6:2a00:1450:4864:20::22b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6BB5D134 for ; Thu, 30 Mar 2023 16:25:42 -0700 (PDT) Received: by mail-lj1-x22b.google.com with SMTP id by14so2113193ljb.12 for ; Thu, 30 Mar 2023 16:25:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680218740; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=q1FWJRMGgz7aV9ZtXAOSh14E/RuMW29Ts/RhMsLc3qw=; b=U+ovZeV09WikUDRmuCGGR4WGciBDtJByqMAPdTtYDhuKlBMFft6o9t9wMZJT1ezICb 8L5lgEs/eeJ9cg34ImBZZk8pxZYkQi46FUaVTYyUdsJb27oBYz7pkIc5xyXGhMye4MH1 3ZO7IWoZcas3YML0sg1EnbCg6do6OeCbVydQCfeOjo0OwcoZ4qh6j/xhwN0gtdmhKUie A03fYpmebDvr36Uy8zLF+N9tCpByDJUj0BEA8rLBmPJkAKehjFqU3tXmsr0/kSoEmP8e oNz17VhWsWG3jlk9koIyMWuF4j4d3FoyS5w2EyR0kvy+rKMeWa7cYPm4GgXveHHqC5G0 BwaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680218740; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=q1FWJRMGgz7aV9ZtXAOSh14E/RuMW29Ts/RhMsLc3qw=; b=Q5dXaFWnzVYhRziwbOfqRazq3VZjREozxQmX7PcqlJ6FU9rYukczLvihSXibHF92hw zimHNawtW6gKFhJVtiVyRdtZyfEHL8wZBux3BZ7zVsZz/aBNrWQ2qInTgK96qzv4Bn89 3IXpVbArwic80/pEyJTqZZUWf80b0AYl0mzvubV2lpFVWCRhHforHIivL8ZRmDNaqr1g jMztBrjWsZSI6QJQGg6F/mezOkwvUqNSUbO/XO+Il30MiFYlzvKe2yrjTIdCvfPhXj9Y 5XRC+YhnurYWThwX0lW83dAJeeg9Gx3rhCRzGJ4HTQ117taePdB0fZaxk2rBrUFqantx inog== X-Gm-Message-State: AAQBX9d4f/zWQtIZzNfRjd5hYFHOhDqCjwOjnYJNE+RCm1EtPHBsbSlb z7sW2QCD/VoQK4vgZnI2GI9khA== X-Received: by 2002:a2e:985a:0:b0:293:2bc6:d50b with SMTP id e26-20020a2e985a000000b002932bc6d50bmr7907414ljj.18.1680218740674; Thu, 30 Mar 2023 16:25:40 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id g26-20020ac2539a000000b004dda80cabf0sm127241lfh.172.2023.03.30.16.25.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 16:25:40 -0700 (PDT) From: Konrad Dybcio Date: Fri, 31 Mar 2023 01:25:27 +0200 Subject: [PATCH v5 13/15] drm/msm/a6xx: Use adreno_is_aXYZ macros in speedbin matching MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v5-13-bf774b9a902a@linaro.org> References: <20230223-topic-gmuwrapper-v5-0-bf774b9a902a@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v5-0-bf774b9a902a@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680218720; l=4317; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Z8b5MMFV+Q5ky2mjKEOT7/xH7FsQTUvRZc+M3VORM24=; b=g9uDfzN3dWgZtQ4KWSuhtL4T30Wvm1Pud1+RnoBzRpI20m2XeZ4pVGB6W8k5a20woxEjOIuALfMj Md3D5irPDWyrCHzQm1qU3chTjQbCAZPyKoSKg2wnb7uZ5ApRAMhV X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761837255621922040?= X-GMAIL-MSGID: =?utf-8?q?1761837255621922040?= Before transitioning to using per-SoC and not per-Adreno speedbin fuse values (need another patchset to land elsewhere), a good improvement/stopgap solution is to use adreno_is_aXYZ macros in place of explicit revision matching. Do so to allow differentiating between A619 and A619_holi. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 18 +++++++++--------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 14 ++++++++++++-- 2 files changed, 21 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 87ff48f7f3be..4665a2e8fdde 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2217,23 +2217,23 @@ static u32 adreno_7c3_get_speed_bin(u32 fuse) return UINT_MAX; } -static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse) +static u32 fuse_to_supp_hw(struct device *dev, struct adreno_gpu *adreno_gpu, u32 fuse) { u32 val = UINT_MAX; - if (adreno_cmp_rev(ADRENO_REV(6, 1, 8, ANY_ID), rev)) + if (adreno_is_a618(adreno_gpu)) val = a618_get_speed_bin(fuse); - else if (adreno_cmp_rev(ADRENO_REV(6, 1, 9, ANY_ID), rev)) + else if (adreno_is_a619(adreno_gpu)) val = a619_get_speed_bin(fuse); - else if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev)) + else if (adreno_is_7c3(adreno_gpu)) val = adreno_7c3_get_speed_bin(fuse); - else if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev)) + else if (adreno_is_a640(adreno_gpu)) val = a640_get_speed_bin(fuse); - else if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev)) + else if (adreno_is_a650(adreno_gpu)) val = a650_get_speed_bin(fuse); if (val == UINT_MAX) { @@ -2246,7 +2246,7 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse) return (1 << val); } -static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev) +static int a6xx_set_supported_hw(struct device *dev, struct adreno_gpu *adreno_gpu) { u32 supp_hw; u32 speedbin; @@ -2265,7 +2265,7 @@ static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev) return ret; } - supp_hw = fuse_to_supp_hw(dev, rev, speedbin); + supp_hw = fuse_to_supp_hw(dev, adreno_gpu, speedbin); ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); if (ret) @@ -2384,7 +2384,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) if (!adreno_has_gmu_wrapper(adreno_gpu)) a6xx_llc_slices_init(pdev, a6xx_gpu); - ret = a6xx_set_supported_hw(&pdev->dev, config->rev); + ret = a6xx_set_supported_hw(&pdev->dev, adreno_gpu); if (ret) { a6xx_destroy(&(a6xx_gpu->base.base)); return ERR_PTR(ret); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 27c30a7694f4..da9f45a13b5d 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -268,9 +268,9 @@ static inline int adreno_is_a630(struct adreno_gpu *gpu) return gpu->revn == 630; } -static inline int adreno_is_a640_family(struct adreno_gpu *gpu) +static inline int adreno_is_a640(struct adreno_gpu *gpu) { - return (gpu->revn == 640) || (gpu->revn == 680); + return gpu->revn == 640; } static inline int adreno_is_a650(struct adreno_gpu *gpu) @@ -289,6 +289,11 @@ static inline int adreno_is_a660(struct adreno_gpu *gpu) return gpu->revn == 660; } +static inline int adreno_is_a680(struct adreno_gpu *gpu) +{ + return gpu->revn == 680; +} + /* check for a615, a616, a618, a619 or any derivatives */ static inline int adreno_is_a615_family(struct adreno_gpu *gpu) { @@ -306,6 +311,11 @@ static inline int adreno_is_a650_family(struct adreno_gpu *gpu) return gpu->revn == 650 || gpu->revn == 620 || adreno_is_a660_family(gpu); } +static inline int adreno_is_a640_family(struct adreno_gpu *gpu) +{ + return adreno_is_a640(gpu) || adreno_is_a680(gpu); +} + u64 adreno_private_address_space_size(struct msm_gpu *gpu); int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, uint32_t param, uint64_t *value, uint32_t *len); From patchwork Thu Mar 30 23:25:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 77467 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp200302vqo; Thu, 30 Mar 2023 16:29:03 -0700 (PDT) X-Google-Smtp-Source: AKy350Z2M0DKVDId998WfYxT5Ye/Rjke7Cp4QH6ecL9HAqc+RFDOlvypG2/X8ngiNAFhVKvRChqt X-Received: by 2002:aa7:c590:0:b0:4ac:b431:4762 with SMTP id g16-20020aa7c590000000b004acb4314762mr22092498edq.23.1680218943391; Thu, 30 Mar 2023 16:29:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680218943; cv=none; d=google.com; s=arc-20160816; b=Jfd4DqCgR36DsJjvwluCmGTR07G3uiJRNCOCvuCN2LQJNTS8JcV0838DpCPchUF3yg C7O5wVNT+7Vx1NhVilt8LPkn3yMoeuvkPxn+Px30RutUcQDOvZEhmF6iJ2qbzNrY2vCZ HDSG05etmBpTO7UHESwcNRUBPmIG2b4w0jZREoQ0vYr13eo0NMeYNFsb+JhbDS84+6uR YR1/a6ze6ykjh7KLCbg7huwz7LQ/f2yyxJGJTLurvlwUPsMviGiqLy46SOAyaEFU9wWV ou+WjZMKEUfBEjI+Iogb2tik2hJqA/uTSBgfzm4FOHyCckgzHE7LIvbodUnKAUAoFpEx 5cEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=hbnKgpdDmdf2EtoeRfnsVRvWlWQl2tvq4ylx1pYZM4M=; b=U9cGQ55OkEulzAEcwQSnBmWybNuBN2xJJBJLxYuEFiEocYohHrzhG0Awaphj4Z9NGx GFKPOb88UIzRIeBWG/LWyCmlPiOL2TwBf79BVaXtJ7T3RzBthFdI3OXdOHSPnAUHMiiY 2EH32GgfshKDsQHtn/bMKK+5WGT3zVF1JhHDAsPRAqjyNXeygVFThAyL0tsFZFYqkeLF qWtuZZxuxxDGpBZkmxzf/rI0h6VE1BtvjL3MT2837FX3fcvfy2yIrviUh5W0iggO03fO jgvg0FbFOcXMYunsxlL4ihWigcdp1k1BKVZkdt0cKza5JbVJYmJ0nLy2PPNpoDgAaEIj wV5Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AKrrOLSQ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id r19-20020a056402035300b004c0c33b95c1si786975edw.324.2023.03.30.16.28.39; Thu, 30 Mar 2023 16:29:03 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AKrrOLSQ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231697AbjC3X0o (ORCPT + 99 others); Thu, 30 Mar 2023 19:26:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48438 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231539AbjC3XZq (ORCPT ); Thu, 30 Mar 2023 19:25:46 -0400 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 665361B0 for ; Thu, 30 Mar 2023 16:25:44 -0700 (PDT) Received: by mail-lf1-x12b.google.com with SMTP id g19so13549407lfr.9 for ; Thu, 30 Mar 2023 16:25:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680218742; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=hbnKgpdDmdf2EtoeRfnsVRvWlWQl2tvq4ylx1pYZM4M=; b=AKrrOLSQYKJQaMXcRrQu0CQl14DrLKp+LUcL/j2RX20kt7z99u9qgo72XeZ83s8bCq iw0dXwXm8erHypA0zavOKPM9MlGrGvGF6ne3J/Ou8EfRgem5VonDGWY6WdqaSpU7rxI5 TzQxd7lwl4g5pU7NPkCgNtkEwjy9trA//15ExGUJleEF+E37+VPdlWZ7H/5/U+vbC4kR fV7q3IssukfY8EG2kx10qEMMa4F0jLWZRJbqW+pu+NZ2qP3epMBulekAX4mVS2lekmoe v5WGNxi2qNuOrSek7dGDXc9COz+QyfDx/b3t3mWbutnVXVx8g9C+72BrX1Sh7Salt/WN L2Lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680218742; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hbnKgpdDmdf2EtoeRfnsVRvWlWQl2tvq4ylx1pYZM4M=; b=Lo2BiKY+iyXD0kbiuz/D3flmQx2Ihs6lwLvsuWOiwYkRSTQbo6oaDmDR9s9rinOxWN i+vFblzUbHl/sTbASUUcGw2yMdtjaD11HlhdiDSL0Xx1dq5xIB/3LxIzrpYlI19KeVj8 I3h7ObDFkPDmUEnmvs+tZLQgCAiam9EjCjmmUcUUat+ywDxLSYTycLY33ogHXrxKMvDd UemtPv9fsmFHSWlzmrJjg0DZt3uhu6UywpweDEJo6GzgW86NPQtFa8rLjou3jbFfo7jy x+/Ywgha4QqD0gpCZ173cvGQz4dW7xy8vFfqrtWN8HtJ3G3gIiq31Cxrbq8o7NBaKEkU 7VyA== X-Gm-Message-State: AAQBX9esSfNcJVq8jBZph1HwzY4rimX3Tp5T/Vt2mkvsWsknnPkb+Gp/ MUVU0voSgd+rNVenrypXqFSQaxSLxVcPAnhR9yI= X-Received: by 2002:ac2:5446:0:b0:4dd:a76e:dfff with SMTP id d6-20020ac25446000000b004dda76edfffmr6583602lfn.23.1680218742650; Thu, 30 Mar 2023 16:25:42 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id g26-20020ac2539a000000b004dda80cabf0sm127241lfh.172.2023.03.30.16.25.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 16:25:41 -0700 (PDT) From: Konrad Dybcio Date: Fri, 31 Mar 2023 01:25:28 +0200 Subject: [PATCH v5 14/15] drm/msm/a6xx: Add A619_holi speedbin support MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v5-14-bf774b9a902a@linaro.org> References: <20230223-topic-gmuwrapper-v5-0-bf774b9a902a@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v5-0-bf774b9a902a@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680218720; l=2033; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=FcRDjVP6HKQEi6DA2ZuPEYKRXdBx6r/IOHWHLE+VmPg=; b=FSpItbK2YTPN5GbTbq1M+JLzFhOzvFHICJuxlu5kd1ZQNz7BQ++PfOJcBCrklW3H2skLcoLX/PxU Eud6bXZwBXYsVuhf8xuEnnGEixe5Z5eNrgEHsJRnS/KjOUtNBmz7 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761837258845672961?= X-GMAIL-MSGID: =?utf-8?q?1761837258845672961?= A619_holi is implemented on at least two SoCs: SM4350 (holi) and SM6375 (blair). This is what seems to be a first occurrence of this happening, but it's easy to overcome by guarding the SoC-specific fuse values with of_machine_is_compatible(). Do just that to enable frequency limiting on these SoCs. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 4665a2e8fdde..c61b1c4090c5 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2165,6 +2165,34 @@ static u32 a618_get_speed_bin(u32 fuse) return UINT_MAX; } +static u32 a619_holi_get_speed_bin(u32 fuse) +{ + /* + * There are (at least) two SoCs implementing A619_holi: SM4350 (holi) + * and SM6375 (blair). Limit the fuse matching to the corresponding + * SoC to prevent bogus frequency setting (as improbable as it may be, + * given unexpected fuse values are.. unexpected! But still possible.) + */ + + if (fuse == 0) + return 0; + + if (of_machine_is_compatible("qcom,sm4350")) { + if (fuse == 138) + return 1; + else if (fuse == 92) + return 2; + } else if (of_machine_is_compatible("qcom,sm6375")) { + if (fuse == 190) + return 1; + else if (fuse == 177) + return 2; + } else + pr_warn("Unknown SoC implementing A619_holi!\n"); + + return UINT_MAX; +} + static u32 a619_get_speed_bin(u32 fuse) { if (fuse == 0) @@ -2224,6 +2252,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_gpu *adreno_gpu, u3 if (adreno_is_a618(adreno_gpu)) val = a618_get_speed_bin(fuse); + else if (adreno_is_a619_holi(adreno_gpu)) + val = a619_holi_get_speed_bin(fuse); + else if (adreno_is_a619(adreno_gpu)) val = a619_get_speed_bin(fuse); From patchwork Thu Mar 30 23:25:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 77468 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp200530vqo; Thu, 30 Mar 2023 16:29:35 -0700 (PDT) X-Google-Smtp-Source: AKy350aDUqdWVz5Ccu3sBQ9q0Nc5Y546GUoFtIIZ3BG7EB1LFrMRJUKbuJ3B4gg/1qYieZJfmUVi X-Received: by 2002:a17:906:3b15:b0:84d:4e4f:1f85 with SMTP id g21-20020a1709063b1500b0084d4e4f1f85mr27569254ejf.59.1680218974833; Thu, 30 Mar 2023 16:29:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680218974; cv=none; d=google.com; s=arc-20160816; b=LdtP0OpwfILyWkZfnxoNmE949AFO1Blcy3XCxLXck449rpKyQ/Y1YoBL1j7l7EVa9O BnHEa8qkZ9SdCorQtPQzqIa7XghBoz8bGgq/3KvBGTmqG5Q4AYc/FpbQkFJUh0CVvh83 O0WsqI0q+dfBBl2mJAMCsj9LP1MFayIh9lmF5eWPKBBb0qVn4caSRUJbw8aRM6ZuGDBt 6lU/tlTdJgYlAndH1DKxrAQ9WrlvDkzy2r6fwdSrSsWzTvD3AleXIrjUgmtAtjdHHzbd 9hOeo/f+ZF6REKSgl/Qo0ra791R+qvIEUdyoBWnXU7oGyTaxAzqE0b7JRCDtacBsAVXQ MJHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=w/CadsX/cgR9x9hYinvKdUNqwtugIvIpkzu1IofxqH4=; b=LlAt+3gcYjQDTfzBV9TFneZLoCjfXj5xQV8siKxQdVLZ4Cehw+U2X6/ofad1r1OCth oOd/CHJM1uWe9O1PL4dJGmuxj+JxIJZvuDXuk2cyV894l5P0340ho4dW+rRbWpVGY4L/ 1VcIEbt3XaXd73tD1ZaKMFU8fPCkopZEPNwTDN+J495ooln212tBQHuwmw0AtOGuiWSn m00KCSJLpP6/WgSvI5vC3IasAoVZwVp6dclrZDYV7PSBZQ1gK/tcgzW+kFpoP9pKv5/K hFk1jXDnTVZ2fy1FNUDJvgqPtq60xBlKaYG0myNgrA9ucy/3FUtQlsknqiD1N240aOsR RprA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=D30vwFl9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id w7-20020a1709064a0700b00939fb8e7aabsi548574eju.784.2023.03.30.16.29.11; Thu, 30 Mar 2023 16:29:34 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=D30vwFl9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231703AbjC3X0u (ORCPT + 99 others); Thu, 30 Mar 2023 19:26:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231545AbjC3XZr (ORCPT ); Thu, 30 Mar 2023 19:25:47 -0400 Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 04F733581 for ; Thu, 30 Mar 2023 16:25:46 -0700 (PDT) Received: by mail-lj1-x233.google.com with SMTP id q14so21281473ljm.11 for ; Thu, 30 Mar 2023 16:25:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680218744; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=w/CadsX/cgR9x9hYinvKdUNqwtugIvIpkzu1IofxqH4=; b=D30vwFl9P7JOarfMELFS1sqqzu5IUG8n0KUVid85FdPQrOmJ3NTQxdPFDCUsWdtYsD L0wE3vWOmVsjxV3qHPMQq9W8LAKWgnt0ZKVqdXNyRYKZ5Ywku5nGZpa9KunzPOvGPutP oioxn89SMqtnuS4FhqTBb2YVfB0v+mfH7s+SL0Qqp4EJMRmsbRGK1DWm0X9a4W8/hTZf KzqAQIVzPYKwSxpFzvv555AU2SZlDQQw2fUfWfU+PAsk9LNmKz+oPVqp4Usa17KBJOhr WekSWu/P6cIDlffYLE/OzOpFoG/sfhD1HNnpS/uFrsE+yZH+IkLnEeJAN9XyN0a3h1A3 aOTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680218744; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=w/CadsX/cgR9x9hYinvKdUNqwtugIvIpkzu1IofxqH4=; b=ELqLuDuWqmyQcWACNfAK/2kQAIHdHHsQpSGzl+9BDlImNqD8hTepPpEgYukDcOt7mJ GXZ1iWXbi5VrXJ3+cAgClJhjV6iojgYK2yCQtRMdqCcS+2pMKMQalc1jBLWfTk/Qee3L W6vMwJHRqmqWyKcjk78b3+3nT0JlTChSv0/qCLjO2kBFcWt6qm5HgQYmwAFqV0iB0Vq+ 3y8VbGh8LiDVQZhQaMmYnx4h+W9CIbwD1KJysSk3PbIodmb964rPgkDHBK7kceQ+JWni +xH6X0RQCzZBSEPXLfWvIveIIseA7DW1AlH8nG2+D1DmY/2YY2oYs1TvpWpUPIHNtwCt s5Tg== X-Gm-Message-State: AAQBX9cj+I5bxR34o2n8FYdnXX4YiRV7LwvWayYkOQwqM1oow3HvC0pP 96Wga1kKCieff+KlKQrgvK/HBQ== X-Received: by 2002:a2e:7019:0:b0:299:c03a:1cf9 with SMTP id l25-20020a2e7019000000b00299c03a1cf9mr7384502ljc.10.1680218744293; Thu, 30 Mar 2023 16:25:44 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id g26-20020ac2539a000000b004dda80cabf0sm127241lfh.172.2023.03.30.16.25.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 16:25:43 -0700 (PDT) From: Konrad Dybcio Date: Fri, 31 Mar 2023 01:25:29 +0200 Subject: [PATCH v5 15/15] drm/msm/a6xx: Add A610 speedbin support MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v5-15-bf774b9a902a@linaro.org> References: <20230223-topic-gmuwrapper-v5-0-bf774b9a902a@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v5-0-bf774b9a902a@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680218720; l=1852; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=sRjMSX3RSLjg5O+bbZnBcjOb5P4ZXSSVfgLMBDfv6/0=; b=2byAdZ0K4ZJknmJ/po2ONEXUn7MAt5HV2jkFIX+85s9yPzd0JQUgigp/xUAsBjXyTePMMNqdtmwy 6QK2s1SeAI6IPLE36ITrYG7f2atB6Yx8W5XnNuZs0n2jYAqiskVp X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761837292098928550?= X-GMAIL-MSGID: =?utf-8?q?1761837292098928550?= A610 is implemented on at least three SoCs: SM6115 (bengal), SM6125 (trinket) and SM6225 (khaje). Trinket does not support speed binning (only a single SKU exists) and we don't yet support khaje upstream. Hence, add a fuse mapping table for bengal to allow for per-chip frequency limiting. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index c61b1c4090c5..7662104c740f 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2153,6 +2153,30 @@ static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) return progress; } +static u32 a610_get_speed_bin(u32 fuse) +{ + /* + * There are (at least) three SoCs implementing A610: SM6125 (trinket), + * SM6115 (bengal) and SM6225 (khaje). Trinket does not have speedbinning, + * as only a single SKU exists and we don't support khaje upstream yet. + * Hence, this matching table is only valid for bengal and can be easily + * expanded if need be. + */ + + if (fuse == 0) + return 0; + else if (fuse == 206) + return 1; + else if (fuse == 200) + return 2; + else if (fuse == 157) + return 3; + else if (fuse == 127) + return 4; + + return UINT_MAX; +} + static u32 a618_get_speed_bin(u32 fuse) { if (fuse == 0) @@ -2249,6 +2273,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_gpu *adreno_gpu, u3 { u32 val = UINT_MAX; + if (adreno_is_a610(adreno_gpu)) + val = a610_get_speed_bin(fuse); + if (adreno_is_a618(adreno_gpu)) val = a618_get_speed_bin(fuse);