From patchwork Thu Mar 30 13:39:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Piyush Malgujar X-Patchwork-Id: 77191 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1156576vqo; Thu, 30 Mar 2023 07:11:25 -0700 (PDT) X-Google-Smtp-Source: AKy350blgLtXjhz8Ve7poVZgngxCdFltehzRg5t3seXh3JvyGu5qq0AJNbXGImM7PWfk6llTWwlT X-Received: by 2002:a17:906:3786:b0:8dd:76d5:a82 with SMTP id n6-20020a170906378600b008dd76d50a82mr22565587ejc.47.1680185485162; Thu, 30 Mar 2023 07:11:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680185485; cv=none; d=google.com; s=arc-20160816; b=Xbv/bZ63QtuYYIbiDCOGrMlM2RYAjkTlMUSe6jcD38+ULZGU2wX2tDY4NOL895o2Dx cF6B+XFo/Gyu90NaKnGGO+kSJbLJZxRd/A1gnSPfEViGUpXVATiWDds3nV0iWsrFQaW/ N0gu6PRbeoE6Bdx/kLt36ZToQhAyZAHGnwzV8GMgd7QQcsSfs/f5Yra1nCorLInqxZC8 HOtWwb9EKd0/hOG/zvb6heIxEopqyIDk9SMLoztgON1CV43tEaV8wInUpkEEXLCORwWD gEzTRK7q/3ANwtdVn/QUZds8NzaLuiyoYA0Tzh03GSUPzMmvpGc5tkeDco4qOVbffwU1 VG+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=igFSrGhqRX8iWs6tf11H1rqPYle1i6Jji98Fd+QZRA8=; b=WN2WzopzcnAmfSU8Vcfav6Z+O1caXIVMoyMdia++rrBNKn9a7jWPB1+JDquL7v0f0X PicdHApYZ2jzV6SJVv/5ZAi6jNVQGG2xPiBcdmWERBKQYI4DhyiTkvK2qku8XFnlhldx DJLilYOQTeI4MGy1apxjxy29GK75F1+UIUZmp4UoBwSXqkywV2eJs6Uey4ZQ98sN9BfW VLlO9H+Gz1acWuMY7SxTspD8Rid+FKS4bIBN6G/zVU00DXN1Rvcwji4h8UfnxQHthsbT At9IPWhuppX5SvT5hi/rBWghMSKEV5UrrHz21XmlJys/r5fm3SHhgcWrZdCflxZRonTs cLxQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0220 header.b="B3RdYZp/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=REJECT dis=NONE) header.from=marvell.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id y9-20020a170906070900b0093117deb464si35686559ejb.88.2023.03.30.07.11.01; Thu, 30 Mar 2023 07:11:25 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0220 header.b="B3RdYZp/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=REJECT dis=NONE) header.from=marvell.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232155AbjC3Nno (ORCPT + 99 others); Thu, 30 Mar 2023 09:43:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57752 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232013AbjC3Nnc (ORCPT ); Thu, 30 Mar 2023 09:43:32 -0400 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2DA30C143; Thu, 30 Mar 2023 06:43:23 -0700 (PDT) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32UDAlfp014499; Thu, 30 Mar 2023 06:43:21 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=igFSrGhqRX8iWs6tf11H1rqPYle1i6Jji98Fd+QZRA8=; b=B3RdYZp/XBcb5GO8LOkOlYeTK/i1jE84TjOBYkhAxUKU6o9tnyYXpLo8Ijm8157gnm82 S7DcpnmKeUrWqa0a2ZVHW62Jja8lnMsLzupNlHFZNlvaXz3hlv6be3Rdh0Hos5KqqS2I wm6+WSJd09nRHoHvTr0+uQEnnzZP4R4+Bir8Pt6dCc0hKRhqo9rXgJhUy9TY3ANNBl+z 5aCdRXQMJHCZhreY3Od3W9Qphv+DCv/7pYzxwgqzSoPEvKx1NrzdZPKVfnTTQYdDGSLs rOdajWoUvEpBYDTE+s91LO1wC+3q7UwOj55hJcjMbfz+PWb4h4Qbm0IlfcIGN48vhLu5 2Q== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3pn2ty2nvq-11 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 30 Mar 2023 06:43:20 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 30 Mar 2023 06:40:26 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 30 Mar 2023 06:40:25 -0700 Received: from localhost.localdomain (unknown [10.110.150.250]) by maili.marvell.com (Postfix) with ESMTP id DB85F3F704A; Thu, 30 Mar 2023 06:40:25 -0700 (PDT) From: Piyush Malgujar To: , , , CC: , , Suneel Garapati , Piyush Malgujar Subject: [PATCH 1/3] i2c: thunderx: Clock divisor logic changes Date: Thu, 30 Mar 2023 06:39:51 -0700 Message-ID: <20230330133953.21074-2-pmalgujar@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230330133953.21074-1-pmalgujar@marvell.com> References: <20230330133953.21074-1-pmalgujar@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: dfDfPFFKH7tN6h7L9r6DizhTM7dfuWbX X-Proofpoint-ORIG-GUID: dfDfPFFKH7tN6h7L9r6DizhTM7dfuWbX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-30_09,2023-03-30_03,2023-02-09_01 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761802175173505093?= X-GMAIL-MSGID: =?utf-8?q?1761802175173505093?= From: Suneel Garapati Handle changes to clock divisor logic for OcteonTX2 SoC family using subsystem ID and using default reference clock source as 100MHz. Signed-off-by: Suneel Garapati Signed-off-by: Piyush Malgujar Acked-by: Andi Shyti --- drivers/i2c/busses/i2c-octeon-core.c | 29 ++++++++++++++++++++---- drivers/i2c/busses/i2c-octeon-core.h | 15 ++++++++++++ drivers/i2c/busses/i2c-thunderx-pcidrv.c | 6 +++++ 3 files changed, 46 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/busses/i2c-octeon-core.c b/drivers/i2c/busses/i2c-octeon-core.c index 845eda70b8cab52a0453c9f4cb545010fba4305d..dfd58bbec47b1f0554ae0c100c680b6ba9be61ec 100644 --- a/drivers/i2c/busses/i2c-octeon-core.c +++ b/drivers/i2c/busses/i2c-octeon-core.c @@ -17,6 +17,7 @@ #include #include #include +#include #include "i2c-octeon-core.h" @@ -658,31 +659,51 @@ int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) void octeon_i2c_set_clock(struct octeon_i2c *i2c) { int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff; - int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000; + int mdiv_min = 2; + /* starting value on search for lowest diff */ + const int huge_delta = 1000000; + /* + * Find divisors to produce target frequency, start with large delta + * to cover wider range of divisors, note thp = TCLK half period. + */ + int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = huge_delta; + + if (octeon_i2c_is_otx2(to_pci_dev(i2c->dev))) { + thp = 0x3; + mdiv_min = 0; + } for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) { /* * An mdiv value of less than 2 seems to not work well * with ds1337 RTCs, so we constrain it to larger values. */ - for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) { + for (mdiv_idx = 15; mdiv_idx >= mdiv_min && delta_hz != 0; mdiv_idx--) { /* * For given ndiv and mdiv values check the * two closest thp values. */ tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10; tclk *= (1 << ndiv_idx); - thp_base = (i2c->sys_freq / (tclk * 2)) - 1; + if (octeon_i2c_is_otx2(to_pci_dev(i2c->dev))) + thp_base = (i2c->sys_freq / tclk) - 2; + else + thp_base = (i2c->sys_freq / (tclk * 2)) - 1; for (inc = 0; inc <= 1; inc++) { thp_idx = thp_base + inc; if (thp_idx < 5 || thp_idx > 0xff) continue; - foscl = i2c->sys_freq / (2 * (thp_idx + 1)); + if (octeon_i2c_is_otx2(to_pci_dev(i2c->dev))) + foscl = i2c->sys_freq / (thp_idx + 2); + else + foscl = i2c->sys_freq / + (2 * (thp_idx + 1)); foscl = foscl / (1 << ndiv_idx); foscl = foscl / (mdiv_idx + 1) / 10; diff = abs(foscl - i2c->twsi_freq); + /* Use it if smaller diff from target */ if (diff < delta_hz) { delta_hz = diff; thp = thp_idx; diff --git a/drivers/i2c/busses/i2c-octeon-core.h b/drivers/i2c/busses/i2c-octeon-core.h index 9bb9f64fdda0392364638ecbaafe3fab5612baf6..8a0033c94a8a291fb255b0da03858274035c46f4 100644 --- a/drivers/i2c/busses/i2c-octeon-core.h +++ b/drivers/i2c/busses/i2c-octeon-core.h @@ -7,6 +7,7 @@ #include #include #include +#include /* Controller command patterns */ #define SW_TWSI_V BIT_ULL(63) /* Valid bit */ @@ -211,6 +212,20 @@ static inline void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data) octeon_i2c_writeq_flush(data, i2c->twsi_base + TWSI_INT(i2c)); } +#define PCI_SUBSYS_DEVID_9XXX 0xB +/** + * octeon_i2c_is_otx2 - check for chip ID + * @pdev: PCI dev structure + * + * Returns TRUE if OcteonTX2, FALSE otherwise. + */ +static inline bool octeon_i2c_is_otx2(struct pci_dev *pdev) +{ + u32 chip_id = (pdev->subsystem_device >> 12) & 0xF; + + return (chip_id == PCI_SUBSYS_DEVID_9XXX); +} + /* Prototypes */ irqreturn_t octeon_i2c_isr(int irq, void *dev_id); int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num); diff --git a/drivers/i2c/busses/i2c-thunderx-pcidrv.c b/drivers/i2c/busses/i2c-thunderx-pcidrv.c index a77cd86fe75ed7401bc041b27c651b9fedf67285..eecd27f9f1730e522dcccafc9f12ea891a3b59ef 100644 --- a/drivers/i2c/busses/i2c-thunderx-pcidrv.c +++ b/drivers/i2c/busses/i2c-thunderx-pcidrv.c @@ -205,6 +205,12 @@ static int thunder_i2c_probe_pci(struct pci_dev *pdev, if (ret) goto error; + /* + * For OcteonTX2 chips, set reference frequency to 100MHz + * as refclk_src in TWSI_MODE register defaults to 100MHz. + */ + if (octeon_i2c_is_otx2(pdev)) + i2c->sys_freq = 100000000; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id f1-20020a6547c1000000b0050bea56f69asi34494195pgs.735.2023.03.30.06.56.37; Thu, 30 Mar 2023 06:56:52 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0220 header.b=fgj5so1Z; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=REJECT dis=NONE) header.from=marvell.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232216AbjC3Nnv (ORCPT + 99 others); Thu, 30 Mar 2023 09:43:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57854 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232184AbjC3Nnd (ORCPT ); Thu, 30 Mar 2023 09:43:33 -0400 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2EEEEBDD5; Thu, 30 Mar 2023 06:43:25 -0700 (PDT) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32UDAlft014499; Thu, 30 Mar 2023 06:43:23 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=WlBWc0WvmdUB+duMbK1s8vpVWPj7G4Dqho4AHs2Pg4c=; b=fgj5so1Zv0JpUtJO+F2Q8TBpVIFa7NltvC1TkePu2MjYpYsWtuBlLIaHalq4q2DdgZSr qi5ikzC43Ty20wZyj0jOu2Gpv9Ny1ONf6x0j8forCCpVsCOQyQGPMlJhMQ+Ku9SlbSaR D9wA5+QDtsOb7hjmR+bXlVLTJcvfDviC3grOneQUvp6yU1vEvYchrq36JCno3zvY1zZO kO0jrHAlHsFp9vYFdGStaSQ3fLMsewbBVvwtEfecMAjodMd8xWvYt4njuwU55wDRpBmR yDjzhX26qJFaEmbY7AZtKaoHC2rc59fRhV/6Wiu+k09EzgII7ofktcKsy/sGb8mOoTiq Gg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3pn2ty2nw9-12 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 30 Mar 2023 06:43:22 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 30 Mar 2023 06:40:38 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 30 Mar 2023 06:40:38 -0700 Received: from localhost.localdomain (unknown [10.110.150.250]) by maili.marvell.com (Postfix) with ESMTP id 502C93F704A; Thu, 30 Mar 2023 06:40:38 -0700 (PDT) From: Piyush Malgujar To: , , , CC: , , Suneel Garapati , Piyush Malgujar Subject: [PATCH 2/3] i2c: thunderx: Add support for High speed mode Date: Thu, 30 Mar 2023 06:39:52 -0700 Message-ID: <20230330133953.21074-3-pmalgujar@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230330133953.21074-1-pmalgujar@marvell.com> References: <20230330133953.21074-1-pmalgujar@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: p0XX1zR1KU1kLDc40tQKlVv6n4MvkkUE X-Proofpoint-ORIG-GUID: p0XX1zR1KU1kLDc40tQKlVv6n4MvkkUE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-30_09,2023-03-30_03,2023-02-09_01 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761801259792150370?= X-GMAIL-MSGID: =?utf-8?q?1761801259792150370?= From: Suneel Garapati Support High speed mode clock setup for OcteonTX2 platforms. Signed-off-by: Suneel Garapati Signed-off-by: Piyush Malgujar --- drivers/i2c/busses/i2c-octeon-core.c | 78 ++++++++++++++++-------- drivers/i2c/busses/i2c-octeon-core.h | 3 + drivers/i2c/busses/i2c-thunderx-pcidrv.c | 3 +- 3 files changed, 57 insertions(+), 27 deletions(-) diff --git a/drivers/i2c/busses/i2c-octeon-core.c b/drivers/i2c/busses/i2c-octeon-core.c index dfd58bbec47b1f0554ae0c100c680b6ba9be61ec..7c49dc8ccbd2ef05fec675d282193b98f2b69835 100644 --- a/drivers/i2c/busses/i2c-octeon-core.c +++ b/drivers/i2c/busses/i2c-octeon-core.c @@ -61,10 +61,19 @@ static int octeon_i2c_wait(struct octeon_i2c *i2c) return octeon_i2c_test_iflg(i2c) ? 0 : -ETIMEDOUT; } - i2c->int_enable(i2c); - time_left = wait_event_timeout(i2c->queue, octeon_i2c_test_iflg(i2c), - i2c->adap.timeout); - i2c->int_disable(i2c); + if (IS_LS_FREQ(i2c->twsi_freq)) { + i2c->int_enable(i2c); + time_left = wait_event_timeout(i2c->queue, + octeon_i2c_test_iflg(i2c), + i2c->adap.timeout); + i2c->int_disable(i2c); + } else { + time_left = 1000; /* 1ms */ + do { + if (time_left--) + __udelay(1); + } while (!octeon_i2c_test_iflg(i2c) && time_left); + } if (i2c->broken_irq_check && !time_left && octeon_i2c_test_iflg(i2c)) { @@ -608,25 +617,27 @@ int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) struct octeon_i2c *i2c = i2c_get_adapdata(adap); int i, ret = 0; - if (num == 1) { - if (msgs[0].len > 0 && msgs[0].len <= 8) { - if (msgs[0].flags & I2C_M_RD) - ret = octeon_i2c_hlc_read(i2c, msgs); - else - ret = octeon_i2c_hlc_write(i2c, msgs); - goto out; - } - } else if (num == 2) { - if ((msgs[0].flags & I2C_M_RD) == 0 && - (msgs[1].flags & I2C_M_RECV_LEN) == 0 && - msgs[0].len > 0 && msgs[0].len <= 2 && - msgs[1].len > 0 && msgs[1].len <= 8 && - msgs[0].addr == msgs[1].addr) { - if (msgs[1].flags & I2C_M_RD) - ret = octeon_i2c_hlc_comp_read(i2c, msgs); - else - ret = octeon_i2c_hlc_comp_write(i2c, msgs); - goto out; + if (IS_LS_FREQ(i2c->twsi_freq)) { + if (num == 1) { + if (msgs[0].len > 0 && msgs[0].len <= 8) { + if (msgs[0].flags & I2C_M_RD) + ret = octeon_i2c_hlc_read(i2c, msgs); + else + ret = octeon_i2c_hlc_write(i2c, msgs); + goto out; + } + } else if (num == 2) { + if ((msgs[0].flags & I2C_M_RD) == 0 && + (msgs[1].flags & I2C_M_RECV_LEN) == 0 && + msgs[0].len > 0 && msgs[0].len <= 2 && + msgs[1].len > 0 && msgs[1].len <= 8 && + msgs[0].addr == msgs[1].addr) { + if (msgs[1].flags & I2C_M_RD) + ret = octeon_i2c_hlc_comp_read(i2c, msgs); + else + ret = octeon_i2c_hlc_comp_write(i2c, msgs); + goto out; + } } } @@ -666,11 +677,13 @@ void octeon_i2c_set_clock(struct octeon_i2c *i2c) * Find divisors to produce target frequency, start with large delta * to cover wider range of divisors, note thp = TCLK half period. */ - int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = huge_delta; + int ds = 10, thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = huge_delta; if (octeon_i2c_is_otx2(to_pci_dev(i2c->dev))) { thp = 0x3; mdiv_min = 0; + if (!IS_LS_FREQ(i2c->twsi_freq)) + ds = 15; } for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) { @@ -683,7 +696,7 @@ void octeon_i2c_set_clock(struct octeon_i2c *i2c) * For given ndiv and mdiv values check the * two closest thp values. */ - tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10; + tclk = i2c->twsi_freq * (mdiv_idx + 1) * ds; tclk *= (1 << ndiv_idx); if (octeon_i2c_is_otx2(to_pci_dev(i2c->dev))) thp_base = (i2c->sys_freq / tclk) - 2; @@ -701,7 +714,9 @@ void octeon_i2c_set_clock(struct octeon_i2c *i2c) foscl = i2c->sys_freq / (2 * (thp_idx + 1)); foscl = foscl / (1 << ndiv_idx); - foscl = foscl / (mdiv_idx + 1) / 10; + foscl = foscl / (mdiv_idx + 1) / ds; + if (foscl > i2c->twsi_freq) + continue; diff = abs(foscl - i2c->twsi_freq); /* Use it if smaller diff from target */ if (diff < delta_hz) { @@ -715,6 +730,17 @@ void octeon_i2c_set_clock(struct octeon_i2c *i2c) } octeon_i2c_reg_write(i2c, SW_TWSI_OP_TWSI_CLK, thp); octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv); + if (octeon_i2c_is_otx2(to_pci_dev(i2c->dev))) { + u64 mode; + + mode = __raw_readq(i2c->twsi_base + MODE(i2c)); + /* Set REFCLK_SRC and HS_MODE in TWSX_MODE register */ + if (!IS_LS_FREQ(i2c->twsi_freq)) + mode |= BIT(4) | BIT(0); + else + mode &= ~(BIT(4) | BIT(0)); + octeon_i2c_writeq_flush(mode, i2c->twsi_base + MODE(i2c)); + } } int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c) diff --git a/drivers/i2c/busses/i2c-octeon-core.h b/drivers/i2c/busses/i2c-octeon-core.h index 8a0033c94a8a291fb255b0da03858274035c46f4..89d7d3bb8e30bd5787978d17d5a9b20ab0d41e22 100644 --- a/drivers/i2c/busses/i2c-octeon-core.h +++ b/drivers/i2c/busses/i2c-octeon-core.h @@ -93,11 +93,13 @@ struct octeon_i2c_reg_offset { unsigned int sw_twsi; unsigned int twsi_int; unsigned int sw_twsi_ext; + unsigned int mode; }; #define SW_TWSI(x) (x->roff.sw_twsi) #define TWSI_INT(x) (x->roff.twsi_int) #define SW_TWSI_EXT(x) (x->roff.sw_twsi_ext) +#define MODE(x) (x->roff.mode) struct octeon_i2c { wait_queue_head_t queue; @@ -212,6 +214,7 @@ static inline void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data) octeon_i2c_writeq_flush(data, i2c->twsi_base + TWSI_INT(i2c)); } +#define IS_LS_FREQ(twsi_freq) ((twsi_freq) <= 400000) #define PCI_SUBSYS_DEVID_9XXX 0xB /** * octeon_i2c_is_otx2 - check for chip ID diff --git a/drivers/i2c/busses/i2c-thunderx-pcidrv.c b/drivers/i2c/busses/i2c-thunderx-pcidrv.c index eecd27f9f1730e522dcccafc9f12ea891a3b59ef..3dd5a4d798f99e9b5282360cf9d5840042fc8dcc 100644 --- a/drivers/i2c/busses/i2c-thunderx-pcidrv.c +++ b/drivers/i2c/busses/i2c-thunderx-pcidrv.c @@ -165,6 +165,7 @@ static int thunder_i2c_probe_pci(struct pci_dev *pdev, i2c->roff.sw_twsi = 0x1000; i2c->roff.twsi_int = 0x1010; i2c->roff.sw_twsi_ext = 0x1018; + i2c->roff.mode = 0x1038; i2c->dev = dev; pci_set_drvdata(pdev, i2c); @@ -209,7 +210,7 @@ static int thunder_i2c_probe_pci(struct pci_dev *pdev, * For OcteonTX2 chips, set reference frequency to 100MHz * as refclk_src in TWSI_MODE register defaults to 100MHz. */ - if (octeon_i2c_is_otx2(pdev)) + if (octeon_i2c_is_otx2(pdev) && IS_LS_FREQ(i2c->twsi_freq)) i2c->sys_freq = 100000000; octeon_i2c_set_clock(i2c); From patchwork Thu Mar 30 13:39:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Piyush Malgujar X-Patchwork-Id: 77185 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1145543vqo; Thu, 30 Mar 2023 06:58:49 -0700 (PDT) X-Google-Smtp-Source: AKy350Zd3iwCk+2WcbP1ZMyKiwLqWlbru5+26HeFrR6f70YDBUOgbF9sBvcok5I1MqfhNUp0zZR3 X-Received: by 2002:a17:903:2803:b0:1a1:bf22:2b6e with SMTP id kp3-20020a170903280300b001a1bf222b6emr19998340plb.43.1680184729235; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id r19-20020a170902e3d300b001a18e0c66a9si33038973ple.249.2023.03.30.06.58.35; Thu, 30 Mar 2023 06:58:49 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0220 header.b=Z9UcGxhI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=REJECT dis=NONE) header.from=marvell.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232036AbjC3Nnl (ORCPT + 99 others); Thu, 30 Mar 2023 09:43:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57828 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232181AbjC3Nnc (ORCPT ); Thu, 30 Mar 2023 09:43:32 -0400 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D39DBDFD; Thu, 30 Mar 2023 06:43:23 -0700 (PDT) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32UDAlfq014499; Thu, 30 Mar 2023 06:43:21 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=Ssk0O0bXBPfhBKJenQvgeKoOFmkN+0GiqUnjxldS3ws=; b=Z9UcGxhIQZFx6FuvYtJiiReWsTwhMauciJKUrm+0aMxm5oDf13jCqZSRX5Sq1vDeFonT vBY1d51DTtZabjKezIHECiOnaz/rwSJr1vGgvsRbSyVkMv8eQEovO4E1lEIEWTSnxZ08 vLWIjUG3obG5Vf/YD0R7tGDzXxb9zjiQ0n//MPvBJOwGuFWAcBAQApSEDMLilXVfdfAh WMkvZjozZakJa7CUF3hqgBoobL5OWc9psuMc+BO2Uql5ogMQo4YumV/g3+5r4KXu/Ubx idiJ1MOlIV0Ql/dKX6LC9IjNBjKCsfFgg+LLDoycqk9ApyaOparATIxZp7Zz5zSaghcf rg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3pn2ty2nvq-12 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 30 Mar 2023 06:43:21 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 30 Mar 2023 06:40:45 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 30 Mar 2023 06:40:45 -0700 Received: from localhost.localdomain (unknown [10.110.150.250]) by maili.marvell.com (Postfix) with ESMTP id C220F3F704A; Thu, 30 Mar 2023 06:40:45 -0700 (PDT) From: Piyush Malgujar To: , , , CC: , , Suneel Garapati , Piyush Malgujar Subject: [PATCH 3/3] i2c: octeon: Handle watchdog timeout Date: Thu, 30 Mar 2023 06:39:53 -0700 Message-ID: <20230330133953.21074-4-pmalgujar@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230330133953.21074-1-pmalgujar@marvell.com> References: <20230330133953.21074-1-pmalgujar@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 5yIs7O4U5wswzkYXU_QdDCdps8dWcBwJ X-Proofpoint-ORIG-GUID: 5yIs7O4U5wswzkYXU_QdDCdps8dWcBwJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-30_09,2023-03-30_03,2023-02-09_01 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761801383002105576?= X-GMAIL-MSGID: =?utf-8?q?1761801383002105576?= From: Suneel Garapati Status code 0xF0 refers to expiry of TWSI controller access watchdog and needs bus monitor reset using MODE register. Signed-off-by: Suneel Garapati Signed-off-by: Piyush Malgujar Acked-by: Andi Shyti --- drivers/i2c/busses/i2c-octeon-core.c | 8 ++++++++ drivers/i2c/busses/i2c-octeon-core.h | 1 + 2 files changed, 9 insertions(+) diff --git a/drivers/i2c/busses/i2c-octeon-core.c b/drivers/i2c/busses/i2c-octeon-core.c index 7c49dc8ccbd2ef05fec675d282193b98f2b69835..3482db7165f243232937e0af148fe996858e9f2e 100644 --- a/drivers/i2c/busses/i2c-octeon-core.c +++ b/drivers/i2c/busses/i2c-octeon-core.c @@ -187,6 +187,7 @@ static int octeon_i2c_hlc_wait(struct octeon_i2c *i2c) static int octeon_i2c_check_status(struct octeon_i2c *i2c, int final_read) { u8 stat; + u64 mode; /* * This is ugly... in HLC mode the status is not in the status register @@ -249,6 +250,13 @@ static int octeon_i2c_check_status(struct octeon_i2c *i2c, int final_read) case STAT_RXADDR_NAK: case STAT_AD2W_NAK: return -ENXIO; + + case STAT_WDOG_TOUT: + mode = __raw_readq(i2c->twsi_base + MODE(i2c)); + /* Set BUS_MON_RST to reset bus monitor */ + mode |= BIT(3); + octeon_i2c_writeq_flush(mode, i2c->twsi_base + MODE(i2c)); + return -EIO; default: dev_err(i2c->dev, "unhandled state: %d\n", stat); return -EIO; diff --git a/drivers/i2c/busses/i2c-octeon-core.h b/drivers/i2c/busses/i2c-octeon-core.h index 89d7d3bb8e30bd5787978d17d5a9b20ab0d41e22..a8d1bf9e89b8b0d21f52ff9f77f0ecf5263b5843 100644 --- a/drivers/i2c/busses/i2c-octeon-core.h +++ b/drivers/i2c/busses/i2c-octeon-core.h @@ -72,6 +72,7 @@ #define STAT_SLAVE_ACK 0xC8 #define STAT_AD2W_ACK 0xD0 #define STAT_AD2W_NAK 0xD8 +#define STAT_WDOG_TOUT 0xF0 #define STAT_IDLE 0xF8 /* TWSI_INT values */